Method and Apparatus for High Frequency Grid Design of ESC to Reduce Membrane Asymmetry

Abstract

Electrostatic chuck (ESC) devices and systems are provided. The ESC may have one or more chuck electrodes and a block electrode surrounding the chuck electrodes. The block electrode may reduce non-uniformities in semiconductor processing operations performed using the ESC. In some implementations, the block electrode is positioned below the chuck electrode.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS A PCT application is being filed contemporaneously herewith as a part of this application. Each application identified in the contemporaneously filed PCT application to which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes.

[0002] A semiconductor processing tool typically includes one or more semiconductor processing chambers that provide an isolated environment therein for processing semiconductor wafers. In some semiconductor processing tools, multiple semiconductor wafers may be processed within a single chamber. In such semiconductor processing tools, such chambers may include multiple wafer processing stations, each having a wafer support or pedestal. In some embodiments, the pedestal may be an electrostatic chuck (ESC), and the ESC may be used to generate an electromagnetic field that clamps the substrate to the ESC and / or a bias toward the ESC.

[0003] Semiconductor processing tools may be used to perform plasma-based processing operations on semiconductor wafers. A plasma source is used to form a plasma into which process gases are flowed, forming neutral particles, ions, and / or radicals of the process gases. These particles may then be flowed to react physically and / or chemically with the target substrate. Electrodes in an electrostatic chuck (ESC) or pedestal on which the substrate sits may be used to generate an electric field that may clamp the substrate to the pedestal and / or urge particles toward the pedestal.

[0004] The background and content discussion contained herein is intended only to provide a general overview of the disclosure. Most of this disclosure presents work by the inventors, and merely being mentioned in the Background section or presented as content anywhere in this specification does not imply that such work is admitted to be prior art. Summary of the Invention

[0005] Disclosed herein are methods and systems for operating a process chamber having an electrostatic chuck. In one aspect of the embodiments herein, an apparatus is disclosed that includes an electrostatic chuck (ESC) for supporting a semiconductor substrate. The ESC includes a top surface for supporting a wafer, one or more clamping electrodes below the top surface, the one or more clamping electrodes configured to electrostatically clamp the wafer to the top surface when energized, and a block electrode having an annular portion, a central portion, and three or more spokes, each spoke having a distal end coupled to the annular portion and a proximal end coupled to the central portion, the annular portion surrounding the one or more clamping electrodes when viewed along an axis perpendicular to the top surface.

[0006] In some embodiments, the one or more clamp electrodes are configured to be powered by an RF source. In some embodiments, the distance between the top surface of the block electrode and the bottom surface of the one or more clamp electrodes is between about 0.05 and about 0.2 inches. In some embodiments, the interior corners formed where each of the three or more spokes join the annulus are rounded. In some embodiments, the three or more spokes are arranged in a radially symmetric pattern. In some embodiments, there are 2·n spokes, where n is an integer greater than 1. In some embodiments, the three or more spokes are 10 spokes. In some embodiments, the one or more clamp electrodes are two clamp electrodes. In some embodiments, the two clamp electrodes are configured to operate with positive and negative polarities, respectively, when powered by a radio frequency (RF) source. In some embodiments, the two clamp electrodes are nominally semicircular electrodes. In some embodiments, the one or more clamp electrodes are planar. In some embodiments, the block electrode is planar.

[0007] In some embodiments, the block electrode comprises a metal mesh. In some embodiments, the block electrode comprises a single piece of metal. In some embodiments, the device further comprises an RF power source, and the number of spokes of the block electrode is based on the frequency of the RF power source. In some embodiments, the one or more clamp electrodes are parallel to the block electrode and are between the block electrode and the top surface. In some embodiments, the one or more clamp electrodes are at least two clamp electrodes, and at least one spoke of the three or more spokes is aligned with a gap between the one or more clamp electrodes when viewed along the first axis. In some embodiments, each spoke has a width measured in a direction perpendicular to the first axis and the proximal and distal ends of each spoke, and a ratio of the total width of all spokes to the inner circumference of the annulus is greater than about 1:10. In some embodiments, the device further comprises a lift pin that does not intersect the three or more spokes.

[0008] In some embodiments, the apparatus further includes a process chamber containing the ESC. In some embodiments, the apparatus further includes a rotary indexer. In some embodiments, the rotary indexer includes a central hub and indexer arms, the central hub being rotatable relative to the chamber about a first axis nominally located in the center of the circular pattern, and each indexer arm having a proximal end fixedly attached to the central hub and a distal end supporting a rotatable wafer support configured to rotate relative to the indexer arm about a corresponding second axis. The apparatus further includes a controller including one or more processors and one or more memories, the one or more processors, the one or more memories, the ESC, the indexer, and the process chamber being operatively connected to one another, and the one or more memory devices storing computer executable instructions for controlling the one or more processors to place a wafer located on the ESC on the rotatable wafer support, rotate the rotatable wafer support and the wafer supported thereon about a corresponding second axis by an amount based at least in part on an angle between two adjacent spokes of the three or more spokes of the block electrode, and place the wafer back on the ESC.

[0009] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 shows a perspective view of a block electrode that is in the same plane as two chuck electrodes.

[0011] [Diagram 2] FIG. 2 shows a graph of thickness as a function of θ for semiconductor wafers processed using various block grid designs.

[0012] [Diagram 3]FIG. 3 illustrates a side view of a processing chamber having an electrostatic chuck according to various embodiments disclosed herein.

[0013] [Figure 4a] FIG. 4a illustrates a perspective view of a chuck electrode and a block electrode according to various embodiments disclosed herein. [Figure 4b] FIG. 4b illustrates a top view of a chuck electrode and a block electrode according to various embodiments disclosed herein.

[0014] [Diagram 5] FIG. 5 shows a graph of thickness non-uniformity as a function of θ for semiconductor wafers processed using block grids having 2, 4, or 10 spokes.

[0015] [Figure 6a] FIG. 6a shows an alternative block electrode design having eight spokes. [Figure 6b] FIG. 6b shows an alternative block electrode design having 10 spokes.

[0016] [Figure 6c] FIG. 6c shows an alternative clamp electrode design having interdigitated electrodes.

[0017] [Figure 7] FIG. 7 shows a cutaway view of a block electrode having fillets between the spokes and the outer ring.

[0018] [Figure 8] FIG. 8 shows a schematic diagram of a block electrode showing the spoke width and arc length.

[0019] [Figure 9] FIG. 9 shows a schematic diagram of a rotary indexer.

[0020] [Figure 10]FIG. 10 shows a side view of the rotary indexer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present disclosure relates to electrostatic chucks (ESCs) used in semiconductor processing. In semiconductor processing equipment, electrostatic chucks are commonly used to clamp a substrate to a pedestal during plasma processes. Electrostatic chucks clamp the substrate by creating an attractive force between the substrate and the chuck. When a chucking voltage is applied to one or more electrodes in the ESC, charges of opposite polarity are induced in the substrate and the electrodes, respectively. In some embodiments, the electrodes may be referred to as "grids." Various designs may be used to enable clamping. In the case of a monopolar ESC with one electrode, the one electrode may have a voltage applied, and an opposite charge may be induced in the substrate, for example, using a plasma generated above the substrate.

[0022] In the case of a bipolar electrostatic chuck, the electrostatic chuck has a pair of coplanar chuck (or clamping) electrodes embedded in a pedestal structure, each connected to a terminal of a power supply or other system configured to apply a potential to the electrodes. Opposite charges interact with the substrate, particularly the bottom surface of the substrate, attracting the substrate to the electrostatic chuck, thereby clamping the substrate to the chuck. In some embodiments, the clamping electrodes are each "D-shaped," although other shapes may be used, such as interdigitated or concentric clamping electrodes. The electrodes may be positioned such that they underlie a wafer that is disposed on the substrate.

[0023] A block electrode (also known as an "outer electrode," "end electrode," or "averaging electrode") may also extend around the chuck electrode. The block electrode may have an annular portion 122 that surrounds the chuck electrode when viewed from above. The block electrode may average out anomalies associated with the positive and negative polarities of the chuck electrode and smooth the interaction of the chuck electrode with the wafer. The block electrode may also interact with the plasma above the wafer during wafer processing operations to improve process uniformity.

[0024] 1 shows a perspective view of an example of a bipolar electrostatic chuck having two clamping electrodes 106 and 107 surrounded by a block electrode 108. The block electrode 108 has an annular portion 122 (shown shaded) as well as two spokes 109a and 109b (the spokes generally run from a central region 105 to the annular portion, it being understood that a diametric strip could be the two spokes as shown in FIG. 1). The spokes may be connected to the central region 105, which may be electrically coupled to a power source, for example, by leads that run through a pedestal that supports the electrostatic chuck in which the electrodes are located.

[0025] ESCs may be manufactured by a sintering process. The electrodes and other elements in the base / ESC and electrical connectors (e.g., metal wiring) may be positioned in a powder, which may be sintered together by heating and / or pressing to form a base with each of the above components embedded. The powder may be a ceramic, such as alumina or alumina nitride, that forms a single piece during sintering. In some embodiments, the powder may be in a "green" state that may be easily machined. The ESC may be constructed by stacking the components / powder together and then firing the entire ESC to sinter the ceramic powder. Because the sintering process leads to expansion / contraction of the various elements of the base and thus movement of these elements (and possible defects due to such movement), aligning the components in fewer planes may simplify manufacturing. In this way, the clamping and blocking electrodes are generally in the same plane to reduce manufacturing costs. Furthermore, the connections to each component, such as electrical contacts to the electrodes, may be positioned along a vertical central axis to reduce manufacturing complexity.

[0026] In some implementations, the block electrode and / or clamp electrode may be a thin sheet of conductive material, such as metal, machined to have a shape as described herein. In some implementations, the electrode may have multiple components. In some implementations, the electrode may have slots or holes or be made of a mesh that allows particles to move through. This may reduce the risk of delamination after sintering, as the ceramic particles may sinter through the electrode rather than just around it. In some implementations, the electrode may be a metal mesh, such as a woven mesh with multiple metal strands that overlap and are electrically connected. Regardless of the specific details of the electrode material, the electrode may be machined into a shape as discussed herein.

[0027] In general, the block electrode may improve the uniformity of the processing operation performed on the substrate. The RF power supplied to the block electrode may control the region where the plasma is formed, particularly the radius of the plasma. Because the plasma process may have center-to-edge non-uniformities due to the plasma, the RF power supplied to the block and clamp electrodes may be adjusted to control the plasma and improve uniformity. However, the block electrode may also introduce some non-uniformity, particularly around the radial edge of the substrate, such as non-uniformity corresponding to the spokes 109a-b. Without being bound by theory, it is believed that the coupling between the block electrode and the wafer affects the processing operation by increasing the non-uniformity corresponding to the location of the central strip, as well as the variation in RF density between the spokes and annular portion of the block electrode.

[0028] FIG. 2 shows a graph of uniformity as a function of azimuthal position for measurements made near the outer edge of the wafer. There are two data sets for the two spoke model, one for the four spoke model, and one for the two spoke model where the inner diameter of the block electrode annulus is larger (resulting in a radially tapered annulus). The two spoke model line corresponds to the block and clamp electrode design shown in FIG. 1. As can be seen, there are large peaks at 0° and 180°, which correspond to where the spokes 109a-b join with the block electrode annulus in the data. Such thickness non-uniformity is undesirable. In some embodiments, such non-uniformity can be reduced by rotating the wafer between processing operations. For example, by rotating the wafer 90° midway through a processing operation, the non-uniformity can be reduced at 0° and 180° and increased at 90° and 270°, reducing the magnitude of the non-uniformity peak at any given radial location. Although it is desirable to reduce the peak non-uniformity, it is generally desirable to also reduce the average non-uniformity.

[0029] This disclosure describes various features that may be employed in the design of an ESC to reduce non-uniformity in processing operations, either in combination or alone. In one embodiment, FIG. 3 illustrates a side view of a process chamber 300. The process chamber may be used with systems or components used for various plasma processing techniques, such as plasma enhanced chemical vapor deposition, plasma etching, plasma stripping or ashing, sputtering, plasma spraying, and the like. The process chamber may include an electrostatic chuck (ESC) 302 (the ESC may also be referred to herein as a pedestal) that supports a substrate 320. The ESC 302 has a block electrode 308 and chuck electrodes 306 and 307. The block and chuck electrodes may have one or more electrical leads 316 that electrically connect the electrodes, directly or indirectly, to one or more power sources 332 that may provide DC and / or RF power to each electrode.

[0030] The ESC 302 may be configured to support a wafer 320, which may be fed into the process chamber 300. The wafer, which may also be referred to as a substrate or semiconductor substrate, may be a wafer of silicon or other semiconductors (e.g., a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer) and includes wafers having one or more layers of materials, such as dielectric, conductive, or semiconducting materials, deposited thereon. It is understood that the process chamber and ESC described herein are designed for 300 mm wafers. Appropriate modifications may be made to scale various elements for larger or smaller wafers (e.g., electrodes may be scaled to accommodate the diameter of the wafer being processed).

[0031] A ring 314 (e.g., an edge ring or an abatement ring) may also be disposed on the ESC 302. The ring 314 may be, for example, a ceramic ring that may protect the pedestal / ESC in the process chamber from damage by the plasma and / or aid in controlling the plasma. In some embodiments, the ring 314 is a replaceable component.

[0032] A showerhead 304 may be positioned above the ESC. During processing operations, process gases may be flowed through the showerhead toward the wafer. During operation, a plasma 310 is formed above the wafer 320. In some embodiments, the showerhead includes or is coupled to a plasma generation system (not shown) that may be used to generate the plasma. The showerhead 304 (or plasma generator system) and the ESC 302 (including clamping and blocking electrodes) may be electrically coupled to an RF power source 332 and a matching network 330 for powering the plasma. During operation, the RF power source 332 and the matching network 330 may be operated at any suitable power to form a plasma having a desired species composition. The plasma 310 has a plasma edge region 312 near the outer edge of the wafer 320.

[0033] A controller 311 is operatively coupled to the RF power supply 332 to control how the RF power supply 332 operates. The controller 311 may be an analog controller, a discrete logic controller, a programmable array controller (PAL), a programmable logic controller (PLC), a microprocessor, a computer, or any other device capable of performing operations to achieve a processing operation. In one exemplary embodiment, the controller determines the amount of power provided to each of the showerhead, the clamp electrode, and the block electrode, and provides commands to the RF power supply 332. In addition to controlling the RF power supply 332, the controller 311 may also be operatively coupled to a gas delivery system 377 and may provide commands to the gas delivery system 377 to deliver an amount of processing gas toward the wafer.

[0034] The gas distribution system 377 may be coupled to one or more gas sources and may include one or more corresponding valves or other flow control components (e.g., mass flow controllers and / or liquid flow controllers). The controller 311 may be connected to one or more valves or other flow control components and switch the state of the valves so that different gases or combinations of gases are flowed at different times and / or flow rates. In some embodiments, one or more gas sources may be fluidly connected to a mixing chamber to allow mixing and / or conditioning of process gases before being flowed over the wafer.

[0035] The RF power source 332 may be a radio frequency (RF) energy source or other energy source capable of powering and energizing the electrodes to form an electric field. In one exemplary embodiment, the RF power source 332 includes an RF generator configured to operate at a desired frequency. For example, the RF generator may be configured to operate within a frequency range of 0.2 MHz to 20.0 MHz. In one exemplary embodiment, the RF generator may operate at 13.56 MHz. In one exemplary embodiment, the RF power source 332 may include a matching network 330 disposed between the RF generator and one or more elements described herein (e.g., the plasma generator system or the ESC). The matching network may be an impedance matching network configured to match the impedance of the RF generator to the impedance of the electrodes connected to the RF generator. In this regard, the matching network may be comprised of a combination of components such as a phase angle detector and a control monitor. However, it will be appreciated that in other embodiments, the matching network may include other or additional components.

[0036] As discussed above, wafers may have non-uniformities resulting from processing operations. Different designs of the ESCs, particularly the clamping and blocking electrodes, may reduce such non-uniformities, particularly those corresponding to the clamping and / or blocking electrodes.

[0037] 4a and 4b show perspective and top views, respectively, of clamping electrodes 306 and 307 and block electrode 308 of one embodiment. As can be seen, block electrode 308 has four spokes 309. FIG. 4b shows a top view illustrating the overlap of the clamping electrode and the spokes of the block electrode. In some embodiments, increasing the number of spokes reduces the non-uniformity peaks at the wafer edge associated with the spokes. FIG. 5 shows a graph of uniformity as a function of azimuthal position along the wafer edge for 2-spoke, 4-spoke, and 10-spoke block electrodes. The 2-spoke block electrode has peaks at 0° and 180°, similar to those in FIG. 2. The 4-spoke block electrode shows non-uniformity peaks every 90°. Meanwhile, the 10-spoke block electrode shows several non-uniformity peaks at several multiples of approximately 36°. Importantly, the reduction in non-uniformity with the additional spokes is greater than simply averaging the two-peak non-uniformity of a two-spoke block electrode to four peaks. Instead, the use of additional spokes reduces the average non-uniformity as well as the local peak non-uniformity. Thus, increasing the number of spokes on a block electrode can result in significant improvements in uniformity in processing operations. In some embodiments, a block electrode may have at least 3, at least 4, at least 6, at least 10, at least 12, or about 16 spokes. In some embodiments, the number of spokes may be an even number. An even number of spokes may be preferred to maintain symmetry across the wafer. However, in some embodiments, the number of spokes may instead be an odd number.

[0038] In some embodiments, the clamping electrode may be semicircular, as shown in Figures 4a and 4b. In embodiments using a two-spoke block electrode, the two clamping electrodes and the block electrode may be coplanar, and the two spokes of the block electrode may pass through the gap between the clamping electrodes. However, in embodiments using two clamping electrodes and more than two spokes of the block electrode, there is not enough space to make the block and clamping electrodes coplanar without reducing the size of the clamping electrode to fit in the space between the spokes. Thus, in some embodiments, the block electrode may be positioned below the clamping electrode such that the clamping electrode is between the block electrode and the wafer. Figures 3 and 4a illustrate such relative positions of the block and clamping electrodes.

[0039] In some embodiments, the block electrode may be located below the clamp electrode, so that the block electrode may interact with other components of the ESC. For example, the block electrode may also capacitively couple with the heating element in the ESC. Typically, the heating element is positioned away from the clamp electrode to reduce any coupling effects. However, a low placement of the block electrode may cause the block electrode to electrically interact with the heating element, which may reduce the efficiency of the block electrode and cause non-uniformity in the processing operation. Therefore, it is desirable to move the block electrode away from the heating element, i.e., closer to the clamp electrode, to minimize any capacitive coupling with the heating element.

[0040] However, in some cases, positioning the block electrode below the clamp electrode may improve the ability of the block electrode to affect the plasma above the wafer. Since defects at the wafer edge are a major source of defects, potential defects and / or non-uniformity may be reduced by adjusting the plasma edge region 312 during or between processing operations, e.g., by varying the power supplied to the block electrode. If the block electrode is positioned vertically relatively closer to the top of the ESC than the clamp electrode, the stable process window for supplying power to the block and clamp electrodes may be centered at edge-weighted process values ​​such that the plasma density is higher near the wafer edge. In some embodiments, this may be undesirable due to limited tunability of the RF power, which affects the plasma properties. Thus, in some implementations, a lower positioned block electrode may shift the stable process window such that the center of the stable process window makes the plasma density more uniform from edge to center and allows more control over the plasma properties using RF power to the block and clamp electrodes.

[0041] Thus, in some embodiments, the block electrode may be a distance 318 below the clamp electrode (the block electrode and the clamp electrode are substantially parallel to each other and to the wafer). In some embodiments, the distance 318 is about 0.1 inches, or between about 0.05 inches and about 0.2 inches. These distances may balance the benefits of reduced capacitive coupling with other components of the ESC against greater control of the plasma through the block electrode. The distance 318 may also affect how the block electrode interacts with other components of the ESC. In addition to the above, a larger distance 318 may allow the block electrode to have more process space control over the plasma.

[0042] In some embodiments, the number of clamp electrodes may be based on the number of spokes. For example, if there are four spokes, there may be four clamp electrodes, each having a 90° arc shape to fit into the space between the spokes and the annulus of the block electrode. In such embodiments, the clamp electrodes and the block electrodes may be in the same plane, or the block electrodes may be below the clamp electrodes. Additionally, while the drawings show two clamp electrodes, it should be understood that there may be only one clamp electrode (e.g., if the block electrode is positioned at a lower height than the clamp electrodes), or there may be multiple clamp electrodes (e.g., two or more). In some embodiments, the clamp electrodes may be interdigitated (FIG. 6c shows an example of interdigitated electrodes having two interdigitated electrodes 606 and 607). In some embodiments, the clamp electrodes may have various configurations, such as a single clamp electrode, interdigitated electrodes, etc.

[0043] In some embodiments, the clamp electrodes and the block electrodes may be configured to reduce or minimize overlap between the block electrodes and the clamp electrodes. Overlap is generally undesirable because the clamp electrodes and the block electrodes may electrically couple to reduce polarization between the wafer and the clamp electrodes, affecting processing operations. Thus, in some embodiments, all gaps between the clamp electrodes may be horizontally aligned with one or more spokes of the block electrodes to reduce overlap, for example as shown in FIG. 1 . In other embodiments, it may be desirable to offset all gaps between the clamp electrodes from the spokes. For example, offsetting all gaps from the spokes may improve symmetry of coupling between the block electrodes and the clamp electrodes. As discussed further herein, a wafer processed on an ESC as described herein may be rotated such that any non-uniformity due to coupling between the block electrodes and the clamp electrodes is minimized. Offsetting the spokes and all gaps between the clamp electrodes may encourage each spoke to produce similar non-uniformity. In this manner, when the wafer is rotated on an ESC, the non-uniformity due to each spoke may be azimuthally distributed in a similar manner across the substrate.

[0044] The block electrode has an outer diameter 340 and an inner diameter 342. The inner diameter refers to the inner diameter of the annular portion of the block electrode (e.g., excluding the spokes). In some embodiments, the inner diameter is up to about the same as the diameter of the wafer being processed using the block electrode (e.g., about 300 mm or less, or about 11.8 inches or less). In some embodiments, the inner diameter is less than about 300 mm. In some embodiments, the outer diameter is at least the diameter of the wafer. In some embodiments, the outer diameter is about 13.3 inches ± 0.1 inches. In some embodiments, the inner diameter is about 11.3 inches ± 0.1 inches. In some embodiments, the inner diameter is about 11.8 inches ± 0.1 inches. In some embodiments, increasing the inner diameter of the annular portion may reduce coupling between the block electrode and the wafer and reduce non-uniformity at the edge of the wafer.

[0045] 6a and 6b show block electrodes 608a and 608b with 8 and 10 spokes, respectively. In general, additional spokes reduce non-uniformity. However, in some embodiments, the number of spokes may be limited by other components of the ESC. For example, the pedestal may have lift pins that support the wafer for a wafer handling robot to place or remove the wafer on the pedestal. Because the lift pins or related components must penetrate the plane of the block electrode, additional spokes may significantly affect pin clearance (or may require a large number of spokes to be arranged asymmetrically to resolve such features, which may increase wafer non-uniformity). Thus, in some embodiments, the number of spokes may be limited based on the location of the lift pins such that the lift pins do not intersect with the spokes of the block electrode, allowing the spokes to be generally radially symmetric. In some embodiments, there are 12 or fewer spokes, 10 or fewer spokes, or 8 or fewer spokes. In some embodiments, the spokes are evenly spaced azimuthally.

[0046] In some embodiments, the number of spokes may be determined based on the frequency of the RF power used in the electrode. For example, the design of the electrode may cause interactions with harmonics of the RF power, which may affect processing operations and are generally undesirable. Thus, in some implementations, for grids designed for use with RF frequencies, the arc length of the annulus between the spokes may be less than about one-quarter of the guided wavelength of the highest harmonic of the RF driving frequency, thereby reducing radiation of harmonic frequencies. For example, for grids used in systems using 13.56 MHz RF power, the arc length may be less than about 18 cm.

[0047] The geometry of the annulus-spoke junction can affect the non-uniformity of the process operation. Without being bound by theory, the RF density can vary between where the spokes connect to the annulus and the annulus furthest from all of the spokes. Rounding the interior corners between the spokes and the annulus can reduce the variation in RF density along the annulus, thereby reducing the non-uniformity at the wafer edge. In some embodiments, the interior corners formed where each spoke joins the annulus may be rounded or filleted. FIG. 7 illustrates one junction between a spoke 709 of a block electrode 708 and an annulus 722 having a rounded corner 748. The dotted lines indicate corners that are not rounded. In some embodiments, each corner may have a radius 750. In some embodiments, the radius is at least about 0.08 inches, or between about 0.08 inches and about 1 inch.

[0048] In some embodiments, the clamping electrode, as shown by electrode 706, may be similarly rounded where it abuts above the rounded corners of the block electrode. As discussed herein, the block electrode may electromagnetically couple to the horizontally overlapping chuck electrode, weakening the electromagnetic coupling between the clamping electrode and the wafer. This is undesirable and potentially wasteful. Thus, in some embodiments, the shape of the clamping electrode may conform to the filleted corners between the spokes and annulus of the block, thereby reducing the overlap between the clamping electrode and the block electrode.

[0049] In some embodiments, the variation in RF density may also be reduced by increasing the thickness of the spokes in a direction perpendicular to the radius along which the spokes extend. FIG. 8 shows a diagram of a block electrode 808 having eight spokes 809 connected to a central region 805. The widths 862 of each spoke may be added together to determine a ratio of total spoke width to circumference, where the circumference is the circumference of a circle of the same radius as the inner end of the annulus. In some embodiments, the ratio of total spoke width to circumference is at least about 1:100 or at least about 1:10. For example, if the total inner circumference of the block electrode is about 35.5 inches (based on an inner diameter of 11.3 inches), then the total width of the spokes may be at least about 3.5 inches. In some embodiments, the width of each spoke may be between about 0.1 inches and about 0.5 inches.

[0050] As noted above, in some embodiments, rotating the wafer relative to the spokes of the block electrode (or relative to the spokes of multiple block electrodes) between processing operations may reduce non-uniformity. In embodiments herein, such peak non-uniformity may be reduced without rotation. In some implementations, in addition to rotating between processing operations, embodiments herein may be used to further reduce peak non-uniformity. In some embodiments, the wafer may be rotated between processing operations. Such rotation may be performed, for example, by an indexer or other wafer handling system. The indexer or other wafer handling system is configured such that the wafer can be rotated relative to a given pedestal and then lowered back onto the given pedestal at a new rotated position relative to the pedestal.

[0051] FIG. 9 illustrates an example of a multi-station chamber with an exemplary rotary indexer system. In FIG. 9, a semiconductor processing tool 900 is shown including a chamber 902 having four wafer processing stations 906 (A-D) therein, each having a corresponding pedestal 908 (A-D) configured to support a corresponding wafer 944 (A-D). Each pedestal 908 may be an ESC according to various embodiments herein. The chamber 902 may have one or more wafer transfer ports 904 that may be provided to allow wafers 944 to be placed on or removed from some of the pedestals 908, such as by a wafer handling robot located outside the chamber 902.

[0052] The semiconductor processing tool 900 may also include a rotary indexer 903 having a number of indexer arms 928 having a proximal end fixedly connected to a central hub 924 configured to rotate about a first axis 938 (which will be understood to be perpendicular to the page with respect to FIG. 9 ) and a distal end provided with a corresponding rotatable wafer support 934. Each rotatable wafer support 934 may have a number of features, such as, for example, contact pads 936, designed to stably support one of the wafers 944 from below during an indexing operation.

[0053] The indexer 903 also includes a second hub 926 that is independently drivable relative to the central hub 924. The second hub 926 may be connected, for example, to a number of tie rods 930, each connected at an opposite end to a corresponding one of the rotatable wafer supports 934, such that as the central hub 924 and the second hub 926 rotate relative to one another, the rotatable wafer supports 934 undergo similar relative rotation. Rotating both the central hub 924 and the second hub 926 in the same direction at the same speed will rotate the indexer arm 928 in unison without rotating the rotatable wafer support 934 relative to the indexer arm 928.

[0054] The pedestals 908 of the semiconductor processing tool 900 may also include a number of lift pins 912 at each wafer processing station 906. The plurality of lift pins 912 may extend or retract relative to a corresponding pedestal 908, thereby lifting or lowering a wafer 944, which may be on the corresponding pedestal 908, from and onto the pedestal 908 below.

[0055] FIG. 10 shows a cross-sectional view of the multi-station chamber of FIG. 9 at a diagonal. In FIG. 10, it can be seen that the lift pins 912 may extend through the pedestal (e.g., through holes in the pedestal) and may be connected to a lift pin ring 914 that allows the lift pins 912 to move up and down relative to and in conjunction with the pedestal in response to movement of a lift pin actuator 916. The lift pins 912 may have a top surface that is typically intended to contact the underside of the wafer 944 and support the wafer 944 from below. The lift pins 912 may typically be movable such that their top surfaces can transition between positions above and below the top surface of the pedestal 908. Other lift pin mechanisms may also be used, such as independently actuated lift pins at each wafer processing station. The lift pins 912 may operate to lift a wafer 944 on top of one of the pedestals 908 away from the pedestal 908 so that a gap exists between the pedestal 908 and the wafer 944 large enough to allow the indexer arm 928 and the rotatable wafer support 934 to pass between the wafer 944 and the pedestal 908. The wafer 944 may rest on contact pads 936 when lowered onto the rotatable wafer support 934, which may support the wafer 944 with relatively minimal contact between the wafer 944 and the rotatable wafer support 934.

[0056] The rotary indexer 903 may have an indexer drive assembly 918 that may include a motor that may be controlled to rotate the central hub 924 and the second hub 926 (in tandem) and thereby rotate the indexer arm 928 and the rotatable wafer support 934 about a first axis 938, or (by rotating the second hub 926 relative to the central hub 924) to rotate the rotatable wafer support 934 about its respective center of rotation 940 relative to the indexer arm 928. In some implementations, the indexer drive assembly 918 may also be attached to a lift actuator 920, in which case a bellows seal 922 may be provided to seal an opening in the chamber 902 through which the central shaft of the rotary indexer 903 may pass. This allows the indexer arm 928 to move up and down as a unit.

[0057] In use, the wafers 944 may be lifted by the lift pins 912 to a raised position while the rotary indexer 903 is positioned such that the indexer arms 928 are sandwiched between different sets of adjacent pedestals 908. Once the wafers 944 are in the raised position, the rotary indexer 903 may be actuated to swing the rotatable wafer supports 934 into position beneath each wafer 944. When all of the rotatable wafer supports 934 are positioned beneath a corresponding wafer 944, the lift pins 912 may be retracted to lower the wafer 944 until it rests on the rotatable wafer supports 934 positioned beneath the wafer 944. The lift pins 912 may be retracted until they no longer extend into the indexer's rotational path, thereby causing the rotary indexer 903 to rotate about the first axis 938 and transport the wafers 944 along an arcuate path from one wafer processing station 906 to another wafer processing station 906. After the rotary indexer 903 has been actuated to move the wafer 944 between different wafer processing stations 906, the lift pins 912 may again be extended to lift the wafer 944 off the rotatable wafer support 934. Once the wafer 944 is no longer supported by the rotatable wafer support 934, the rotary indexer 903 may again be actuated to rotate the indexer arm 928 so that the rotatable wafer support 934 is no longer under the wafer 944. Once the rotatable wafer support 934 is no longer under the wafer 944, the lift pins 912 may again be actuated to retract into the pedestal 908 to lower the wafer 944 onto the pedestal 908.

[0058] Alternatively, the indexer arm 928 may be kept fixed and the second hub 926 may be rotated relative to the central hub 924 such that the rotatable wafer support 934 (on which the wafer is supported) is rotated relative to the indexer arm 928, and thus relative to the pedestal 908. The rotated wafer may then be placed back on the same pedestal from which it was lifted, but at a different rotational position relative to those pedestals. In some examples, wafers may be moved between stations and rotated to have different relative rotational positions with respect to similar features (e.g., electrodes) of each pedestal on which each wafer is placed.

[0059] Further discussion of rotational indexers capable of rotating wafers in place can be found in U.S. patent application Ser. No. 15 / 867,599, entitled "ROTATIONAL INDEXERS WITH ADDITIONAL ROTATIONAL AXES," which is incorporated herein for all purposes.

[0060] In some embodiments, the indexer of FIG. 9 may be configured to rotate the rotatable wafer support 934 based on the configuration of spokes of the blocking electrodes of the ESCs that are part of the wafer processing station. For example, the wafers may be lifted by lift pins from a pedestal and then placed on a rotating indexer as described above. The wafers may then be rotated some amount in place before being lifted again from the indexer by lift pins and then placed back on the pedestal from which they were obtained. In some embodiments, the amount of rotation during each such rotational movement may be based on the angle between the spokes of the blocking electrodes. Thus, any peaks in non-uniformity during a processing operation that correspond to the spokes may be reduced by changing the position of the spokes relative to the wafer being processed, i.e., the position of the non-uniformity on the wafer. In some embodiments, the processor may rotate the rotatable wafer support 934 by an amount such that a location on the wafer that was centered on the radial centerline of the spokes before the rotation is rotationally offset from that radial centerline relative to the center of the blocking electrode after the rotation. In some embodiments, the rotation offset for each rotation may be 360° / N / (x+1), where N=the number of spokes, and x=the number of times the wafer is rotated. Thus, if the block electrode has four spokes and the wafer is rotated twice (i.e., in a first rotation position, a second rotation position, and a third rotation position), the wafer will be rotated 30° each time it is rotated. Thus, the wafer is processed three times, with the spokes at 0 / 90 / 180 / 270, 30 / 120 / 210 / 300, and 60 / 150 / 240 / 330 relative to the pedestal during each processing operation. In some embodiments, wafer rotation may occur during transfer between stations (i.e., the wafer may be rotated by different amounts relative to different electrodes in different pedestals, similar to what may occur, for example, if the wafer remains on the same pedestal). In other embodiments, as noted above, the wafer may be rotated without being transferred between stations, or may remain on a single station but be rotated relative to the station for subsequent processing operations.

[0061] As mentioned above, in some implementations, the controller 311 is part of a system, which may be part of the above examples, including the rotary indexer of FIGS. 9 and 10. Such systems may include semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling the operation of the system before, during, and after processing of the semiconductor wafer or substrate. This electronics may be referred to as a "controller" that may control various parts or subparts of one or more systems. Depending on the processing requirements and / or type of system, the controller 311 may be programmed to control any of the processes disclosed herein, such as delivery of process gases in some systems, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid supply settings, position and motion settings, transfer of wafers in and out of tools and other transfer tools and / or load locks that connect or interface with the particular system.

[0062] Broadly speaking, a controller may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that, for example, receive instructions, issue instructions, control operations, enable cleaning operations, enable end-point metrology, and the like. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute the program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more process steps during the processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0063] The controller may be part of or coupled to a computer that is integrated, coupled, or otherwise networked to the system, or a combination thereof, in some implementations. For example, the controller may be all or part of a host computer system in the "cloud" or in a fab that allows remote access to wafer processing. The computer may provide remote access to the system to monitor the current progress of processing operations, review the history of past processing operations, and review trends or performance metrics from multiple processing operations to modify parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network that may include a local network or the Internet. The remote computer may include a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that defines parameters for each processing step that is performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed or the type of tool that the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, such as by including one or more separate controllers networked together and working toward a common purpose, such as the process and control described herein. An example of a controller distributed for such a purpose includes one or more integrated circuits on the chamber that are combined to control a process on the chamber and communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer).

[0064] Without being limited thereto, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the processing and / or production of semiconductor wafers.

[0065] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool parts, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or one or more of the tools used in material transport to bring containers of wafers into and out of tool locations and / or load ports within a semiconductor manufacturing factory. summary

[0066] A system and method have been provided that provides improved plasma generation capabilities over conventional systems. The plasma generator system reduces downtime between plasma generation processes compared to conventional systems, and does so while reducing exposure of surrounding system components to high power. As a result, the improved plasma generator system includes components such as RF components, gas flow distributors, and tubes that have improved service life compared to conventional plasma generator system components. Additionally, system maintenance costs are reduced.

[0067] When phrases such as "for each <item> of one or more <items>," "each <item> of one or more <items>," and the like are used herein, they should be understood to include both a group of single items and a group of multiple items. That is, the phrase "each" is used in the sense that the phrase is used in programming languages ​​to refer to each item, whatever the population of items being referenced. For example, if the population of items being referenced is a single item, then the term "each" refers only to that single item and does not imply that there must be at least two of these items (despite the fact that, according to dictionary definitions, the term "each" is often defined to mean "one of two or more"). Similarly, the term "set" or "subset" should not, in and of itself, be considered to necessarily encompass multiple items, and it will be understood that a set or subset can encompass only one member or multiple members (unless the context suggests otherwise).

[0068] Also, in this disclosure and claims, when there are ordinal markers, e.g., (a), (b), (c)..., it should be understood that their use is not intended to convey any particular order or sequence, except to the extent such order or sequence is expressly stated. For example, when there are three steps labeled (i), (ii), and (iii), it should be understood that these steps may be performed in any order (or simultaneously, unless otherwise contraindicated) unless otherwise indicated. For example, when step (ii) involves processing an element produced in step (i), step (ii) may be considered to occur at some point after step (i). Similarly, when step (i) involves processing an element produced in step (ii), it should be understood that the reverse is true. Also, the use of ordinal markers such as "first" herein, e.g., "first item," should not be read as suggesting, implicitly or inherently, that a "second" instance, e.g., "second item," is required.

[0069] The term "between," when used herein in conjunction with a range of values, should be understood to include the beginning and ending values ​​of the range, unless otherwise indicated. For example, between 1 and 5 should be understood to include the numbers 1, 2, 3, 4, and 5 as well as the numbers 2, 3, and 4.

[0070] Various modifications of the implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit and scope of the disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure and the principles and novel features disclosed herein.

[0071] Certain features described herein in the context of separate implementations can also be combined and implemented in a single implementation. Conversely, various features described in the context of one implementation can also be implemented separately in multiple implementations or in any suitable subcombination. Furthermore, even if features are described above as working in a particular combination and are initially claimed as such, in some cases one or more features may be deleted from the claimed combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0072] Similarly, even if the figures show operations in a particular order, it should not be understood that the operations need to be performed in the particular order or sequence shown, or that all of the operations shown be performed, to achieve desirable results. Additionally, the figures may show one or more exemplary processes in the form of flow diagrams. However, other operations not shown may be included in the exemplary processes shown in the schematic form. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the operations shown. In certain circumstances, multitasking or parallel processing may be advantageous. Additionally, the distinctions between the various system components in the above implementations should not be understood as requiring such distinctions in all implementations, and it should be understood that the described program components and systems may generally be integrated into or packaged in a single software product. Additionally, the following claims include other implementations. In some instances, the operations recited in the claims may be performed in a different order and still achieve desirable results.

Claims

1. 1. An apparatus including an electrostatic chuck (ESC) for supporting a semiconductor substrate, the ESC comprising: a top surface for supporting a wafer; one or more clamping electrodes beneath the top surface, the one or more clamping electrodes being configured, when powered, to electrostatically clamp the wafer to the top surface; A block electrode, An annular portion; The center and three or more spokes, each spoke having a distal end coupled to the annular portion and a proximal end coupled to the central portion; a block electrode, the annulus surrounding the one or more clamp electrodes when viewed along an axis perpendicular to the top surface; An apparatus comprising:

2. 10. The apparatus of claim 1, wherein the one or more clamp electrodes are configured to be powered by an RF source.

3. 10. The apparatus of claim 1, wherein the distance between a top surface of the block electrode and a bottom surface of the one or more clamp electrodes is between about 0.05 to about 0.2 inches.

4. 2. The device of claim 1, wherein an interior angle formed where each of the three or more spokes joins the annular portion is rounded.

5. 10. The device of claim 1, wherein the three or more spokes are arranged in a radially symmetric pattern.

6. 2. The apparatus of claim 1 , wherein there are 2·n spokes, where n is an integer greater than 1.

7. 2. The apparatus of claim 1, wherein the three or more spokes is ten spokes.

8. The apparatus of claim 1 , wherein the one or more clamp electrodes are two clamp electrodes.

9. 9. The apparatus of claim 8, wherein the two clamping electrodes are configured to operate with positive and negative polarities, respectively, when powered by a radio frequency (RF) source.

10. 9. The apparatus of claim 8, wherein the two clamp electrodes are nominally semicircular electrodes.

11. An apparatus according to any preceding claim, wherein the one or more clamp electrodes are planar.

12. 11. The apparatus of claim 1, wherein the block electrode is planar.

13. The apparatus of any one of claims 1 to 10, wherein the block electrode comprises a metal mesh.

14. 11. The apparatus of claim 1, wherein the block electrode comprises a single piece of metal.

15. 11. The apparatus of claim 1, further comprising an RF power source, the number of spokes of the block electrode being based on a frequency of the RF power source.

16. 11. An apparatus according to any preceding claim, wherein the one or more clamp electrodes are parallel to the block electrode and lie between the block electrode and the top surface.

17. 11. The apparatus of any one of claims 1 to 10, wherein the one or more clamp electrodes are at least two clamp electrodes, and at least one of the three or more spokes is aligned with a gap between the one or more clamp electrodes when viewed along the first axis.

18. 11. The device of any one of claims 1 to 10, wherein each spoke has a width measured in a direction perpendicular to the first axis and the proximal and distal ends of each spoke, and wherein a ratio of the total width of all spokes to an inner circumference of the annular portion is greater than about 1:

10.

19. The apparatus of any one of claims 1 to 10, further comprising a lift pin that does not intersect the three or more spokes.

20. The apparatus of any one of claims 1 to 10, further comprising a process chamber containing the ESC.

21. The apparatus of any one of claims 1 to 10, further comprising a rotary indexer.

22. 22. The apparatus of claim 21, the rotary indexer includes a central hub and indexer arms, the central hub rotatable relative to the chamber about a first axis nominally located at the center of the circular pattern, each indexer arm having a proximal end fixedly attached to the central hub and a distal end supporting a rotatable wafer support configured to rotate relative to the indexer arm about a corresponding second axis; The apparatus further comprises a controller including one or more processors and one or more memories; the one or more processors, the one or more memories, the ESC, the indexer, and the process chamber are operatively connected to each other; the one or more memory devices; placing a wafer positioned on the ESC onto the rotatable wafer support; rotating the rotatable wafer support and the wafer supported thereon about the corresponding second axis by an amount based at least in part on an angle between two adjacent spokes of the three or more spokes of the block electrode; Reposition the wafer on the ESC. A device storing computer-executable instructions for controlling said one or more processors.

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