Method and semiconductor module

Abstract

In one embodiment, the method is for producing a semiconductor module (1), the method comprising: - providing a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); providing a bottom metal disk (3); - pressing the semiconductor component (2) onto a bottom metal disk (3) with a preconfigured non-uniform pressure profile (P); Including, - a bottom main surface (23) facing the bottom metal disc (3); When viewed from above on the bottom main surface (23), the pressure profile (P) has a minimum value (N1) in a central region (C) of the semiconductor component (2) that is surrounded by a circumferential maximum value (M) of the pressure profile (P), which in turn is surrounded by a circumferential minimum value (N2) of the pressure profile (P).

Description

[Technical field]

[0001] A method for producing a semiconductor module is provided. A semiconductor module produced by such a method is also provided. [Background technology]

[0002] WO 2020 / 078816 discloses a semiconductor module. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved is to provide a semiconductor module with improved reliability. [Means for solving the problem]

[0004] This object is achieved, inter alia, by a method and a semiconductor module as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, in a semiconductor module, a semiconductor component is pressed onto a bottom metal disk by a pressure profile having a circumferential maximum along the radial direction that is between a local minimum in a central region and a circumferential minimum of the pressure profile. Such a pressure profile, also referred to as a pressure distribution, can result in improved contact between the semiconductor component and the bottom metal disk, and thus enhanced cooling and / or higher current can be achieved.

[0006] In at least one embodiment, the method of manufacture comprises: providing a semiconductor component configured for a voltage of at least 0.6 kV and having a bottom major surface and an opposing top major surface; providing a bottom metal disk; and then - pressing the semiconductor components onto the bottom metal disk with an intentionally non-uniform pressure profile or creating said pressure profile between the semiconductor components against the bottom metal disk; Thus, a pressure profile can be predefined, for example, where the top major surface faces the top metal disk, the semiconductor component is located directly between the bottom metal disk and the top major surface, and the method further includes forming a clip body that is parallel to the bottom major surface and laterally surrounds the semiconductor component partially covering the top major surface, the clip body is in direct contact with the bottom metal disk, the clip body is made of plastic, the clip body and the top metal disk press the semiconductor component onto the bottom metal disk, and the pressure profile is present in the completed semiconductor module when it is being operated.

[0007] A semiconductor module is further provided. The above-described method can produce a semiconductor module as described below in relation to at least one of the following embodiments. Thus, features of the semiconductor module are also disclosed for the method and vice versa.

[0008] In at least one embodiment, a semiconductor module comprises one or more semiconductor components configured for a voltage of at least 0.6 kV having a bottom major surface and an opposite top major surface, and a bottom metal disk against which the semiconductor components are pressed with a pressure profile, the bottom major surface facing the bottom metal disk. For example, when viewed from a top view of the bottom major surface, the pressure profile has a local minimum in a central region of the semiconductor component surrounded by a circumferential maximum of the pressure profile, the circumferential maximum being surrounded by the circumferential minimum of the pressure profile. Preferably, the pressure of the local minimum in the central region is lower than the pressure of the circumferential maximum of the pressure profile, although it is also possible that the same pressure is present at the circumferential maximum and the local minimum.

[0009] For example, a fast recovery diode (FRD) is provided in which the wafer attachment is optimized to enhance electrical performance.

[0010] The at least one semiconductor component is, for example, a wafer. The semiconductor component can also be an injection enhanced gate transistor (IEGT), an integrated gate-commutated thyristor (IGCT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a gate turn-off thyristor (GTO), a gate commutated thyristor (GCT), a junction gate field-effect transistor (JFET), a phase controlled thyristor (PCT), or a diode. For example, the semiconductor component is made of silicon Si. However, the semiconductor components may alternatively be based on wide band gap semiconductor materials such as SiC, Ga2O3 or GaN.

[0011] For example, the semiconductor component is a power device, which means, for example, that the semiconductor component is configured for a maximum voltage of at least 0.6 kV, or at least 1.2 kV, or at least 2.8 kV. Alternatively or additionally, the semiconductor component can be configured for a maximum current of at least 10 A, or at least 0.1 kA, or at least 1 kA.

[0012] The semiconductor module is, for example, a power module for converting direct current from a battery into alternating current for an electric motor in a vehicle such as a hybrid vehicle or a plug-in electric vehicle, or in a railway such as a commuter train.

[0013] When multiple semiconductor components are present in a semiconductor module, all of the semiconductor components can be of the same type and may be electrically connected in series, or different types of semiconductor components can be combined with each other.

[0014] Thus, the semiconductor module can be an FRD with a novel design of attachment of the semiconductor components, for example silicon wafers, to the bottom metal disk, for example molybdenum disk, and a strain buffer is introduced. The semiconductor components are attached to the bottom metal disk in such a way that they control the pressure distribution, resulting in a three-dimensional curvature of the wafer. One option is to attach the semiconductor components to the bottom metal disk by a clip body, for example a molded ring instead of silicone rubber (SR), which serves to insulate and at the same time increase the striking distance. A second option is the attachment of the semiconductor components to the bottom metal disk by a low temperature bonding (LTB) process, where the bonding line is structured in two dimensions. Further options are also possible to achieve the desired pressure profile. Both options increase the reverse bias safety operating area (RBSOA), which is demonstrated by an increase in the durability at frequency operation in power converters with IGCTs.

[0015] Components such as FRDs are unavoidable for the operation of power converters with diode-less IGBT modules, IEGTs or IGCTs. The demands on the continuously increasing current carrying capacity of power converters lead to an increase in the area of ​​the individual FRDs. For example, in the 4.5 kV class, we can find individual FRDs with a diameter of a silicon wafer ranging from 30 mm to 120 mm. When the device area exceeds 1 cm2 chip, it becomes more difficult for the FRD to go through without failure high on-state currents in the kA range and fast reverse recovery processes from direct current (DC) link voltages of 2.8 kV and above, i.e. 4.5 kV class.

[0016] The fault current depends primarily on the design of the FRD. A proper doping profile on the anode semiconductor side can minimize dynamic avalanches leading to current filaments caused by entering the negative differential resistance (NDR) operating region and subsequent failure by melting a hole through the semiconductor component. The fault current is determined by the thermal resistance R of the junction to the case. th j-c The LTB process also depends on this R th j-c It is known to reduce noise and provide higher ratings.

[0017] Typically, the semiconductor component is bonded to the bottom metal disk on one side. As a result, there is a bond line between the semiconductor component and the bottom metal disk, about 10 μm to 50 μm thick, made of silver or copper, which conducts well thermally and electrically. This results in a much lower R than the free floating (FF) packaging option, where an unbonded silicon wafer is pressed directly between two molybdenum disks, forming a so-called dry contact. th j-c is obtained.

[0018] According to at least one embodiment, the bottom metal disk is made of one or more metals. For example, the bottom metal disk is a disk made of molybdenum or a molybdenum alloy. "Disk" can mean that the thickness of each component is at most 10% of the diameter or average diameter of the above components. The average diameter means twice the average radius obtained by dividing the area content of each component by π and then dividing by the square root of the result.

[0019] According to at least one embodiment, the bottom metal disk has a radius r0, and the position of the circumferential maximum value M of the pressure profile P is between 0.5r0 and 0.9r0. In this case, the bottom metal disk and / or the semiconductor component can be rotationally symmetric, i.e., circular, when viewed from above. Therefore, for the radius r of the bottom metal disk, 0 ≦ r ≦ r0 applies. In the case of a non-rotationally symmetric shape, the zero position can be located at the center of gravity, and r can extend from 0 to the maximum distance of the center of gravity from the edge of the bottom metal disk.

[0020] According to at least one embodiment, the radius rS of the semiconductor component is between 0.8r0 and r0, or between 0.9r0 and r0, or between 0.92r0 and 0.99r0. That is, the semiconductor component can be slightly smaller than the bottom metal disk or can have the same size as the bottom metal disk.

[0021] According to at least one embodiment, for the minimum pressure pN1, the circumferential maximum pressure pM, and the circumferential minimum pressure pN2 in the central region, 0 ≦ pN2 ≦ 0.5pM ≦ pN1 < pM or 0.1pM ≦ pN2 ≦ 0.4pM ≦ pN1 ≦ 0.9pM or 0.1pM ≦ pN2 ≦ 0.6pM ≦ pN1 ≦ 0.9pM applies. Further, pN2 < pN1, for example, pN1 - pN2 ≧ 0.1pM or pN1 - pN2 ≧ 0.2pM can apply.

[0022] According to at least one embodiment, when viewed in a cross-section passing through the minimum value and the semiconductor component, the pressure profile P is P(r) = A / (1 + Br 2 + Cr4 +Dr 6 +Er 8 ) can be approximated as +F, where r is a dimensionless variable representing the distance to the minimum and / or center of the bottom metal disk and / or semiconductor component. For example, at least one of A / pM and C, D, E, and F / pM is a positive number. B is a negative number.

[0023] According to at least one embodiment, P(r)=A / (1 + Br 2 +Cr 4 +Dr 6 +Er 8 ) + F is true from -rS to rS, that is, r is between {rS} and {rS}, where {} indicates the numerical value of the quantity value with a tolerance of up to 0.1 pM or up to 0.05 pM or up to 0.02 pM. For example, 0.25 pM ≤ A ≤ pM and -2 ≤ B ≤ -0.5 and 0 ≤ C ≤ 2 and 0 ≤ D ≤ 6 and 0 ≤ E ≤ 10 and 0 ≤ F ≤ 0.3 pM. Alternatively, 0.1 pM ≤ A ≤ pM and -6 ≤ B ≤ -0.1 and 0 ≤ C ≤ 10 and 0 ≤ D ≤ 25 and 0 ≤ E ≤ 30 and 0 ≤ F ≤ 0.6 pM. The term "tolerance of ~" means "±", that is, for example, "tolerance of up to 0.1 pM" means ±0.1 pM.

[0024] According to at least one embodiment, pN1 < pM. Alternatively, pN1 = pM applies. According to at least one embodiment, the semiconductor module further comprises one or more clip bodies. At least one clip body can completely or partially surround the semiconductor component in a lateral direction parallel to the bottom main surface. Further, at least one clip body partially covers the upper main surface.

[0025] According to at least one embodiment, the clip body is in direct contact with the bottom metal disk and / or the semiconductor component. For example, the side of the semiconductor component is completely and directly covered by the clip body. The side of the bottom metal disk may be completely or partially directly covered by the clip body. Also, the top surface of the bottom metal disk may be partially and directly covered by the clip body.

[0026] According to at least one embodiment, the clip body is made from at least one plastic, which may, for example, include one or more additives to adjust the thermal and / or mechanical properties of the plastic, for example, the plastic is an epoxide.

[0027] According to at least one embodiment, the clip body is electrically insulating: during operation of the semiconductor module, no current is intended to be conducted through the clip body, and the clip body may provide electrical insulation between the pole pieces and / or the metal disk.

[0028] According to at least one embodiment, the clip body is configured to press the semiconductor component onto the bottom metal disk. This can be achieved, for example, by the geometry of the clip body. For example, if the semiconductor component is curved relative to the bottom metal disk, the portion of the clip body on the lateral surface of the semiconductor component can be stressed, so that the portion of the clip body above the top major surface can press the semiconductor component in a direction toward the bottom metal disk.

[0029] According to at least one embodiment, when viewed in a top view of the bottom major surface, a circumferential maximum of the pressure profile is located within an opening in the clip body such that the circumferential maximum is not covered by the clip body as might otherwise be the case.

[0030] According to at least one embodiment, at least partially between the semiconductor component and the bottom metal disk there is at least one free-floating region in which the semiconductor component is floating freely with respect to the bottom metal disk. In other words, in the respective region there is a so-called dry contact. Thus, in said region the semiconductor component may be in direct contact with the bottom metal disk and / or no condensed matter components are present between the bottom metal disk and the semiconductor component in said region.

[0031] According to at least one embodiment, the semiconductor module further comprises at least one bond material located at least partially between the semiconductor component and the bottom metal disk. In the at least one connection region, the semiconductor component is fixedly connected to the bottom metal disk by the at least one bond material. "Fixedly connected" may mean that in the intended application, the semiconductor component cannot move relative to the bottom metal disk in the at least one connection region.

[0032] According to at least one embodiment, there is both at least one free-floating region and at least one connected region, so that the relative movement of the bottom metal disk with respect to the semiconductor component is only partially constrained.

[0033] According to at least one embodiment, the at least one bond material is present in both the at least one free-floating region and the at least one connected region, e.g., the at least one bond material has a constant thickness across the bottom major surface.

[0034] According to at least one embodiment, the thickness of the at least one bond material is at least 10 μm and / or at most 100 μm. Thus, the at least one bond material can be relatively thick.

[0035] According to at least one embodiment, the at least one connection region is located at at least one of a circumferential maximum and a circumferential minimum of the pressure profile.Alternatively or additionally, the central region does not include a connection region.

[0036] According to at least one embodiment, the at least one bond material is selected from the following group: solder paste, silver paste, silver sheet, sintered body. For example, the at least one bond material comprises or consists of one or more of the following metals: Ag, Al, Bi, Cu, In, Mo, Ni, Pb, Sb, Ti, W. For example, the bond material consists of silver or a silver alloy.

[0037] According to at least one embodiment, the semiconductor module further comprises an upper metal disk arranged on the upper main surface. The diameter of the upper metal disk is smaller than the diameter of the semiconductor component. When viewed in a top view of the upper main surface, the circumferential maximum of the pressure profile is covered by the upper metal disk, or alternatively, the circumferential maximum is located outside the upper metal disk. The upper metal disk may be a molybdenum disk.

[0038] According to at least one embodiment, at least one of the bottom metal disk and the top metal disk, when present, includes a curvature configured to provide a pressure profile such that at least one of the metal disks intentionally does not have a flat surface facing an assigned semiconductor component.

[0039] According to at least one embodiment, the semiconductor component is bent such that, when viewed in a cross section perpendicular to the bottom major surface, the bending profile has a maximum in a central region between two adjacent inflection points and in a flat region along the edge of the semiconductor component. Alternatively or additionally, the same may apply to the differential bending, i.e., the distance between the semiconductor component and the bottom metal disk.

[0040] According to at least one embodiment, the maximum relative bending of the semiconductor component is up to 3×10 -4or up to 1×10 -4 and the maximum relative bending is the maximum absolute bending divided by the diameter of the semiconductor component. For example, the maximum absolute bending is up to 0.3 mm, or up to 0.1 mm, or up to 40 μm. The same can be applied to the differential bending.

[0041] According to at least one embodiment, the width of the semiconductor component is at least 25 mm or at least 5 cm, alternatively or additionally up to 25 cm. Thus, the semiconductor components can be relatively large.

[0042] The method and semiconductor module described herein will be described in more detail below by way of exemplary embodiments with reference to the drawings. Parts that are the same in the individual figures are indicated by the same reference numerals. However, the relationship between elements is not shown to scale, and rather individual elements may be exaggerated to facilitate understanding. [Brief description of the drawings]

[0043] [Figure 1] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Diagram 2] FIG. 2 is a schematic pressure profile diagram of the semiconductor module of FIG. [Diagram 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 4] 4 is a schematic top view of the semiconductor module of FIG. 3. [Diagram 5] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 6] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 7] 3A-3C are schematic diagrams of the displacement of the semiconductor components and bottom metal disk of an exemplary embodiment of a semiconductor module described herein. [Figure 8]1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 9] 1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 10] 1 is a schematic diagram of the electrical and thermal characteristics of an exemplary embodiment of a semiconductor module described herein compared to a reference device. [Figure 11] FIG. 2 is a schematic perspective view of a semiconductor module and a reference device as described herein. [Figure 12] 1 is a schematic cross-sectional view of a semiconductor component of a semiconductor module as described herein. [Figure 13] 1 is a schematic cross-sectional view of a semiconductor component of a semiconductor module as described herein. [Figure 14] 1 is a schematic cross-sectional view of a semiconductor component of a reference device. [Figure 15] FIG. 2 is a schematic top view of pressure sensitive paper used in the semiconductor modules described herein. [Figure 16] 1A and 1B are schematic top and cross-sectional views of a reference device. [Figure 17] 1A-1D are schematic top and respective schematic cross-sectional views of an exemplary embodiment of a semiconductor module described herein; [Figure 18] 1A-1D are schematic top and respective schematic cross-sectional views of an exemplary embodiment of a semiconductor module described herein; [Figure 19] 1A-1D are schematic top and respective schematic cross-sectional views of an exemplary embodiment of a semiconductor module described herein; [Figure 20] 1A-1D are schematic top and respective schematic cross-sectional views of an exemplary embodiment of a semiconductor module described herein; [Figure 21] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 22] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 23] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Figure 24] 1 is a schematic top view of an exemplary embodiment of a semiconductor module described herein. [Diagram 25] 1 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor module described herein. [Figure 26] 2 is a schematic diagram of manufacturing parameters of a method for producing an exemplary embodiment of a semiconductor module described herein. [Figure 27] 4 is a schematic diagram of a pressure profile for an exemplary embodiment of a semiconductor module described herein. [Figure 28] 1 is a schematic block diagram of an exemplary embodiment of a method for producing a semiconductor module as described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] 1 shows an embodiment of a semiconductor module 1. The semiconductor module 1 comprises a semiconductor component 2, which is for example a silicon wafer configured as an IEGT, IGCT, IGBT, GTO, PCT, FRD or GCT. The semiconductor component 2 is mounted on a bottom metal disk 3. For example, the bottom metal disk 3 is a molybdenum disk. A bottom main surface 23 of the semiconductor component 2 can be at least partially in direct contact with a bottom metal disk top surface 30. A top main surface 24 of the semiconductor component 2 is remote from the bottom metal disk 3.

[0045] The semiconductor component 2 is pressed onto the bottom metal disk top surface 30 with a pressure profile P (see FIG. 2). As with the semiconductor component 2 and the bottom metal disk 3, the pressure profile P may be rotationally symmetric. Thus, the bottom metal disk 3 has a radius r0, and the radius of the semiconductor component 2 is also r0 or slightly smaller. The schematic diagram of FIG. 2 starts from the center of the bottom metal disk 3 and the semiconductor component 2.

[0046] In the first central region C, A1, the pressure profile P has a minimum value N1. At the minimum value N1, there is a pressure pN1. Next, in the second central region A2, there is a circumferential maximum value M of the pressure profile P at which there is a global maximum pressure pM at a radius rM. Next, as the radius r increases, the pressure decreases, for example, in a monotonic and / or differentiable manner. In the outer third region A3, there is a circumferential minimum value N2 having a pressure pN2. For example, the pressure pN2 is present at or near the edge of the semiconductor component 2. Thus, the pressure profile P has a maximum value N in the second region A2.

[0047] For example, the first region A1 and the second region A2 and / or the second region A2 and the third region A3 are delimited by inflection points of the pressure profile P. At the minimum value N1, the maximum value M, and optionally also the circumferential minimum value N2, there may be a zero derivative of the pressure profile P.

[0048] For example, in the case of the first region A1, 0 ≦ r < 0.5r0 applies. Alternatively or additionally, for the third region A3, 0.9 < r ≦ r0 applies.

[0049] That is, the boundary between the first region A1 and the second region A2 may be at an r for which 0.3 ≦ r < 0.6r0 or 0.4 ≦ r < 0.6r0 applies. Similarly, the boundary between the second region A2 and the third region A3 may be at an r for which 0.7 ≦ r < r0 applies or 0.8 ≦ r < 0.9r0.

[0050] For example, 0 < (pM - pN1) ≦ (pM - pN2), and pN1 < mP or alternatively pN1 = pM.

[0051] 3 and 4 show another embodiment of the semiconductor module 1. In this embodiment, the pressure profile P is obtained by using a clip body 5, for example, the clip body 5 is made of an epoxide. An exemplary material of the clip body 5 is an epoxy mold compound (EMC). The coefficients of thermal expansions (CTE) of said EMC of the clip body 5 can be at least 3 ppm / ° C. and / or at most 50 ppm / ° C. Alternatively or additionally, the glass transition temperature Tg of the EMC of the clip body 5 is at least 120° C. and / or at most 300° C. Alternatively or additionally, the Young's modulus E and / or the flexural modulus of elasticity of the EMC of the clip body 5 is at least 10 GPa and / or at least 40 GPa.

[0052] 3 and 4, the clip body 5 directly covers the top major surface 24 and the bottom metal disk top surface 30. The sides of the semiconductor component 2 are directly covered completely by the clip body 5. The sides of the bottom metal disk 3 are directly covered completely or also partially by the clip body 5. Besides being shown, the semiconductor component 2 and the bottom metal disk 3 can have the same radius.

[0053] For example, the clip body 5 protrudes laterally by at least 2 mm and / or at most 2 cm from the bottom metal disc 3 and / or the semiconductor component 2. Alternatively or additionally, said lateral protrusion is at least 2% and / or at most 20% of r0.

[0054] For example, the thickness of the clip body 5 above the upper main surface 24 is at least 1 mm and / or at most 1 cm. Alternatively or additionally, said thickness is at least 1% and / or at most 10% of r0, or at least 50% and / or at most 300% of the thickness of the semiconductor component 2.

[0055] For example, the covering width L of the clip body 5 on the upper main surface 24 is at least 1 mm and / or at most 1 cm. Alternatively or additionally, said covering width L is at least 2% and / or at most 20% of r0.

[0056] As can be seen from Fig. 4, the semiconductor module 1 is of rotationally symmetric design when viewed from above. The cross-sectional views shown herein refer to a cross-section along one of the dashed dotted lines passing through the center of the semiconductor module 1. Compare Fig. 4. The same may be true for all other embodiments.

[0057] In Figures 5 and 6 the working principle of the clip body 5 is shown. Optionally, the semiconductor module 1 comprises an upper metal disk 4, which is for example a molybdenum disk. The bottom metal disk 3 can be arranged on a bottom pole piece 71, which is for example a copper plate. An additional upper pole piece, not shown in Figures 5 and 6, can be present on the upper metal disk 4 correspondingly. On the side of the upper metal disk 4 remote from the semiconductor component 2 there is also an upper pole piece 72, which is for example also a copper plate. Optionally, the metal disks 3, 4 may have an adjustment structure 73 in the middle.

[0058] According to Fig. 5, all components 71, 3, 2, 4 are planar, resulting in no or almost no displacement z perpendicular to the bottom pole piece 71. However, this situation is only idealized. In reality, comparing Fig. 6, there is a considerable displacement z at least in the semiconductor component 2 and possibly also in the bottom metal disc 3. This displacement z results, for example, from temperature differences between assembly and use of the semiconductor module 1 and / or from high currents in the kA range through the semiconductor component 2. It should be noted that Fig. 6 shows a situation where no clamping pressure is applied to the top metal disc 4 and the bottom pole piece 71, resulting in a pressure of substantially only 1 bar.

[0059] In the intended application of the semiconductor module 1, such a displacement may reduce the contact area, in particular between the bottom main surface 23 and the bottom metal disk top surface 30, and thus limit the performance of the semiconductor module 1 as well. When the semiconductor module 1 is in use, the components 71, 3, 2, 4 may be pressed together with a clamping force of, for example, 1 kN to 0.1 MN. For r≈90 mm, said force may be about 0.04 MN. For example, the pressure resulting from the clamping force is between 2 MPa and 20 MPa.

[0060] 6 shows that the upper portion 52 of the clip body 5 at the upper main surface 24 is bent relative to the lateral portion 53 of the side surface. For example, such bending exerts additional force on the semiconductor component 2 to obtain the desired pressure profile P. Compare FIG.

[0061] When no clamping force is applied, a gap 25 may exist between the semiconductor component 2 and the bottom metal disk 3. This gap 25 is, for example, located in the second region and / or the third region. For example, when a clamping force is applied, the circumferential maximum M of the pressure profile P is located where the gap 25 would have been in the absence of the clamping force.

[0062] The clip body 5 is produced, for example, as follows. In a first step, the semiconductor component 2 is applied, for example at room temperature, directly onto the bottom metal disk 3. The semiconductor component 2 and the bottom metal disk 3 may be flat when the clip body 5 is formed.

[0063] In a second step, the clip body 5 is created, for example, by clamping the semiconductor component 2 and the bottom metal disk 3 together at high temperature when the material of the clip body 5 is in a liquid state. The clamping can be achieved by a mold for the clip body, the interior of which has the shape of the clip body 5 to be formed.

[0064] Then, in a third step, the material of the clip body 5 is injected into the mold. After some time, the liquid material of the clip body 5 solidifies. After solidification, the resulting configuration of the semiconductor component 2, the bottom metal disk 3 and the clip body 5 is unclamped and cooled in a fourth step. Due to this cooling, bending of the semiconductor component 2 and also optionally the bottom metal disk 3 occurs. The material of the clip body 5 is, for example, a thermosetting plastic, such as a thermosetting resin.

[0065] For example, the clip body 5 is manufactured at a temperature of at least 130° C. and / or at most 260° C. Thus, when clamped together, the semiconductor component 2 and the bottom metal disk 3 can have such high temperatures.

[0066] Below the glass transition temperature of the clip body 5, e.g., at room temperature or the operating temperature of the module 1, a portion on the top main surface 24 of the clip body 5 acts as a lever that presses the semiconductor component 2 onto the bottom metal disk 3. This pressure by the lever is possible, for example, because the semiconductor component 2 and / or the bottom metal disk 3 are bent at said temperatures. In particular, at room temperature, a gap may exist between the semiconductor component 2 and the bottom metal disk 3 in the area where the clip body 5 is applied and the top metal disk 4 is not applied, as viewed from above. Compare FIG. 6.

[0067] Room temperature may mean 23° C. The operating temperature of the finished semiconductor module 1 is, for example, at least −40° C. and / or at most 160° C. The operating temperature may be below the glass transition temperature of the clip body 5.

[0068] Then, in a fifth step, in which the top metal disk 4 and the bottom metal disk 3 are pressed onto the semiconductor component 2 after the clip body 5 has been formed, a pressure profile P can be formed. This pressing is performed, for example, by pole pieces 71, 72.

[0069] Thus, the pressure profile P may only be present after pressing the top metal disk 4 inside the housing, but the bent wafer shape of the semiconductor component 2 is present immediately after completing the molding process of the clip body 5 and cooling the semiconductor component 2 and the bottom metal disk 3.

[0070] In Fig. 7 the displacement z for the case of Fig. 6 is shown when no force is applied to the components 71, 4. This can be applied when there is no clamping force. At r = 0 there is a maximum displacement z3 of the bottom metal disk 3 and a maximum displacement of the semiconductor component 2. In the second region A2, in the vicinity of rM with the circumferential maximum value M there is a relative minimum zN in the displacement of the semiconductor component 2.

[0071] For example, 300 μm≧z3≧zM>zN>0. In other aspects, what is true for Figures 1 and 2 may also be true for Figures 3-7, and vice versa.

[0072] In Figures 8 to 10, a reference device 9 is compared with an embodiment of a semiconductor module 1, for example an FRD.

[0073] Figure 8 further shows the capability of the 4.5 kV FRD when tested in a continuous regime in a power converter, also called frequency test, F-test. The lowest durability shows the free-floating FF design concept without clip body 5, as shown above. The durability of the FF concept can be increased by increasing the clamping force from 40 kN to 50 kN. However, this represents an extra cost for the customer and is not always possible.

[0074] Using the clip body 5 as a molding compound to attach the semiconductor component 2, e.g. a silicon wafer, to the bottom metal disk can improve the capabilities of the FF concept without increasing the clamping force. The contact between the bottom main surface 23 and the bottom metal disk 3 is still dry, but the pressure distribution from the wafer center to the edge is different. Its performance in the F test is nearly equal at f=300 Hz and nearly equal at f=100 Hz when a suitable EMC molding compound is used for the clip body 5, compared to the reference device 9, where the semiconductor component 2 and the bottom metal disk 3 are connected by LTB. See Figure 9. For example, EMC K1 has a higher CTE, a higher Tg, and a lower E than EMC K2.

[0075] Therefore, in Figure 8, the 55 cm 2 The final let-through current Ip in the F test of a 4.5 kV FRD with an area of ​​55 cm 2 is shown. The DC link voltage is 2.85 kV, f=100 Hz. 2 Figure 1 shows the final let-through current Ip of a diode at F-test for a 4.5kV FRD with an area of ​​1000 V. The DC link voltage is again 2.85 kV, f=300 Hz. At this frequency, the EMC K1 gives comparable performance to the LTB design.

[0076] A similar improvement in performance is observed during AC blocking tests at 4.5kV, 50Hz, 5 seconds. Using a design concept with clip body 5 allows the temperature range of stable blocking to be increased by +5°C, i.e., increased thermal stability, resulting in a different pressure distribution than standard LTB designs.

[0077] Therefore, Figure 10 has an area of ​​55 cm 21 shows a thermal stability test of a 4.5 kV FRD of 1000 Ω / s. The voltage waveform is an AC half-sine wave at 4.5 kV and f=50 Hz, and the duration of the test is 5 seconds. The performance is improved by 5° C. for the semiconductor module 1 described herein compared to the corresponding LTB design, which is equal for both types of molding compounds K1, K2, due to the different pressure distribution resulting from the different curvatures.

[0078] Thus, the semiconductor module 1 described herein uses controlled device bow and / or curvature to achieve advantageous pressure distribution that provides the best device durability.

[0079] Figure 11 shows the difference in wafer curvature after mounting a 91 mm diameter silicon wafer 2 on the molybdenum disc 3 for LTB on the right and the clip body 5 design on the left. The latter shows a clear flattened area near the wafer edge. In this case, the silicon wafer 2 is pressed against the molybdenum disc 3 in a wide area at the edge towards the center of the wafer 2. The result is a lower resistance and a lower R due to the higher pressure. th j-c There is more current flowing outside the wafer edge through a larger area having a larger current. The wafer edge of the design with clip body 5 is less likely to overheat and the module 1 will not fail in reverse blocking mode due to thermal runaway. It is most likely to fail in reverse recovery which occurs at higher currents.

[0080] This is also shown in Figures 12-14. While the FF design gives a random shape, the semiconductor module 1 described herein shows a relatively large flattened area at the wafer periphery and a lower curvature of about 20 μm (see Figures 12 and 13). The large dome-shaped curvature of the LTB is the result of bonding two different materials together, and the resulting curvature is about 60 μm (see Figure 14).

[0081] FIG. 15 shows the pressure-sensitive paper used in the semiconductor module 1 and reference device 9 described herein. A denser hatching pattern represents a higher pressure. As can be seen from the left part of FIG. 15, the pressure profile P has a lower pressure p at the edge and in the central region C, but a higher pressure p in between.

[0082] In contrast, in the FF design without the clip body 5 (see the central part of Figure 15), the pressure profile P shows a higher pressure at the edge of the wafer than the semiconductor module 1 described in this specification and than the LTB reference device 9 shown in the right part of Figure 15.

[0083] In other aspects, what is true for Figures 1-7 may also be true for Figures 8-15, and vice versa.

[0084] In the F test, wafers with higher peripheral pressures can typically fail along the wafer edge during reverse blocking between switching events. The semiconductor module 1 described herein can fail in switching mode mostly during reverse recovery, and failure patterns can begin to develop, in large part as a result of current filamentation due to NDR. The failure current can be close to that of the LTB design, which has a lower R across the entire wafer surface due to bonding the silicon wafer to the molybdenum disk. th j-c has.

[0085] Based on these findings, the FRD back-end design concept described herein has higher robustness during hard switching without using conventional LTB techniques to reduce costs and increase production yield. Methods for achieving a large flat area along the wafer edge at pressure profile P can use various methods, such as the clip body 5 described above. Further methods are described below. Thus, localized reduction of contact thermal and electrical resistance at desired locations on the wafer surface can be achieved by, for example, using a clip body 5 as described above, - using wafer-molybdenum bonding at specific surface areas; - using curved metal discs, and / or -Use of specific manufacturing parameters This can be achieved by wafer bow design.

[0086] A reference device 9 using LTB is shown in Figure 16. The conventional LTB concept involves depositing a bond material 6 between a silicon wafer and a molybdenum disk, making it uniform across the entire surface of the two parts to be joined. This creates a mismatch of the parts due to thermal stresses and the coefficient of thermal expansion (CTE) at the dome-shaped bend, as presented in Figure 14.

[0087] In contrast to this uniform surface bonding, it is targeted to deposit the bond material 6 between the semiconductor component 2 and the bottom metal disk 3 only in certain preferential areas (see Figs. 17-23) to achieve a local bond line or local bond interface, thereby obtaining the desired warpage of the wafer-molding package. Multiple shapes and patterns formed by the bond material 6 should be envisaged, resulting in various three-dimensional deformations of the semiconductor component 2 and the bottom metal disk 3.

[0088] Various bond materials 6 may be used, such as solder paste, silver paste or silver sheet, resulting in a typical bond line thickness between 10 μm and 100 μm. Various joining techniques may be used, such as LTB, brazing, sintering or soldering.

[0089] The structuring of the bond line can be achieved by deposition of a bond material 6 in selected areas. This can be achieved, for example, by stencil or screen printing of solder or silver paste, or by transfer of a silver sheet with a predetermined shape.

[0090] Structuring of the bond interface can be achieved, for example, by structured coating of the wafer with a thin (compared to the bond line) bonded or non-bonded metal layer or by structuring of the bond material 6 prior to the bonding process, for example by structuring hot stamp pressing of the bond material 6 prior to the wafer-Mo bonding process, which sinters the bond material 6 in selected areas respectively and prevents wafer-Mo sintering in subsequent processes).

[0091] By structuring the bond line, the bond material 6 is only present in the area of ​​the bond between the semiconductor component 2 and the bottom metal disk 3. By structuring the bond interface, the bond material 6 is present over the entire surface of the semiconductor component 2 and the bottom metal disk 3, so that the bond material 6 is present and provides mechanical, electrical and / or thermal support for the structure, but no bond is present in selected areas.

[0092] 17, the bond material 6 is limited to the outer regions and the central region C does not include the bond material 6. The bond material 6 may extend to the edge of the semiconductor component 2. For example, the width of the bond material 6 is between 0.1r0 and 0.5r0, or between 0.15r0 and 0.3r0, where r0 is the radius of the bottom metal disk 3 and / or the semiconductor component 2.

[0093] 18, the bond material 6 is limited to a central region C, and the outer regions are free of bond material 6. Thus, the bond material 6 may cover the center of the semiconductor component 2. For example, the bond material 6 extends towards the edges up to 0.8r0, or up to 0.5r0, or up to 0.3r0.

[0094] According to the embodiment of Fig. 19, the bond material 6 is applied over the entire semiconductor component 2. However, only in the outer regions there are connection regions 60, where bonding between the semiconductor component 2 and the bottom metal disk 3 is achieved. In the central region C there is a free-floating region 62, where bonding between the semiconductor component 2 and the bottom metal disk 3 is not achieved by the bond material 6. For example, in this case the width of the connection region 60 is between 0.1r0 and 0.5r0, or between 0.15r0 and 0.3r0.

[0095] 20, the bond material 6 is also applied over the entire semiconductor component 2, but the outer regions correspond to the free-floating regions 62, and the central region C is the connection region 60. For example, the connection region 60 extends towards the edge of the semiconductor component 2 up to 0.8r0, or up to 0.5r0, or up to 0.3r0.

[0096] In Fig. 21 it is shown that there are two circle-like rings of bond material 6. For example, the outer ring starts at the edge of the semiconductor component 2. The central region C can be free of bond material 6. For example, the width of the ring is between 0.05r0 and 0.4r0, or between 0.15r0 and 0.35r0. The inner ring of bond material 6 is located, for example, between 0.2r0 and 0.7r0. Besides what is shown, there can optionally be an inner dot of bond material 6 covering the center of the semiconductor component 2 and having a radius of, for example, up to 0.3r0 or up to 0.15r0.

[0097] According to Fig. 22, there is a circle-like outer ring of bond material, e.g., similar to Fig. 22. Additionally, there is a relatively large inner dot of bond material, e.g., the radius of the inner dot is at least 0.2r0 or at least 0.3r0 and / or at most 0.8r0 or at most 0.6r0.

[0098] 23, the bond material 6 is shown to correspond to an outer ring, for example starting at the edge of the semiconductor component 2. For example, the width of the ring of bond material 6 is between 0.1r0 and 0.5r0, or between 0.2r0 and 0.4r0.

[0099] Optionally, the ring comprises a plurality of recesses 64. The depth of the recesses 64 into the ring is, for example, at least 10% or at least 30% and / or at most 90% or at most 60% of the width of the ring. For example, there are at least 5 and / or at most 32 recesses 64. The recesses 64 may be equidistantly spaced.

[0100] According to Fig. 24, the bond material 6 is deposited as dots in the central region C. For example, the radius of the dots is at least 0.2r0 or at least 0.3r0 and / or at most 0.8r0 or at most 0.6r0.

[0101] Optionally, said central dot comprises a number of depressions 63. The radial extension of the depressions 63 towards the edge of the semiconductor component 2 is for example at least 10% or at least 30% and / or at most 90% or at most 60% of the diameter of the dot. For example, there are at least 5 and / or at most 32 depressions 63. The depressions 63 may be arranged equidistantly.

[0102] Also, in the embodiment of Figures 23 and 24, there may be additional rings or dots of bond material 6.

[0103] According to Figures 21-24, the bond material 6 corresponds to a connection region 60, similar to Figures 18 and 19. However, similar to Figures 20 and 21, there may also be free-floating regions 62 of the bond material in Figures 22-25.

[0104] In the embodiment of Figures 17 to 24, a clip body 5 may additionally be present.

[0105] In other aspects, what is true for Figures 1-15 may also be true for Figures 17-24, and vice versa.

[0106] In Fig. 25 it is shown that the pressure profile P is achieved by the bottom pole piece 71 and / or the top pole piece 72. Between the pole pieces 71, 72 there is a space 74 for the metal disks 3, 4 and the semiconductor component 2. In cross section, the pole pieces 71, 72 can be of hump or double hump type so that there can be one or two thickness maxima. Other than as shown in Fig. 25, the thickness maxima do not have to be exactly opposite each other, but rather the thickness maxima are laterally displaced, for example by at least 0.02r0 and / or by up to 0.2r0.

[0107] Such non-planar pole pieces 71 , 72 can be combined with a clip body 5 and a bond material 6 .

[0108] Therefore, what is true for Figures 1-24 can also be true for Figure 25, and vice versa.

[0109] 26 shows that the pressure profile P can be achieved, for example, by having different bonding conditions during application of the connection between the semiconductor component 2 and the bottom metal disk 3 by the bond material 6. For example, the bonding pressure p and / or bonding temperature T applied to the semiconductor component 2 and the bottom metal disk 3 and the bond material 6 during bonding increases towards the edge of the semiconductor component 2. In the central region C and the third region A3, the pressure p and / or temperature T can be approximately constant, so that a sudden change in pressure and / or temperature T can occur in the second region A2.

[0110] Such process parameter variations may also be combined with non-planar pole pieces 71, 72, clip bodies 5 and / or bond materials 6.

[0111] In other aspects, what is true for Figures 1-25 may also be true for Figure 26, and vice versa.

[0112] Further exemplary pressure profiles P are shown in Figure 27. For example, the pressure profile P may be expressed as P(r) = A / (1 + Br 2 +Cr 4 +Dr 6 +Er 8 )+F.

[0113] In the particular embodiment of FIG. 28, {A}=0,64, B=-1, E=5, and C=D=F=0, where {} denotes the numerical value of the respective quantity value, and r is a unitless variable representing the distance to the minimum and / or center of the bottom metal disk 3 and / or semiconductor component 2.

[0114] The pressure profile P as approximated by the above equation may be applied to all embodiments of the semiconductor module 1.

[0115] In other aspects, what is true for Figures 1-26 may also be true for Figure 27, and vice versa.

[0116] FIG. 28 shows a schematic diagram of a manufacturing method for producing the semiconductor module 1. In a first method step S1 a semiconductor component 2 and a bottom metal disk 3 are provided.

[0117] In a second method step S2, the semiconductor component 2 is pressed onto the bottom metal disk 3 with a pressure profile. This step S2 may be performed immediately after method step S1, during installation of the semiconductor module 1, or in the intended use of the semiconductor module 1, i.e. under operating conditions. For example, such a pressure profile P may not be present immediately after assembling the semiconductor component 2 on the bottom metal disk 3, and the desired pressure profile P may result later from operating the semiconductor module 1 as intended. In another embodiment, the desired pressure profile P may be present immediately upon assembling the semiconductor component 2 on the bottom metal disk 3.

[0118] In FIG. 28, it is shown that step S2 can include sub-steps S21, S22 or S23, and steps S21, S22 and S23 can be used in any combination. In step S21, a clip body 5 is applied to obtain, for example, the semiconductor module 1 of FIG. 1 to FIG. 15. See in particular FIG. 5 and FIG. 6. In step S22, a bond material 6 is applied to obtain, for example, the semiconductor module 1 of FIG. 17 to FIG. 24. Step S22 can include providing method parameters in processing the bond material 6, as shown in relation to FIG. 26. In step S23, pole pieces 71, 72 are provided to obtain, for example, the semiconductor module 1 of FIG. 25.

[0119] In other aspects, what is true for Figures 1-27 may also be true for Figure 28, and vice versa.

[0120] Thus, the semiconductor module 1 described herein may be an FRD with a defined profile of curvature and a respective pressure distribution across the wafer interface between the silicon wafer and the molybdenum strain buffer. Thus, a FRD with high robustness in hard switching conditions can be achieved without using conventional LTB techniques. The use of silver contaminants can be eliminated, reducing the cost of the process. Optionally, an LTB process with spatial tuning of the pressure distribution along the wafer when structuring the bond material 6 can also be used.

[0121] Thus, a new generation of FRDs is provided that is more robust in hard switching conditions. New designs can be utilized on new FRDs that have larger areas than exist today.

[0122] Thus, the semiconductor module 1 described herein has a defined spatial distribution of pressure at the interface between the silicon wafer 2 and the molybdenum disk 3. Optionally, the silicon wafer 2 and the molybdenum disk 3 are attached together by a clip body, forming a desired three-dimensional deformation, warpage or curvature of the resulting package. Optionally, the silicon wafer 2 and the molybdenum disk 3 are bonded together by a bond material 6 that is present at the interface with a specific pattern, thus forming a desired three-dimensional deformation, warpage or curvature of the package, or by using any bonding technique, such as low-temperature bonding, sintering, soldering or brazing. The bond material 6 between the silicon wafer 2 and the molybdenum disk 3 may be a silver-containing material, a lead-containing material, a copper-containing material, a tin-containing material, a bismuth-containing material, an indium-containing material, a zinc-containing material, an antimony-containing material, an aluminum-containing material, a nickel-containing material.

[0123] Components shown in the figures illustratively follow a designated order of direct overlap, unless otherwise indicated. Components that are not in contact in the figures are illustratively spaced apart from one another. Where lines are drawn parallel to one another, corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the drawn components relative to one another are accurately reproduced in the figures.

[0124] The semiconductor module described herein is not limited to the description based on the exemplary embodiments, but rather specifically includes any novel feature and any combination of features, including any combination of features in the claims, even if the feature or combination itself is not explicitly specified in the claims or exemplary embodiments. [Explanation of symbols]

[0125] Reference sign 1 Semiconductor module 2. Semiconductor Components 23 Bottom main surface 24 Upper main surface 25 void 3 Bottom Metal Disc 30 Bottom metal disk top surface 4 Upper Metal Disc 5 Clip Body 52 Top 53 Horizontal part 6 Bonding Materials 60 Connection Area 62 Free-floating area 63 Depression 64 Recess 71 Bottom pole piece 72 Upper pole piece 73 Adjustment structure 74 Space for semiconductor components and metal disks 8 Pressure Sensitive Paper 9 Reference Device A..Area C central area FF Free Floating Device Final let-through current in Ip A or kA K. Plastic materials L Covering width LTB Low Temperature Junction Device M Maximum value of the pressure profile in the circumferential direction N1 Minimum in the central region of the pressure profile Circumferential minimum of N2 pressure profile P Pressure Profile p Pressure r radius r0 Radius of the bottom metal disk SR Silicone Rubber Tp Final passage temperature in °C z-displacement zM Maximum absolute bending zN Relative minimum bending

Claims

1. A method for producing a semiconductor module (1), comprising the steps of: - providing a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); - providing a bottom metal disc (3) and a top metal disc (4); - pressing said semiconductor component (2) onto said bottom metal disk (3) with a preconfigured non-uniform pressure profile (P); Including, - said bottom main surface (23) faces said bottom metal disc (3) and said top main surface (24) faces said top metal disc (4), said semiconductor component (2) being located directly between said bottom metal disc (3) and said top main surface (24); the method further comprises forming a clip body (5) surrounding the semiconductor component (2) in a lateral direction parallel to the bottom main surface (23) and partially covering the top main surface (24); - said clip body (5) is in direct contact with said bottom metal disc (3); - said clip body (5) is made of plastic; - the clip body (5) and the top metal disc (4) press the semiconductor component (2) onto the bottom metal disc (3); - in a top view of the bottom main surface (23), the pressure profile (P) has a local minimum (N1) in a central region (C) of the semiconductor component (2) surrounded by circumferential maxima (M) of the pressure profile (P), which circumferential maxima (M) are surrounded by circumferential minima (N2) of the pressure profile (P), which pressure profile (P) is present in the completed semiconductor module (1) when it is operated.

2. said bottom metal disk (3) has a radius r0 and the position rM of said circumferential maximum (M) of said pressure profile (P) is between 0.5r0 and 0.9r0; the radius r of the semiconductor component is between 0.8r and r, and r is less than r; 13. The method according to claim 1, wherein for the pressure pN1 of the local minimum (N1), the pressure pM of the circumferential maximum (M) and the pressure pN2 of the circumferential minimum (N2) in the central region (C), the following applies: 0.1 pM ≦ pN2 ≦ 0.4 pM ≦ pN1 ≦ 0.9 pM.

3. When viewed in a cross section through the local minimum (N1) and the semiconductor component (2), the pressure profile (P) can be approximated as follows: P(r)=A / (1+Br ２ +Cr ４ +Dr ６ +Er ８ )+F、 In the formula, r is the distance to the minimum value (N1), A / pM and F / pM, and at least one of C, D and E are positive numbers; 10. The method of claim 9, wherein B is a negative number.

4. P(r) = A / (1+Br ２ +Cr ４ + Dr. ６ +Er ８ ) + F is true for {-rS} ≤ r ≤ {rS} with a tolerance of up to 0.1 pM; 2. The method of claim 1, wherein 0.25 pM≦A≦pM, and −2≦B≦−0.5, and 0≦C≦2, and 0≦D≦6, and 0≦E≦10, and 0≦F≦0.3 pM.

5. 10. The method according to any one of the preceding claims, wherein the clip body (5) is manufactured at a temperature between 130°C and 260°C when the material from which the clip body (5) is made is initially in a liquid state.

6. When viewed from above on the bottom main surface (23), the circumferential maximum value (M) of the pressure profile (P) is located within an opening of the clip body (5) such that the circumferential maximum value (M) is not covered by the clip body (5); a portion of the clip body (5) on the top main surface (24) acts as a lever to press the semiconductor component (2) onto the bottom metal disc (3); 10. The method according to any one of the preceding claims, wherein the clip body (5) terminates away from the upper metal disc (4) such that there is no contact between the clip body (5) and the upper metal disc (4).

7. 10. The method according to any one of the preceding claims, wherein the semiconductor component (2) is bent when the arrangement comprising the clip body (5), the semiconductor component (2) and the bottom metal disk (3) is cooled from the manufacturing temperature of the clip body (5) back to room temperature, i.e. 23°C.

8. 10. The method according to any one of the preceding claims, wherein the pressure profile (P) is formed when the top metal disc (4) and the bottom metal disc (3) are pressed against the semiconductor component (2) after the clip body (5) is formed.

9. 10. The method according to any one of the preceding claims, wherein the operating temperature of the completed semiconductor module (1) is between -40°C and 160°C inclusive, and the clip body (5) is solid at said operating temperature.

10. when the semiconductor component (2) is bent at room temperature, i.e., 23° C., or at least one of the operating temperatures, and when viewed in a cross section perpendicular to the bottom main surface (23), the bending profile has a maximum value in the central region (C) between two adjacent inflection points and in flat regions along the edges of the semiconductor component (2); The maximum relative bending of the semiconductor component (2) is up to 3×10 －４ 4. The method according to claim 1, wherein the maximum relative bending is the maximum absolute bending divided by a diameter of the semiconductor component (2).

11. A semiconductor module (1), a semiconductor component (2) configured for a voltage of at least 0.6 kV and having a bottom main surface (23) and an opposite top main surface (24); - a plastic clip body (5), - an upper metal disc (4) facing said upper main face (24); a bottom metal disk (3) against which said semiconductor component (2) is pressed with a pressure profile (P), said bottom main surface (23) facing said bottom metal disk (3); Equipped with in a top view of the bottom main surface (23), the pressure profile (P) has a local minimum (N1) in a central region (C) of the semiconductor component (2) surrounded by circumferential maxima (M) of the pressure profile (P), the circumferential maxima (M) being surrounded by circumferential minima (N2) of the pressure profile (P), the semiconductor component (2) is located directly between the bottom metal disk (3) and the top major surface (24); - said clip body (5) partially covers said upper main surface (24); - said clip body (5) is in direct contact with said bottom metal disc (3); - a semiconductor module (1), wherein said clip body (5) and said top metal disc (4) press said semiconductor component (2) onto said bottom metal disc (3).

12. 13. The semiconductor module (1) according to claim 12, wherein at least one free-floating region (62) is at least partially present between the semiconductor component (2) and the bottom metal disk (3), in which the semiconductor component (2) is freely floating relative to the bottom metal disk (3).

13. the diameter of said upper metal disk (4) is smaller than the diameter of said semiconductor component (2); A semiconductor module (1) according to any one of the two preceding claims, wherein, in a top view of the upper main surface (24), the circumferential maximum value (M) of the pressure profile (P) is covered by the upper metal disk (4).

14. 10. The semiconductor module (1) according to the preceding claim, wherein at least one of the bottom metal disc (3) and the top metal disc (4) comprises a curvature configured to provide the pressure profile (P).

15. The semiconductor component (2) is selected from the group consisting of injection enhanced gate transistors, metal oxide semiconductor field effect transistors, metal-insulator-semiconductor field effect transistors, insulated gate bipolar transistors, bipolar junction transistors, thyristors, and junction gate field effect transistors; 10. The semiconductor module (1) according to any one of the four preceding claims, wherein the width of the semiconductor component (2) is at least 25 mm and at most 25 cm.

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