Adaptive Predictive Control System

Abstract

The present disclosure describes a system, method, and apparatus for a plasma processing system. The method includes receiving a reference signal defining a target value for a parameter controlled at an output in the plasma processing system, obtaining a measurement of the parameter controlled at the output, and calculating a delay between the target value of the setpoint signal and a corresponding actual parameter value achieved at the output. The method also includes providing a time shift amplitude error indicative of an error between the target value and the actual parameter value based on the delay, and adjusting at least one actuator based on the delay and the time shift amplitude error prior to when the actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS Claiming priority under 35 USC §119 This application for patent claims priority to U.S. patent application Ser. No. 17 / 685,898, filed March 3, 2022 and entitled "ADAPTIVE PREDICTIVE CONTROL SYSTEM," U.S. patent application Ser. No. 17 / 685,931, filed March 3, 2022 and entitled "SYSTEMS AND METHODS FOR DELAY AND AMPLITUDE CORRECTION," and U.S. patent application Ser. No. 17 / 685,842, filed March 3, 2022 and entitled "MULTI-STEP PREDICTIVE CONTROL SYSTEM," all of which are assigned to the assignee hereof and are expressly incorporated herein by reference.

[0002] Control systems have important applications in many technology fields, including plasma applications, semiconductor processing and other material processing, robotics, vehicle control systems for automobiles, aircraft, and spacecraft, and other electronic, manufacturing, and industrial systems. Semiconductor processing and other advanced material processing rely on increasingly sophisticated plasma processes. Such plasma processes, in turn, require increasingly sophisticated power and control systems to make the inherently unstable and nonlinear plasma more precise and consistent. Such plasmas are used for processes such as plasma etch processes, plasma-enhanced chemical vapor deposition (CEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma-assisted atomic layer deposition (PA-ALD), RF sputtering deposition, and other plasma processing applications.

[0003] In some plasma processing recipes, it is desirable to provide a pulsed waveform with multiple states (or power levels) as illustrated by the example waveform of FIG. 2. Each recipe includes a number of pulse cycles (PC), a number of pulses per pulse cycle, and a number of states per pulse. Each state has a different target power level. In this example, two pulse cycles are shown, the first pulse cycle has six pulses, each of which has three states. The second pulse cycle has four pulses, each of which has four states. The plasma processing system includes many actuators to achieve the desired application of power, as shown in FIG. 2. However, in many cases, different actuators have inherently different response times (e.g., some actuators respond much faster than others) and / or the actuators operate in an asynchronous manner, so that the actuators respond differently to the control signal. In the context of the present disclosure, actuators may include higher level components such as, but not limited to, generators, match networks, remote plasma sources, and bias supplies. Additionally, actuators may include lower level components such as, but not limited to, DC rail supplies, RF amplifiers, variable capacitors, and bias supplies and power supplies in remote plasma sources. In today's plasma processing systems, control over high-level and low-level actuators (e.g., for precision and consistency) is important in light of the increasing speeds of actuators and the resulting ever-decreasing dimensions of processed workpieces.

[0004] As an additional example, an RF generator for providing the pulsed waveform of FIG. 2 may have an actuator including a DC section and a power amplifier, where the DC section provides a rail voltage to a power amplifier, which uses the rail voltage to provide the desired pulsed waveform (e.g., FIG. 2). The power amplifier is relatively fast (e.g., about 250 nanoseconds) compared to changes in the target voltage, while the DC section or rail is relatively slow (e.g., about 1 millisecond). As a result, existing control systems tend to hold the rail at a high level (e.g., at the highest level required for a given pulse cycle) for the majority of the pulse cycle. However, this can lead to overheating of components and premature system failure and maintenance needs, as well as inefficiencies, since the rail is often much higher than is needed at any given moment in time (i.e., for a given condition within a pulse of the pulse cycle). Summary of the Invention [Means for solving the problem]

[0005] The following presents a simplified summary of one or more aspects and / or embodiments disclosed herein. As such, the following summary should not be considered an extensive overview of all envisioned aspects and / or embodiments, nor should it be considered to identify key or critical elements of all envisioned aspects and / or embodiments, or to delineate the scope associated with any particular aspect and / or embodiment. As such, the following summary is intended only to present certain concepts of one or more aspects and / or embodiments of the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0006] An aspect of the present disclosure may be characterized as a plasma processing control system comprising a user interface configured to receive a reference signal defining a target value for a controlled parameter provided to a controlled output in the system. The system also comprises at least one sensor for obtaining a measurement of the controlled parameter controlled at the controlled output. In addition, the system includes a delay / amplitude estimator configured to calculate a delay between a target value of the reference signal and a corresponding actual value of the controlled parameter achieved at the controlled output, and provide a time-shifted amplitude error indicative of an error between the target value and the actual parameter value based on the delay. The predictive control section is configured to adjust at least one actuator based on the delay and the time-shifted amplitude error in advance of when an actual value is required at an actuator output of the at least one actuator while maintaining the controlled parameter at the controlled output within a threshold range.

[0007] Another aspect may be characterized as a method for controlling a plasma processing system. The method includes receiving a reference signal defining a target value for a parameter controlled at an output in the plasma processing system and obtaining a measurement of the parameter controlled at the output. The method also includes calculating a delay between the target value of the reference signal and a corresponding actual parameter value achieved at the output, and providing a time shift amplitude error indicative of an error between the target value and the actual parameter value based on the delay. At least one actuator is adjusted based on the delay and the time shift amplitude error prior to when the actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range.

[0008] Yet another aspect may be characterized as a plasma processing control system comprising a processor and a non-transient memory comprising instructions for receiving a reference signal defining a target value for a parameter controlled at an output in a plasma processing system. The system also comprises a field programmable gate array and instructions for programming the field programmable gate array including instructions for programming the field programmable gate array to obtain measurements of the parameter controlled at the output, receive a target value for the parameter controlled at the output, and calculate a delay between the target value of the reference signal and a corresponding actual parameter value achieved at the output. The instructions for programming the field programmable gate array also include instructions for providing a time shifted amplitude error indicative of an error between the target value and the actual parameter value based on the delay, and adjusting at least one actuator based on the delay and the time shifted amplitude error prior to when the actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range. [Brief description of the drawings]

[0009] Various objects and advantages of the present disclosure as well as a more complete understanding will become apparent and will be more readily understood by reference to the following detailed description and appended claims, when considered in conjunction with the accompanying drawings.

[0010] [Figure 1] FIG. 1 is a block diagram illustrating a system level view of a plasma processing system.

[0011] [Diagram 2] FIG. 2 illustrates a multi-level pulsed waveform that can be produced by the RF generator disclosed herein.

[0012] [Diagram 3] FIG. 3 is a block diagram depicting an aspect of an RF generator.

[0013] [Figure 4] FIG. 4 is a graph depicting the output of the slow and fast actuators of FIG.

[0014] [Figure 5A] FIG. 5A is another graph depicting operating aspects of the slow and fast actuators of FIG.

[0015] [Figure 5B] FIG. 5B is yet another graph depicting the operating profile of the slow and fast actuators of FIG.

[0016] [Figure 6] FIG. 6 is a block diagram depicting an exemplary RF generator.

[0017] [Figure 7] FIG. 7 illustrates a method for selecting a master state that allows slow down control in the power generation system of FIG.

[0018] [Figure 8] FIG. 8 illustrates another method of selecting a master state that allows slow speed control in the power generation system of FIG.

[0019] [Figure 9] FIG. 9 is a block diagram illustrating an embodiment of the RF generator depicted in FIG.

[0020] [Figure 10] FIG. 10 illustrates details of an embodiment of the DC controller depicted in FIG.

[0021] [Figure 11]FIG. 11 illustrates an n-level control algorithm for an RF generator having a DC section that provides rail voltages to an RF amplifier to provide a pulsed waveform to a plasma load or other non-linear load.

[0022] [Figure 12] FIG. 12 illustrates another n-level control algorithm for an RF generator having a DC section that provides rail voltages to an RF amplifier to provide a pulsed waveform to a plasma load or other nonlinear load.

[0023] [Figure 13] Figure 13A illustrates simulated waveforms for target and output power corresponding to the system shown in Figures 1 and 9. Figure 13B illustrates simulated waveforms for rail voltage corresponding to the system shown in Figures 1 and 9. Figure 13C illustrates simulated waveforms for phase / drive voltage and drive voltage threshold corresponding to the system shown in Figures 1 and 9.

[0024] [Figure 14] Figure 14A illustrates details of the first and second cycles of the waveform shown in Figure 13A. Figure 14B illustrates details of the first and second cycles of the waveform shown in Figure 13B. Figure 14C illustrates details of the first and second cycles of the waveform shown in Figure 13C.

[0025] [Figure 15] Figure 15A illustrates details of the third and fourth cycles of the waveform shown in Figure 13A. Figure 15B illustrates details of the third and fourth cycles of the waveform shown in Figure 13B. Figure 15C illustrates details of the third and fourth cycles of the waveform shown in Figure 13C.

[0026] [Figure 16]Figure 16A illustrates a detail of the fifth cycle of the waveform shown in Figure 13A. Figure 16B illustrates a detail of the fifth cycle of the waveform shown in Figure 13B. Figure 16C illustrates a detail of the fifth cycle of the waveform shown in Figure 13C.

[0027] [Figure 17] Figure 17A illustrates a detail of the sixth cycle of the waveform shown in Figure 13A. Figure 17B illustrates a detail of the sixth cycle of the waveform shown in Figure 13B. Figure 17C illustrates a detail of the sixth cycle of the waveform shown in Figure 13C.

[0028] [Figure 18] Figure 18A illustrates a detail of the seventh cycle of the waveform shown in Figure 13A. Figure 18B illustrates a detail of the seventh cycle of the waveform shown in Figure 13B. Figure 18C illustrates a detail of the seventh cycle of the waveform shown in Figure 13C.

[0029] [Figure 19] Figure 19A illustrates a detail of the eighth cycle of the waveform shown in Figure 13A. Figure 19B illustrates a detail of the eighth cycle of the waveform shown in Figure 13B. Figure 19C illustrates a detail of the eighth cycle of the waveform shown in Figure 13C.

[0030] [Figure 20] FIG. 20 is a block diagram depicting aspects of a control system and a plasma processing system.

[0031] [Figure 21] FIG. 21 is a block diagram illustrating an embodiment of a generator implementing the control system of FIG.

[0032] [Figure 22]Figure 22A is a graph depicting the operating aspects of the generator depicted in Figure 21. Figure 22B is a graph depicting the operating aspects of a control system that attempts to minimize energy. Figure 22C is a graph depicting the operating aspects of maximizing speed while dissipating more energy.

[0033] [Figure 23A] FIG. 23A illustrates an example of the control section depicted in FIG. 22C.

[0034] [Figure 23B] FIG. 23B depicts an alternative embodiment of the control section depicted in FIG. 22C.

[0035] [Figure 24] FIG. 24 is a block diagram illustrating an embodiment of the predictive control partition of FIGS. 20, 21, 23A, and 23B.

[0036] [Diagram 25] FIG. 25 is a collection of graphs illustrating the differences in actuator control and energy dissipation between the control methods.

[0037] [Figure 26] FIG. 26 is a block diagram depicting a hybrid control approach that incorporates aspects of the control readiness and predictive methodologies described herein.

[0038] [Figure 27] FIG. 27 is a block diagram illustrating an example control architecture that may be used to implement the control functionality of FIG.

[0039] [Figure 28] FIG. 28 is a block diagram illustrating an example control architecture that may be used to implement the control functionality of FIG.

[0040] [Figure 29]FIG. 29 is a block diagram illustrating an example control architecture that may be used to implement the control functionality of FIG.

[0041] [Diagram 30] FIG. 30 is a flow chart depicting a method that may be followed in connection with embodiments disclosed herein.

[0042] [Diagram 31] FIG. 31 illustrates an embodiment of a delay / amplitude estimator.

[0043] [Diagram 32] FIG. 32 illustrates another embodiment of the delay / amplitude estimator.

[0044] [Diagram 33] FIG. 33 illustrates a delay / amplitude estimator with a specific embodiment of the processor and filters.

[0045] [Diagram 34] FIG. 34 illustrates details of a time shift error generator, which may or may not be identical to the time shift error generator shown in FIGS. 31-33.

[0046] [Diagram 35] FIG. 35 is a flow chart illustrating a method of predictive control.

[0047] [Diagram 36] FIG. 36 provides an illustrative example of the noise removal process.

[0048] [Figure 37] 37A and 37B depict graphs of normalized signal amplitude versus time for a controlled parameter according to various aspects of the present disclosure, and control output values ​​used to adjust an actuator according to various aspects of the present disclosure.

[0049] [Figure 38] FIG. 38 illustrates a detailed schematic diagram of the predictive control section of FIG. 23B in accordance with one or more aspects of the present disclosure.

[0050] [Figure 39] FIG. 39 is a block diagram illustrating an example control architecture that may be used to implement the control functionality of FIG. 20 in accordance with various aspects of the disclosure.

[0051] [Diagram 40] FIG. 40 illustrates an example of a process flow that may be implemented in the predictive control section of FIGS. 20, 21, 23A, and 23B in accordance with various aspects of the present disclosure.

[0052] [Diagram 41] FIG. 41 is a flow chart depicting a method for controlling aspects of a plasma processing system.

[0053] [Diagram 42] FIG. 42 is a block diagram depicting aspects of a computing system that may be utilized in connection with the embodiments disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] Detailed Description The present disclosure relates generally to RF generators for plasma processing, and more specifically to more efficient control of rail voltages used to power RF power amplifiers that produce multi-level pulsed outputs.

[0055] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0056] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, some blocks in these flowcharts or block diagrams may represent modules, segments, or portions of code comprising one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions described in the blocks may occur out of the order described in the figures. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may sometimes be executed in the reverse order. It should also be noted that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

[0057] Terms such as "first," "second," "third," and the like may be used herein to describe various elements, components, regions, layers, and / or sections, but it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section without departing from the teachings of the present disclosure.

[0058] Spatial relative terms such as "below," "below," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped over, an element described as "below" or "below" or "below" the other element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "below" can encompass both an upward and downward orientation. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein may be interpreted accordingly. Additionally, it should also be understood that when a layer is referred to as being "between" two layers, this may be the only layer between the two layers, or one or more intervening layers may also be present.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that as used herein, the terms "comprises" and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as " / ".

[0060] The embodiments of the present disclosure are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. Thus, variations from the illustrated shapes, for example, as a result of manufacturing techniques and / or tolerances, are expected. Thus, the embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, and include, for example, deviations in shapes resulting from manufacturing. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the present disclosure.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this specification.

[0062] 1 illustrates a system level diagram of a plasma processing system 100 with actuators including a generator 102 for a user to provide various types of waveforms (such as pulsed waveforms) to a nonlinear and / or chaotic load 104 (e.g., plasma load) based on a user-defined power output 106, which may be a person, input from another controller, or input from a control component within the plasma processing 100. The RF generator (or "generator" for short) 102 may include a user interface 108, a master control unit (MCU) 110, a control section 112 (e.g., an FPGA, a CPU, or a combination of FPGA and CPU), and power generation and sensors 114. Other actuators depicted in FIG. 1 include a match network 116, an RF source 118, a bias supply 120, and a power supply 122 coupled to the bias supply 120. 1 may include lower level components (that are subcomponents of the higher level components), such as, for example, but not limited to, DC rail supplies, RF amplifiers, variable capacitors, and direct current (DC) power supplies in bias supply 120. In general, FIG. 1 depicts a multi-actuator and multi-knob nonlinear system, and aspects of the disclosure detailed further herein relate to control for multi-actuator and multi-knob systems.

[0063] In many instances, the actuators of a plasma processing system may include many actuators, where the actuators operate at different speeds. As an example, Figure 3 depicts a power generation system 304 including a fast actuator 314 and a slow actuator 316, and Figure 4 is a graph of the normalized amplitude over time of the fast actuator output (output from fast actuator 314) and the slow actuator output from slow actuator 316. These signals illustrate various other actuator outputs that may be generated using the methods, systems, and devices of the present disclosure, which in various embodiments may be inherently scalable (at least in part due to their tensor nature and their use of tensor signal processing engines).

[0064] In general, the actuator outputs depicted in Figure 4 are values ​​that an actuator physically achieves in response to receiving a corresponding control signal. The value of an actuator output may be, for example, a value of a controlled parameter, such as, for example, but not limited to, voltage, current, phase, frequency, forward power, reflected power, and reflection coefficient. The particular parameter that is adjusted will depend on the actuator being controlled and the control methodology being utilized.

[0065] A "fast" actuator output may be considered fast because its slew rate ((max-min / Tmax-Tmin)) may relatively exceed that of a "slow" actuator output. In other words, over a given amount of time, a fast actuator output may move between values ​​at a rate that is much greater than a relatively slower slow actuator output. Although this disclosure provides many examples in which a fast actuator comprises an RF amplifier and a slow actuator comprises a DC rail, these are merely examples to help explain how the control systems and methodologies disclosed herein operate, and the control methodologies disclosed herein are generally applicable to different types of actuators.

[0066] While Figure 4 illustrates how the actuators may operate over time (e.g., in conjunction with processing steps to vary the output waveform of the power generation system 304), Figure 5A is a graph depicting the time it takes each of the fast actuator 314 and the slow actuator 316 to reach an output in response to a step command. More specifically, Figure 5A shows a graph of the normalized amplitude over time of the fast actuator output and the slow actuator output, with both outputs reacting to a step input and going from a minimum to a maximum value. The normalized cross delay X Dmay be defined as the difference between the time that the slow actuator output reaches its maximum value (due to a step input from minimum to maximum value) and the time that the fast actuator output control reaches its maximum value (due to a step input from minimum to maximum value). Normalized inverse cross delay RX D is the normalized cross delay X D may be defined similarly to, but with a step input going from a maximum to a minimum, the normalized inverse cross delay RX D is the time between the fast and slow controls at which they reach their minimum values. In other words, the normalized cross delay X D can be defined as follows:

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[0067] In the formula, TD F is the control delay of the fast actuator output, and TD S is the control delay of the slow actuator output. Normalized inverse cross delay RX D can be equivalently defined (assuming a response time going from high to low as symmetrical to low to high).

[0068] The control rate or dynamic load demand response time is the control delay TD of the slow actuator output S This time delay does not affect operation as long as it exceeds 100 s. However, due to the fast nature of plasma transients, on the order of a few nanoseconds, DC converters, RF amplifiers, and other actuators can typically only just keep up with the required control ratios or dynamic load demand response times, if at all.

[0069] For example, one illustrative advanced plasma processing system has a fast actuator control output TD for RF amplifier drive / bias voltages in 250 nanoseconds (ns). F and a slow actuator control output TD for DC rail voltages of 1.5 milliseconds (ms). Swhere the slow actuator output is four orders of magnitude slower than the fast actuator output and about six orders of magnitude slower than nanosecond-scale "near-instantaneous" plasma dynamics.

[0070] As another example, a more advanced plasma processing system may have a slow actuator output T D of 1.5 microseconds (μsec). S , which is three orders of magnitude better than the exemplary system shown above, but this response time is still not ideal. In this exemplary system, the added speed of the slow actuator may come at the cost of not reaching high power levels and requiring several RF amplifiers, such as four RF amplifiers, to achieve only 3 kilowatts (kW) of power.

[0071] Another challenge faced in the context of controlling multiple actuators is the asynchronous operation that may occur between the actuators. For example, Figure 5B depicts an example of asynchronous control that may be used in connection with two actuators. Problems associated with differential response times and / or differential delays are addressed by various embodiments disclosed herein.

[0072] According to one aspect of the disclosure, control over the actuators may be performed reactively (as discussed with reference to FIGS. 6-19) to address the latency issues discussed above, and according to another aspect, the actuators may be controlled preemptively (as discussed herein with reference to FIGS. 20-30) to address the latency and asynchronous issues discussed above.

[0073] Referring to FIG. 6, what is shown is a block diagram depicting aspects of a plasma processing system. As shown, a set point 605 (also referred to as a reference signal 605) is provided to a control section 602, which may define a target value or multiple target values ​​for any controlled parameter. Although a single set point 605 is shown in FIG. 6, it should be appreciated that there may be multiple set points (e.g., defining multi-level or arbitrary waveforms) received at the control section 602. In the context of FIG. 6, the set point 605 defines a target output waveform desired at the output of the match network 116. As discussed further herein, the set point 605 may be a streaming set point. The control section 602 may be implemented, for example, in an FPGA and / or other processing components (e.g., a processor associated with processor-executable instructions). The target waveform defined by the set point 605 may be any arbitrary waveform and is not limited to a pulsed waveform such as that seen in FIG. 2. The power generation system 304 attempts to provide an output waveform (e.g., forward power) to the nonlinear and / or chaotic load 104 (e.g., a plasma load) that tracks a target waveform. The control section 602 uses feedback from the output waveform of the power generation system 304 to control the power generation system 304 to track the target waveform.

[0074] A component providing a rail voltage is an example of a slow actuator 316 because the rail typically does not change value as quickly as the fast actuator 314. On the other hand, the fast actuator 314 may use a switching topology or other means to implement rapid changes in current and / or voltage, for example. A half-bridge or full-bridge switching amplifier are two examples of a fast actuator 314. The fast actuator 314 and the slow actuator 316 cooperate to generate an output waveform based on a control signal from the control section 602. The control section 602 may include separate controllers for the fast actuator 314 and the slow actuator 316. For example, the fast controller 610 may control the fast actuator 314 and the slow controller 612 may control the slow actuator 316. The fast controller 610 and the slow controller 612 may cooperate to control aspects of the power generation system 304. For example, the fast controller 610 may instruct the slow controller 612 to instruct the slow actuator 316 to provide additional power to the fast actuator 314 when the fast controller 610 recognizes that the fast actuator 314 cannot provide enough power to follow the target waveform at a given power level provided by the slow actuator 316. However, it should be understood that while the slow actuator 316 may provide power to the fast actuator 314, in other embodiments the fast actuator 314 may provide power to the slow actuator 316.

[0075] 7, a method that may be implemented in the slow speed controller 612 to select a master state that is the only state that may reduce the output of the slow speed actuator 316 is described. Both the fast speed controller 610 and the slow speed controller 612 have a bias range of 0-100%. Assuming that the slow speed actuator 316 provides power to the fast actuator 314, the slow speed controller 612 may assign a master state (block 702) at any time that the fast speed controller 610 commands the slow speed controller 612 to increase the power level of the slow speed actuator 316. The slow speed controller 612 may also assign a master state (block 704) at the end of any repeating sequence of power output (e.g., pulse cycle) to the previous state that requires the highest fast power delivery section output for the current repeating sequence of power output. In some cases, the master state selected in block 704 will be different from that selected in block 702. As power delivery progresses, if the state that was assigned as the master state returns, the slow speed controller 612 checks whether the slow speed actuator 316 can reduce its output while still allowing the power generation system 304 to track the target waveform for that state (decision 706). If so, the slow speed controller 612 commands the slow speed actuator 316 to reduce its output (block 708). These two master state selections in blocks 702 and 704 may then be repeated until all repeated sequences of power output are completed (decision 710).

[0076] Alternatively, FIG. 8 illustrates another method for controlling the fast actuator 314 and the slow actuator 316. Although the method 800 focuses on the determination within a single pulse, in view of the present disclosure, one skilled in the art can extend the method 800 to multiple pulse cycles without undue experimentation. The method 800 begins by generating a multi-level power waveform based on a target waveform using the fast actuator 314 to derive power from the fast actuator 314 (block 802). RF power amplifiers and DC rails are individual non-limiting examples of the fast actuator 314 and the slow actuator 316 discussed in the method 800. The generated waveform may have multiple pulse cycles, with each pulse cycle having multiple repeating pulses, and each pulse may have three or more states with each state having a different power level. The method 800 further includes controlling the fast actuator 314 with a control or drive or bias range (block 804). The upper limit of this range is further illustrated herein as the dashed horizontal line in Figures 13C, 14C, 15C, 116C, 17C, 18C, and 19C, which are all approximately 5V, for example. In addition to controlling the fast actuator 314, the method 800 also controls the slow actuator 316 (block 806). Given these control parameters and the target waveform, the slow controller 612 ramps up the slow actuator 316 (block 810) if the target waveform requires the fast actuator 314 to exceed its output range (i.e., exceed the range of the fast controller 610) (decision 808=yes). If such a condition exists (e.g., the state ramps up the rail voltage), the method 800 makes that state (which ramped up the output of the slow actuator 316) the master state (block 812). The method 800 then determines whether the current pulse has ended (decision 814). If the target waveform can be met within the range of the fast actuator 314 (ie, within the range of the fast controller 610) (decision 808=N / A), no changes in the slow actuator 316 or master state occur.However, for each state, the method 800 checks to see if the current state is the master state (decision 818) and, if so, allows the current state to reduce the output of the low-speed actuator 316, if possible (decision 820). If both conditions are not met (decision 820=no), the method 800 determines if the current pulse has ended (decision 814). If both conditions are met (decision 820=yes), the low-speed controller 612 commands the low-speed power delivery section 316 to reduce its output (block 822) and then the method 800 determines if the current pulse has ended (decision 814).

[0077] Regardless of how method 800 arrives at the pulse end determination (decision 814), if the pulse is not ended, method 800 proceeds to the next state (block 815). If the pulse is ended, method 800 assigns the master state to the previous state in the current one of the pulse cycles that had the greatest fast power delivery section control signal (block 816) and proceeds to the next pulse (decision 824).

[0078] 9, shown is a block diagram depicting an exemplary plasma processing system 900 in which the power generation and sensor 914 of the generator 102 comprises a DC section 908, which is an example of the slow actuator 316, and a power amplifier 906, which is an example of the fast actuator 314. The UI 108 controls the user selected phase / drive threshold or reference voltage

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[0079] The RF driver 902 provides a phase / drive control signal.

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[0080] The control functionality of the generator 102 depicted in FIG. 9 is distributed between an RF controller 910 and a DC controller 913. In particular, the RF controller 910 determines the phase / drive signals based on an error signal that is produced based on the difference (produced by a summing junction 911) between the target waveform (defined by the setpoint 605) and a feedback signal from a sensor 905 (representing the output waveform). If the desired power output can be achieved solely through adjustment of the power amplifier 906 (i.e., at the current rail voltage), then the RF controller 910 simply commands the RF driver 902 to provide a control signal to the power amplifier 906 that corresponds to the desired power output for that state. However, if the desired power output is achieved when the phase / drive control signal is adjusted to a reference voltage

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[0081] When the next pulse begins, the master state from the previous state can remain the master state as long as there was no previous state in the pulse cycle that required a higher drive / phase voltage. Whenever either of these two situations occurs and the master state rolls around again in this next pulse, the controllers 910 and 912 will look at the power requirement from the target waveform and determine if it can be met without raising the rails, and if the rails can be lowered while still achieving the target waveform. If power can be lowered for this state, the DC controller 913 will apply the rail control signal V to the DC section 908 to lower the rails. cc At the same time, RF controller 910 commands DC / rail driver 904 to pass phase / drive control signals to power amplifier 906 to adjust its output to meet the power requirements for the current state (a level that may be lower than the degraded rail).

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[0082] The RF power amplifier 906 is controlled by either a drive voltage or a phase signal, and thus the control signal is represented as Phase / Drive Control Signal

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[0083] A specific embodiment of the DC controller 913 can be seen in Figure 10. The DC controller 1013 is configured to compare the threshold value with the threshold value of the previous pulse.

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[0084] The rail reduction component 1010 can determine whether to reduce the output of the DC section 908 while keeping the drive / phase voltage of the RF power amplifier 906 below the drive / phase voltage threshold based on whether the target waveform can be met using a lower DC section output. In other words, typically, as the rail voltage is reduced, the drive / phase voltage is increased so that the combined changes still meet the target waveform of the setpoint 605. If the rail is reduced too much, the drive / phase voltage will be raised above the drive / phase voltage threshold, and such a decision would typically not be accepted. Instead, the rail voltage will be reduced to a certain limit as possible while keeping the drive / phase voltage below the drive / phase voltage threshold. In some cases, the control algorithm attempts to push the drive / phase voltage just below the threshold, thereby maximizing the rail reduction for a given condition. On the other hand, some control algorithms may prefer a controller that keeps the drive / phase voltages slightly further below the threshold and reduces the rails less for a given condition, i.e., slower response, but which may lead to greater stability. The design of this aspect of the controller does not change the way in which this disclosure is implemented and should be left to the designer to choose the preferred tradeoff.

[0085] The operation of the controllers 910 and 912 can be further illustrated through reference to the method 1100 shown in FIG. 11 and the plots of FIG. 13-1913. FIG. 7A, 7B, and 7C show example timing diagrams for the generator's target waveform (FIG. 13A) (e.g., the output of the power amplifier 906 or the generator 102), rail voltage (FIG. 13B), and drive / phase voltage (FIG. 13C) over eight different pulse cycles. As shown, the output power is equal to the target waveform (i.e., effective power tracking is achieved in most cases of the present simulation), but FIG. 14A, 14B, 14C and FIG. 16A, 16B, and 16C show several cases where the target waveform is not reached immediately in response to changes in the target waveform. The rail voltage (e.g., as provided by the DC section 908) is a variable that is slow to control and can be controlled more efficiently than was possible in the prior art (e.g., lowering the rail voltage more frequently than was possible in the art). The drive or phase voltage output by the power amplifier 906 is a controllable aspect of the RF power amplifier 906. The eight illustrated pulse cycles in Figures 7A-19C are walk-through waveforms derived from simulations and illustrating various features of the method 1100 that are not known in the art. Figures 7A-19C provide more detailed views of certain pulse cycles from Figures 13A-13C. Each pulse cycle has a different number of pulses, and each pulse has a different number of states. For example, in Figures 8A, 8B, and 8C, a first and second pulse cycle can be seen, each with three pulses, and each pulse has four states. In Figures 15A, 15B, and 15C, a third and fourth pulse cycle can be seen, with the third pulse cycle having three pulses and five states per pulse, and the fourth pulse cycle having four pulses and five states per pulse cycle. In these simulated pulse cycles, the RF power amplifier 906 is seen to determine the rail voltage from the DC section 908 and then uses the drive or phase voltages to determine the final output power based on the available rail voltage.The threshold can be seen as a dotted line near 5V in the bottom plot, and whenever the drive / phase voltage reaches or exceeds this threshold, the rail voltage is raised to provide more power to the RF power amplifier 906. In some cases, the rail does not rise fast enough to meet the increased power requirements of the target waveform, and multiple threshold crossings in a short period of time can occur as the rail is raised in a stepwise fashion, such as illustrated in Figures 17A, 17B, and 17C (where the target waveform is not reached until the fifth pulse in the pulse cycle). The third and fourth cycles in Figures 15A, 15B, and 15C show an instance where the power requirements of the target waveform are low enough that the rail voltage can be lowered, reducing power consumption and heating compared to the prior art method. Figures 14A, 14B, and 14C also show a comparison between the conventional method for raising the rail voltage and that of the present disclosure. It can be seen that the first threshold crossing leads to a rail voltage increase which in the conventional method would have been raised to the rail maximum, but in the present disclosure the rail is raised to about 100V and then at the next threshold crossing it is raised again to the rail maximum of around 140V. As a result, this more granular tracking of the target waveform leads to a significant reduction in wasted power as seen in the area between the dashed line (resulting from the conventional "2-level algorithm") and the solid line (resulting from the N-level algorithm disclosed herein).

[0086] The user can begin the process by setting the number of pulse cycles (max_PC), the number of pulses in each pulse cycle (max_n), and the number of states in each pulse (max_S) (block 1102). When power delivery begins (i.e., the first pulse cycle), and at the beginning of each subsequent pulse cycle, the master state start can be arbitrary (i.e., any (or none) of the states in the first pulse of a pulse cycle can be the master state) (block 1104), since the method 1100 avoids relying on memory of states or drive / phase voltages during the cycle. In other words, each pulse cycle selects a new first master state without knowledge of or reliance on any master state from previous pulse cycles, and thus the initial master state can be chosen arbitrarily by the designer. Along these same lines, once the first master state is determined in a pulse cycle, that master state cannot degrade the rail until at least the second pulse in the current pulse cycle. In other words, even if a state raises a rail and becomes the master state in the first pulse of a new pulse cycle, it will not be able to lower the rail voltage until the second pulse in the pulse cycle. This feature is illustrated in FIG. 9. The exception to this rule is when a state attempts to raise a rail voltage and then lower the voltage rail, both in the same state. In this case of a rapid rise and fall of the rail voltage, the first state will be able to perform this rail drop. This is the exception to block 1104, but the exception is not explicitly illustrated.

[0087] Then, for the current state, the DC controller 913 determines, for example, the required drive / phase voltage

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[0088] For example, in Figures 14A, 14B, and 14C, for the first state of the first pulse of the first pulse cycle, the power requirement of the target waveform is fairly low, about 85V, and therefore a relatively low drive / phase voltage is capable of achieving this target waveform even though the rail voltage starts out fairly low (about 85V). Thus, decision 1106 for the first state of the process will be N / A. If decision 1106=N / A, the rail controller can determine whether the current state has become the master state via a previous decision. For example, a previous threshold crossing (decision 1106) or a previous end of pulse identification (block 1116) may set the master state for the current pulse even if the current pulse does not experience a threshold crossing. More specifically, state 5 in the first pulse of pulse cycle 3 is the state with the highest drive / phase voltage in pulse cycle 3.

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[0089] Returning to decision 1107, if the current state is not the master state, method 1100 determines whether the current pulse has ended (decision 1112). Similarly, after the rail is lowered (block 1109), method 1100 determines whether the current pulse has ended (decision 1112). If not, method 1100 proceeds to the next state and the decisions (at block 1106, and possibly at block 1107) are repeated. For example, for the first three states of each pulse in the first pulse cycle, decision 1112=not applicable, and method 1100 loops back to decision 1106 for the next state (block 1114).

[0090] When the end of the current pulse is reached (decision 1112=yes), the RF controller 910 attempts to set the master state based on the previous drive / phase voltages in the current pulse cycle (block 1116). More specifically, the RF controller 910 looks back at the phase / drive voltages per state in the current pulse cycle and identifies the maximum value therein. For example, at the end of the first pulse of the first pulse cycle of Figures 14A, 14B, and 14C, the phase / drive controller will determine that state 4 had the highest drive / phase voltage level for the pulse cycle up to that point, and therefore will set the master state to state 4 (block 1116) (if it was not already the master state). This same analysis at the end of the second pulse will again determine that state 4 had the highest drive / phase voltage level, and therefore will leave state 4 as the master state. In the second cycle, the first state becomes the master state by exceeding the threshold (decision 1106=yes), then state 4 becomes the master when it exceeds the threshold (decision 1106=yes), and at the end of the second pulse, the phase / drive controller will look back at all states in the second pulse cycle and determine that state 4 required the highest drive / phase voltage level, and therefore will leave state 4 as the master state (block 1116). As another example, the phase / drive controller assigns the master state to state 5 in the third cycle, and through this look back analysis, the phase / drive controller assigns the master state to state 3 in the fourth cycle. On the other hand, if state 1 required a higher drive / phase voltage level than state 4 during the first two pulses of the second pulse cycle, the phase / drive controller will make state 1 the master state. As another example, in the third pulse cycle, no state reaches the threshold (decision 1106 ≠ true for any state), but at the end of the first pulse, the phase / drive controller will determine that state 5 had the highest drive / phase voltage level in the third pulse cycle and make state 5 the master state.It should be apparent from these examples that the phase / drive controller, via block 1116, can select a new master state at the end of each pulse.

[0091] In any event, at the end of each pulse, method 1100 determines if the current pulse cycle is finished (decision 1118). If not, method 1100 proceeds to the next pulse (block 1115), and if the pulse cycle is finished, method 1100 assesses if the process is finished (i.e., all pulse cycles have been completed) (decision 1120). If not, method 1100 proceeds to the next pulse cycle (block 1114) and returns to block 1104, where the phase / drive voltages and rail voltages are held the same up to the first state of the new pulse cycle, the master state being arbitrarily selected by the designer.

[0092] Pulse cycle 8 illustrates an additional feature of method 1100 that is not explicitly shown, namely, that the rail voltage has a minimum value. It can be seen that state 3 in pulse cycle 8 becomes the master state via block 1116 at the end of the first pulse and remains the master state in the subsequent pulses because no other state needs to raise the rail (decision 1106) or has a higher phase / drive voltage (block 1116). However, unlike the previous example, even though state 3 is the master state and the phase / drive voltage required to achieve the target waveform is below a threshold (decision 1106=not applicable), the rail controller does not lower the rail voltage as would be required by block 1109. This is because the rail voltage is at a minimum value and therefore cannot be further lowered. In other words, block 1109 would be skipped or not applied if the rail voltage is already at its minimum value.

[0093] FIG. 12 illustrates another n-level control algorithm for RF generator 102. Method 1200 focuses on decisions within a single pulse, but in view of this disclosure, one of ordinary skill in the art can extend method 1200 to multiple pulse cycles without undue experimentation. Method 1200 begins by generating a multi-level power waveform based on a target waveform using an RF power amplifier with variable output and deriving power from DC section 908, which provides a variable rail voltage (block 1202). A multi-level (or n-level) power waveform can be seen, for example, in FIG. 13A. The multi-level power waveform (output or generated waveform) and the target waveform (input) are typically close in shape for the method to be effective in tracking the target waveform, and therefore, for purposes of this disclosure, FIG. 13A will be used to discuss both the input and output waveforms. RF power amplifier 906 and DC section 908 are non-limiting examples of the RF power amplifier and DC section discussed in method 1200. The generated waveform has multiple pulse cycles, each pulse cycle having multiple repeating pulses, and each pulse has three or more states, each state having a different power level.

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[0094] Regardless of how method 1200 arrives at the pulse end determination (decision 1214), if the pulse has not ended, method 1200 proceeds to the next state (block 1215). If the pulse has ended, method 1200 continues by determining whether the maximum drive voltage

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[0095] 20, shown is a block diagram depicting aspects of a predictive and tensor control approach that may be utilized in connection with a plasma processing system 2000. Shown in FIG. 20 is a tensor control block 2001, coupled to the user interface 108, actuators 2008, and sensors 905. Shown within the tensor control block 2001 is a delay / amplitude estimator 2004 and a predictive control section 2012. The tensor control block 2001 (also referred to as the detection, estimation, and prediction engine 2001) represents the collective functionality of the delay / amplitude estimator 2004 and the predictive control section 2012. As discussed further herein, the delay / amplitude estimator 2004 and the predictive control section 2012 may be further separated or merged into functional subcomponents, and the functionality of the delay / amplitude estimator 2004 and the predictive control section 2012 may be performed in a pipeline processing type approach or may be provided continuously, as will be understood by those skilled in the art in light of this disclosure.

[0096] With reference to FIG. 20, reference is simultaneously made to FIG. 30, which is a flow chart depicting steps that may be traversed in connection with the embodiments disclosed herein. The user interface 108 is configured to receive (block 3002) a set point 605 that defines a target value (or set point) for a controlled parameter applied to a controlled output in the system. The target value may represent a multi-level pulsed waveform or any arbitrary waveform. As shown, the controlled output in the system 2000 may include a load output 2030, which is a node coupled to a nonlinear and / or chaotic load 104, and / or the controlled output may include one or more actuator outputs 2032. In other words, the tensor controller 2001 may be used to control one or more controlled parameters in the load output 2030, which may include power-related parameters, including, for example, but not limited to, DC power, forward power, reflected power, reflection coefficient, frequency, and current. In addition, the tensor controller 2001 may be used to control the controlled parameters applied in the actuator output 2032. The controlled parameters applied to the actuator outputs 2032 may include the power-related parameters listed above (with respect to the output 2130 (load output)) and control-related parameters such as phase control signals, frequency control signals, and voltage control signals. In addition, one or more particular actuator outputs 2032 may be fed as inputs 2034 to one or more other actuators 2008.

[0097] As shown, the at least one sensor 905 is configured to obtain measurements of parameters (block 3004), such as the power-related and control-related parameters listed above. The at least one sensor 905 may include, for example, but not limited to, directional couplers, VI sensors, current transducers, and simple voltage sensors. Those skilled in the art will appreciate that signals from the at least one sensor 905 may be sampled and converted to a digital format for use by the tensor controller 2001.

[0098] The delay / amplitude estimator 2004 is configured to calculate (block 3006) a delay between a target value of the reference signal and a corresponding actual parameter value achieved at the controlled output. The delay / amplitude estimator 2004 is also configured to provide (block 3008) a time-shifted amplitude error 2052 indicative of an error between the target value and the actual parameter value based on the delay. According to one aspect, the predictive control section 2012 is configured to adjust (block 3010) at least one of the actuators 2008 (based on the delay 2050 (at block 3006) and the time-shifted amplitude error 2052 (at block 3008)) in advance of when an actual parameter value is required (at the actuator output of at least one actuator) while beneficially maintaining a controlled parameter at the controlled output within a threshold range.

[0099] For example, and referring briefly to FIG. 25, what is shown is an actuator output 2534 (e.g., rail voltage V ) that is produced (using the tensor controller 2001) in response to a desired setpoint that comprises three pulses, each pulse including three target values ​​(desired at the controlled output for the controlled parameter), namely, state 1, state 2, and state 3. rail2 is an example of a control system for load output 2030. Each state of the desired setpoint corresponds to a target value of a controlled parameter (e.g., forward power) at output 2030. As shown, during pulse 1, actuator output 2534 is adjusted at t1, very closely related to the time when this is needed, i.e., at the time of the setpoint change from state 1 to state 2. However, during pulse 2, actuator output 2534 is adjusted at t2, prior to when actuator output 2534 needs to be increased to produce the target value of state 2 at output 2030. As a result, the controlled parameter (e.g., forward power) at the controlled output (e.g., load output 2030) will reach the desired setpoint faster than previous control methodologies that attempted to minimize energy dissipation (using actuator output 2562) and faster than previous methods that attempted to maximize speed of response (using actuator output 2564). As discussed further herein, the predictive functionality of the predictive control section 2012 enables the tensor controller 2001 to adjust an actuator (e.g., rail voltage) ahead of time when this is needed by predicting the effect of adjusting the actuator ahead of time when this is needed, so that adverse outcomes (e.g., setpoint errors or overvoltage conditions) are avoided.

[0100] For example, referring to Figures 22A, 22B, and 22C, shown are three graphs each depicting the same desired set point shown in Figure 25 with the same three desired states per pulse. Figure 22A depicts the controlled parameter actually achieved in the controlled output using predictively produced actuator output 2534, Figure 22B depicts the controlled parameter actually achieved in the controlled output using actuator output 2562, and Figure 22C depicts the controlled parameter actually achieved in the controlled output using actuator output 2564. As shown in Figure 22A, the controlled parameter is closer to the desired set point during pulse 2 when the controlled actuator is controlled to produce actuator output 2534 (in advance of when this is needed) compared to the controlled parameter value in both Figures 22B and 22C.

[0101] As discussed further herein, the delay / amplitude estimator 2004 may be implemented with different levels of complexity, but in general, the delay / amplitude estimator 2004 is configured to detect a delay 2050 between a desired set point (from the user interface 108) and the time when the actual output of one or more actuators 2008 reaches the set point. As discussed further herein, the reference may be a time-varying streaming set point (e.g., a set point reflecting the pulses and states of FIG. 2), and as discussed further herein, the delay 2050 may be determined based on a cross-correlation between the streaming set point and the actual time-varying output of one or more actuators 2008 in the system. Also, as discussed further herein, the delay 2050 may be a simple delay (e.g., between the set point and the output when the set point is achieved), or a delay 2050 based on several constituent delay components, including a delay within the actuator 2008 and / or an external delay outside the actuator 2008. Using knowledge of the delay 2050, the delay / amplitude estimator 2004 may continually determine a time-shifted amplitude error 2052, which generally indicates an error value based on the difference between the streaming setpoint and the output determined after the streaming input and output waveforms have been relatively time-shifted (based on the delay 2050) such that a portion of the output waveform is aligned with a corresponding portion of the reference waveform that gave rise to the portion of the output waveform. Once the output waveform is aligned with the streaming setpoint, an error value represented as the time-shifted amplitude error 2052 may be calculated.

[0102] The predictive control section 2012 utilizes delay 2050 and time shifted amplitude error 2052 to predict how the control signal and / or actuator output will react to a potential control signal change prior to actually changing the control signal. By predicting how the actuator output will be affected (prior to actually changing the control signal to the actuator 2008), the predictive control section 2012 may adjust the control signal to achieve a desired result. For example, based on the predicted control signal output, the predictive control section 2012 may adjust the control output to reduce the time it takes to achieve a desired actuator output, to reduce energy dissipation, to prevent damaging over-voltage and / or over-current conditions, and / or to achieve any desired balance between speed, accuracy, and energy.

[0103] It should be appreciated that Figure 20 is a simplified depiction of what may be implemented at the tensor level with many set points, many control signals, and many actuators 2008. It should also be appreciated that the actuators may be higher level actuators (such as generators, match networks, RF sources, and bias supplies) and lower level components within the higher level actuators. For example, the DC section 908 and the power amplifier 906 are examples of actuators within a generator that may be controlled (as discussed further herein as a non-limiting example). As a further example, the voltage of the DC section may be controlled and the frequency of the power amplifier may be controlled using the tensor controller 2001.

[0104] As another example, the match network 116 is an example of an actuator 2008, which also comprises an actuator, such as a variable capacitor, that may be controlled using the delay estimation and predictive control aspects of the delay / amplitude estimator 2004 and predictive control section 2012, respectively. For example, it is envisioned that the variable capacitor of the match network 116 may be controlled using the delay / amplitude estimator 2004 and predictive control section 2012, either alone (e.g., based on reflected power) or in conjunction with the variable frequency drive of the generator 102. As a further example, the bias supply 120 is an actuator 2008, which comprises actuators 2008, such as a power supply (e.g., for establishing rail voltages) and a switching section for establishing timing of a periodic asymmetric voltage waveform. These actuators 2008 of the bias supply may be controlled (using the estimation and prediction techniques of the delay / amplitude estimator 2004 and predictive control section, respectively) to control the bias supply 120. Alternatively, other actuators of the bias source may be controlled in consideration of other actuators, such as the RF source 118 and / or the generator 102, to synchronize the bias source 120, the RF source 118, and / or the generator 102 to achieve a desired plasma processing recipe result and / or to prevent undesired plasma modulation (e.g., due to intermodulation frequencies).

[0105] More generally, various aspects of delay estimation and prediction control may enable direct unhindered (or response delay-free) control of parallel multi-actuator or multi-knob nonlinear control systems (such as plasma processing systems 100, 2000). Controllers utilizing delay estimation and prediction may enable more responsiveness of parallel multi-actuator nonlinear and / or chaotic control systems (e.g., maximizing dynamic range in real time). Also, the delay estimation and prediction aspects of the present disclosure may enable improved control of parallel multi-actuator nonlinear and / or chaotic control systems (e.g., to maximize speed of response and achieve the shortest response time to reach a desired setpoint value). The delay estimation and prediction aspects may also enable all of the above functions and advantages to be achieved even when some of the actuators of the control system are arbitrarily slower than other actuators of the control system.

[0106] Another aspect of the delay estimation and predictive control of the present disclosure may allow all of the above functions and advantages to be achieved even when multi-level pulsing with a number of states (up to an arbitrary number) is desired and / or arbitrary waveform tracking is required for nonlinear and / or chaotic dynamic loads. Yet another aspect may also allow all of the above functions and advantages to be achieved while minimizing the control energy expended in the system. As discussed further herein, the delay estimation and predictive control aspect may also allow all of the above functions and advantages to be achieved while protecting the hardware from failures associated with high dissipation, high current, and / or high voltage. Yet another aspect of the delay estimation and predictive control methodology may also allow all of the above functions and advantages to be achieved while making sure that all the different actuators work together cooperatively such that no actuator is controlling itself in a manner that impedes, impedes, or interferes with the control of the other actuators in a way that would cause the system response to be slower or require more energy to be achieved from any or all of the other actuators.

[0107] 21, shown is a plasma processing system 2100 comprising a generator 2102 similar to the generator 102 depicted in FIG. 9, except that the control aspects of the generator 2102 differ from the generator 102. The generator 2102 depicted in FIG. 21 is presented as a non-limiting example of an actuator 2008, which is a higher level actuator, in which the control aspects of the delay / amplitude estimator 2004 and predictive control section 2012 may be implemented. In the depicted generator 2102, the DC section 908 and the power amplifier 906 are examples of actuator 2008, which is a lower level actuator described with reference to FIG. 20. More specifically, the DC section 908 is an example of the slow actuator 316, and the power amplifier 906 is an example of the fast actuator 314, described with reference to FIGS. 3, 4, 5A, and 5B.

[0108] As shown, both the delay / amplitude estimator 2004 and the predictive control section 2012 receive measurements of a controlled parameter that is controlled at an output 2130 in the plasma processing system 2100. In this example, the output 2130 is at the output of the match network 116, but in other cases, other outputs and other parameters in the plasma processing system 2100 may also be measured (depending on the delay to be calculated). In addition, the delay / amplitude estimator 2004 and the predictive control section 2012 receive a reference signal that defines a target value for the controlled parameter that is controlled at the output 2130. The controlled parameter that is controlled at the output 2130 depicted in FIG. 21 may be, for example, at least one of a forward power, a reflected power, and a reflection coefficient.

[0109] The delay / amplitude estimator 2004 is configured to calculate a delay between a target value of the reference signal (e.g., a forward power value of a multi-level pulsed waveform) and a corresponding actual controlled parameter value achieved at the output 2130. Additionally, the delay / amplitude estimator 2004 is configured to provide a time-shifted amplitude error 2052 indicative of the error between the target value and the actual parameter value based on the delay.

[0110] In this example, the predictive control section 2012 predicts the actual voltage V while maintaining a control parameter (e.g., forward power) at the output 2130 within a threshold range. rail is configured to adjust DC section 908 based on the delay and time shift amplitude error 2052 prior to when is needed at the actuator output 2132 of DC section 908. The threshold range may be, for example, ±0.5% of a target value (e.g., a forward power value) defined by the reference signal.

[0111] The threshold range may also be based on the change or difference in error between the desired reference set point and the achieved set point per time step. In some implementations, for example, continuously, the predictive control section 2012 may effect adjustments to the DC section 908 quickly and frequently within each control clock cycle to achieve the desired speed and / or energy dissipation. However, the predictive control section 2012 may also dynamically provide upper and lower limits for the allowable change in the magnitude of the DC section 908 such that at any instant in time (under steady state conditions), the predictive control section may maintain the desired or achieved set point error at, near, or close to zero. In other words, under steady state conditions, the change or difference in the error of the steady state measurement per time step may be maintained as follows:

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[0112] To maintain Equation 2, the predictive control section 2012 calculates the rail voltage V over a system time step. rail Change in set point amplitude of

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[0113] Predictive control section 2012 is for rail voltage V rail , while the predictive control section 2012 limits the change in the specific rail voltage V to provide the desired power condition at the output 2130. rail The rail voltage V rail begins to change, the rail voltage V rail may be preemptively adjusted (due to the inherent delay of the DC section 908). In addition, as discussed further herein, the rail voltage V rail may be adjusted (based on predicted energy dissipation) to reduce energy losses while at the same time reducing the rail voltage V rail is bounded to mitigate against any error between the target value of the controlled parameter (defined by the reference signal) and the actual parameter value applied at the output 2130. More specifically, the error mitigation (e.g., to maintain a threshold level of error) is achieved by adjusting the rail voltage V such that the power amplifier 906 can adjust to maintain the parameter at the output 2130 at the desired setting (set by the reference signal). rail This is achieved by bounding the change in

[0114] 23A, what is shown is a block diagram depicting a control section 2301A comprising, among other components, a delay / amplitude estimator 2004 and a predictive control section 2012. As shown, the control section 2301A comprises a setpoint streaming module 2310 coupled to both the delay / amplitude estimator 2004 and a frame synthesizer and combiner 2312, which is also coupled to the delay / amplitude estimator 2004. Additionally, an optional energy controller 2322 is shown coupled to the delay / amplitude estimator 2004 and to a predictor 2306, which is functionally shown as part of the predictive control section 2012. The optional energy controller 2322 comprises an energy calculator 2318 and a state duration adjuster 2320, which form the depicted connection between the optional energy controller 2322 and the predictor 2306. Also shown within the predictive control section 2012 is a controller 2308 configured to provide one or more actuator control signals 2054. Those skilled in the art will appreciate, in light of this disclosure, that the functional entities depicted in Figure 23A may be combined into fewer functional units or further separated. Also, the functional entities depicted in Figure 23A may be implemented across different types of underlying hardware, such as a programmed field programmable gate array (FPGA) or one or more processors (also referred to as CPUs) capable of executing processor executable code stored in memory.

[0115] For example, referring to FIG. 23B, shown is another control partition 2301B, which is an example of how the control partition 2301A depicted in FIG. 23A may be realized across hardware. More specifically, the frame synthesizer and combiner 2312 may be implemented by processor executable code executed by a processor (e.g., as part of a central processing unit (CPU)). Also, in FIG. 23B, the setpoint streaming module 2310 of FIG. 23A is distributed between a first setpoint streaming module 2310A (the first setpoint streaming module 2310A is implemented by processor executable code executed by a processor (e.g., as part of a central processing unit (CPU))) and a second setpoint streaming module 2310B, which is implemented by a programmed FPGA. In addition, the frame reader 2302 and the TSP RAM are both coupled together, both arranged between the frame synthesizer and combiner 2312, and both coupled to each other. The remaining components depicted in FIG. 23A (other than the frame synthesizer and combiner 2312 and the setpoint streaming module 2310A) are implemented by the programmed FPGA of FIG. 23B.

[0116] In operation, the frame synthesizer and combiner 2312 functions to remove noise from measurements received from the sensors 905 and generate frames from the cleaned measurement data. For purposes of this disclosure, a frame is a set of samples processed in a batch, so a frame can be processed in parallel and then the output of the frame processing can be serialized. The frame or synthesized frame data can be provided to the delay / amplitude estimator 2004 to enable parallel processing of the synthesized frame data. An aspect of the frame synthesizer and combiner 2312 is that it allows measurements to be formatted to more easily fit into the structure of an FPGA.

[0117] The setpoint streaming modules 2310A and 2310B generally function to receive a target setpoint input (e.g., a desired multi-level pulsed or multi-state setpoint with desired waveform shape and timing specifications per state) from the user interface 108, and the setpoint streaming modules 2310A and 2310B may produce, generate, and transmit (to the delay / amplitude estimator 2004) a setpoint waveform with multiple pulsing levels or states and according to other desired waveform shapes and timing specifications per pulsing level or state. While some conventional exemplary plasma processing systems have requirements for one or two states or one or two level pulsing in a setpoint signal provided to a control module of a controller for the plasma processing system, some emerging exemplary systems may have requirements for four states or four level pulsing, which the setpoint waveform streaming modules 2310A, 2310B may accommodate. More specifically, the setpoint streaming modules 2310A, 2310B, by virtue of their tensorized nature, may receive multiple desired inputs and provide multiple desired outputs as part of a desired setpoint waveform to produce a corresponding multiple-input multiple-output (MIMO) setpoint waveform.

[0118] As shown, the setpoint streaming module 2310A may produce an initial model (first model), Model 1, based on the desired setpoint waveform shape and parameters from a user interface. For example, a user (e.g., a human or a signal from a controller) may specify certain attributes for the setpoint waveform, such as, but not limited to, power level, rise time, overshoot, and steady state value. The setpoint streaming module may also convert these specifications into a system model. Based on the system model (Model 1), the setpoint streaming module 2310A may generate a seed waveform. When generating the seed waveform, an optimized number of uniformly and / or non-uniformly sampled points may be used, and the number of sample points may correspond to a number of points that may reduce the regression or interpolation processing burden in the FPGA (thus reducing time and resource usage). The seed waveform generated by the setpoint streaming module 2310A may correspond to points that define a single entire setpoint waveform pulse cycle for the next two interrupts of the CPU, while omitting any data that is repetitive or redundant for constructing the setpoint waveform. The setpoint streaming module 2310A may transmit the set of seed waveform data to the setpoint streaming module 2310B. Details of implementing an example setpoint streaming module may be found in U.S. Patent Application No. 17 / 509,539, filed October 25, 2021, and entitled “Robust Tensorized Shaped Setpoint Waveform Streaming Control,” which is incorporated by reference.

[0119] A frame reader 2302 associated with the TSP RAM 2304 functions within the FPGA to receive and read frames received from the frame synthesizer and combiner 2312. The TSP RAM may allow for four state or four level pulsing. An example of a TSP-RAM system to which the present disclosure may be adapted is disclosed in U.S. Patent Application No. 17 / 516,578, filed November 1, 2021, and entitled "Tensor Non-Linear Signal Processing Random Access Memory" (incorporated by reference).

[0120] As shown, the delay 2050 output from the delay / amplitude estimator 2004 may be a function of both the system delay 2314 and the device delay 2316, resulting in a total delay n Δtotal More specifically, the device delay 2316 may be an internal delay n d The internal delay n d corresponds to the number of samples between receiving an input to the control sections 2301A, 2301B and generating one or more actuator control signals 2054. This value may be determined during production of the control sections 2301A, 2301B or may simply be read from memory. The system delay 2314 is calculated as an unknown delay n(t) which may be calculated as further disclosed herein with reference to FIGS. 31-34. Δ Equipped with.

[0121] As shown, the predictive control section 2012 uses a second model, Model 2, to calculate the total delay n(t) Δtotaland a predictor 2306 that predicts the result of applying the time shift amplitude error 2052 to one or more actuator control signals 2054, which predictive control section further modifies the one or more actuator control signals 2054 based on the prediction to provide a more robust control signal for one or more actuators 2008 (e.g., DC section 908 and power amplifier 906, etc.) of the plasma processing system 2000.

[0122] Delay (n Δtotal In addition to receiving the time shift amplitude error 2052 and the energy indicator signal 2370 from an energy calculator 2318, the predictor 2306 may receive a state duration adjustment signal 2372 from a state duration adjuster 2320, which are optional components that allow the amount of energy dissipated to be managed. In operation, the energy monitor 516 calculates the energy consumed in any one cycle or system time step as the sum of the integral (over time of the actuator signal) multiplied by a conversion constant to discretize the energy of a single system time step. In the context of slow and fast actuators, the energy consumed may be calculated as follows:

number

[0123] The state duration adjuster 2320 generally operates to calculate the duration of any one state, compare it to the control delay and crossover delay, and then provide a state duration adjustment signal 2372 to enable the predictor 2306 to ensure that the controlled actuators (e.g., DC section 908 and power amplifier 906) have enough time in advance to activate a specific state with the desired level of energy consumption while maintaining fast response behavior.

[0124] 24, shown is an example of a predictive control section 2012. As shown, the predictor 2306 in the embodiment depicted in FIG. 24 comprises a boundary enforcer 2406 in communication with both a boundary detector 2404 and a second model 2403, which also communicates with the second model 2403. As shown, the predictor 2306 generates an adjusted delay signal 2450 (n Δtotal’ ) and the adjusted time shift amplitude error 2452 (time shift amplitude error') to the controller 2308.

[0125] More specifically, the second model 2403 provides a model of the plasma processing system 2000 and allows prediction of how the actuator output 2032 will respond to potential changes in the control signals provided to the actuators 2008. As one skilled in the art would appreciate, the second model 2403 may be generated using a mathematical model for the plasma processing system 2000 as a whole and / or a mathematical model for the individual actuators 2008, which may be augmented with empirical measurements. As shown in FIG. 24, the second model 2403 may be continuously updated based on control feedback 2454 from the controller 2308 and measurements from the sensor 905 (which may provide measurements of the actuator output 2032, such as the controlled parameter value).

[0126] In operation, the second model 2403 determines whether a controlled parameter (e.g., forward power) at the load output 2030 varies with the actuator (e.g., the rail voltage v rail ) would deviate beyond a threshold error to the boundary detector 2404. The second model 2403 may also provide an indication to the boundary detector 2404 as to whether the actuator settings may cause, for example, but not limited to, an over-voltage condition, a runaway control condition, and / or instability. As yet another example, the boundary detector 2404 may also utilize the second model 2403 to determine whether adjustments to the actuator based on the energy indicator signal 2370 and the state duration adjustment signal 2372 would cause an error between the setpoint and the controlled parameter.

[0127] If the boundary detector 2404 detects that controlling an actuator based on the time shift error signal would cause problems, the boundary detector 2404 may pass a boundary enforcement condition to the boundary enforcer 2406, which may produce an adjusted time shift amplitude error signal 2452 that limits the amount the actuator may change. More specifically, the controller 2308 will adjust one or more actuator control signals 2054 provided to the corresponding actuators 2008 based on changes made to the magnitude of the adjusted time shift amplitude error 2452.

[0128] 26, shown is an example of a generator 2602 that utilizes a hybrid approach between the responsive control methodology described with reference to FIGS. 9-19 and the predictive control approach described with reference to FIGS. 20-25. As shown, generator 2602 is similar to generator 102 depicted in FIG. 9, except that tensor controller 2001 may be used to provide a delayed signal 2650RF to RF controller 910 and a delayed signal 2650DC to DC controller 913. In this control approach, the predictive mechanism described with reference to FIGS. 20-25 is not utilized, and thus generator 2602 predicts the rail voltage V in advance of when it is needed. rail While it is not possible to adjust the rail voltages, the delay signals 2650RF, 2650DC may be used to enforce boundaries to limit the amount the rail voltages can be moved.

[0129] 27, 28, and 29, shown are block diagrams depicting various arrangements that may be used to implement the functionality of the delay / amplitude estimator 2004 and predictive control section 2012. More specifically, the variations depicted in Figs. 27, 28, and 29 show mathematical variations for implementing the same functions of the delay / amplitude estimator 2004 and predictive control section 2012 described with reference to Figs. 20-26. For example, with reference to Fig. 27, the functions of the delay / amplitude estimator 2004 and predictive control section 2012 may be distributed among different components. More specifically, the calculations for the time shift amplitude error 2052 are provided by the predictor block, and the calculations for the adjusted time shift amplitude error (time shift amplitude error') are provided by the delay compensator block. The variation of Fig. 27 may be preferred in systems that are limited in terms of computing power.

[0130] In contrast, implementation of the functional aspects of the delay / amplitude estimator 2004 and predictive control section 2012 of Fig. 28 may preferably be performed in a system with a larger amount of computational power due to the parallel processing utilized. More specifically, multiple delay estimator blocks may calculate delay errors for many actuators in parallel, which may be passed to a scalable standard tensor controller, which results in the calculation of a time shift amplitude error, implementing the controller 2308 and predictor 2306. As a result, multiple control signals for the actuators 2008 are provided in parallel.

[0131] 29, shown is yet another variation that can be used with legacy systems that adds additional functionality to compensate for delays in each actuator. As shown, multiple actuator control errors are received at an augmented tensor controller 2902, where each actuator control error is the error between a reference signal for the actuator and a corresponding actuator output. The errors are added as additional states to the tensor controller 2001. In this implementation, the depicted system delay estimator block 2904 calculates the delays based on measurements and set points at the output of the match network.

[0132] 31-36 will delve into the embodiments and details of the delay / amplitude estimator 2004 shown in FIGS. 20, 21, 23A, and 23B. In general, the delay / amplitude estimator 2004 determines (1) a reference signal that defines a target value for a parameter controlled at the output in the system (e.g., a desired waveform setpoint and forward power measured at the output of the match network resulting from the setpoint) and (2) a measurement of the parameter controlled at the output via the reference signal, resulting in a total time delay n(t). Δtotal This also determines the total time delay n(t) Δtotalto determine an amplitude error based on a time shift comparison of the measured value (or actual parameter value) and the reference signal. This amplitude error is the time shift amplitude error referred to above. The amplitude error takes noise and dynamic uncertainties into account to a large extent, allowing the system to counteract them. The total time delay and time shift amplitude error are used in the predictive control section to predict the actuator output and further modify the control signal to the actuator to achieve the desired output within the noise and dynamic uncertainty thresholds. The adjusted control signal can then be passed to the driver or other actuator to achieve the desired output. In essence, the actuator control signal can be modified prior to timing dictated by the reference signal alone. This optimizes output parameters such as power efficiency that may be degraded by delays in the system. Similarly, the control signal can be adjusted prior to the reference signal (setpoint) timing to take into account the predicted maximum noise and dynamic uncertainties, again optimizing the output parameters and keeping the output within the threshold range.

[0133] More specifically, the delay / amplitude estimator performs a cross-correlation between the measurement waveform (or discretized data) and the setpoint waveform (or discretized data) using a set of initial guesses regarding the total time delay between the measurement waveform and the setpoint waveform. The time delay determined by this cross-correlation can be used in the predictive control section to adjust the control signal. At the same time, the delay / amplitude estimator can identify noise and dynamic uncertainties in the measurement signal / value and provide errors or compensation for these amplitude errors to the predictive control section. In some cases, a maximum bounded limit resulting from the noise and dynamic uncertainties can be used to provide more robust control. The predictive control section can then use these amplitude errors and time delays to predict the outcome at the actuator if a corresponding control signal is passed to the actuator and further adjust the control signal based on this prediction. For example, the predictive control section 2012 may dynamically place upper and lower limits on the allowable change in actuator magnitude so that at any instant in time (under steady state conditions), the predictive control section 2012 may maintain the desired setpoint or achieved setpoint error at, near, or close to zero. Details of this prediction will be further explained with respect to Figures 37-41. The reference signal can take a variety of forms, including, for example, a time-varying streaming setpoint, such as an arbitrary waveform or a pulsed waveform as seen in Figure 2.

[0134] In some implementations, the delay / amplitude estimator may group measurements and setpoints into frames to allow for parallel processing of the comparison, cross-correlation, and calculation. When measurements y(t) are grouped into frames, the measurements are expressed as y i [k], where i is the frame number and k is the sample number within a given frame. When the setpoint waveform r(t) is divided into a group of frames, the discretized waveform is i[k]. Frames of repeating setpoints can be analyzed together (in parallel), which is particularly useful when pulsed or periodic waveforms are used. One time delay can be determined for each frame, allowing these delays to be determined in parallel on a processor such as an FPGA, CPU, or a combination of the two that runs the delay / amplitude estimator. The frame data can be generated in the setpoint streaming as described above or within the delay / amplitude estimator (see, for example, optional estimator frame combiner 3203 of FIGS. 32 and 33).

[0135] In some embodiments, the set points and measurements can be grouped into frames via a frame combiner, such as frame combiner and combiner 2312 of FIG. 23A, to enable parallel processing of the frames. The frame combiner and combiner 2312 can clean the measurements and generate frames from the cleaned data. For purposes of this disclosure, a frame is a set of samples processed in a batch, and thus, the frames can be processed in parallel and then the output of the frame processing can be serialized. The frames or the combined frame data can be provided to a hypothesis tester 3108 to enable parallel processing of the combined frame data (i.e., processing in parallel frames).

[0136] More generally, various aspects of the delay / amplitude estimator may enable direct unhindered (or no response delay) control of parallel multi-actuator or multi-knob nonlinear control systems (such as plasma processing system 100). More specifically, the delay / amplitude estimator enables (1) deterministic measurement, control, and aggregation of signal amplitude; (2) simultaneous amplitude and phase sinusoidal measurement, control, and signal aggregation; (3) simultaneous amplitude, phase, and frequency sinusoidal measurement, control, and signal aggregation; (4) time delay, cross delay, and inverse cross delay for measurement, control, and aggregate arbitrary signals; (5) time delay, cross delay, and inverse cross delay for measurement, control, and aggregate arbitrary signals when data is merged from multiple sensing or processing sources; (6) all of the above for n → infinity sinusoidal measurement, control, and aggregate signals in the presence of different noise sources and types; (7) all of the above for arbitrary measurement, control, and aggregate signals in the presence of different noise sources and types; and (8) all of the above in the presence of different noise sources and types and different interference sources and types. The delay / amplitude estimator is particularly effective in its ability to process inputs in a joint and tensor manner to address large-scale nonlinear and / or chaotic multiple-input multiple-output (MIMO) systems. The delay / amplitude estimator can also factor in bounded levels of dynamic uncertainty in the system, response, numerical, quantization, modeling, specification, timing, estimates, measurements, predictions, and detection. All of the above can also be scaled to shorter sampling biases, non-uniform sampling, different numbers of inputs and / or outputs, real-time processors, and hardware / software architectures.

[0137] The embodiments of the delay / amplitude estimator discussed with respect to FIGS. 31-34 are particularly useful when processing resources are limited because simpler prediction operations based on these three inputs are performed serially while more complex operations such as finding the time delay, noise, and dynamic uncertainty are performed in parallel.

[0138] 31 illustrates an embodiment of a delay / amplitude estimator 3102 configured to receive or access as inputs synthesized frame data (data that has been cleaned and filtered to remove irrelevant inputs), set points, and measurements for one or more control parameters. In some embodiments, the delay / amplitude estimator 3102 may be part of a plasma processing system. From these inputs, the delay / amplitude estimator 3102 produces two outputs: a total estimated time delay for the system, n(t), Δtotal The time shift amplitude error largely accounts for (or encompasses) at least noise and dynamic uncertainty, among other lesser sources of amplitude error. The time shift refers to the fact that the setpoint is time shifted (i.e., delayed) by the determined total time delay before the time shift amplitude error is determined. These outputs are provided to a predictor (e.g., 2306 in FIG. 23A) of the predictive control section 2012, which uses them to predict how the control signals and / or actuator outputs would react to a potential control signal change based on the delays and the time shift amplitude error, prior to actually changing the control signal. By predicting how the actuator output and / or energy dissipation would be affected (prior to actually changing the control signal to the actuator), the predictive control section 2012 may preemptively adjust the control signals to achieve a desired outcome and maintain the output within a threshold range. For example, based on the predicted control signal output, the predictive control section 2012 may adjust the control output to reduce the time it takes to achieve a desired actuator output, to reduce energy dissipation, to prevent damaging over-voltage and / or over-current conditions, and / or to achieve any desired balance between speed, accuracy, and energy.

[0139] The delay / amplitude estimator 3102 may include a hypothesis tester 3108, a delay extraction 3110, a noise and uncertainty signal extraction 3112, and a time shift amplitude error generator 3114. The hypothesis tester 3108 may determine metrics for any extraction algorithm. For example, in the illustrated embodiment, the hypothesis tester 3108 determines setpoints for one or more actuators and corresponding measurements for one or more actuators (i.e., what the output was from the previous setpoint), and generates a delay guess n(t). Δm , (or “delayed guessing”) to perform a series of cross-correlations between the setpoints and the measurements, and calculate the cost function J, as given by Equation 3 below: m (n(t) Δm ) (and cost function values).

number

[0140] where m is the delayed guess n(t) Δm is the exponential of the set of cost functions J m (n(t) Δm ) value is the corresponding delayed guess n(t) Δm These time-shifted versions of the setpoint (or target value of the reference signal) are associated with a setpoint that is time-shifted by r its [k]. In other words, r its [k] is the input set point r i [k] is a delayed or time-shifted version of the cost function J for multiple frames k based on the setpoint target values ​​and the corresponding actual parameter values ​​achieved at the output. m (n(t) Δm ) is the measurement or corresponding actual parameter value y i [k] and time shift set point r i [kn(t) Δm ], and the set point r i The target value of [k] is the delayed guess n(t)Δm The cross-correlation is performed by comparing the different delay estimates n(t) in the set of delay estimates to identify the one that minimizes the error between the time shift setpoint and the measurement. Δm Allows the exploration of n i The innermost summation across considers the frame, n k The intermediate summation across considers sample k in a given frame i and l The outermost sum across is α l and β l Consider a coefficient that is used for consecutive samples (ie, a sample set) within the same frame, and thus can lead to multiple sets of samples.

[0141] Variable alpha l and β l are design parameters that are defined during design, calibration, and tuning, allowing better scaling of values ​​to fit real hardware. They can be considered as part of the first model or model 1 (depicted in Figures 23A and 23B). The * operator represents a tensor operation. The summation operations allow for parallelization of frames for different control paths (i.e., for MIMO systems); although three nested summations are shown, other combinations can also be utilized without departing from the scope and intent of the present disclosure. In the illustrated embodiment, parallelization is achieved across four dimensions, but the present disclosure is scalable to more dimensions depending on the problem. The result of each cost function operation is a delay estimate n(t) Δm For all tested values ​​of n(t), the total delay n(t) can be stored in a memory (e.g., 3308 in FIG. 33). The system calculates the total delay n(t) for each parallelized frame. Δtotal Although Equation 3 demonstrates a specific cost function, this is merely illustrative and various other cost functions known to those skilled in the art may be used to calculate the best delay guess n(t). Δm can be used to find out.

[0142] To enhance the use of limited computational resources, measurements and setpoints can be grouped into frames and parallelized. Equation 3 assumes such frame processing of data, and thus i is used to represent frame and k to represent sample number. The cost function can be evaluated in parallel (e.g., across four dimensions) due to the present tensor approach (setpoints and measurements are subdivided into multiple frames such that r and y are matrices (or tensors where multiple inputs and / or outputs are utilized, and thus each r and y is a matrix of matrices). The measurements in Equation 3 are grouped into tensors y i [k], where i corresponds to the parallel frame number "i". i [k] corresponds to the different input measurements and controls as a function of frame “i” and sample “k”, and thus {i=1, …, n f}, where k is the sample number for each measurement with parallel frame “i”, and thus {k=1, …, n s}. The set points are then added to another tensor r i [k], where i corresponds to the parallel frame number "i", and the set point can be an arbitrary waveform. i [k] corresponds to different set points as a function of frame “i” and sample “k”, and thus {i=1, …, n f}, where k is the sample number per setpoint with parallel frame "i", and thus {k=1, ..., n s}.

[0143] Cost function J m (n(t) Δm ), the delay extraction 3110 then calculates a cost function J for a given frame. m (n(t) Δm ) the best delay or total delay n(t) that maximizes ΔtotalIn other words, the delay extraction 3110 can determine the set of setpoint time shifts r that best align with the synthesized frame data. its J corresponding to (k) m (n(t) Δm ) function.

[0144] Any part or any cost function in Equation 3 can be expressed as the cost function J m (n(t) Δm ) one set point time shift set for each value r its [k], and the time shift set of these set points r its [k] can be passed to the Noise and Uncertainty Signal Extraction (NUE) 3112. The time shift is that each set point is Δm This means that the total delay n(t) is Δtotal can be passed to both the NUE 3112 and the predictive control section (e.g., predictive control section 2012 of FIGS. 20, 21, and / or 23A). Since the total delay per frame is determined, n(t) Δtotal It will be appreciated that is a tensor with a value per frame, and there may be different total delays for different control paths.

[0145] The NUE 3112 calculates the total delay n(t) from the delay extraction 3110. Δtotal , the time shift version r of the set point from the hypothesis tester 3108 its [k], which may be called the "selected time shift setpoint" Δtotal , and removes the delay from the comparison between the measurement point and the set point via Equation 4 below.

number

[0146] During the ceremony, NIU i[k] is the amplitude difference between the selected time shift setpoint and the measurement. In other words, the amplitude difference could be determined from the raw measurements and the setpoint, but any time delay that was present would lead to inaccuracies in the amplitude difference since this would not be determined from a phase-matched waveform or data set. To overcome this, the setpoint is calculated by multiplying the total delay n(t) by the Δtotal The measurement is then time shifted or delayed by a time shift setpoint and the difference between the time shift setpoint and the measurement is determined. i NIUi[k] can be passed directly to the predictive control section 2012 and used to predict the output based on the control signal. However, further information such as noise and dynamic uncertainty can be collected from NIUi[k], which are then used to predict the output of NIUi[k]. i [k] can be passed to a predictive control section 2012 to provide more robust control than it would provide alone. i [k] is not passed directly to the predictive control section 2012 but is further analyzed.

[0147] Time deviation amplitude difference NIU i [k] can be split into at least two main parts: noise and dynamic uncertainty, and these can then be used to generate bounds for the control signals in the predictive control section 2012. One way to develop these bounds is to remove the noise from the measurements and then use the denoised time shift amplitude difference to find the dynamic uncertainty. Optionally, the known dynamic uncertainty can then be plugged back into a model of the bounded measurements to determine the noise.

[0148] In an embodiment, matched sample points within a set of frames can be averaged to obtain an average value for that sample point across the set of frames that effectively negates the effects of noise. For example, a measurement with a repeating pattern of power pulses is split into four frames, each frame may have the same setpoint waveform but slightly different output measurements due to noise and uncertainty. For every sample point k, there will be four data values, one per frame. Given the same setpoint for every four frames, an ideal system would produce four identical output or measurement signals / values. However, in reality, the four measurement points at the same sample point in the four frames will differ, at least in part, due to noise. By averaging these four measurement sample points, knowing that averaging a noisy signal over a sufficient period of time will negate or average out the noise, the resulting average will represent a largely noise-free output (i.e., remove the effects of noise). Thus, for the four exemplary frames, an average across all four frames can be taken at each sample point to give a single averaged frame with a waveform that is the average of the four frames and is therefore at least somewhat free of noise. This may be referred to as the average frame or denoised frame or set of measurements. Those skilled in the art will appreciate that this noise reduction becomes stronger and more accurate as the number of frames increases. Also, note that this is just one of many denoising processes that may be implemented in the NUE.

[0149] Although not shown in FIGS. 31-33, in some embodiments, an optional energy controller 2322 may adjust the calculated total delay n(t) to allow for more optimized energy consumption. Δtotal An offset can be provided to be added to or subtracted from the

[0150] FIG. 36 provides an illustrative example of the noise removal process in the NUE. A repeating arbitrary waveform is subdivided into n frames, with the first three and nth frames shown in the figure. Each frame finds a repeating portion of the arbitrary waveform such that the data within each frame should be aligned with each other by sample point k. For example, looking at sample k=10, it can be seen that the measured data is mostly at the same amplitude and has mostly the same decay slope, but there is some variation between frames due to noise and dynamic uncertainties. For each sample point k, an average across all n frames can be found to give a corresponding sample point in the output averaged frame. By finding an average across all frames, the averaged frame is largely noise-free, which then allows the NUE to locate and identify dynamic uncertainties.

[0151] If there is any mismatch between frames, for example if the waveforms change over time (e.g. due to different periods in the plasma processing recipe), the frames can be denoised in batches such that averaging is performed over aligned frames in one batch and aligned frames in a second batch, etc. If such mismatch occurs, there will be multiple averaged output frames. In the illustrated example, all frames are aligned, thus resulting in only a single output averaged frame. Although FIG. 36 is illustrated in terms of an arbitrary waveform, pulsed and more regular waveforms can also be denoised via the illustrated averaging method.

[0152] This noise reduction is done by NIU i [k], and therefore mainly removes the noise part from u d From this, we obtain the noise-reduced time shift amplitude difference NIU i The difference between [k] and the set point is the average dynamic uncertainty u d [k]. This average dynamic uncertainty is then given by

number

[0153] Once the noise and dynamic uncertainties are accounted for, Equation 5 can be used to identify a bounded set of measurements (or a worst-case scenario with respect to noise and dynamic uncertainties) as follows:

number

[0154] In the formula, y i [k] wc is the set point r i The worst-case or bounded set of measurements assuming [k]. This may also be referred to as bounding the uncertain noisy waveform of the system being controlled. The worst-case scenario for the noise found in the noise removal process is (NIU i [k]) L1 norm of additive white Gaussian noise times the square of the variance in that noise or

number

number

[0155] Although the average dynamic uncertainty is described, this value is mathematically not distinguished in this application from uncertainty, disturbance, and parameter uncertainty, and these terms can be used synonymously.

[0156] NUE3112 is the worst-case, or boundary set, y i [k] wc or the L1 norm of noise and dynamic uncertainty (i.e.,

number

number

[0157] The predictive control section 2012 utilizes the total time delay and time shift amplitude errors to control one or more actuators whose net effect is to control one or more outputs of the system. In other words, it can predict the boundaries of the control effect such that operation is at the boundaries and minimum performance requirements can be maintained where better performance can be achieved when operating within the boundaries. More specifically, the predictive control section 2012 uses these values ​​to predict how the control signals and / or actuator outputs will react to potential control signal changes prior to actually changing the control signals. By predicting how the actuator outputs will be affected (prior to actually changing the control signals to the actuators 2008), the predictive control section 2012 may adjust the control signals to achieve a desired outcome. For example, based on the predicted control signal outputs, the predictive control section may adjust the control outputs to reduce the time it takes to achieve a desired output of the actuators, reduce energy dissipation, prevent damaging over-voltage and / or over-current conditions, and / or achieve any desired balance between speed, accuracy, and energy.

[0158] n(t) Δtotal , n(t) Δ , and n d Note that n(t) is not a scalar, but can be a vector, matrix, or tensor depending on the number of inputs and outputs of the system. In its simplest manifestation, it is a vector corresponding to the delays associated with the different inputs and outputs, which becomes a matrix when, for example, the delay also depends on the input / output levels (very common in RF amplifiers in the presence of dead times), and n(t) if other entities such as device tolerances, temperature ranges, reflection coefficients (to mention only a few) also affect the value. Δtotal For example, each control / actuator path in our system between the input and the actuator control has a different path and therefore a different internal delay n dFor example, the rail, frequency, and drive actuator may each have a different internal delay n d Similarly, each of these three actuators may have different delays depending on the product they are implemented in. For example, different chipsets in the controllers of three different products, each with the same rails, frequencies, and drive actuators, may have an internal delay tensor n with nine values. d This could lead to...

[0159] Also, the total delay n(t) Δtotal Note that n(t) can be a simple delay, such as the difference between the reference signal and the actuator output measurement. However, more complex delays can also be determined based on several constituent delays, such as those inside and outside the actuator (e.g., an internal delay within the actuator and an external delay outside the actuator). In one embodiment, the total delay n(t) Δtotal is a function of both system and device delays (e.g., 2314 and 2316 in FIG. 23A). More specifically, the total delay n(t) Δtotal is the internal delay n due to calculations determined by the processor design (e.g., FPGA and / or CPU design). d This internal delay n d corresponds to the number of samples between receiving an input to the control section and generating a control output. This value is known from the factory and is therefore not calculated by the system disclosed herein, but rather is read from memory. The unknown delay n(t) Δ is what this disclosure seeks to determine. Δ is the known internal delay n d When added to the total delay n(t), we get the following equation 6: Δtotal Gives.

number

[0160] Total delay n(t) ΔtotalNotwithstanding this definition of , in practice, hardware limitations may lead to alternative estimates of the total delay. For example, when resources are more limited,

number

number

number

[0161] In some embodiments, the set points can be provided by a user interface (UI) 108 as shown in Figure 21 (e.g., in the form of a target multi-level pulsed waveform) or by a set point streaming module 2310 of Figure 23A (e.g., in the form of set points). The set point streaming module 2310 can generate a waveform from a set of discrete set points. The set points or synthesized frame data can be provided to a hypothesis tester 3108 and a time shifted amplitude error generator 3114.

[0162] In some embodiments, measurements of parameters of the actuator outputs can be obtained from one or more sensors, such as sensor 905 of Figures 20 and / or 21. For example, the sensors may reside in the power generation section of the system, such as power generation and sensors 914 of Figure 21. The measurements can be provided to hypothesis tester 3108 and noise and uncertainty signal extraction 3112.

[0163] 32 provides an alternative embodiment of the Delay / Amplitude Estimator 3102 in which the processing of setpoints and measurements occurs before the signal reaches the hypothesis tester. The Delay / Amplitude Estimator 3202 is configured to receive or have access to the synthesized frame data (cleaned and filtered data), setpoints, and measurements for one or more control parameters as inputs, and provides two outputs: the total estimated time delay for the system, n Δtotal and time shift amplitude error. These outputs are provided to a predictor (e.g., 2306 in FIG. 23A ) of the predictive control section 2012, which uses them to predict the results of applying the delay and time shift amplitude error to the control signal, and based on this prediction, further modify the control signal to provide a more robust control signal for one or more actuators, such as RF and DC / rail drivers of the plasma processing system.

[0164] Similar to FIG. 31, the delay / amplitude estimator 3202 may include a hypothesis tester 3208, a delay extraction 3210, a noise and uncertainty signal extraction 3212, and a time shift amplitude error generator 3214, all of which operate in a manner similar to the elements of the same name in FIG. 31, and therefore the descriptions of those elements apply equally to FIG. 32.

[0165] The main difference in FIG. 32 is that the input is provided to an optional Estimator Frame Synthesizer 3203, which parallelizes the incoming signal into frames for parallel use within the Delay / Amplitude Estimator 3202. In particular, the Estimator Frame Synthesizer 3203 subdivides the input frames into frames that are identical in size and can be highly parallelized. When operating on the synthesized frame data, the Estimator Frame Synthesizer 3203 may vary some frames based on setpoints and measurements, for example, where there is a mismatch between the CPU and FPGA clocking. The setpoint frames can be passed to an ideal signal processor 3204, which is a r i [k], where i is the frame number and k is the sample number. In other words, an ideal signal processor 3204 determines the desired setpoint frame and data and waveform characteristics (e.g., periodicity, rise time, settling time, overshoot, etc.) as detailed in U.S. Patent Application No. 17 / 509,539, filed October 25, 2021, and entitled “Robust Tensorized Shaped Setpoint Waveform Streaming Control” (incorporated by reference). Measurements, e.g., raw measurements and synthesized frame data, are passed to a processor and filter 3206, which generates a matrix or tensor representation of the setpoint frame as y i Generate a matrix or tensor representation of the measurements as [k]. These matrices or tensors r i [k] and y i Both [k] are passed to the hypothesis tester 3208 where operation continues as described in Figure 31. In addition, the ideal signal processor 3204 also generates a setpoint frame r i [k] to the time shift amplitude error generator 3214, the NUE 3212, and the processor and filter 3206. Additionally, the processor and filter 3206 passes the measurement frame y i Pass [k] to NUE3212.

[0166] It will be appreciated that the functionality of the delay / amplitude estimators 3102 and 3202 and the predictive control section 2012 may be performed in parallel or may be effected serially.

[0167] 33 illustrates the delay / amplitude estimator 3202 with a specific embodiment of the processor and filter 3206. An embodiment of the processor and filter 3206 receives the parallel measurement frames y from the estimator frame combiner 3203. i (k) includes a parallel frame processing component 3302 that receives the frame (k).

[0168] In order to process the data in real time, the stale data can be flushed. However, instead of simply deleting this stale data, it can be filtered into a smaller data set and stored in a memory such as TSP_RAM 3308 to be recalled when needed. To match 3312 the measurements for phase shifts (due to the measurement system), the processor and filter 3306 passes the measurements through a minimum / zero phase filter bank 3310, whose coefficients are also stored in a memory (e.g., 3308) and expanded biquadically in real time. Stale data that is not filtered and stored can be flushed via the data averager forgetter 3304.

[0169] All other aspects of FIG. 33 are substantially similar to FIG. 32, and the description for FIG. 32 is equally applicable to FIG. 33 and will not be repeated for the sake of brevity.

[0170] FIG. 34 illustrates details of a time shift amplitude error generator, which may or may not be the same as the time shift amplitude error generators 3114 and 3214 shown in FIGS. 31-33. This time shift amplitude error generator 3414 is responsible for determining the total delay, the measurement, the setpoint, the time shift setpoint, and the L1 norm of noise and average dynamic uncertainty, and then generating the time shift amplitude error that is used by the predictive control section to generate control signals for the actuators. More specifically, the difference between the measurement and the setpoint is found in 3402. Another input to 3414 is the bounds or worst case set of measurements y i [k] wc or, as shown, the time shift set point r its [k] and the L1 norm may be input to the time shift amplitude error generator 3414, which may be used to determine the bounds or worst case set of measurements y i [k] wc can be determined in the time shift amplitude error generator 3414 via 3404 and 3406. In other words, the L1 norm is determined by the time shift set point r its [k], the bounds or worst case set of measurements y i [k] wc The variable delay 3410 can provide a total time delay n(t) Δtotal and calculate the bounds or worst case set of measurements y i [k] wc y is shifted (e.g., by a number of samples). i [k] wc -y i [kn(t) Δtotal ] wc Finding out is ynd i [k] wc which gives the total time delay n(t) Δtotal is the noise and disturbance in the output that is corrected for the output ynd i [k] wc Then, (r i [k]-y i [k])-(ynd i [k]wc ) is subtracted from the result of 3402 to give the time shift amplitude error. These operations also i [k]-y i [k])-(y i [k] wc -y i [kn(t) Δtotal ] wc )

[0171] 35 illustrates a method of predictive control that begins with a user-provided setpoint or setpoint waveform (block 3502) and raw measurements of the control output resulting from the setpoint (block 3504). These inputs are then used to calculate, for example, a cost function J m and time delay guess n Δm are used to find the time delay n that is compared in the cross-correlation to minimize the time error between the setpoint and the measurement. Δtotal (block 3506). Δtotal can be used to shift or delay the setpoint (block 3508), and the amplitude difference between the time shift setpoint and the measurement can be found (block 3510). Noise can then be removed from this time shift amplitude, for example by averaging aligned sample points across multiple frames of data (block 3512), and the average dynamic uncertainty can then be found from the denoised time shift amplitude difference (block 3514). Optionally, the average dynamic uncertainty can then be used along with the measurement to ascertain the standard deviation σ of the noise (optional block 3516). The total time delay n(t) Δtotal can be used to determine the time shift amplitude error (block 3518) along with the noise and dynamic uncertainty (or just the denoised time shift amplitude difference and dynamic uncertainty). Δtotalcan then be used to find a control signal for controlling one or more actuators (block 3520), where the control signal is configured to affect actuator changes before the setpoint for that actuator occurs while keeping the output within the bounds. Further modification of the control signal via a predictor can also be implemented as discussed elsewhere in this disclosure.

[0172] In some embodiments, the total time delay n(t) Δtotal Finding the delayed guesses n(t), where m is the number of guesses to be tested, is Δm and (2) set point and measurement frame r i [k] and y i In terms of the tensor representation of [k], the cost function J m For example, this can occur in a hypothesis tester such as 3108 or 3208 in Figures 31 and 32, respectively. Δtotal Finding the cost function J m The delayed guess n(t) that maximizes Δm and call this the total time delay n(t) Δtotal This can occur, for example, in a delay extraction such as 3110 or 3210 in Figures 31 and 32, respectively. In some embodiments, the method of Figure 35 involves expressing the total time delay n Δtotal To find the delay, we use different delay guesses n(t) Δm Set points and measurement frames for r i [k] and y i [k] can be used.

[0173] Finding the noise and dynamic uncertainty is intended to provide bounds on the final control signal to be developed. In other words, the control signal should consider the worst case of noise and dynamic uncertainty, and thus the L1 norm of the noise and dynamic uncertainty is used to determine the coefficients used to generate the time shift amplitude error (block 3518). For example, NUE, such as 3112 or 3212 in Figures 31 and 32, respectively, is the noise

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[0174] For purposes of this disclosure, the time delay n(t) d , n(t) Δ , n(t) Δm , and n(t) Δtotal has units of number of samples, although other units of time can also be implemented with little variation in the operations disclosed herein. The name n(t) indicates that these delays are functions of continuous time. However, in some embodiments the delays can be discretized in terms of sample points rather than on a continuous time scale.

[0175] The implementation shown in Figures 31-36 allows slower hardware to achieve gains, but additional functionality and performance is possible via a multi-step look-ahead predictor, as described with respect to Figures 37-41.

[0176] FIG. 37A depicts a graph 3700-a of normalized signal amplitude versus time for a controlled parameter according to various aspects of the disclosure. The normalized signal amplitude may correspond to measurement data of a first signal, such as a signal measured at the output of an actuator (e.g., RF driver 902, DC / rail driver 904, power amplifier 906), feed-forward power, reflected power, reflection coefficient, or any other applicable signal that may be measured in the system and controlled via a control signal. Graph 3700-a depicts two waveforms 3702-a and 3702-b, where waveform 3702-a is produced in response to a control signal generated by an implementation of a multi-step look-ahead prediction algorithm (e.g., in predictive control section 2012), while waveform 3702-b is produced in response to a control signal generated by a prior art control algorithm. Graph 3700-a further depicts a setpoint / reference amplitude, also referred to as a target value, that is desired for the measurement signal. As described above, the setpoints can be provided by a user interface (UI) 108 as shown in Figure 21 (e.g., in the form of a target multi-level pulsed waveform) or by a setpoint streaming module 2310 (e.g., setpoint streaming modules 2310A, 2310B) of Figure 23B (e.g., in the form of setpoints). The setpoint streaming module 2310 can generate a waveform from a set of discrete setpoints.

[0177] Some aspects of the present disclosure are directed to a multi-step look-ahead predictor configured to internally estimate and / or predict the response of a nonlinear system, such as, but not limited to, a nonlinear and chaotic plasma chamber / generator, to a control actuation. In some cases, the predictive control section 2012 of FIG. 23B may perform one or more internal calculations / operations between adjacent measurements. For example, the predictor 2306 may perform one or more internal calculations without a measurement corresponding to the control delivered by the controller 2308 being available for one or more internal clock cycles because, for a number of reasons, such as, for example, the actuation hardware (e.g., power amplifiers, matches, DC rails, etc.) is much slower than the controller, the sensing hardware cannot measure the raw data that needs to be input to the controller to calculate the actuation value, the sensing hardware has a failure and is no longer available (temporarily and / or indefinitely), the sensing hardware is exposed to high levels of noise and / or interference, and the sensing hardware needs to be recalibrated, to name a few non-limiting examples.

[0178] As can be seen, graph 3700-a depicts one or more internal clock cycles (indicated by the short dotted arrow) and one or more clock cycles (indicated by the longer dashed arrow). In this example, there are eight (8) internal clock cycles per clock cycle, and measurement data is available every eight internal clock cycles. FIG. 37A uses triangle symbols to depict when new measurement data enters the predictive control partition 2012. For example, measurement data is available at t=t k , t k+n , t k+2n etc. The internal clock cycle (e.g., t = t k+1 ...t k+n-1), there may not be any measurement data available. However, according to aspects of the disclosure, a predictive control section, comprising at least a predictor 2306, a second model (e.g., model 2) of the system, and a controller 2308, may calculate internal control signal values ​​and predicted internal measurements (e.g., responsive to the calculated internal control signal values) to enhance the quality of the control output (e.g., actuator control) delivered by the controller 2308 when the next measurement is available.

[0179] FIG. 37B depicts a graph 3700-b of control output values ​​used to adjust an actuator versus time, according to various aspects of the disclosure. Control signal waveform 3705-a may be an example of a control output / actuator control generated by predictive control section 2012, according to aspects of the disclosure, and used to produce the measurement data seen in waveform 3702-a of FIG. 37A. Additionally, control signal waveform 3705-b may be an example of a control output / actuator control generated by a prior art control algorithm and used to produce the measurement data seen in waveform 3702-b. As can be seen, graph 3700-b shows a number of control signal values ​​3720-a, 3720-b, and 3720-c that are actually sent to the actuator, as well as a number of internal control signal values ​​3715 that are calculated over one or more of the internal clock cycles between the measurements. For example, at time t=t k In, the controller 2308 sends a first control signal 3705-a to the actuator, where the first control signal 3705-a is based on a previous / most recent internal control signal value 3720-a, for example, calculated by the controller 2308 over the last internal clock cycle of the previous clock cycle.

[0180] According to various aspects of the present disclosure, the predictive control section 2012 waits a time t until the next measurement is available. k and k+n In some cases, the internal control signal value 3715 may be calculated based on the most recent available measurement (e.g., time tk For example, the controller may calculate the u in FIG. k+1 The predictor 2306 may then feed back a first internal control signal value 3715, denoted as k+1 ) and sends it to the controller 2308, based on which the controller 2308 calculates another internal control signal value (u k+2), and so on. In other words, the internal control signal values ​​and predicted internal measurements are processed by the predictor 2306 and the controller 2308 in a loop-like manner, with the internal control signal values ​​(e.g., the control feedback in FIG. 23B) being based on the previous / most recent predicted internal measurements. Thus, as can be seen, while the controller 2308 controls the actuators in the current clock cycle using the internal control signal values ​​calculated over the last internal clock cycle of the previous clock cycle, the controller 2308 and the predictor 2306 continue to optimize the actuator control that will be applied over the next clock cycle. In some cases, this optimized actuator control for the next clock cycle may be based on the most recent or previous "actual" measurements (i.e., for the current clock cycle), one or more internal control signal values, and / or internal predicted measurements calculated over the internal clock cycles of the current clock cycle. Thus, instead of calculating a single control signal value every clock cycle, as seen in control signal waveform 3705-b produced by the prior art control algorithm, multiple internal control signal values ​​may be calculated based on multiple predicted internal measurements predicted (i.e., by predictor 2306 and a second model (e.g., model 2) of the present system), and the final internal control signal value (e.g., optimized control signal) may be applied as the actuator control for the next clock cycle. As seen in FIG. 37A, the multi-step look-ahead prediction described above facilitates reducing the time required to achieve a desired set point compared to the prior art. For example, the normalized amplitude of waveform 3702-a meets the desired set point within two clock cycles, while the normalized amplitude of waveform 3702-b does not meet the desired set point even after three clock cycles.

[0181] FIG. 38 illustrates a detailed schematic diagram 3800 of the predictive control section 2012 of FIG. 23B according to one or more aspects of the present disclosure. As can be seen, the predictive control section includes a predictor 2306 and a controller 2308, which further includes a second model (e.g., second model 2403), a model parameterization module 3850, a delay compensator 3834, a model updater 3839, a filter 3833 (e.g., a smoothing filter), and a tensor memory (e.g., tensor memories 3823-a, 3823-b). In some cases, the predictive control section 2012 may be implemented using a second model (e.g., second model 2403), which is generated based on an adaptation mechanism. The second model may be used to describe the plasma dynamics or any other measurable signal / controlled parameter / controlled output of the system of FIG. 21. In a broad sense, the second model may be modeled using one or more parameterized functions (e.g., tensorial nonlinear parameterized functions) as follows: k It may be used to describe the plasma dynamics in

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[0182] where the system time resolution is:

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[0183] As can be seen, the model parameterization module 3850 of the predictor 2306 may take one or more inputs from other elements of the system of FIG. 23B and produce one or more outputs. For example, the model parameterization module 3850 may take one or more inputs from other elements of the system of FIG. 23B and produce one or more outputs. For example, the model parameterization module 3850 may take one or more inputs from other elements of the system of FIG. 23B, such as the time shift amplitude error, the total estimated delay for the system, n Δtotal, model 1, and setpoint streaming module 2310. In addition, the model parameterization module 3850 may also receive predicted internal measurements 3813 as calculated by model 2 (e.g., second model 2403). The model parameterization module 3850 may be electronically, logistically, and / or communicatively coupled to a tensor memory 3823-a, which may store data related to the various MIMO coupling tensors listed above in Equations 7 and 8.

[0184] At the beginning of the process, a set of models corresponding to frames in terms of CPU clock cycles may be input into the FPGA's setpoint streaming module 2310B. In some embodiments, the set of models may correspond to Model 1 in the setpoint streaming module 2310A. In some embodiments, the set of models may comprise one or more of the setpoint sequences and one or more models corresponding to specific portions of one or more frames. Alternatively, the set of models may comprise point-wise models representing an initial guess for the process. In either case, the FPGA may begin generating points for this for interpolation, which are then passed to the system based on which Model 1 is generated. These points may be associated with or may define the setpoint sequence. Furthermore, the interpolation of the setpoint sequence may be used to generate Model 1 in some embodiments. In some cases, the predictor 2306 may receive Model 1 and setpoint streaming, for example, Model 1 may be passed through the setpoint streaming module 2310, which is then used to initialize Model 2 in the predictor 2306. In some examples, the initial parameterization for model 2 may be based on the parameterization for model 1. In other words, the starting or initial values ​​for model 2 are the same as or similar to model 1. This initial parameterization for model 2 may be updated as the multi-step look-ahead predictor provides measurement predictions in accordance with aspects of the present disclosure. For example, the model parameterization module 3850 may receive the predicted internal measurements 3813 as calculated by model 2, which may then be used to calculate the error e k This error, also referred to as prediction or modeling error in some cases, e k corresponds to the difference between the current model used to generate the predicted measurements and the actual model derived from the measurements 3835. kmay be used to update the parameterization of a second model used to predict the measurements. A filter 3833, which may be an example of a smoothing filter, filters the error e k The model updater 3839 may receive the smoothed and / or cleaned error e received from the filter 3833 and clean it to remove noise and other disturbances so that it can be processed by the model updater 3839. k Based on this, the smoothing filter 3833 may determine a change in the parameterization of the second model. In some embodiments, the model updater 3839 may output an updated tensor (θ). As described above, the parameterization of functions f and g in equations 7 and 8 may be done through the tensor θ. The updated tensor output by the model updater 3839 may be fed back to the model parameterization module 3850 and used to update a second model (e.g., the second model 2403) used for subsequent predictions. In some cases, the θ tensor may be passed through a one-sample delay so that it is received at the next clock cycle, or alternatively, at the next internal clock cycle. The smoothing filter 3833 may also be coupled to the tensor memory 3823-b in some embodiments. In some cases, the tensor memory 3823-b may be the same as or similar to the tensor memory 3823-a.

[0185] The delay compensator 3834 is configured to calculate the delay between the predicted measurement from the model parameterization module 3850, the actual measurement, the time shift amplitude error 2052, and / or n(t) Δtotal and the adjusted time shift amplitude error 2452 and / or the adjusted time delay n(t) fed into the controller 2308. Δtotal The controller 2308, together with the setpoint streaming module 2310, may then output the adjusted time shift amplitude error 2452 and / or the adjusted time delay n(t) Δtotal21.' to calculate actuator control signals that are sent to the drivers (eg, RF driver 902 and DC / rail driver 904 in FIG. 21).

[0186] Turning now to FIG. 39, shown is a block diagram 3900 illustrating an example control architecture that may be used to implement the control functionality of FIG. 20 according to various aspects of the disclosure. In some embodiments, the control architecture may be implemented across a CPU 3911 and an FPGA 3921. The CPU 3911 and / or FPGA 3921 may be similar or substantially similar to the CPU and / or FPGA described above in connection with FIG. 23B. The CPU 3911 and / or FPGA 3921 may receive measurement data from the sensors 905, and the measurements may be blocked / chunked into frames via a frame composer and combiner 2312 in the CPU to enable parallel processing. The frame composer and combiner 2312 may clean the measurements and generate frames from the cleaned data. For purposes of this disclosure, a frame is a set of samples processed in a batch, thus the frames may be processed in parallel and then the output of the frame processing may be serialized. The frame synthesizer and combiner 2312 may also be configured to process the synthesized frames such that they are suitable for further processing in the delay / amplitude estimator 2004 in the FPGA 3921. In some embodiments, the set points can be provided by the UI 108 as shown in FIG. 21 (e.g., in the form of a target multi-level pulsed waveform) or by the set point streaming module 2310 of the CPU 3911, e.g., in the form of a set point. The set point streaming module 2310 may be similar or substantially similar to the set point streaming described above in connection with FIG. 23A and / or 23B. In some cases, the set point streaming module 2310 generates a waveform from a set of discrete set points.

[0187] The CPU 3911 may further comprise a memory and logic module 3916 that is electronically, logistically, and / or communicatively coupled to the setpoint streaming module 2310 and the frame compositor and combiner 2312. The memory and logic module 3916 of the CPU 3911 may also communicate with a TSP processor 3927 in the FPGA 3921, which may comprise the frame reader 2302 and the TSP RAM 2304, described above in connection with FIG. 23B. In some cases, the memory and logic module 3916 may store the composited frames and / or coefficients of the setpoint streaming, which allows communication between the FPGA and the CPU even though they are operating at different speeds. Although not required, in some embodiments, the memory and logic module 3916 stores data in the form of a matrix of matrices. The TSP processor 3927 may communicate with one or more of the elements of the FPGA 3921 (e.g., delay / amplitude estimator 2004, controller 2308, predictor 2306, setpoint streaming module 2310B) as depicted by the large shaded triangles. The delay / amplitude estimator 2004 calculates the n(t) Δtotal and the time shifted amplitude error to the predictor 2306. The predictive control section 2012, which includes the predictor 2306 and the controller 2308, operates in a loop-like manner, exchanging predicted internal measurements and internal control signal values, respectively, until the next measurement is available. The controller 2308 transmits actuator control, for example, at or near the time the next measurement arrives from the sensor 905.

[0188] As described above in connection with Figures 37A and 37B, in some cases the controller 2308 may calculate the control signal value at a clock cycle rate that is faster (e.g., once every 31.25 nanoseconds) than the clock cycle rate at which the control signal is passed to the actuator (e.g., once every 250 nanoseconds), or alternatively, at the clock cycle rate at which the actual measurement / parameter value of the controlled parameter is available.

[0189] FIG. 40 illustrates an example of a process flow 4000 implemented in a multi-step look-ahead predictor (e.g., predictive control section 2012) according to various aspects of the disclosure. Here, the start of each "longer" clock cycle (i.e., the clock cycle corresponding to when measurements are fed to the controller 2308) is represented by an index of the form "k+i×n", where "i" increases incrementally after each clock cycle. Additionally, internal clock cycles are represented by indexes of the form "k+i×n+m", where 0≦m≦n.

[0190] As can be seen, measurements (e.g., controlled parameters such as forward power, reflected power, reflection coefficient, frequency, RF drive / bias voltage, to name a few non-limiting examples) are used by the controller 2308 to generate output control signals (u k-n+1 ) at or near the time when the actuator is adjusted using k and is output by the controller 2308. k-n+1 is based on the last internal control signal value calculated from the previous "longer" clock cycle. The "kn" exponent is the kth index since it corresponds to the previous clock cycle. old The controller 2308 may be referred to as the most recent measurement x k Based on the control feedback / internal control signal value u k+1 The predictor starts a multi-step look-ahead prediction by sending a control signal value u k+1 , and transmits the predicted internal measurement value x to the controller 2308. k+1The controller 2308 processes the predicted internal measurements and outputs the predicted internal measurements x k+1 Based on the different internal control signal value u k+2 This process is repeated until the last internal clock cycle, when the next measurement is available. k+n or x k_new The internal state of the predictor or the last internal measurement, which may be expressed as: k+n is the internal measurement x k+n or x k_new In addition, the last / most recent predicted internal measurement x k+n This clock cycle (i.e., t k The final control signal value u for the "longer" clock cycle starting at k+n+1 or u k_new+1 is the actuator control (i.e., t k+n ) and output to drivers 902, 904.

[0191] As used herein, a tensor y k may be used to refer to a measurement tensor corresponding to a controlled output, such as the output coupled to a plasma processing chamber. Alternatively, the tensor y k may refer to a measurement tensor for a first controlled parameter in the system, such as the forward power or the output of the power amplifier 906, and the tensor x k is the RF driver voltage (V θ ) or another controlled parameter. In some cases, the measurement tensor y k takes as input a measurement tensor x kAs seen in FIG. 40, the control algorithm depicted with process flow 4000 may also be implemented for use in a MIMO system where there are multiple inputs and multiple outputs. For example, x k and y k may correspond to measurement data received from different sensors 905. In such a case, multiple control signals (e.g., both internal and output control) may be calculated for the multiple actuators 2008. In other words, the predictive control section 2012 may be deployed to internally predict the multiple controlled parameters measured at the multiple sensors 905 and calculate multiple output control signals for adjusting the multiple actuators 2008.

[0192] In some embodiments, when a measurement arrives, the predicted measurement of the second model for that sample / internal clock cycle may be compared to the actual measurement to update the second model. For example, the error may be calculated from the following equations (9) and (10), where k in the equations is the time at which the measurement is made available.

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[0193] Furthermore, using equations 7, 8, 9, and 10, the second model calculates the next internal predicted measurement, i.e., until a new measurement arrives, at time t k and in Equation 12 below:

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[0194] Optionally, Δf k and Δg k can be used to update the second model every internal clock cycle (e.g., every 31.25 ns when actuator controls are sent every 250 ns), and thus, from equations 11 and 12, Δf k and Δg k can be calculated as follows:

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[0195] Wherein, in equations 13 and 14:

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[0196] Therefore, respectively,

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[0197] In some embodiments, the control architectures of Figures 38 and 39 may be implemented in a parallel structure, which may allow for the addition of one or more operations. For example, using a parallel structure, the hardware implementation of Figure 38 may be replicated multiple times (e.g., eight times in an example where an internal control signal is generated every 31.25 nanoseconds and a control output is generated every 250 nanoseconds) as a series of blocks, with each block being triggered a predefined amount of time after the previous temporal block. In some cases, the duration of time between when a block is triggered and when a subsequent block is triggered may be based on the duration of an internal clock cycle. In some situations, a parallel implementation as a series of temporal blocks, achieved by pipelining a multi-step look-ahead prediction mechanism, may allow for longer processing times (e.g., 250 nanoseconds) and reduced combined control rates (e.g., about 31.25 nanoseconds).

[0198] 41 illustrates a method 4100 for controlling a nonlinear system, such as a plasma processing system, according to one or more implementations. The method 4100 may be implemented using one or more of the control partition 2112, the predictive control partition 2012, an FPGA, and a CPU, as described in connection with the previous figures.

[0199] In step 4102, the method 4100 includes receiving a reference signal that defines a target value for a parameter to be controlled at an output within the plasma processing system.

[0200] The method further includes obtaining a measurement of a parameter to be controlled at the output, hi some embodiments, the parameter is measured at a first sampling frequency, the first sampling frequency corresponding to a plurality of clock cycles, each clock cycle having a first clock cycle duration (step 4104).

[0201] In step 4106, the method includes calculating one or more internal control signal values ​​over one or more internal clock cycles of a second clock cycle duration, the second clock cycle duration being less than the first clock cycle duration. Then, in step 4108, the method 4100 includes predicting one or more internal measurements of the controlled parameter over one or more internal clock cycles based on the one or more internal control signal values ​​using the second model.

[0202] In step 4110, the method includes adjusting at least one actuator over one or more clock cycles having a first clock cycle duration, the adjusting being based on one or more control output values. In some cases, the one or more control output values ​​are based, at least in part, on one or more internal control signal values ​​and one or more predicted internal measurements.

[0203] The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in processor executable code encoded in a non-transitory tangible processor readable storage medium, or in a combination of the two. For example, referring to FIG. 42, shown is a block diagram 4200 depicting the physical components utilized to realize the control section 112, 302, 602, 912, 2112, 2301A, 2301B, and 2612, and / or the tensor control device 2001, according to an exemplary embodiment. As shown, in this embodiment, a non-volatile memory 4220 is coupled to a bus 4222, which is also coupled to a random access memory ("RAM") 4224, a processing portion (including N processing components) 4226, a field programmable gate array (FPGA) 4227, and a transceiver component 4228 including N transceivers. None of these components are required, and any combination of these may be included in the systems disclosed herein. For example, if FPGA 4227 is implemented, processing portion 4226 may not be used, and vice versa. Although the components depicted in FIG. 42 represent physical components, FIG. 42 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 42 may be realized by common constructs or distributed among additional physical components. It is also envisioned that other existing and yet to be developed physical components and architectures may be utilized to implement the functional components described with reference to FIG. 42.

[0204] In general, the non-volatile memory 4220 is a non-transient memory that functions to store (e.g., persistently store) data and processor-executable code (including executable code associated with effecting the methods described herein). For example, in some embodiments, the non-volatile memory 4220 includes boot loader code, operating system code, file system code, and non-transient processor-executable code to facilitate execution of the methods for selecting a master state and thereby more effectively controlling the ramping up and ramping down of the rail voltages of the DC section 908, as described with reference to Figures 5 and 6, further described herein.

[0205] In many implementations, the non-volatile memory 4220 is realized by a flash memory (e.g., NAND or ONENAND memory), although it is envisioned that other memory types may be utilized as well. While it may be possible to execute code from the non-volatile memory 4220, executable code in the non-volatile memory is typically loaded into RAM 4224 and executed by one or more of the N processing components in the processing portion 4226.

[0206] The N processing components associated with RAM 4224 generally operate to execute instructions stored in non-volatile memory 4220 to select a master state, thereby enabling a method for more effectively controlling the ramping up and ramping down of rail voltages. For example, non-transient processor executable code for effecting the methods described with reference to Figures 5 and 6 may be persistently stored in non-volatile memory 4220 and executed by the N processing components associated with RAM 4224. As one skilled in the art would appreciate, processing portion 4226 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing component, or a combination of hardware and software processing components (e.g., an FPGA or an FPGA including a digital logic processing portion).

[0207] Additionally or alternatively, the processing portion 4226 may be configured to effect one or more aspects of the methodologies described herein (e.g., methods for selecting a master state and thereby more effectively controlling the DC rail voltage of the slow actuator 316 as described in FIGS. 3 and 6 or the DC / rail driver 904 of FIGS. 9 and 21). For example, non-transient processor-readable instructions may be stored in the non-volatile memory 4220 or in the RAM 4224 and executed on the processing portion 4226 to cause the processing portion 4226 to implement a method for controlling the DC / rail driver 904 and the RF driver 902. Alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 4220 and accessed by processing portion 4226 (e.g., during boot-up) to configure hardware configurable portions of processing portion 4226 to provide functionality for control sections 112, 302, 602, 912, 2112, 2301A, 2301B, 2612.

[0208] Alternatively, the FPGA 4227 may include non-transient processor executable code for facilitating execution of a method for selecting a master state and thereby more effectively controlling the rise and fall of the slow actuator 316 as described further herein with reference to Figure 3. The FPGA 4227 may include on-board memory for accessing data such as the target multi-level waveforms, or may access off-chip memory such as non-volatile memory 4220 accessible via bus 4222.

[0209] The input component 4230 operates to receive a signal (e.g., feedback from the sensor 905 and / or a signal from the user interface 108, such as a target multi-level pulsed waveform) indicative of one or more aspects of the target waveform or condition of the nonlinear and / or chaotic load 140. The signal received at the input component may include, for example, a measurement of the power delivered to the plasma processing chamber. The output component generally operates to provide one or more analog or digital signals to generally effect the operational aspects of the control section 302. For example, the output portion 4232 may provide a controller signal to the RF driver 902 or a control signal to the DC / rail driver 904, described with reference to FIG. 9.

[0210] The depicted transceiver component 4228 includes N transceiver chains that may be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., WiFi, Ethernet, Profibus, etc.).

[0211] Some portions are presented in terms of algorithms or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory, such as a computer memory. These algorithmic descriptions or representations are examples of techniques used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processes leading to a desired result. In this context, operations or processes involve physical manipulations of physical quantities. Typically, though not necessarily, such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, or otherwise manipulated. At times, primarily for reasons of common usage, it has proven convenient to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numeric values, or the like. It should be understood, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels. Unless specifically stated otherwise, throughout this specification, discussions utilizing terms such as "processing," "computing," "calculating," "determining," and "identifying," or the like, should be understood to refer to the actions or processes of a computing device, such as one or more computers or similar electronic computing devices or devices that manipulate or transform data represented as physical electronic or magnetic quantities in memories, registers, or other information storage, transmission, or display devices of a computing platform.

[0212] As will be appreciated by those skilled in the art, aspects of the present invention may be embodied as a system, method, or computer program product. Thus, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0213] As used herein, the recitation of "at least one of A, B, and C" is intended to mean "either A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications of these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A plasma processing system, comprising: a user interface configured to receive a reference signal defining a target value for a controlled parameter to be provided to a controlled output in the system; at least one sensor for obtaining a measurement of the controlled parameter to be controlled at the controlled output; A delay / amplitude estimator, the delay / amplitude estimator comprising: calculating a delay between the target value of the reference signal and a corresponding actual parameter value of the controlled parameter achieved at the controlled output; providing a time shift amplitude error indicative of an error between the target value and the actual parameter value based on the delay; a delay / amplitude estimator configured to: a predictive control section configured to adjust the at least one actuator based on the delay and the time shifted amplitude error in advance of when an actual parameter value is needed at an actuator output of the at least one actuator while maintaining the controlled parameter at the controlled output within a threshold range; A system comprising:

2. The system of claim 1 , wherein the controlled output is an output coupled to a plasma processing chamber.

3. 3. The system of claim 2, wherein the user interface is configured to at least one of: allow an operator of the system to set the target value; and allow a controller to set the target value.

4. The system of claim 2 , wherein the at least one actuator comprises a DC section configured to apply a DC rail voltage to a power amplifier.

5. 5. The system of claim 4, wherein the predictive control section comprises a boundary detector configured to determine an amount that the DC rail voltage can change within the control clock cycle while still allowing the power amplifier to respond within the control clock cycle.

6. The system of claim 1 , wherein the predictive control section comprises an energy controller configured to adjust the at least one actuator based at least in part on a predicted energy dissipation.

7. The system of claim 1 , wherein the controlled parameter is one of a forward power, a reflected power, or a reflection coefficient.

8. The system of claim 1 , wherein the controlled output is the actuator output of the actuator.

9. The system of claim 1 , wherein the delay comprises an internal delay and an external delay.

10. 1. A method for controlling a plasma processing system, the method comprising: receiving a reference signal defining a target value for a parameter to be controlled at an output within the plasma processing system; obtaining a measurement of the parameter to be controlled at the output; calculating a delay between the target value of the reference signal and a corresponding actual parameter value achieved at the output; providing a time shifted amplitude error indicative of an error between the target value and an actual parameter value based on the delay; adjusting the at least one actuator based on the delay and the time shift amplitude error prior to when an actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range; A method comprising:

11. The method of claim 10 , wherein the output is coupled to a plasma processing chamber.

12. The method of claim 10 , wherein adjusting the at least one actuator comprises adjusting a DC section configured to apply a DC rail voltage to a power amplifier.

13. 13. The method of claim 12, wherein the method includes determining an amount that the DC rail voltage can change within a control clock cycle while allowing the power amplifier to respond within the control clock cycle.

14. The method of claim 10 , wherein the method includes adjusting the at least one actuator based at least in part on a predicted energy dissipation.

15. The method of claim 10 , wherein the controlled parameter is one of a forward power, a reflected power, or a reflection coefficient.

16. The method of claim 10 , wherein the output is an actuator output of the at least one actuator.

17. The method of claim 10 , wherein calculating the delays includes calculating an internal delay and an external delay.

18. 1. A plasma processing system, comprising: A processor; a non-transient memory comprising processor readable instructions for receiving a reference signal defining a target value for a parameter to be controlled at an output within the plasma processing system; A field programmable gate array; programming instructions for programming the field programmable gate array; wherein the programming instructions include: obtaining a measurement of the parameter to be controlled at the output; receiving the target value for the parameter to be controlled at the output; calculating a delay between the target value of the reference signal and a corresponding actual parameter value achieved at the output; providing a time shifted amplitude error indicative of an error between the target value and an actual parameter value based on the delay; adjusting the at least one actuator based on the delay and the time shift amplitude error prior to when an actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range; and programming instructions for programming the field programmable gate array to perform the steps of:

19. 1. A plasma processing system, comprising: a user interface configured to receive a reference signal defining a target value for a parameter to be controlled at an output within the plasma processing system; at least one sensor for obtaining a measurement of the parameter to be controlled at the output; A delay / amplitude estimator, the delay / amplitude estimator comprising: calculating a delay between the target value of the reference signal and a corresponding actual parameter value achieved at the output; providing a time shift amplitude error indicative of an error between the target value and the actual parameter value based on the delay, the error including at least noise and dynamic uncertainty; a delay / amplitude estimator configured to: a predictive control section configured to preemptively adjust at least one actuator based on the delay and the time shift amplitude error; A plasma processing system comprising:

20. 20. The plasma processing system of claim 19, wherein the time-shifted amplitude error is based on a difference between a time-shifted version of the target value and the corresponding actual parameter value achieved at the output.

21. 20. The plasma processing system of claim 19, wherein the predictive control section is further configured to adjust the at least one actuator in advance of when an actual parameter value is desired at an actuator output of the at least one actuator while maintaining the output within a threshold range.

22. 20. The plasma processing system of claim 19, wherein the delay / amplitude estimator is configured to process the target and actual parameter values ​​in a parallelized frame.

23. 23. The plasma processing system of claim 22, wherein the delay / amplitude estimator is configured to calculate an instance of the delay for each parallelized frame.

24. 20. The plasma processing system of claim 19, further comprising a time shift error generator configured to calculate the time shift amplitude error using the delay, the noise, and the dynamic uncertainty.

25. The plasma processing system includes: the target value of the reference signal; the corresponding actual parameter value achieved at the output; and A set of delayed guesses and and searching for a cost function based on a set of cost function values, each of the cost function values ​​corresponding to a different one of the set of delay estimates; a time-shifted set of target values ​​of the reference signal, each of the target values ​​being shifted by a different one of the set of delay hypotheses; To generate 20. The plasma processing system of claim 19, further comprising a hypothesis tester configured to:

26. 26. The plasma processing system of claim 25, further comprising a noise and uncertainty signal extraction, the noise and uncertainty signal extraction configured to select a time shift set of target values ​​from the time shift set of target values ​​as a selected time shift set of target values ​​that corresponds to one of the set of delay guesses that corresponds to a maximum value of the set of cost function values.

27. 27. The plasma processing system of claim 26, wherein the noise and uncertainty signal extraction is further configured to identify noise and dynamic uncertainty in the corresponding actual parameter values ​​from differences between the selected time shifted set of target values ​​and the corresponding actual parameter values.

28. 20. The plasma processing system of claim 19, wherein the delay comprises an internal delay and an external delay.

29. 1. A method of modifying a control signal to one or more actuators based on measurements of one or more parameters of an output of the one or more actuators and based on a setpoint, the method comprising: Finding a total time delay that minimizes the total time delay between (1) a time-shifted version of the setpoint and (2) the measurement; selecting one of the time-shifted versions of the setpoint corresponding to the total time delay as a set of selected time-shifted setpoints; determining an amplitude difference between the measurements and the selected set of time shift setpoints; removing noise from the amplitude difference to form a denoised amplitude difference; using the denoised amplitude difference to find a dynamic uncertainty of the amplitude difference; generating a time shift amplitude error using the noise, the dynamic uncertainty, and the total time delay; providing control signals to the one or more actuators that predictively account for the total time delay and the time shift amplitude error; A method comprising:

30. 30. The method of claim 29, wherein finding the total time delay uses cross-correlation between the measurements and the time-shifted versions of the setpoint using a set of initial guesses for the total time delay between the measurements and the time-shifted versions of the setpoint.

31. 30. The method of claim 29, wherein finding the total time delay comprises minimizing a cost function over multiple frames of the measurements, wherein frames that include repeated portions of the measurements are analyzed in parallel.

32. 30. The method of claim 29, wherein the total time delay is a tensor representing multiple inputs and multiple outputs.

33. 30. The method of claim 29, wherein the time-shifted version of the setpoint, the measurement, and the dynamic uncertainty are used to find a standard deviation of the noise.

34. 1. A non-transitory, tangible, computer-readable storage medium, the non-transitory, tangible, computer-readable storage medium being encoded with processor-readable instructions for implementing a method for generating a control signal that preemptively accounts for delay and amplitude errors in a control system, the method comprising: determining measurements at the output of one or more actuators; Finding a total time delay that minimizes a total time delay between (1) a time-shifted version of a setpoint for the one or more actuators and (2) the measurement; selecting one of the time-shifted versions of the setpoint corresponding to the total time delay as a set of selected time-shifted setpoints; determining an amplitude difference between the measurements and the selected set of time shift setpoints; removing noise from the amplitude difference to form a denoised amplitude difference; using the denoised amplitude difference to find a dynamic uncertainty of the amplitude difference; generating a time shift amplitude error using the noise, the dynamic uncertainty, and the total time delay; preemptively controlling the one or more actuators to account for the total time delay and the time shift amplitude error; A non-transitory tangible computer readable storage medium, comprising:

35. 35. The non-transitory, tangible computer-readable storage medium of claim 34, wherein the time shift amplitude error accounts for control system noise.

36. 36. The non-transitory, tangible computer-readable storage medium of claim 35, wherein the time shift amplitude error accounts for dynamic uncertainties of a control system.

37. 35. The non-transient, tangible, computer readable storage medium of claim 34, further comprising: using the dynamic uncertainty and the measurement value to find the noise removed from the amplitude difference.

38. 35. The non-transitory, tangible computer readable storage medium of claim 34, wherein the controlling occurs prior to a time dictated by the set point.

39. 1. A plasma processing system, comprising: a user interface configured to receive a reference signal defining a target value for a controlled parameter to be provided to a controlled output in the system; at least one sensor for obtaining a measurement of the controlled parameter to be controlled at the controlled output, the controlled parameter being measured at a first sampling frequency, the first sampling frequency corresponding to one or more clock cycles, each clock cycle having a first clock cycle duration; Predictive control category and The predictive control section comprises: calculating one or more internal control signal values ​​over one or more internal clock cycles of a second clock cycle duration, the second clock cycle duration being less than the first clock cycle duration; predicting one or more internal measurements of the controlled parameters over the one or more internal clock cycles based on the one or more internal control signal values ​​using an internal model; adjusting at least one actuator over the one or more clock cycles having the first clock cycle duration based on one or more control output values, the one or more control output values ​​being based at least in part on the one or more internal control signal values ​​and the one or more predicted internal measurements; A system configured to:

40. each clock cycle having the first clock cycle duration comprises a plurality of internal clock cycles having the second clock cycle duration; 40. The system of claim 39, wherein the predictive control partition is further configured to calculate a prediction error by comparing the measured value of the controlled parameter to a predicted internal measured value of the controlled parameter every clock cycle.

41. the predictive control section is further configured to calculate a time-shifted amplitude error of the controlled parameter over at least one clock cycle having the first clock cycle duration, the time-shifted amplitude error indicative of an error between a target value and an actual parameter value of the controlled parameter achieved at the controlled output; 40. The system of claim 39, wherein at least one of the control output values ​​is based on an internal control signal value and the time-shifted amplitude error of the controlled parameter.

42. The predictive control section includes: calculating a first internal control signal value over a first internal clock cycle, wherein calculating the first internal control signal value is based on comparing an actual parameter value of the controlled parameter at the first internal clock cycle to a predicted measured value of the controlled parameter at the first internal clock cycle; calculating a second internal control signal value over a second internal clock cycle, the second internal clock cycle being after the first internal clock cycle, and calculating the second internal control signal value based on predicting an internal measurement value of the controlled parameter at the second internal clock cycle based on the first internal control signal value; 42. The system of claim 41, further configured to:

43. The predictive control partition comprises a model parameterization partition, the model parameterization partition comprising: The initial model and the one or more predicted internal measurements; and one or more time shift amplitude errors; and one or more delays between the target values ​​of the reference signals and the corresponding actual values ​​of the controlled parameters; a target value of the controlled parameter; 40. The system of claim 39, configured to parameterize the internal model using one or more of:

44. 44. The system of claim 43, wherein the predictive control partition comprises a model updater configured to determine at least one change in a parameterization of an internal model of the system based on one or more of actual parameter values ​​of the controlled parameters and the prediction error, and wherein the at least one change in the parameterization is determined when the actual parameter values ​​are available, at the one or more internal clock cycles, or a combination thereof.

45. 45. The system of claim 44, wherein the model parameterization section is further configured to update the internal model based on at least one change in the parameterization.

46. 46. ​​The system of claim 45, wherein the model updater is further configured to calculate a change in a parameterization of the internal model for each internal clock cycle based on an interpolation between a previously calculated internal model and a currently calculated internal model, the previously calculated internal model and the currently calculated internal model being based on actual parameter values ​​of the controlled parameters.

47. the controlled output being an output coupled to a plasma processing chamber; the user interface is configured to at least one of allow an operator of the system to set the target value and allow a controller to set the target value; 40. The system of claim 39, wherein the at least one of

48. 40. The system of claim 39, wherein the controlled parameter is one of forward power, reflected power, a reflection coefficient, an RF driver voltage to a power amplifier, or a DC rail voltage to a power amplifier.

49. 1. A method for controlling a plasma processing system, the method comprising: receiving a reference signal defining a target value for a parameter to be controlled at an output within the plasma processing system; obtaining measurements of the parameter controlled at the output, the parameter being measured at a first sampling frequency, the first sampling frequency corresponding to a plurality of clock cycles, each clock cycle having a first clock cycle duration; calculating one or more internal control signal values ​​over one or more internal clock cycles of a second clock cycle duration, the second clock cycle duration being less than the first clock cycle duration; predicting one or more internal measurements of the controlled parameters over the one or more internal clock cycles based on the one or more internal control signal values ​​using an internal model; adjusting at least one actuator over the one or more clock cycles having the first clock cycle duration based on one or more control output values, the one or more control output values ​​being based at least in part on the one or more internal control signal values ​​and the one or more predicted internal measurements; A method comprising:

50. each clock cycle having the first clock cycle duration comprises a plurality of internal clock cycles having the second clock cycle duration; 50. The method of claim 49, further comprising: calculating a prediction error of the first signal by comparing the measurement of the first signal to a predicted internal measurement over a previous internal clock cycle every clock cycle.

51. The method further includes calculating a time shift amplitude error of the controlled parameter, the time shift amplitude error indicative of an error between a target value and an actual parameter value of the controlled parameter achieved at the controlled output; 50. The method of claim 49, wherein at least one of the control output values ​​is based on an internal control signal value and a time-shifted amplitude error of the controlled parameter.

52. The method comprises: calculating a first internal control signal value over a first internal clock cycle, wherein calculating the first internal control signal value is based on comparing an actual parameter value of the controlled parameter at the first internal clock cycle to a predicted measured value of the controlled parameter at the first internal clock cycle; calculating a second internal control signal value over a second internal clock cycle, the second internal clock cycle being after the first internal clock cycle, and calculating the second internal control signal value based on predicting an internal measurement value of the controlled parameter at the second internal clock cycle based on the first internal control signal value; 52. The method of claim 51, further comprising:

53. The method comprises: The initial model and the one or more predicted internal measurements; and one or more time shift amplitude errors; and one or more delays between the target values ​​of the reference signals and the corresponding actual values ​​of the controlled parameters; the target value of the controlled parameter; 50. The method of claim 49, further comprising parameterizing the internal model using one or more of:

54. The method comprises: determining at least one change in a parameterization of the internal model of the system based on one or more of the actual parameter values ​​and the prediction errors of the controlled parameters, wherein the at least one change in parameterization is determined when the actual parameter values ​​are available, at the one or more internal clock cycles, or a combination thereof; updating the internal model based on at least one change in the parameterization; 54. The method of claim 53, further comprising:

55. 55. The method of claim 54, further comprising calculating a change in a parameterization of the internal model for each internal clock cycle based on an interpolation between a previously calculated internal model and a currently calculated internal model, the previously calculated internal model and the currently calculated internal model being based on actual parameter values ​​of the controlled parameters.

56. the controlled output being an output coupled to a plasma processing chamber; the user interface is configured to at least one of allow an operator of the system to set the target value and allow a controller to set the target value; 50. The method of claim 49, wherein the at least one of

57. 50. The method of claim 49, wherein the controlled parameter is one of forward power, reflected power, a reflection coefficient, an RF driver voltage to a power amplifier, or a DC rail voltage to a power amplifier.

58. 1. A non-transitory, tangible, computer readable storage medium, the non-transitory, tangible, computer readable storage medium being encoded with processor readable instructions for performing a method for controlling a plasma processing system, the method comprising: receiving a reference signal defining a target value for a parameter to be controlled at an output within the plasma processing system; obtaining measurements of the parameter controlled at the output, the parameter being measured at a first sampling frequency, the first sampling frequency corresponding to a plurality of clock cycles, each clock cycle having a first clock cycle duration; calculating one or more internal control signal values ​​over one or more internal clock cycles of a second clock cycle duration, the second clock cycle duration being less than the first clock cycle duration; predicting one or more internal measurements of the controlled parameters over the one or more internal clock cycles based on the one or more internal control signal values ​​using an internal model; adjusting at least one actuator over the one or more clock cycles having the first clock cycle duration based on one or more control output values, the one or more control output values ​​being based at least in part on the one or more internal control signal values ​​and the one or more predicted internal measurements; A non-transitory tangible computer readable storage medium, comprising:

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