System and design method for high speed transceiver board (HSTB) of massive MIMO wireless unit

Abstract

The present invention relates generally to network devices, and more particularly to the design and architecture of High Speed ​​Transceiver Boards (HSTBs) for Massively Multiple Input / Output (MIMO) wireless units.

Description

[Technical field]

[0001] The present invention relates generally to network devices, and more particularly to the design and architecture of High Speed ​​Transceiver Boards (HSTBs) for Massively Multiple Input / Output (MIMO) wireless units. [Background technology]

[0002] The following description of related art is intended to provide background information regarding the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, this section should be understood as being used only to enhance the reader's understanding of the present disclosure and not as an admission of prior art.

[0003] 5G communication systems are expected to be implemented in sub-6 GHz and higher radio frequency (millimeter (mm) wave) bands, for example 60 gigahertz (GHz), to achieve higher data rates. To reduce radio wave propagation loss and extend transmission distances, beamforming, massive multiple input multiple output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and large-scale antenna technologies are described for use in 5G communication systems.

[0004] MIMO (Multiple Input, Multiple Output) is a wireless antenna technology that deploys one or more antennas at both the transmitter and receiver to increase the quality, throughput, and capacity of a wireless link. MIMO uses techniques known as spatial diversity and spatial multiplexing to reuse the same time and frequency resources to transmit independent, separately coded data signals, known as "streams."

[0005] MIMO is used in many modern wireless and RF technologies, including Wi-Fi and Long Term Evolution (LTE). 3GPP first specified MIMO for LTE in 2008 in its Release 8, a variant of which used two transmitters and two receivers, i.e. 2×2 MIMO. Subsequent increases in processing power have allowed the use of more simultaneous data streams in wireless networks with current 4G LTE networks using 4×4 MIMO. The very short wavelengths at mm-wave frequencies have resulted in smaller antenna dimensions, and for 5G NR, 3GPP has specified 32 antennas (32×32 MIMO). This increase in the size of MIMO antennas has led to the term Massive MIMO.

[0006] Massive MIMO is based on three key concepts: spatial diversity, spatial multiplexing, and beamforming. Existing disclosures on Massive MIMO Radio Unit (MRU) designs / architectures make the entire device very expensive, power-hungry, thermally inefficient, bulky, and require interoperability and coupling with various separate / currently independent / mismatched, cabled components such as antenna components and transceiver elements, which complicates the overall design and construction. Thus, there is a need for an MRU that efficiently integrates all these components with each other and accordingly provides a cost-effective solution where an integrated antenna filter unit (AFU) is used and blind-mates with the RF front-end board, making it a cable-less design. Summary of the Invention

[0007] In one aspect, the present disclosure relates to a high speed transceiver board (HSTB). The HSTB may include a number of transceivers providing lower L1 layer processing. The HSTB may further include a digital front-end section. The HSTB may be configured to receive an external predetermined input direct current (DC) voltage and down-convert the received external predetermined input DC voltage to a number of lower voltages based on requirements from different devices on the board.

[0008] In one embodiment, any or a combination of a power management integrated chipset (PMIC), a DC-DC converter, and a low dropout (LDO) linear regulator device may generate the multiple lower voltages.

[0009] In one embodiment, an antenna filter unit (AFU) may be operatively coupled to the HSTB to facilitate beamforming to multiple users.

[0010] In one embodiment, a radio frequency (RF) front-end module (RFEM) may be operatively coupled to the HSTB to receive RF control signals from the HSTB and process the received RF control signals through one or more gain blocks and power amplifiers to amplify the received RF control signals across one or more of the multiple transmit / receive chains to generate power from each chain.

[0011] In one embodiment, each of the multiple transceivers may be configured with multiple RF chains to handle the control signals and power.

[0012] In one embodiment, multiple chains for processing control signals and power can be DC and RF blind coupled to the RFEM to eliminate cabling complexity and avoid RF signal oscillation.

[0013] In one embodiment, one transceiver among the multiple transceivers may be configured to receive digital data / signals from a combined centralized and distributed unit (CCDU) ​​via a predetermined interface and transmit the received digital data / signals to the remaining multiple transceivers.

[0014] In one embodiment, the remaining transceivers may be configured to process high speed RF signals via analog-to-digital (ADC) converters and digital-to-analog (DAC) converters to act as a digital front end to convert transmitted digital data / signals to high speed RF signals across each set of RF chains associated with each of the remaining transceivers.

[0015] In another embodiment, the HSTB may be configured to provide power to the RF board.

[0016] In another embodiment, the HSTB may include a clock synchronization unit configured for synchronization.

[0017] In another embodiment, the clock synchronization unit may include any or a combination of an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.

[0018] In one embodiment, the HSTB may include at least one of digital high speed signals, switching power supplies, clock sections, and radio frequency signals designed on multiple layers in a printed circuit board (PCB).

[0019] In one embodiment, multiple layers in the PCB include routing channels for routing RF and Aurora signals that run at high speed on adjacent layers.

[0020] In one aspect, the present disclosure relates to a user device communicatively coupled to an HSTB, the user device may be configured to receive a connection request from the HSTB, transmit an acknowledgment of the connection request to the HSTB, and transmit a number of signals in response.

[0021] In one aspect, the present disclosure relates to a communication method that may be performed by a user equipment (UE) communicatively coupled to a high speed transceiver board (HSTB).

[0022] In one aspect, the present disclosure relates to a non-transitory computer-readable medium including processor-executable instructions that cause a processor to receive a connection request from a high-speed transceiver board HSTB, transmit an acknowledgment of the connection request to the HSTB, and transmit a plurality of signals in response, the HSTB including a plurality of transceivers providing lower L1 layer processing, and a digital front-end section in which the HSTB receives an external predetermined input direct current (DC) voltage and down-converts the received external predetermined input DC voltage to a plurality of lower voltages based on requirements from different devices on the board.

[0023] Object of the invention An object of the present invention is to provide greater spectral efficiency by enabling the antenna array to focus a narrow beam towards the user.

[0024] An object of the present invention is to provide a more energy efficient system since the antenna array is concentrated in a small specific section, which requires less radiated power and reduces the energy requirements of the massive MIMO system.

[0025] An object of the present invention is to increase the data rate and capacity of wireless systems.

[0026] It is an object of the present invention to facilitate more reliable and accurate user tracking.

[0027] The object of the present invention is to eliminate high power consumption.

[0028] An object of the present invention is to reduce latency and increase network reliability.

[0029] An object of the present invention is to provide a cableless design of a massive MIMO radio unit.

[0030] It is an object of the present invention to provide a Massive MIMO standalone unit mounted in a single convection-cooled enclosure and weighing less than 25-29 kg.

[0031] The objective of the present invention is to provide a Massive MIMO standalone unit consisting of a lower layer PHY section, an ORAN compliant fronthaul over a 25G optical interface, and digital front-end support for 32 transmit and receive chains using three commercial-grade FPGAs.

[0032] An object of the present invention is to provide a massive MIMO standalone unit that includes an IEEE 1588v2 PTP-based clock synchronization architecture over a 25G optical interface using a system synchronizer IC and a clock generator.

[0033] An object of the present invention is to provide a High Speed ​​Transceiver Board (HSTB) configured to receive an external -48V input DC voltage and downconvert it to various lower voltages (such as to 12V, then from 12V to 5V and 1V, among other combinations, as desired) based on the requirements from different devices on the board.

[0034] The accompanying drawings, which are incorporated herein and form a part of the present invention, illustrate exemplary embodiments of the disclosed method and system, with like reference numerals referring to the same parts throughout the different drawings. The components in the drawings are not necessarily drawn to scale, emphasis instead being placed on clearly illustrating the principles of the invention. Some drawings may use block diagrams to illustrate components and may not show the internal circuitry of each component. Those skilled in the art will appreciate that the inventions in such drawings include inventions in electrical components, electronic components, or circuits commonly used to implement such components. [Brief description of the drawings]

[0035] [Figure 1]1 illustrates an example design architecture of a massive MIMO wireless unit, according to an embodiment of the present disclosure. [Diagram 2] 1 illustrates an example design architecture of a high speed transceiver board (HSTB) in accordance with an aspect of the present disclosure. [Diagram 3] 1 illustrates an example combined representation of a user equipment (UE) with a MIMO radio unit according to an aspect of the present disclosure. [Figure 4] In accordance with an embodiment of the present disclosure, an exemplary computer system is shown in or with which embodiments of the present invention may be utilized. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The above will become more apparent from the following more detailed description of the invention.

[0037] In the following description, for the purpose of explanation, various specific details are set forth to provide a thorough understanding of the embodiments of the present invention. However, it will be apparent that the embodiments of the present disclosure may be practiced without these specific details. Each of the several features described below can be used alone or in any combination with other features. Individual features may not address all of the above problems, or may address only some of the above problems. Some of the above-described problems may not be fully addressed by any of the features described herein.

[0038] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with a helpful description for implementing the exemplary embodiments. It will be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the invention as described.

[0039] In the following description, specific details are provided to provide a thorough understanding of the present embodiments. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. For example, components such as circuits, systems, networks, processes, etc. may be shown as components in block diagram form in order to avoid obscuring the embodiments in unnecessary detail. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0040] It should also be noted that the particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many operations may occur in parallel or concurrently. Additionally, the order of operations may be rearranged. A process terminates when an operation of a process is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, or the like. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or to the main function.

[0041] The words "exemplary" and / or "demonstrative" are used herein in the sense of serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Moreover, any aspect or design described herein as "exemplary" and / or "illustrative" should not necessarily be construed as preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those skilled in the art. Furthermore, to the extent the detailed description or claims use similar terms, such terms, such as "includes," "has," "contains," and the like, are intended to be inclusive in the same manner as the open-ended transitional term "comprising," without excluding any additional or other elements.

[0042] Throughout this specification, references to "one embodiment" or "embodiment" or "aspect" or "one aspect" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0043] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "comprising" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] In this disclosure, various embodiments are described using terminology used in some communication standards (e.g., 3rd Generation Partnership Project (3GPP), Extensible Radio Access Network (xRAN), and Open Radio Access Network (O-RAN)) as illustrative examples only. Various embodiments of the present disclosure may also be easily modified and applied to other communication systems.

[0045] Typically, a base station is a network infrastructure that provides wireless access to one or more terminals. A base station has coverage, which is defined as a predefined geographical area based on the distance a signal can be transmitted. In addition to "base station," a base station may be referred to as an "access point (AP)," "evolved NodeB (eNodeB) (eNB)," "5G node (fifth generation node)," "next generation NodeB (gNB)," "radio point," "transmit / receive point (TRP)," or other terms having equivalent technical meanings.

[0046] The present disclosure relates to an ORAN-compliant 5G Massive MIMO Radio Unit (MRU) (hereinafter alternatively and synonymously referred to as "5G MRU" or "RU"). In an exemplary and non-limiting embodiment, the present disclosure provides a hardware architecture and design of a 5G Massive MIMO Radio Unit (MRU) based on multiple antenna configuration 32T32R in standalone mode, the proposed 5G MRU is a radio unit connected to a Composite Central Distributed Unit (CCDU) ​​over a fronthaul interface using a 25G optical interface and is compliant with 3GPP (3rd Generation Partnership Project)® based ORAN (Open Radio Access Network) specifications. The proposed MRU, in an exemplary implementation, has three cell-sites and can be configured to be used with three (3) corresponding MRUs, each of which can be connected to a CCDU via a 25G interface.

[0047] In an exemplary embodiment, the proposed 5G MRU includes a low PHY (physical) portion of the L1 layer with 7.2X network layers split (O-RAN Alliance Fronthaul Specification between O-DU and O-RRU), a baseband section, an RF (radio frequency) front-end module (RFEM), and an antenna filter unit (AFU) as part of a single enclosure / unit for easy and efficient installation. However, it should be understood that the design and architecture of each of the components / units of the proposed RU are novel and original with respect to the proposed invention, and therefore each will be protected by a respective patent application.

[0048] In an exemplary embodiment, with reference to FIG. 1, the proposed 5G MRU 100 includes a high speed transceiver board (HSTB) 200 having a lower layer PHY section, an ORAN compliant fronthaul over a 25G optical interface 204, and digital RF front-end support 250 for 32 transmit and receive chains using, for example, three commercial grade FPGAs / transceivers (202-1 through 202-3, hereafter collectively referred to as 202), which are integrated onto a dense 26 layer of the HSTB 200. It should be understood that although the disclosure is described with respect to FPGAs, any other equivalent transceivers are fully within the scope of the disclosure, and thus the scope of each FPGA should be treated as the scope of any transceiver or technically equivalent component such as an ASIC.

[0049] In an exemplary embodiment, the development and bitstream generation of the L1 lower layer PHY can be implemented / performed in the FPGA 202 itself. The L1 upper layer can be configured in the CCDU below the tower, and L2 and L3 are configured in the distributed units, and the macro site usually includes a central unit node (server side) and a distributed unit node (configured between the CU and the RU). The present invention merges the central unit node with the distributed unit nodes to form a CCDU that interfaces with the RU / MRU via a 25G optical interface as proposed in this disclosure. The proposed MRU can further include an IEEE 1588v2 PTP-based clock synchronization architecture on the 25G optical interface 204 using a system synchronizer IC and a clock generator.

[0050] The proposed MRU 100 may further include an integrated 8×8 MIMO antenna with 32 cavity filters as one unit known as an antenna filter unit (AFU) 280. The proposed MRU 100 may be blind mated as configured and have a cableless design.

[0051] In an exemplary and non-limiting aspect of the present disclosure, the proposed 5G MRU 100 is a 200W high power gNB operating at macro class (typically 6.25W or 38dBm per antenna port) and configured to provide a macro-level wide area solution for coverage and capacity useful in dense urban configurations and within hot zone / hot spot areas with high traffic and QoS requirements. The proposed 5G MRU 100 brings together a lower layer PHY section, a commercial grade RFGA based RF transceiver for 32 transmit and receive chains (as part of the HSTB 200), an RF Front End Module (RFEM) 250 including RF power amplifiers, low noise amplifiers (LNAs), and RF switches for the 32 chains, and an 8*8 MIMO antenna in conjunction with 32 cavity filters known as an Antenna Filter Unit (AFU) 280, weighing less than 25-29 kg, as part of a single convection cooled enclosure. In one aspect, the macro gNB can provide superior coverage and capacity in dense urban clutter due to support of eight downlink beams and four uplink beams in multiple UE situations. The proposed 5G MRU 100 can be deployed in high-rise buildings, dense clutter, and hotspot locations where traffic demand is significantly higher and 4G gNB alone cannot serve for increased coverage and capacity.

[0052] In another aspect, the proposed 5G MRU 100 can be configured as a design with an integrated antenna and cavity filter solution that does not require the use of cables, making the 5G MRU 100 a cableless design. The proposed 5G MRU 100 can be deployed at tower sites, i.e., GBT and GBM. The MRU can be rapidly deployed to deliver high performance with less power consumption, making the MRU a power-efficient solution. The proposed 5G MRU can be connected to the CCDU down the tower on a single 25G optical fronthaul interface that is compliant with 3GPP ORAN.

[0053] In one aspect, the proposed 5G MRU is a high-power gNB (Next Generation Node B) operating at macro class (typically ≦38 dBm per antenna port) and can be configured to complement macro-level wide area solutions for coverage and capacity. In an exemplary aspect, the high-level architecture of the proposed 32T32R 5G NR MRU can include a high-speed transceiver board (HSTB) 200, a 32T32R RF front-end module (RFEM) board 250, an antenna filter unit (AFU) 280, and mechanical housings (in one example, there may be two housings, one for the HSTB 200 and one for the RFEM 250). The proposed MRU structure further facilitates and enables optimal heat dissipation for operation in weather conditions ranging from −10 degrees Celsius to 50 degrees Celsius.

[0054] In an exemplary embodiment, the proposed 5G NR MRU 100 packs together a lower layer PHY section, an RF transceiver based on a commercial grade RFGA for 32 transmit and receive chains with RF sampling (no intermediate frequency stage) (as part of the HSTB 200), an RF front-end module (RFEM) 250 including RF power amplifiers, low noise amplifiers (LNAs), and RF switches for the 32 chains, and an 8*8 MIMO antenna in conjunction with 32 cavity filters known as an antenna filter unit (AFU) 280 weighing ≦29 kg in a single convection-cooled enclosure.

[0055] In an exemplary embodiment, the proposed MRU 100 includes 64 connectors, 32 on each of the transmit and receive sides, and two DC connectors, each with 25 pins, for a total of 50 pins for the two DC connectors. These connectors are configured with HSTB 200 such that they blindly connect / map / mate / sandwich the RFEM boards one on top of the other.

[0056] In one aspect, the proposed design architecture consists of a control plane, a user plane and a synchronization plane, where the control plane is configured to control the configuration of the units / sub-units forming part of the proposed MRU 100 from a distance-plane perspective, the user plane consists of user data and finally, the synchronization plane is configured to utilize the Precision Time Base Protocol (PTP) in the current 25G interface to synchronize the units / sub-units to a global clock using a timing protocol (i.e. a slave device will synchronize its clock in terms of phase and frequency with the master device) and maintain alignment / synchronization with the CCDU.

[0057] It should be appreciated that the proposed MRU meets all RF performance requirements mentioned in the 3GPP® standard (TS38.141) after integrating a TDD-based 5G NR MRU with a Crest Factor Reduction (CFR) and Digital Pre-Distortion (DPD) module in a digital front-end lineup. Moreover, the MRU has low power consumption and is optimally heat-treated with an IP65 ingress-protected mechanical housing.

[0058] High Speed ​​Transceiver Board (HSTB) 200 1 and 2, in an exemplary embodiment, the HSTB 200 may include three (3) FPGA chipsets 202-1, 202-2, and 202-3 for lower L1 layer processing and digital front-end section. The HSTB 200 may be configured to receive an external -48V input DC voltage and downconvert it to various lower voltages (such as to 12V, then from 12V to 5V and 1V, among other combinations, as desired) based on requirements from different devices on the board. Any or combination of the power supply section 208 including power management integrated chipsets (PMICs) 206, 208-1, and 208-2, and low dropout (LDO) regulator devices 210 may be used to generate a regulated power supply.

[0059] In one embodiment, the HSTB 200 may be configured to receive an external -48V input DC voltage. The HSTB 200 may downconvert the received voltage to 28V using an isolated power supply and downconvert it again to 12V using a non-isolated power supply.

[0060] In an exemplary implementation, the transceiver 202-1 can be configured to receive digital data / signals from the CCDU and transmit them to the transceiver 202-2 / 202-3, which will convert the digital data to RF signals across 32 chains that will be operatively coupled to the RF board 212 (e.g., one transceiver can handle / manage 16 chains / control signals and power, and a second transceiver can handle / manage an additional 16 chains / control signals and power (that will be blind-coupled for DC and RF). The RF board 212, which is a passive element, obtains power from the HSTB 200 to reduce and optimize overall cost and draw as much power as needed from the HSTB 200 itself. In one embodiment, the power received by the transceivers 202-2, 202-3 can be regulated through a combination of a power management integrated circuit (PMICS) 206 and a switching buck / boost regulator / LDO device 210.

[0061] In one embodiment, the RF board 212 may include multiple BALUNs to provide impedance transformation and deliver optimal power during ADC and DAC conversion.

[0062] In one aspect, the complete system can be synchronized within the HSTB 200 (e.g., using the clock / sync section 214) via IEEE 1588v2 based PTP over the 25G fronthaul interface 204 with a PTP client to the implemented synchronization circuitry. The proposed circuitry can include any or a combination of ultra-low noise clock generation PLLs, programmable oscillators, and system synthesizers. Additionally, the clock / sync section 214 can include system synthesizers, ADC and DAC clock generators, system clocks, and Peripheral Component Interconnect Express (PCIe) generators that provide synchronization between the clocks of the transceiver 202-1 and the transceivers 202-2, 202-3.

[0063] 2 shows an example overall design architecture of the proposed HSTB 200, which may include subsystems including, but not limited to, FPGA-based RF transceivers, digital high speed signals, switching power supplies, clock sections, and radio frequency signals designed on a 26-layer PCB. The PCB design may include proprietary design techniques to route RF and Aurora signals running at high speeds of 25 GT / s on adjacent layers and meet the design specifications.

[0064] In one aspect, the HSTB 200 can be configured with transceivers (such as FPGAs) to acquire data from a CCDU residing in an ODC (Outdoor Cabinet) via a 25 Gigabit fiber interface (exemplary) and process the acquired digital data to provide RF signal(s). The other two transceivers can then be configured to act as a digital front-end to process high-speed RF signals via analog-to-digital (ADC) converters and digital-to-analog (DAC) converters. The analog signals will then be sent to an RF connector that will blind mate with an RFEB. The transceivers configured on the HSTB can be configured to provide 78 bands (exemplary) of RF signals to 32 chips on transmit and 32 chips on receive. In an exemplary aspect, the size of the proposed HSTB may be about 530*360mm and will be configured as a 26 or more layer board.

[0065] 2 illustrates exemplary components of the HSTB 200, in other embodiments the HSTB 200 may include fewer components, different components, components in a different arrangement, or additional functional components than those illustrated in FIG 2. Additionally or alternatively, one or more components of the HSTB 200 may perform functions described as being performed by one or more other components of the HSTB 200.

[0066] FIG. 3 illustrates an exemplary coupled representation of a user equipment (UE) with an MRU. As illustrated, the UE 302 may be communicatively coupled to the MRU 100. The coupling may be via a wireless network 304. In an exemplary embodiment, the communication network 304 may include at least a portion of one or more networks having one or more nodes that transmit, receive, forward, generate, buffer, store, route, switch, process, or any combination thereof, such as, by way of example and not limitation, one or more messages, packets, signals, waves, voltage or current levels, any combination thereof, and the like. The UE 302 may be any handheld device, mobile device, palmtop, laptop, smartphone, pager, and the like. As a result of the coupling, the UE 302 may be configured to receive a connection request from the MRU 100, transmit an acknowledgment of the connection request to the MRU 100, and further transmit a number of signals in response to the connection request.

[0067] Exemplary Computer System 400 FIG. 4 illustrates an exemplary computer system in which or with which embodiments of the present disclosure may be utilized, according to an embodiment of the present disclosure. As illustrated in FIG. 4, computer system 400 may include an external storage device 410, a bus 420, a main memory 430, a read-only memory 440, a mass storage device 450, a communication port 460, and a processor 470. Those skilled in the art will recognize that a computer system may include more than one processor and communication port. Processor 470 may include various modules associated with embodiments of the present invention. Communication port 460 may be an RS-232 port for use with a modem-based dial-up connection, a 10 / 100 Ethernet port, a gigabit or 10 gigabit port using copper or fiber, a serial port, a parallel port, or any other existing or future port. Communication port 460 may be selected depending on the network, such as a local area network (LAN), a wide area network (WAN), or any network to which the computer system is connected. Memory 430 may be a random access memory (RAM), or any other dynamic storage device commonly known in the art. Read-only memory 440 may be any static storage device(s). Mass storage 450 may be any current or future mass storage solution that can be used to store information and / or instructions.

[0068] The bus 420 communicatively couples the processor(s) 470 with other memory, storage, and communication blocks.

[0069] Optionally, operator and management interfaces such as a display, keyboard, and cursor control devices may also be coupled to bus 420 to support direct operator interaction with the computer system. Other operator and management interfaces may be provided through a network connection connected through communications port 460. The above components are intended only to illustrate various possibilities. The exemplary computer system described above is not intended to limit the scope of the present disclosure.

[0070] In one aspect of the present disclosure, a communication method is disclosed that may be performed by a user equipment (UE) communicatively coupled to a high speed transceiver board (HSTB) (200). The HSTB may include a number of transceivers providing lower L1 layer processing. The HSTB may further include a digital front-end section. The HSTB may be configured to receive an external, predetermined input direct current (DC) voltage and down-convert the received external, predetermined input DC voltage to a number of lower voltages based on requirements from different devices on the board.

[0071] Although considerable emphasis has been placed herein on the preferred embodiment, it should be understood that many embodiments may be made and many changes may be made in the preferred embodiment without departing from the principles of the invention. These and other changes in the preferred embodiment of the invention will be apparent to those skilled in the art from the disclosure herein, and it should be clearly understood that the foregoing description is to be taken merely as illustrative and not limiting of the invention.

[0072] Portions of the disclosure of this patent document contain material that is subject to intellectual property rights, including but not limited to copyright, designs, trademarks, IC layout designs, and / or trade dress protection, belonging to Jio Platforms Limited (JPL) or its affiliates (hereinafter referred to as the Owner). The Owner has no objection to anyone copying this patent document or the patent disclosure to the extent that it appears in a Patent and Trademark Office patent application or records, but otherwise reserves all rights. All rights to such intellectual property are fully reserved by the Owner.

[0073] Advantages of the Invention The present invention provides a wireless unit with higher spectral efficiency by enabling its antenna array to focus a narrow beam towards the user.

[0074] The present invention provides a more energy efficient system since the antenna array is concentrated into a small specific section, which requires less radiated power, reducing the energy requirements of the massive MIMO system.

[0075] The present invention provides a radio unit that increases the data rate and capacity of a wireless system.

[0076] The present invention provides a wireless unit that facilitates more reliable and accurate user tracking.

[0077] The present invention provides a wireless unit that eliminates high power consumption.

[0078] The present invention provides a wireless unit that reduces latency and increases network reliability.

[0079] The present invention provides a cable-less design for a massive MIMO radio unit.

[0080] The present invention provides a Massive MIMO standalone unit housed in a single convection-cooled enclosure and weighing less than 25-29 kg.

[0081] The present invention provides a Massive MIMO standalone unit that includes a lower layer PHY section, an ORAN compliant fronthaul over a 25G optical interface, and digital front-end support for 32 transmit and receive chains using three commercial-grade FPGAs.

[0082] The present invention provides a massive MIMO standalone unit that includes an IEEE 1588v2 PTP-based clock synchronization architecture over a 25G optical interface using a system synchronizer IC and a clock generator.

[0083] The present invention provides a High Speed ​​Transceiver Board (HSTB) configured to receive an external -48V input DC voltage and downconvert it to various lower voltages (such as to 12V, then from 12V to 5V and 1V, among other combinations, as desired) based on the requirements from different devices on the board.

Claims

1. A high speed transceiver board (HSTB) (200), a plurality of transceivers (202-1, 202-2, 202-3) providing lower L1 layer processing; A digital front end section, comprising: Receive a predetermined external input direct current (DC) voltage; down-converting the received external predetermined input DC voltage to multiple lower voltages based on requirements from different devices on the HSTB (200); and the digital front end section configured as follows:

2. The HSTB (200) of claim 1, wherein any one or combination of a power management integrated chipset (PMIC) (206), a DC-DC converter (208), and a low dropout (LDO) linear regulator device (210) is configured to generate the multiple lower voltages.

3. The HSTB (200) of claim 1, wherein the HSTB (200) is operatively coupled with an antenna filter unit (AFU) (280) to facilitate beamforming to multiple users.

4. 2. The HSTB (200) of claim 1, operatively coupled to a radio frequency (RF) front-end module (RFEM) (250) to receive RF control signals and process the received RF control signals through one or more gain blocks (252) and power amplifiers (254) to amplify the received RF control signals across one or more of a plurality of transmit / receive chains and generate power from each chain.

5. The HSTB (200) of claim 1, wherein each of said plurality of transceivers (202-1, 202-2, 202-3) is configured with a plurality of radio frequency (RF) chains for processing control signals and power.

6. The HSTB (200) of claim 5, wherein the multiple RF chains for processing the control signals and the power are blind-coupled to a radio frequency (RF) front-end module (RFEM) (250) for DC and RF to eliminate cabling complexity and avoid RF signal oscillation.

7. One transceiver (202-1) among the plurality of transceivers (202-1, 202-2, 202-3), receiving digital data / signals from a Composite Centralized Distributed Unit (CCDU) ​​via a predetermined interface; The HSTB (200) of claim 1, configured to transmit the received digital data / signals to the remaining transceivers (202-2, 202-3).

8. The remaining transceivers (202-2, 202-3) acts as a digital front-end section for processing high frequency radio frequency (RF) signals via analog-to-digital (ADC) and digital-to-analog (DAC) converters; 8. The HSTB (200) of claim 7, configured to convert the transmitted digital data / signals to high speed RF signals across a respective set of at least 16 RF chains associated with each of the remaining plurality of transceivers (202-2, 202-3).

9. The HSTB (200) of claim 1, wherein the HSTB (200) is configured to provide power to a radio frequency (RF) board (212).

10. The HSTB (200) of claim 1, wherein the HSTB (200) comprises a clock synchronization unit (214) for synchronization.

11. 11. The HSTB (200) of claim 10, wherein the clock synchronization unit (214) comprises any one or combination of an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.

12. 10. The HSTB (200) of claim 1, wherein the HSTB (200) comprises at least one of digital high speed signal, switching power supply, and clock sections designed on multiple layers in a printed circuit board (PCB).

13. 13. The HSTB (200) of claim 12, wherein the layers in the PCB include a plurality of routing channels for routing radio frequency (RF) and Aurora signals running at high speeds on adjacent layers.

14. A user equipment (UE) communicatively coupled to a high speed transceiver board (HSTB) (200), the UE comprising: receiving a connection request from the HSTB (200); Sending an acknowledgment of said connection request to said HSTB (200); configured to transmit a plurality of signals in response thereto; The HSTB (200), a plurality of transceivers (202-1, 202-2, 202-3) providing lower L1 layer processing; A digital front end section, comprising: Receive a predetermined external input direct current (DC) voltage; down-converting the received external predetermined input DC voltage to multiple lower voltages based on requirements from different devices on the board; and the digital front end section configured to:

15. A communication method performed by a user equipment (UE) communicatively coupled to the high speed transceiver board (HSTB) (200) of claim 1.

16. A non-transitory computer readable medium containing processor-executable instructions, the non-transitory computer readable medium comprising: Receive a connection request from a high speed transceiver board (HSTB) (200); causing the HSTB (200) to send an acknowledgment of the connection request; processor-executable instructions that cause a plurality of signals to be transmitted in response thereto; The HSTB (200), a plurality of transceivers (202-1, 202-2, 202-3) providing lower L1 layer processing; A digital front end section, comprising: Receive a predetermined external input direct current (DC) voltage; down-converting the received external predetermined input DC voltage to multiple lower voltages based on requirements from different devices on the board; and the digital front end section configured to:

Images