Single-Side Via Filling Process for Through Vias

Abstract

Methods and apparatuses for single-sided filling of through vias in a substrate are provided herein. In some embodiments, a method for filling through vias in a substrate includes bonding a first side of a substrate having through vias to a carrier plate with an adhesive layer, exposing the through vias to a conductive layer disposed between the carrier plate and the first side of the substrate, and plating the substrate using the conductive layer as a conductive seed layer to fill the through vias with a conductive material.

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate generally to semiconductor substrate processing. [Background technology]

[0002] In semiconductor packaging, one or more layers of die are typically stacked on a substrate to form an integrated circuit. The various circuit elements are connected through conductive connectors to form a complete circuit, which may contain millions of individual circuit elements. Interconnects provide electrical connections between the various circuit elements and the device's external contact elements, such as pins for connecting the integrated circuit to other circuits. Interconnects are typically formed through metal-filled through-vias in the substrate. Copper is often used as the metal fill for the vias. However, copper will likely diffuse to the surroundings unless it is contained in, for example, a liner. However, conventional through-via filling process flows require complex deposition of liner layers, seed layers, and planarization of secondary field deposition.

[0003] Accordingly, the inventors have provided herein an improved method and apparatus for filling through vias in a substrate. Summary of the Invention

[0004] Methods and apparatuses for single-sided filling of through vias in a substrate are provided herein. In some embodiments, a method for filling through vias in a substrate includes bonding a first side of a substrate having through vias to a carrier plate with an adhesive layer, exposing the through vias to a conductive layer disposed between the carrier plate and the first side of the substrate, and plating the substrate using the conductive layer as a conductive seed layer to fill the through vias with a conductive material.

[0005] In some embodiments, a method for filling through vias in a substrate includes bonding a first side of a substrate having through vias to a carrier plate with an adhesive layer, exposing the through vias to a conductive layer disposed between the carrier plate and the first side of the substrate, plating the substrate using the conductive layer as a conductive seed layer to fill the through vias with a conductive material, removing the carrier plate from the substrate, covering an upper surface of the substrate with an upper polymer layer, and covering a lower surface of the substrate with a lower polymer layer.

[0006] Other and further embodiments of the present disclosure are described below.

[0007] Embodiments of the present disclosure, briefly summarized above and described in more detail below, can be understood by reference to exemplary embodiments thereof as illustrated in the accompanying drawings, which, however, depict only typical embodiments of the present disclosure and therefore should not be considered limiting in scope, since the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0008] [Figure 1] 1 is a flowchart of a method of filling through vias in a substrate in accordance with at least some embodiments of the present disclosure. [Figure 2A] 1 is a schematic cross-sectional view of a substrate removed from a carrier plate, in accordance with at least some embodiments of the present disclosure. [Figure 2B] 2B is a schematic cross-sectional view of the substrate of FIG. 2A coupled to a carrier plate, according to at least some embodiments of the present disclosure. [Diagram 3] 1 is a schematic cross-sectional view of a substrate coupled to a carrier plate, according to at least some embodiments of the present disclosure. [Figure 4] 1 is a schematic cross-sectional view of a substrate having a filled through via and covered with a membrane layer, in accordance with at least some embodiments of the present disclosure. [Diagram 5]1 is a schematic cross-sectional view of a substrate coupled to a carrier plate, according to at least some embodiments of the present disclosure. [Figure 6A] FIG. 1 illustrates a single substrate plating apparatus in accordance with at least some embodiments of the present disclosure. [Figure 6B] FIG. 1 illustrates a two-substrate plating apparatus in accordance with at least some embodiments of the present disclosure.

[0009] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Methods and apparatus are provided herein for single-sided filling of through vias in a substrate. The methods and apparatus described herein provide an alternative to conventional through-silicon via (TSV)-like filling processes that include deposition of a conformal PVD seed layer prior to the filling process. The methods described herein include exposing the through via to a temporary bottom seed layer to facilitate filling the through via by a plating process, to advantageously overcome much of the cost and complexity of filling blind through vias, generally using specialized chemicals and complex deposition and etching processes, followed by in situ deposition chemical mechanical polishing (CMP). The methods provided herein also advantageously facilitate faster filling than double-sided approaches, with less tendency for voids in the through via.

[0011] FIG. 1 illustrates a flow chart of a method for filling through vias in a substrate according to at least some embodiments of the present disclosure. The substrate (e.g., substrate 220) can be any suitable type of substrate, such as an interposer or an advanced substrate (e.g., an active substrate with embedded features). The substrate can be made of silicon, glass, or other suitable materials. The method 100 includes, at 102, bonding a first side (e.g., first side 208) of a substrate having through vias (e.g., through vias 240) to a carrier plate (e.g., carrier plate 210) with an adhesive layer (e.g., adhesive layer 230). In some embodiments, the substrate is about 200 to about 500 microns thick. In some embodiments, the through vias have a diameter of about 20 to about 120 microns. In some embodiments, the through vias have a diameter of about 20 to about 60 microns. In some embodiments, the substrate is rectangular in shape and has a side that is about 0.4 to about 0.6 meters.

[0012] FIG. 2A illustrates a schematic cross-sectional view of a substrate 220 removed from a carrier plate 210, according to at least some embodiments of the present disclosure. The substrate 220 includes a plurality of through vias 240 disposed through the substrate 220 and extending from a first side 208 to a second side 212 opposite the first side 208. In some embodiments, as illustrated in FIG. 2A, an adhesive layer 230 is disposed on or applied to the first side 208 of the substrate 220. In some embodiments, the adhesive layer 230 may be disposed on or applied to the carrier plate 210. In some embodiments, the adhesive layer 230 is applied via spin coating or spray coating as a film or as a liquid. In some embodiments, the adhesive layer 230 is a temporary layer. In some embodiments, if the adhesive layer 230 is applied as a liquid, the liquid may be partially cured to reduce splatter or contamination. Adhesive layer 230 can be suitably thick enough to bond substrate 220 to carrier plate 210, yet thin enough to allow for easy removal. In some embodiments, adhesive layer 230 is from about 2 to about 100 microns thick, such as from about 2 to about 50 microns thick or from about 2 to about 5 microns thick.

[0013] FIG. 2B illustrates a schematic cross-sectional view of the substrate 220 of FIG. 2A coupled to a carrier plate 210, according to at least some embodiments of the present disclosure. The carrier plate 210 generally covers ends 218 of a plurality of through vias 240 on a first side 208 of the substrate 220. In some embodiments, the carrier plate 210 comprises a conductive layer 204 formed on an upper surface of the carrier plate 210 and adjacent to an adhesive layer 230. In some embodiments, the conductive layer 204 forms a conductive seed layer having a thickness of about 1000 to about 5000 angstroms. In some embodiments, the conductive layer 204 comprises a copper layer. In some embodiments, the carrier plate 210 comprises a conductive layer 204, such as a copper layer disposed on a glass or stainless steel core or sublayer. In some embodiments, the carrier plate 210 is a solid plate without through holes.

[0014] The method 100 includes exposing 104 through vias in a conductive layer disposed between the carrier plate and the first side of the substrate. In some embodiments, as shown in Figures 2A and 2B, the adhesive layer 230 is a non-conductive adhesive layer. In such embodiments, the method 100 includes forming through holes 216 in the adhesive layer 230 at locations corresponding to or aligned with the through vias 240 such that the conductive layer 204 of the carrier plate 210 is exposed to the through vias 240. The drilling may include mechanical drilling, laser drilling, or the like.

[0015] FIG. 3 illustrates a schematic cross-sectional view of a substrate 220 bonded to a carrier plate 210, according to at least some embodiments of the present disclosure. In some embodiments, as illustrated in FIG. 3, the adhesive layer 230 is a conductive adhesive layer that forms a conductive seed layer. In such embodiments, the adhesive layer 230 does not need to be etched to expose the through vias 240, as the conductive adhesive layer is sufficient to facilitate subsequent plating processes thereon. In some embodiments, the conductive adhesive layer has a sheet resistance value of about 86 to about 3400 meters ohms per square (m*ohm / sq). In some embodiments, if the carrier plate 210 includes a conductive layer 204, the conductive adhesive layer has a sheet resistance value of about 860 to about 3400 m*ohm / sq. In some embodiments, if the carrier plate 210 does not include a conductive layer 204 and the conductive adhesive layer forms a conductive seed layer, the conductive adhesive layer has a sheet resistance value of about 86 to about 344 m*ohm / sq.

[0016] Referring again to FIG. 1 , the method 100 includes, at 106, plating a substrate using a conductive layer as a conductive seed layer (e.g., conductive layer 204, conductive adhesive layer, foil layer 520) to fill the through vias with a conductive material (e.g., conductive material 408). In some embodiments, plating the substrate to fill the through vias is advantageously performed without an intervening deposition process in the through vias, e.g., without a PVD or CVD process. Plating the substrate may be performed via any suitable horizontal or vertical plating process. For example, FIG. 6A shows a schematic diagram of a single substrate plating apparatus 600A and FIG. 6B shows a schematic diagram of a two substrate plating apparatus 600B in accordance with at least some embodiments of the present disclosure. Both the single substrate plating apparatus 600A and the two substrate plating apparatus 600B generally include a chamber body 602 defining an interior volume 610 therein.

[0017] The interior volume 610 contains a liquid bath 604 having metal ions of a suitable composition for electroplating. The liquid bath 604 is filled high enough to submerge the carrier plate 210 coupled to the substrate 220. The chamber body 602 is coupled to a pump 615 configured to regulate and replenish the flow of the liquid bath 604 in the interior volume 610. A heater 620 may be coupled to the chamber body 602 to control the temperature of the plating process. For the single substrate plating apparatus 600A, a first power supply 606 is coupled on one side to an anode 630 disposed in the interior volume 610 and on another side to the carrier plate 210. The conductive seed layer of the carrier plate 210 attracts the metal ions, e.g., copper ions, in the liquid bath 604, thereby filling the through vias 240 of the substrate 220 with metal.

[0018] For the two-substrate plating apparatus 600B, a first power supply 606 is coupled on one side to an anode 630 disposed in the interior volume 610 and on the other side to a first of the carrier plates 210. A second power supply 616 is coupled on one side to a second anode 632 disposed in the interior volume 610 and on the other side to a second of the carrier plates 210. The conductive seed layers of the two carrier plates 210 attract metal ions, e.g., copper ions, in the liquid bath 604, thereby filling the through vias 240 of the substrate 220 with metal.

[0019] Referring again to FIG. 1, the method 100 optionally includes, at 108, removing the carrier plate from the substrate. In some embodiments, after plating the substrate, removing the carrier plate from the substrate by applying heat to the adhesive layer. The method 100 includes, at 110, covering an upper surface of the substrate with an upper film layer (e.g., upper film layer 420) and covering a lower surface of the substrate with a lower film layer (e.g., lower film layer 410). In some embodiments, the upper and lower film layers have a thickness of about 10 to about 50 micrometers. The upper and lower film layers may serve to at least one of passivate or planarize the substrate. In some embodiments, the method 100 includes drilling holes (e.g., holes 418) through the upper film layer and drilling holes (e.g., holes 422) through the lower film layer to expose the conductive material in the through via. In some embodiments, covering the upper surface and covering the lower surface of the substrate includes applying a liquid polymer to the upper surface, which when cured forms an upper film layer, and applying a liquid polymer to the lower surface, which when cured forms a lower film layer. The upper film layer may generally comprise an upper polymer layer. The lower film layer may generally comprise a lower polymer layer. In some embodiments, the upper film layer and the lower film layer comprise Ajinomoto Build-Up Film (ABF)®, available from and registered trademark of Ajinomoto Co., Inc., located in Tokyo, Japan.

[0020] 4 shows a schematic cross-sectional view of a device 400 comprising a substrate 220 with a filled through via and covered with a membrane layer, according to at least some embodiments of the present disclosure. The through via 240 is filled with a conductive material 408. In some embodiments, the membrane layer may comprise an upper membrane layer 420 disposed on the second side 212, or upper surface, of the substrate 220. In some embodiments, a lower membrane layer 410 is disposed on the first side 208, or lower surface, of the substrate 220. During the plating process, the conductive material 408 may be overfilled 440 or underfilled. The lower membrane layer 410 and the upper membrane layer 420 may compensate for the overfilled 440 or underfilled through via 240 and advantageously form a generally flat planar surface for subsequent processing without costly or cumbersome CMP processes.

[0021] The upper membrane layer 420 may include one or more holes 418 aligned with one or more of the plurality of through vias 240 to expose the conductive material 408 to form a metal interconnect for a subsequent layer. The lower membrane layer 410 may include one or more holes 422 aligned with one or more of the plurality of through vias 240 to expose the conductive material 408 to form a metal interconnect for a subsequent layer. The one or more holes 418 and the one or more holes 422 may be formed via any suitable method, for example, via laser ablation, plasma etching with a hard mask, or mechanical drilling. In some embodiments, the upper membrane layer 420 and the lower membrane layer 410 may be laminated in a plate by heat and vacuum after forming the one or more holes 418 and the one or more holes 422.

[0022] FIG. 5 shows a schematic cross-sectional view of a substrate 220 bonded to a carrier plate 210, according to at least some embodiments of the present disclosure. In some embodiments, the adhesive layer 230 is a temporary adhesive layer applied to the carrier plate 210. In some embodiments, the temporary adhesive layer comprises a non-conductive adhesive. In some embodiments, a second adhesive layer 510 is bonded to the first side 208 of the substrate 220. The second adhesive layer 510 may comprise a permanent adhesive layer. In some embodiments, the second adhesive layer 510 is a conductive layer. The second adhesive layer 510 is generally thinner than the adhesive layer 230. A foil layer 520 may be bonded between the adhesive layer 230 and the second adhesive layer 510. In some embodiments, the foil layer 520 is a copper foil layer. The foil layer 520 may provide a conductive layer that is used as a conductive seed layer for filling the through vias 240 in a plating process.

[0023] Returning to FIG. 1 , in some embodiments, prior to plating the substrate to fill the through vias, the method 100 includes applying a temporary adhesive layer (e.g., adhesive layer 230) to the carrier plate and applying a second adhesive layer (e.g., second adhesive layer 510) to the substrate. In some embodiments, the method 100 includes bonding a foil layer (e.g., foil layer 520) to the second adhesive layer on the opposite second adhesive side of the substrate and attaching the foil layer to the temporary adhesive layer applied to the carrier plate. In some embodiments, after plating the substrate to fill the through vias, the temporary adhesive layer is removed from the foil layer. In some embodiments, after plating the substrate to fill the through vias, the foil layer and the second adhesive layer are removed. In some embodiments, the foil layer is removed via an etching process. In some embodiments, the second adhesive layer is removed via a solvent cleaning process. In some embodiments, the method 100 includes forming a redistribution layer on the substrate configured to route electrical connections from the plurality of through vias 240 filled with conductive material 408 to other device components.

[0024] As used herein, the term about can include within ten percent of the specified value. While the above is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method of filling through vias in a substrate, comprising the steps of: bonding a first side of the substrate having a through via to a carrier plate with an adhesive layer; exposing the through via to a conductive layer disposed between the carrier plate and the first side of the substrate; plating the substrate using the conductive layer as a conductive seed layer to fill the through vias with a conductive material; A method comprising:

2. The method of claim 1 , wherein the conductive layer is a layer formed on an upper surface of the carrier plate.

3. the adhesive layer is a non-conductive adhesive layer, Etching the adhesive layer at locations corresponding to the through vias such that the conductive layer formed on the carrier plate is exposed at the through vias. The method of claim 2 , further comprising:

4. The method of claim 1 , further comprising, after plating the substrate, removing the carrier plate from the substrate by applying heat to the adhesive layer.

5. The method of claim 4 , further comprising covering an upper surface of the substrate with an upper polymer layer and covering a lower surface of the substrate with a lower polymer layer to passivate and planarize the substrate.

6. 6. The method of claim 5, further comprising forming holes through the upper and lower polymer layers via laser ablation, plasma etching, or mechanical drilling to expose the conductive material in the through via.

7. The method of claim 1 , wherein the adhesive layer is a conductive adhesive layer used as the conductive seed layer.

8. The method of any one of claims 1 to 6, wherein the conductive layer is about 1000 to about 5000 angstroms thick.

9. the adhesive layer is a temporary adhesive layer applied to the carrier plate; applying a second adhesive layer to the substrate; bonding a foil layer to the second adhesive layer on a side of the second adhesive layer opposite the substrate, the foil layer forming the conductive layer; Attaching the foil layer to the temporary adhesive layer applied to the carrier plate; The method of claim 1 , further comprising:

10. the second adhesive layer being a permanent adhesive; removing the temporary adhesive layer from the foil layer; performing an etching process to remove said foil layer and said second adhesive layer; The method of claim 9 further comprising:

11. The method of claim 10 , wherein the second adhesive layer is thinner than the adhesive layer.

12. The method of any one of claims 1 to 6, wherein the substrate is about 200 to about 500 microns thick.

13. The method of any one of claims 1 to 6, wherein the adhesive layer is from about 2 to about 100 microns thick.

14. 7. The method of claim 1, wherein plating the substrate is performed without an intervening deposition process in the through via.

15. The method of claim 1 , wherein the carrier plate comprises a copper layer disposed on a glass or stainless steel core.

16. The method of any one of claims 1 to 6, wherein the through vias have a diameter of about 20 to about 120 microns.

17. covering an upper surface of the substrate with an upper polymer layer and covering a lower surface of the substrate with a lower polymer layer to passivate and planarize the substrate; 7. The method of claim 1, further comprising: covering the upper surface and covering the lower surface of the substrate comprising applying a liquid polymer to the upper surface that, when cured, forms the upper polymer layer; and applying the liquid polymer to the lower surface that, when cured, forms the lower polymer layer.

18. 7. The method of claim 1, wherein the carrier plate does not include a conductive layer, and the adhesive layer comprises a conductive adhesive layer having a sheet resistance value of about 86 to about 344 meter ohms per square (m*ohm / sq).

19. The method according to any one of claims 1 to 6, wherein the substrate is made of glass or silicon.

20. The method of claim 1 , wherein the conductive material is copper.

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