Power semiconductor device with shallow conduction region - Patents.com

Abstract

The power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the mesa adjacent to the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration greater than the first doping concentration.

Description

[Technical field]

[0001] The present disclosure relates to semiconductor devices, and in particular to Junction Field Effect Transistor (JFET) power semiconductor devices. [Background technology]

[0002] A conventional n-channel vertical JFET structure 10 is shown in FIG. 1A. The vertical JFET structure 10 includes an n+ drain layer 26 on which an n- drift layer 15 is formed. An n-type channel region 24 is on the drift layer 15, and an n+ source layer 16 is on the channel region 14. An n++ source contact layer 38 is on the n+ source layer. A drain resistor contact 28 is on the drain layer 26, and a source resistor contact 40 is on the source contact layer 38. The channel region 24, the source layer 16, and the source contact layer 38 are provided as part of a mesa 12 on the drift layer 15. A p+ gate region 18 is provided as part of the mesa 12 adjacent the channel region 24. A p++ shield region 32 is provided adjacent to the gate region 18, and a gate resistor contact 36 is formed on the shield region 32. A passivation layer 42 is on the gate resistor contact 36 and the shield region 32.

[0003] FIG. 1A shows one half of a vertical JFET unit cell structure 10. The overall structure is symmetrical about axis 30 and includes two gate regions 18 as part of mesa 12 on opposite sides of channel region 24. That is, only a cross section of one half of a JFET device is shown in FIG. 1A. The portion shown can be mirrored along vertical axis 30 to obtain the full pitch of the device's unit cells. A complete JFET device includes many such unit cells. For clarity, FIG. 1C shows an entire JFET unit cell 10 including half cells 10A, 10B sharing the same mesa 12.

[0004] Referring again to FIG. 1A, the channel of the vertical JFET structure 10 is formed in the mesa 12. The channel width in the n-type region is in the horizontal direction, away from the pn junction between the gate region 18 and the channel region 24. The channel width is into the plane of FIG. 1A, and the channel length is in the vertical direction. Such a vertical JFET structure with a short channel length may be called a Static-Induction Transistor (SIT). In a SIT, the channel length is selected based on a tradeoff between low on-resistance in the on-state (short channel) and resistance to Drain-Induced Barrier Lowering (DIBL) in the off-state. A conventional p-channel JFET may have a similar structure, but the conductivity type is reversed from that shown in FIG. 1A.

[0005] In operation, conduction between the source layer 16 and the drain layer 26 is adjusted by applying a reverse bias to the gate region 18 with respect to the source layer 16. To switch off an n-channel device such as the JFET structure 10, a negative gate-source voltage, or simply the gate voltage (V GSA reverse bias (Gate-to-Source Voltage) is applied to the gate region 18. When no voltage is applied to the gate region 18, charge carriers can freely flow from the source layer 16 through the channel region 24 and the drift layer 15 to the drain layer 26. Conversely, referring to FIG. 1B, when a reverse bias is applied to the gate region 18, a depletion region 33 is formed at the interface between the gate region 18 and the surrounding n-type region, i.e., the channel region 24, and the source layer 16. The depletion region 33 may extend into the drift layer 15. As its name suggests, the depletion region 33 is depleted of charge carriers. When the magnitude of the reverse bias applied to the gate region 18 is large enough, the depletion region extends to cover the entire width of the channel region 24, pinching off the channel region 24 and impeding or blocking the flow of charge carriers between the source layer 16 and the drift layer 15. 1A, in mesa JFET structure 10, the "width" of channel region 24 is in the same direction as the width of mesa 12. Thus, the lateral width of mesa 12 defines the width of channel region 24.

[0006] The threshold voltage of a JFET device refers to the gate voltage at which the device begins to conduct. The threshold voltage of the device is very sensitive to the width of the channel region 24, since pinch-off of the channel region 24 occurs when the gate voltage is large enough such that the depletion region 33 spreads across the channel layer 24. As noted above, in the conventional vertical JFET structure 10 shown in FIGS. 1A and 1B, the width of the channel region 24 is determined by the width of the mesa 12. The width of the mesa 12 is determined by the manufacturing process, i.e., the masking and etching process, used to form the mesa 12. Such manufacturing processes result in various tolerances. Manufacturing variations in these tolerances can lead to significant variations in threshold voltage from device to device, even within the same manufacturing run. Summary of the Invention

[0007] A power transistor device according to some embodiments includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the mesa adjacent to the channel region. The channel region and the source layer have the first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conduction region and a shallow conduction region between the deep conduction region and the gate region. The deep conduction region has a first doping concentration, and the shallow conduction region has a second doping concentration greater than the first doping concentration.

[0008] In some embodiments, the shallow conduction region extends vertically between the drift layer and the source layer, and the deep conduction region extends vertically between the drift layer and the source layer.

[0009] The channel region may comprise silicon carbide and the shallow conduction region may be about 1E17 cm -3 and the deep conduction region may have a doping concentration greater than about 1E17 cm -3 It may have a doping concentration lower than

[0010] The channel region may comprise silicon carbide and the shallow conduction region may be about 3E17 cm -3 ~About 5E18cm -3 The deep conduction region may have a doping concentration of about 1E16 cm -3 ~About 5E16cm -3 In some embodiments, the shallow conduction region may have a doping concentration of about 1E18 cm -3 and the deep conduction region may have a doping concentration of about 1.5E16 cm -3 The shallow conduction region may have a doping concentration that is at least about 10 times greater than the doping concentration of the deep conduction region.

[0011] The shallow conduction region may have a graded doping profile that is graded in a lateral direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state.

[0012] The shallow conduction region may have a width of about 0.1 to 0.3 microns in a lateral direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state.

[0013] The shallow conduction region may have a width in a lateral direction perpendicular to a direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state that may be about one-third of half the width of the mesa. The shallow conduction region may include an implanted region within the mesa.

[0014] The power transistor device may further include a breakdown tuning region between the shallow conduction region and the gate region, the breakdown tuning region may have the first conductivity type and may have a third doping concentration less than the second doping concentration of the shallow conduction region.

[0015] The vertical junction field effect devices exhibit a variation in threshold voltage as a function of mesa width of less than 20 V / micron, in some embodiments less than 10 V / micron, and in some embodiments less than 5 V / micron.

[0016] The power transistor device may be a junction field effect transistor (JFET). The drift layer, the channel region, and the gate region may comprise silicon carbide.

[0017] The width of the shallow channel region in a lateral direction, which may be perpendicular to the direction of current flow when the device is in an on-state, may be independent of the width of the mesa in the lateral direction.

[0018] The width of the deep channel region in the lateral direction perpendicular to the direction of current flow when the device is in the on-state may be directly proportional to the width of the mesa in the lateral direction.

[0019] The gate region may include a first gate region, the shallow conduction region may include a first shallow conduction region, and the power transistor device may further include a second gate region in the mesa opposite the first gate region, and the channel region is between the first gate region and the second gate region. The device may include a second shallow conduction region in the channel region between the deep conduction region and the second gate region. The second shallow conduction region may have a third doping concentration greater than the first doping concentration of the deep conduction region.

[0020] The first gate region may be surrounded by a breakdown adjustment region in the mesa such that the breakdown region is above, below, and to the sides of the gate region adjacent the channel region in the mesa. The breakdown adjustment region may have the first conductivity type and may have a third doping concentration that may be less than the second doping concentration of the shallow conduction region.

[0021] The deep conduction region and the channel region may be disposed on opposite sides of the shallow conduction region in a lateral direction perpendicular to a direction of current flow in the power transistor device.

[0022] A power transistor device according to some embodiments includes a drift layer having a first conductivity type, a mesa on the drift layer including a channel region on the drift layer and a source layer on the channel region, and a gate region in the mesa on a side of the channel region. The channel region and the source layer have the first conductivity type. The gate region has a second conductivity type opposite the first conductivity type. The vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 20V / micron.

[0023] A method of forming a power transistor device includes providing a drift layer having a first conductivity type, forming a source layer having the first conductivity type on the drift layer, forming a mesa by selectively etching a portion of the source layer and the drift layer to form a trench extending into the drift layer and adjacent the trench defining a mesa, the mesa having a mesa sidewall adjacent the trench, forming a shallow conduction region in the mesa extending between the drift layer and the source layer, and forming a gate region having a second conductivity type in the mesa, the gate region may be adjacent to a channel region in the mesa. The channel region includes a deep conduction region adjacent to the shallow conduction region, the shallow conduction region may be between the deep conduction region and the gate region, and the shallow conduction region may have a higher doping concentration than the deep conduction region.

[0024] Forming the shallow conduction region may include performing an angled ion implantation of dopant ions of a first conductivity type into the mesa sidewall at a first implant energy to form a shallow conduction region in the mesa, and a portion of the drift layer in the mesa forming a deep conduction region adjacent the shallow conduction region.

[0025] Forming the gate region may include implanting dopant ions of a second conductivity type into the mesa sidewall at a second implant energy that may be lower than the first implant energy to form a gate region in the mesa, and a shallow conduction region may be between the gate region and the deep conduction region, the second conductivity type being opposite to the first conductivity type.

[0026] Forming the mesa may include forming an etch mask on the source layer and etching the source layer and the drift layer to form the mesa in a region under the etch mask. Forming the shallow conduction region may include implanting dopant ions of the first conductivity type into the mesa sidewalls using the etch mask as an implantation mask.

[0027] The etch mask may include a SiO2 etch mask on the source layer and a silicon nitride mask on the SiO2 mask, and the method may further include forming a second etch mask on the mesa and the trench, patterning the second etch mask to expose the mesa and a floor of the trench adjacent the mesa and to expose one or more surface regions at an edge region of the device, and implanting dopant ions of a second conductivity type into the mesa sidewalls and the junction termination region at a second implant energy lower than the first implant energy to form a gate region in the mesa and an edge termination region in the edge region. The shallow conduction region is between the gate region and the deep conduction region, and the second conductivity type is opposite to the first conductivity type.

[0028] The second etch mask may include SiO2, and patterning the second etch mask may include selectively etching the second etch mask using a silicon nitride mask as an etch stop layer.

[0029] A power transistor device according to some embodiments includes a drift layer having a first conductivity type, a mesa on the drift layer including a channel region on the drift layer and a source layer on the channel region, the channel region and the source layer having the first conductivity type, and a gate region in the mesa adjacent to the channel region, the gate region having a second conductivity type opposite the first conductivity type. A breakdown tuning region may be provided in the mesa between the channel region and the gate region, the breakdown tuning region having the first conductivity type. The channel region may have a first doping concentration and the breakdown tuning region may have a second doping concentration that may be lower than the first doping concentration.

[0030] The channel region may include a deep conduction region and a shallow conduction region between the deep conduction region and the breakdown adjustment region. The shallow conduction region may have a first doping concentration and the deep conduction region may have a third doping concentration that may be lower than the first doping concentration. The breakdown adjustment region surrounds the gate region at the mesa.

[0031] The accompanying drawings, which are included to provide a further understanding of the disclosure and which are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and, together with the detailed description, serve to explain the principles of the disclosure. There is no intention to show structural details of the disclosure in more detail than may be necessary for a fundamental understanding of the disclosure and various ways in which it may be practiced. [Brief description of the drawings]

[0032] [Figure 1A] FIG. 1 illustrates a conventional JFET device structure. [Figure 1B] FIG. 1 illustrates a conventional JFET device structure. [Figure 1C] FIG. 1 illustrates a conventional JFET device structure. [Figure 2A] FIG. 1 illustrates a JFET device structure according to some embodiments. [Figure 2B] FIG. 1 illustrates a JFET device structure according to some embodiments. [Figure 2C] FIG. 1 illustrates a channel doping profile for a JFET device structure in accordance with some embodiments. [Diagram 3] FIG. 1 illustrates a channel doping profile and associated electric field strength and electron energy for a JFET device structure in accordance with some embodiments. [Figure 4A] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4B] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4C]1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4D] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4E] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4F] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4G] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4H] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 4I] 1A-1D illustrate a process for fabricating a JFET device structure according to some embodiments. [Figure 5A] 5A-5C illustrate a process for fabricating a JFET device structure according to a further embodiment. [Figure 5B] FIG. 1 illustrates a JFET device structure according to a further embodiment. [Figure 5C] Figure 5B illustrates several possible channel doping profiles for the JFET device structure. [Figure 5D] Figure 5B illustrates several possible channel doping profiles for the JFET device structure. [Figure 5E] Figure 5B illustrates several possible channel doping profiles for the JFET device structure. [Figure 6] FIG. 1 illustrates an example circuit including a JFET device in accordance with some embodiments. [Figure 7] 1 is a flowchart illustrating a process for fabricating a JFET device in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Embodiments of the inventive concepts will be more fully described with reference to the non-limiting embodiments and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale, and that features of some embodiments may be used with other embodiments that one of ordinary skill in the art would recognize, even if not explicitly described herein. Descriptions of well-known components and processing techniques may be omitted so as not to unnecessarily obscure aspects of the disclosure. The examples used herein are intended only to facilitate an understanding of how the disclosure may be implemented and to enable those skilled in the art to further implement aspects of the disclosure. Thus, the examples and embodiments herein should not be construed as limiting the scope of the disclosure, which is defined solely by the appended claims and applicable law. Additionally, it should be noted that the same reference numerals represent similar parts throughout the drawings.

[0034] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be called a second element, and similarly, a second element can be called a first element, without departing from the scope of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] When an element such as a layer, region, or substrate is described as being "on" or "extending onto" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is described as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Similarly, when an element such as a layer, region, or substrate is described as being "on" or "extending over" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is described as being "directly on" or "extending directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0036] Relative terms such as "bottom," "top," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the drawings. These terms, and those described above, are intended to encompass different orientations of the device in addition to the orientation illustrated in the drawings.

[0037] The terms used herein are only for describing certain embodiments and are not intended to be limitations of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, as used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of stated features, integers, steps, processes, elements, and / or components, but are further understood not to exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meanings relevant to the present specification and related art.

[0039] JFET devices are sometimes called static induction transistors, but the term JFET will be used in the following description, however, it will be appreciated that the embodiments described herein may be applied to any device that uses a depletion region to tailor the conductivity of a channel in a mesa.

[0040] Power electronic devices fabricated using silicon carbide (SiC) are capable of high blocking voltages. For power devices with blocking voltages in the range of 600V-1000V, SiC JFETs have a chip area 2-3 times smaller than SiC MOSFETs. SiC JFETs can also be fabricated with simpler manufacturing processes than MOSFETs, which can lead to lower manufacturing costs. In addition, SiC JFET devices do not have a SiO2-SiC interface. This can increase device reliability because the oxide layer can break down under high voltage operation. JFET devices have the disadvantages of normally-on devices. However, their advantages may outweigh their disadvantages in power applications such as high reliability Si-SiC heterogeneous integrated circuits.

[0041] In vertical SiC JFETs optimized for low resistance, it is desirable for the devices to have a predictable threshold voltage for circuit performance. However, as noted above, the threshold voltage of a vertical JFET is highly sensitive to the width of the mesa of the device. Some embodiments described herein are based on the recognition that the sensitivity of the threshold voltage to mesa width in a vertical JFET device is related to the conductivity of the portion of the channel whose width varies with the mesa width. Some embodiments described herein may reduce the sensitivity of the threshold voltage to mesa width changes by providing a stepped or graded doping profile in the channel region.

[0042] For example, in some embodiments, the channel is divided into a highly conductive shallow channel region near the gate region and a less conductive deep channel region. In some embodiments, the shallow channel may be self-aligned to the mesa edge, such that only the width of the less conductive deep channel region is sensitive to the mesa width. This may reduce the sensitivity of the threshold voltage of the device to the mesa width. The total central conductivity of the channel itself may be kept constant or nearly constant, since the conductivity of the channel is dominated by the more conductive shallow channel region. Some embodiments may provide an order of magnitude or more reduction in the sensitivity of the threshold voltage to the mesa width by appropriate selection of the doping concentrations of the shallow and deep channel regions.

[0043] Some embodiments may therefore avoid the traditional trade-off between JFET channel conductivity and threshold voltage sensitivity to mesa width changes; that is, in traditional structures, the more conductive the channel, the more sensitive it is to mesa width changes. Some embodiments may therefore make the mesa width narrower and dope the channel region more heavily to increase conductivity while reducing the sensitivity of threshold voltage to mesa width.

[0044] As shown in FIGS. 1A and 1B, the JFET channel of a conventional structure has a substantially constant doping such that it has uniform conductivity regardless of the channel width. According to some embodiments described herein, the JFET channel doping is graded such that the deeper portion of the JFET channel near the center of the mesa is more lightly doped, while the shallower portion of the JFET channel (closer to the gate junction) is more heavily doped. Additionally, in some embodiments, the doping of the shallower portion of the JFET channel may be self-aligned with respect to the edge of the mesa. These aspects combine to make the threshold voltage of the JFET device insensitive to changes in the width of the mesa without incurring a trade-off in channel conductivity.

[0045] FIG. 2A illustrates an n-channel vertical JFET structure 100 according to some embodiments. The vertical JFET structure 100 includes an n+ drain layer 26 on which an n- drift layer 15 is formed. An n-type channel region 114 is on the drift layer 15, and an n+ source layer 16 is on the channel region 114. An n++ source contact layer 38 is on the n+ source layer. A drain resistor contact 28 is on the drain layer 26, and a source resistor contact 40 is on the source contact layer 38. The channel region 114, the source layer 16, and the source contact layer 38 are provided in a mesa 12 on the drift layer 15. A p+ gate region 18 is provided as part of the mesa 12 adjacent to the channel region 24. A p++ shield region 32 is provided adjacent to the gate region 18, and a gate resistor contact 36 is on the shield region 32. A passivation layer 42 covers the gate resistor contact 36 and the shield region 32. An optional sidewall protection layer 61 is on the exposed sidewall of mesa 12. Sidewall protection layer 61 may have a thickness of, for example, 20-30 nm, in some embodiments 23-27 nm, and in some embodiments 25 nm.

[0046] In some embodiments, the doping concentration of the channel region 114 may be graded along the width of the mesa 12 (which corresponds to the width of the channel region 114), such that the channel region 114 has a lower doping concentration near the center of the mesa 12 and a higher doping concentration near the gate region 18.

[0047] For example, in the embodiment shown in FIG. 2A, the channel region 114 has a two-step gradient profile, which divides the channel region 114 into a deep conduction region 122 and a shallow conduction region 124 between the deep conduction region 122 and the gate region 18. The channel region 114 may include both the shallow conduction region 124 and the deep conduction region 122 adjacent to the gate region 18, and both the shallow conduction region 124 and the deep conduction region 122 extend vertically between the drift layer 15 and the source layer 16. The shallow conduction region 124 extends vertically (e.g., in the y-direction, or direction of carrier flow, as shown in FIG. 2A) between the drift layer 15 and the source layer 16, and the deep conduction region 122 extends vertically between the drift layer 15 and the source layer 16. Thus, the deep conduction region 122 and the channel region 18 are disposed on opposite sides of the shallow conduction region 124 in a lateral direction perpendicular to the direction of current flow in the device 100 (eg, the x-direction).

[0048] The deep conduction region 122 is disposed near the center of the mesa 12 and has a doping concentration that is lower than the doping concentration of the shallow conduction region 124. For example, the shallow conduction region 124 may have a doping concentration that is at least about 10 times greater than the doping concentration of the deep conduction region 122. In some cases, the shallow conduction region 124 may have a doping concentration that is at least about 20 times greater, and in some cases at least about 100 times greater, than the doping concentration of the deep conduction region 122.

[0049] In some embodiments, the shallow conductive region 124 is approximately 1E17 cm -3 For example, about 1E17cm -3 ~1E19cm -3 In some embodiments, the shallow conductive region 124 has a doping concentration of about 3E17 cm -3 ~5E18cm -3 In some embodiments, the shallow conductive region 124 has a doping concentration of about 1E18 cm -3 The doping concentration is .

[0050] In some embodiments, the deep conductive region 122 is approximately 5E15 cm -3 ~1E17cm -3 In some embodiments, the deep conductive region 122 has a doping concentration of about 5E16 cm -3 For example, about 5E15cm -3 ~5E16cm -3 In some embodiments, the deep conductive region 122 has a doping concentration of about 1.5E16 cm -3 The doping concentration is .

[0051] In some embodiments, the shallow conduction region has a doping concentration that is at least about 10 times greater than the doping concentration of the deep conduction region, and in some cases at least about 100 times greater.

[0052] Deep conduction region 122 may, in some embodiments, have the same doping concentration as drift layer 15 because shallow conduction region 124 may be formed by ion implantation into the portion of the epitaxial layer that forms drift layer 15.

[0053] In some embodiments, the shallow conduction region 124 may have a width of about 0.1 to 0.3 microns in a lateral direction (x-direction shown in FIG. 2A) perpendicular to the direction of carrier flow (y-direction shown in FIG. 2A) through the channel region 114 when the vertical JFET 100 is in the on state. In some embodiments, the shallow conduction region has a width in a lateral direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in the on state that is about one-third of one-half the width of the mesa.

[0054] Although shown as an n-channel device, it will be appreciated that the JFET device structure 100 can be formed as a p-channel device by switching the n-type layers to p-type, and vice versa.

[0055] In some embodiments, vertical JFET 100 according to some embodiments may exhibit a variation in threshold voltage as a function of mesa width of less than 20 V / micron. In some embodiments, vertical JFET 100 according to some embodiments may exhibit a variation in threshold voltage as a function of mesa width of less than 10 V / micron, and in some embodiments, less than 5 V / micron.

[0056] Although a two-step graded doping profile is shown in FIG. 2A, the channel region 114 may have other doping profiles. For example, various possible doping profiles are shown in FIG. 2C, which includes a graph of various channel doping profiles across the entire mesa width according to some embodiments. In FIG. 2C, the total channel width is 2W. Thus, each channel region 114 in one half of the mesa has a width of W.

[0057] FIG 2C(a) shows a two-step doping profile in which each half of the mesa includes a more heavily doped shallow conduction region 124 and a more lightly doped deep conduction region 122. FIG 2C(b) shows a three-step doping profile in the channel region 114. FIG 2C(c) shows a doping profile in which the interface between the shallow conduction region 124 and the deep conduction region 122 is graded from a higher doping concentration to a lower doping concentration. The doping profile shown in FIG 2C is exemplary and many other doping profiles are possible within the scope of the inventive concept.

[0058] As shown in FIG. 2A, the shallow conduction region 124 extends vertically between the drift layer 15 and the source layer 16, and the deep conduction region 122 extends vertically between the drift layer 15 and the source layer 16.

[0059] In some embodiments, the shallow conduction region has a graded doping profile that is graded in a lateral direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state.

[0060] Figure 3(a) is a graph of doping concentration, Figure 3(b) is a graph of electric field strength, and Figure 3(c) is a graph of electron energy with respect to position along the horizontal direction of the channel for a conventional JFET structure 10. Similarly, Figure 3(d) is a graph of doping concentration, Figure 3(e) is a graph of electric field strength, and Figure 3(f) is a graph of electron energy with respect to position along the horizontal direction of the channel for a JFET structure 100 according to some embodiments.

[0061] As shown in FIG. 3(a), in the conventional structure, the channel region has a constant doping concentration N ch In contrast, as shown in FIG. 3(d), in some embodiments of structures, the channel region is doped with a p-type gate region (doped with a doping concentration N g Low doping concentration N in the deep conducting region away from d and high doping concentration N in the shallow conduction region near the p-type gate region h The shallow conduction region may have a width δ of about 0.2 microns in some embodiments.

[0062] As shown in Fig. 3(b) and Fig. 3(e), the peak electric field (E m ) is higher in JFET structure 100 because the junction is formed by a more highly doped n-channel region than in conventional structure 10, whereas the built-in voltage is the same in both cases. The gate-source breakdown voltage is determined by the junction between gate region 18 and source layer 16 insofar as Nh, the n+ doping of shallower conduction region 124, is lower than the n+ doping of source layer 16. Thus, JFET structure 100 should not have a lower gate-source breakdown voltage than conventional JFET structure 10.

[0063] Solving the Poisson equation for the static electricity gives the threshold voltage (V T ) and V vs. mesa width T In the embodiment described herein, a sensitivity of N d (Doping in the center of the channel) is N ch (channel doping in conventional structures), so V T The sensitivity of is reduced.

[0064] N ch For a constant doped channel with V T is calculated as follows:

number

[0065] V according to mesa width W T The change in is calculated as follows:

number

[0066] N h and N d For a two-step doped channel with V T is calculated as follows:

number

[0067] V according to mesa width W T The change in is calculated as follows:

number

[0068] V in conventional structure T is N ch However, in some embodiments, V T is significantly lower than the value of Nd are sensitive to.

[0069] Simulations were performed to compare the performance of the conventional structure with structures according to some embodiments. The simulations were performed using a gate voltage (V barrier ) as V T The simulation used a mesa width of 1.2 microns, a mesa width variation of ±0.2 microns, a p+ implant depth into the mesa of 0.2 microns on each side, an n+ implant depth into the channel of 0.2 microns for the new structure, and a -3 N ch , 1E16cm -3 N d , and 3E17cm -3 N h Under these conditions, the above analytical model was used with the V T Results and V T As shown in Table 1, the V T V varied from -5.0 V to -16.6 V when the mesa width was varied by ±0.2 μm. In contrast, for the structure formed as described herein, V T changed only from -9.3 V to -10.4 V when the mesa width was changed by ±0.2 microns.

[0070] Therefore, V with respect to the mesa width T has been shown to be reduced by more than a factor of 10 when structures as described herein are used. [Table 1]

[0071] In some embodiments, the vertical junction field effect device may exhibit a threshold voltage variation as a function of mesa width of less than 20V / micron. In some embodiments, the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 10V / micron, and in some embodiments less than 5V / micron. In some embodiments, the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of between 5V / micron and 20V / micron.

[0072] A process flow for forming a JFET structure according to some embodiments is shown in Figures 4A-I. In Figures 4A-I, the relative sizes of the various layers and regions are exaggerated for clarity and are not drawn to scale. The process flow shown in Figures 4A-I is for fabricating an n-channel JFET device. In the case of a p-channel JFET device, the conductivity type of the device layers / regions is inverted from n-type to p-type or vice versa.

[0073] 4A, an n+ SiC substrate 26 is provided having a thickness of about 350 microns. The substrate 26 may have a 2H, 4H, 6H or 3C polytype and may have an on-axis or off-axis orientation. The n+ substrate 26 will form the drain layer 26 of the completed JFET device.

[0074] An n-epitaxial layer 15 having a thickness of about 8 microns is formed on a substrate 26. Such an epitaxial layer thickness is suitable for devices having a blocking voltage of 600-800V. For higher voltage ratings, the n-epitaxial layer 15 is thicker. The n-epitaxial layer 15 has a thickness of about 5E15 cm. -3 ~1E17cm -3 In some embodiments, approximately 1E16 cm -3 ~5E16cm -3 In a particular embodiment, the n-epitaxial layer 15 may have a doping concentration of about 1.5E16 cm -3The thickness and / or doping of n-epitaxial layer 15, which forms the drift layer of the device, may be selected to provide a desired on-state resistance and / or off-state voltage blocking capability for the device.

[0075] 4B, the n+ source layer 16 and n++ source contact layer are formed by implanting n-type ions, such as silicon, into the epitaxial layer 15 at a volume and implant energy. The n+ source layer 16 has a thickness of about 0.5 microns and a surface area of ​​about 1E18 cm. -3 The n+ source contact layer 38 may have a thickness of approximately 0.5 microns and may be degenerately doped to enable formation of a source ohmic contact thereto.

[0076] Referring to FIG. 4C, a mask 46 is formed on the top surface of the structure. The mask 46 is formed to have a thickness of about 1 micron and is formed by depositing a layer 46A of SiO2 by plasma enhanced chemical vapor deposition (PECVD), followed by a layer 46B of silicon nitride. The structure is then etched to form trenches 48 that define the mesas 12. As shown in FIGS. 2A and 2B, the half of the structure to the right of axis 30 is shown for ease of understanding. The trenches 48 have a width of about 1.2 microns, and the mesas have a total width of about 1.2 microns. The trenches 48 may be etched to a depth of about 2 microns into the n-epitaxial layer 15.

[0077] After the trench formation step, the mask 46 may have a residual thickness of approximately 0.7 microns. Referring to Figure 4D, with the mask 46 in place, an angled ion implantation 50 is performed to implant n+ shallow channel regions 124 into the sidewalls of the mesa 12. The n+ shallow channel regions 124 are approximately 1E17 cm -3 ~1E19cm -3 , in some cases about 3E17cm -3 ~5E18cm -3The n+ shallow channel region 124 may be implanted with a maximum implant energy of about 700-800 keV to obtain the desired implant depth. The implant may be performed multiple times at high temperature and at a tilt angle of 35-40 degrees from vertical to ensure that the bottom of the trench sidewalls are not screened. The implant may be performed at four twist angles spaced 90 degrees from each other.

[0078] Referring to FIG. 4E, a second SiO2 layer 48 is deposited over the structure and patterned to form an opening 49 in an edge termination region 57 of the structure. Pattern etch conditions are selected to use the underlying silicon nitride layer 46B as an etch stop so that the mask 46 is not removed as the second SiO2 layer 48 is patterned. An angled ion implant 52 is performed to simultaneously implant p+ gate region 18 into the sidewalls of mesa 12 and edge termination region 55 into edge termination region 57. The p+ gate 18 is deposited at a depth of approximately 1E18 cm. -3 ~1E19cm -3 The p+ gate region 18 may be implanted with a maximum implant energy of about 300-400 keV to obtain the desired implant depth. The implant may be performed multiple times at high temperature and at a tilt angle of 35-40 degrees from vertical to ensure that the bottom of the trench sidewalls is not screened. The implant may be performed at four twist angles spaced 90 degrees from each other.

[0079] 4F, an ion implantation step 54 is performed to implant p++ shield regions 32 into the surface of trench 48. In ion implantation step 54, p-type ions may be implanted into the surface of the trench at a maximum implantation energy of about 350 keV. After ion implantation step 54, a junction termination extension (JTE) region (not shown) may be formed in edge termination region 57 by ion implantation. All implanted dopants may then be activated by annealing at 1550° C. for 30 minutes using a carbon cap.

[0080] Referring to FIG. 4G, SiO 2 This layer may be deposited on the structure using PECVD and isotropically etched using, for example, an Inductively Coupled Plasma (ICP) etch to form a sidewall protection layer 61 on the exposed sidewalls of mesa 12 adjacent trench 48. Sidewall protection layer 61 may have a thickness of, for example, 20-30 nm, in some embodiments 23-27 nm, and in some embodiments 25 nm.

[0081] Referring to Figure 4H, a layer 63 of Ni having a thickness of 100 nm may be deposited on the structure and annealed at 750°C to form a silicide at the bottom of the trench 48. Unreacted Ni may then be etched and the structure annealed at up to 1000°C to form the gate ohmic contact 36 on the p+ shield region 32 in the gate pad region and the source ohmic contact 40 on the source contact layer 38. Additional conventional fabrication processes such as trench fill 72, planarization, metallization 74, backside metallization 76 and laser annealing may then be performed to complete the device fabrication as shown in Figure 4I.

[0082] FIG. 5A illustrates a process for fabricating a JFET device structure according to further embodiments. As shown in FIG. 5A, in some embodiments, the implantation energies and volumes of the n-type implant 50 (FIG. 4D) to form the shallow conduction region 124 and the p-type implant 52 (FIG. 4E) to form the gate region 18 may be selected such that after implantation and annealing, an n-breakdown tuning region 202 remains around the gate region 18, including between the shallow conduction region 124 and the gate region 18 and between the source region 16 and the gate region 18. The shallow conduction region 124 is between the deep conduction region 122 and the breakdown tuning region 202. The breakdown tuning region 202 has a thickness of about 5E15 cm. -3 ~About 1E17cm -3 , in some embodiments, about 1E16 cm -3~About 5E16cm -3 , in a specific embodiment, about 1.5E16 cm -3 The breakdown adjustment region 202 may have a net n-type doping concentration of about 100 nM. The breakdown adjustment region 202 may have a doping concentration similar to that of the deep conduction region 122, but need not be equal to the doping concentration of the deep conduction region 122.

[0083] The breakdown tuning region 202 is provided such that a gate-source PN junction is formed by the p+ gate region 18 and the n- region. This may increase the gate-source breakdown voltage. The n- breakdown tuning region 202 surrounding the p+ gate region 18 is also self-aligned to the edge of the mesa 12 and in some embodiments may be formed using a graded implant with the addition of a lower energy n- implant.

[0084] FIG 5B illustrates a JFET device structure 200 including an n-breakdown tuning region 202 between the shallow conduction region 124 and the gate region 18, and FIGs 5C, 5D, and 5E illustrate several possible channel doping profiles for the JFET device structure of FIG 5B. As can be seen in FIG 5C, the breakdown tuning region 202 is a doping concentration N h Doping concentration N lower than b has.

[0085] Doping concentration N b is the doping concentration N of the deep conduction region 122 d For example, in FIG. 5C, the breakdown adjustment region 202 has a doping concentration N d Doping concentration N is approximately equal to b FIG. 5D shows the doping concentration N b However, the doping concentration N d FIG. 5E shows a doping profile with a doping concentration N bHowever, the doping concentration N d The doping profile is lower than that of the control.

[0086] Although shown as an n-channel device, it will be appreciated that the JFET device structure 200 can be formed as a p-channel device by switching the n-type layers to p-type, and vice versa.

[0087] SiC JFET devices, according to some embodiments, may provide improved yields due to reduced sensitivity of threshold voltage to mesa width. Alternatively or additionally, such devices may maintain yields while allowing tighter designs (e.g., narrower mesas) that improve performance.

[0088] An example circuit including a JFET device according to some embodiments is shown in Figure 6. As shown in Figure 6, a vertical SiC JFET 100 according to some embodiments can be connected to a silicon MOSFET 150 in a modified cascode topology, where the SiC JFET is driven directly and the shift in the SiC JFET threshold voltage is desirably very low.

[0089] The JFET devices described herein may be advantageously used as normally-on SiC JFET switches and for other SiC JFET applications such as in solid-state circuit breakers.

[0090] More broadly, some embodiments described herein can be used in any vertical channel junction field effect device with mesa / trench features where important properties of the device are sensitive to mesa width and it is important to reduce the sensitivity of those properties to mesa width.

[0091] 7 illustrates a method of forming a vertical junction field effect transistor. The method includes providing a drift layer having a first conductivity type (block 702), forming a source layer having a first conductivity type on the drift layer (block 704), and forming a mesa by selectively etching a portion of the source layer and the drift layer to form a trench extending into the drift layer and adjacent the trench to define the mesa (block 706). This has a mesa sidewall adjacent to the trench. The method further includes forming a shallow conductive region in the mesa extending between the drift layer and the source layer (block 708), and forming a gate region having a second conductivity type in the mesa (block 710). The gate region is adjacent to a channel region in the mesa, the channel region including a deep conductive region adjacent to the shallow conductive region, such that the shallow conductive region is between the deep conductive region and the gate region. The shallow conductive region has a higher doping concentration than the deep conductive region.

[0092] Forming the shallow conduction region may include performing an angled ion implantation of dopant ions of a first conductivity type into the mesa sidewall at a first implant energy to form a shallow conduction region in the mesa, and a portion of the drift layer in the mesa forming a deep conduction region adjacent to the shallow conduction region.

[0093] Forming the gate region may include implanting dopant ions of a second conductivity type into the mesa sidewall at a second implant energy lower than the first implant energy to form a gate region in the mesa, a shallow conduction region between the gate region and the deep conduction region, the second conductivity type being opposite to the first conductivity type.

[0094] In some embodiments, forming the mesa includes forming an etch mask on the source layer and etching the source layer and the drift layer to form the mesa in a region beneath the etch mask. Forming the shallow conduction region may include implanting dopant ions of the first conductivity type into the mesa sidewalls using the etch mask as an implantation mask.

[0095] The etch mask may include a SiO2 etch mask on the source layer and a silicon nitride mask on the SiO2 mask, and the method further includes forming a second etch mask on the mesa and the trench, patterning the second etch mask to expose the mesa and a floor of the trench adjacent the mesa, and implanting dopant ions of a second conductivity type into the mesa sidewalls and the junction termination region at a second implant energy lower than the first implant energy to expose one or more surface regions at an edge region of the device to form a gate region in the mesa and an edge termination region in the edge region. The shallow conduction region is between the gate region and the deep conduction region, and the second conductivity type is opposite to the first conductivity type.

[0096] The second etch mask may include SiO2, and patterning the second etch mask includes selectively etching the second etch mask using the silicon nitride mask as an etch stop layer.

[0097] Although embodiments of the inventive concepts have been described in considerable detail with reference to certain configurations thereof, other embodiments are possible. The field plates and gates can have many different shapes and can be connected to the source contacts in many different ways. Thus, the spirit and scope of the invention should not be limited to the particular embodiments described above.

Claims

1. A drift layer (15) having a first conductivity type; a mesa (12) on the drift layer, the mesa including a channel region (114) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; a gate region (18) in the mesa adjacent the channel region, the gate region (18) having a second conductivity type opposite to the first conductivity type; the channel region includes a deep conduction region (122) and a shallow conduction region (124) between the deep conduction region and the gate region; The deep conduction region has a first doping concentration and the shallow conduction region has a second doping concentration greater than the first doping concentration.

2. 2. The power transistor device of claim 1 , wherein the shallow conduction region extends vertically between the drift layer and the source layer, and the deep conduction region extends vertically between the drift layer and the source layer.

3. The channel region comprises silicon carbide and the shallow conduction region is about 1E17 cm －３ and the deep conduction region has a doping concentration greater than about 1E17 cm －３ 2. The power transistor device of claim 1 having a doping concentration less than

4. The channel region comprises silicon carbide and the shallow conduction region is about 3E17 cm －３ ~About 5E18cm －３ and the deep conduction region has a doping concentration of about 1E16 cm －３ ~About 5E16cm －３ 2. The power transistor device of claim 1 having a doping concentration of:

5. The shallow conduction region is approximately 1E18 cm －３ and the deep conduction region has a doping concentration of about 1.5E16 cm －３ 5. The power transistor device of claim 4 having a doping concentration of:

6. 2. The power transistor device of claim 1, wherein the shallow conduction region has a doping concentration that is at least about ten times greater than a doping concentration of the deep conduction region.

7. 2. The power transistor device of claim 1 , wherein the shallow conduction region has a graded doping profile that is graded in a lateral direction perpendicular to a direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state.

8. 2. The power transistor device of claim 1, wherein said shallow conduction region has a width of about 0.1 to 0.3 microns in a lateral direction perpendicular to a direction of carrier flow through said channel region when the vertical junction field effect device is in an on-state.

9. 2. The power transistor device of claim 1, wherein the shallow conduction region has a width in a lateral direction perpendicular to a direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state that is approximately one-third of one-half of a width of the mesa.

10. 2. The power transistor device of claim 1, wherein the shallow conduction region comprises an implanted region in the mesa.

11. 2. The power transistor device of claim 1, further comprising a breakdown adjustment region between said shallow conduction region and said gate region, said breakdown adjustment region having said first conductivity type and having a third doping concentration lower than said second doping concentration of said shallow conduction region.

12. 10. The power transistor device of claim 1, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of less than 20V / micron.

13. 10. The power transistor device of claim 1, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of less than 10V / micron.

14. 10. The power transistor device of claim 1, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of less than 5V / micron.

15. 10. The power transistor device of claim 1, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of between 5V / micron and 20V / micron.

16. 10. The power transistor device of claim 1 comprising a junction field effect transistor (JFET).

17. 10. The power transistor device of claim 1 , wherein the drift layer, the channel region, and the gate region comprise silicon carbide.

18. 2. The power transistor device of claim 1, wherein a width of said shallow channel region in a lateral direction perpendicular to a direction of current flow when said device is in an on-state is independent of a width of said mesa in said lateral direction.

19. 2. The power transistor device of claim 1, wherein a width of said deep conduction region in a lateral direction perpendicular to a direction of current flow when said device is in an on-state is directly proportional to a width of said mesa in said lateral direction.

20. the gate region includes a first gate region, the shallow conduction region includes a first shallow conduction region, and the power transistor device includes: a second gate region on the mesa opposite the first gate region, the channel region being between the first gate region and the second gate region; a second shallow conduction region in the channel region between the deep conduction region and the second gate region; 2. The power transistor device of claim 1, wherein the second shallow conduction region has a third doping concentration greater than the first doping concentration of the deep conduction region.

21. 21. The power transistor device of claim 20, wherein the first gate region is surrounded by a breakdown adjustment region in the mesa, the breakdown adjustment region having the first conductivity type and a third doping concentration that is lower than the second doping concentration of the shallow conduction region.

22. 2. The power transistor device of claim 1, wherein the deep conduction region and the channel region are disposed on opposite sides of the shallow conduction region in a lateral direction perpendicular to a direction of current flow in the power transistor device.

23. A drift layer (10) having a first conductivity type; a mesa (12) on the drift layer, the mesa including a channel region (14) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; a gate region (18) in the mesa on a side of the channel region, the gate region (18) having a second conductivity type opposite to the first conductivity type; The vertical junction field effect device is a power transistor device that exhibits a threshold voltage variation with mesa width of less than 20V / micron.

24. 24. The power transistor device of claim 23, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of less than 10 V / micron.

25. 24. The power transistor device of claim 23, wherein the channel region comprises silicon carbide and the vertical junction field effect device exhibits a threshold voltage variation with mesa width of less than 5V / micron.

26. 24. The power transistor device of claim 23, wherein said channel region comprises silicon carbide and said vertical junction field effect device exhibits a threshold voltage variation with mesa width of between 5V / micron and 20V / micron.

27. the channel region includes a deep conduction region (122) and a shallow conduction region (124) between the deep conduction region and the gate region; 24. The power transistor device of claim 23, wherein the deep conduction region has a first doping concentration and the shallow conduction region has a second doping concentration greater than the first doping concentration.

28. 28. The power transistor device of claim 27, wherein the shallow conduction region extends vertically between the drift layer and the source layer, and the deep conduction region extends vertically between the drift layer and the source layer.

29. The channel region comprises silicon carbide and the shallow conduction region is about 1E17 cm －３ and the deep conduction region has a doping concentration greater than about 1E17 cm －３ 30. The power transistor device of claim 27 having a doping concentration less than

30. 28. The power transistor device of claim 27, wherein the shallow conduction region has a graded doping profile that is graded in a lateral direction perpendicular to a direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state.

31. 28. The power transistor device of claim 27, wherein the shallow conduction region has a width in a lateral direction perpendicular to a direction of carrier flow through the channel region when the vertical junction field effect device is in an on-state that is approximately one-third of one-half of a width of the mesa.

32. 28. The power transistor device of claim 27, further comprising a breakdown adjustment region between the shallow conduction region and the gate region, the breakdown adjustment region having the first conductivity type and having a third doping concentration lower than the second doping concentration of the shallow conduction region.

33. Providing a drift layer having a first conductivity type (702); forming a source layer having the first conductivity type on the drift layer (704); forming a mesa by selectively etching (706) the source layer and a portion of the drift layer to form a trench extending into the drift layer and adjacent the trench defining a mesa, the mesa having a mesa sidewall adjacent the trench; forming a shallow conductive region in the mesa extending between the drift layer and the source layer (708); forming a gate region (710) having a second conductivity type in the mesa, the gate region adjacent a channel region in the mesa, the channel region including a deep conduction region adjacent to the shallow conduction region, the shallow conduction region being between the deep conduction region and the gate region; A method of forming a power transistor device, wherein the shallow conduction region has a higher doping concentration than the deep conduction region.

34. 34. The method of claim 33, wherein forming the shallow conduction region comprises performing an angled ion implantation of dopant ions of a first conductivity type into the mesa sidewall at a first implant energy to form the shallow conduction region in the mesa, a portion of the drift layer in the mesa forming the deep conduction region adjacent to the shallow conduction region.

35. 35. The method of claim 34, wherein forming the gate region comprises implanting dopant ions of a second conductivity type into the mesa sidewall at a second implant energy lower than the first implant energy to form the gate region in the mesa, the shallow conduction region being between the gate region and the deep conduction region, the second conductivity type being opposite to the first conductivity type.

36. Forming the mesa includes: forming an etch mask over the source layer; 35. The method of claim 34, further comprising: etching the source layer and the drift layer to form the mesa in an area under the etch mask, and forming the shallow conduction region comprises implanting dopant ions of the first conductivity type into the mesa sidewalls using the etch mask as an implantation mask.

37. The etch mask is SiO on the source layer. ２ Etch mask and the SiO ２ a silicon nitride mask on the mask, the method comprising: forming a second etch mask over the mesa and the trench; patterning the second etch mask to expose the mesa and a floor of the trench adjacent the mesa and to expose one or more surface areas at an edge region of the device; 37. The method of claim 36, further comprising implanting dopant ions of a second conductivity type into the mesa sidewalls and a junction termination region at a second implant energy lower than the first implant energy to form the gate region in the mesa and an edge termination region in the edge region, wherein the shallow conduction region is between the gate region and the deep conduction region, and the second conductivity type is opposite to the first conductivity type.

38. The second etch mask is SiO ２ 40. The method of claim 37, wherein patterning the second etch mask comprises selectively etching the second etch mask using a silicon nitride mask as an etch stop layer.

39. A drift layer (10) having a first conductivity type; a mesa (12) on the drift layer, the mesa including a channel region (114) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; a gate region (18) in the mesa adjacent the channel region, the gate region (18) having a second conductivity type opposite to the first conductivity type; a breakdown adjustment region (202) in the mesa between the channel region and the gate region, the breakdown adjustment region (202) having the first conductivity type; 1. A power transistor device, comprising: a first doping concentration in the channel region and a second doping concentration in the breakdown adjustment region, the second doping concentration being less than the first doping concentration.

40. the channel region includes a deep conduction region (122) and a shallow conduction region (124) between the deep conduction region and the breakdown adjustment region; 40. The power transistor device of claim 39, wherein the shallow conduction region has the first doping concentration and the deep conduction region has a third doping concentration less than the first doping concentration.

41. 40. The power transistor device of claim 39, wherein the breakdown tuning regions are above and below the gate region at the mesa and on a side of the gate region adjacent the channel region at the mesa.

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