Composite structure including a thin monocrystalline layer on a support substrate made of polycrystalline silicon carbide and related manufacturing method

Abstract

The present invention relates to a composite structure for the fabrication of microelectronic components, comprising a thin monocrystalline layer disposed on a support substrate made of polycrystalline silicon carbide, said support substrate having a preferred crystal orientation, wherein: C 422 The texture coefficient is less than 30%; C 220 The texture coefficient is greater than 60%, or C 111 +C 222 +C 511 The sum of the texture coefficients is over 70%. The present invention also relates to a method for fabricating such a composite structure.

Description

Detailed Description of the Invention

[0001] [Technical field] The present invention relates to the field of semiconductor materials for microelectronic components. The present invention particularly relates to a composite structure comprising a thin monocrystalline layer arranged on a support substrate made of polycrystalline silicon carbide. The thin monocrystalline layer is preferably made of silicon carbide and the composite structure is intended for power electronics applications.

[0002] [Background technology] SiC is becoming widely used to create innovative power devices to meet the requirements of growing electronics applications, especially electric vehicles. Indeed, power devices and integrated power systems based on single crystal silicon carbide can handle much higher power densities and do so in a smaller active area than their conventional silicon equivalents.

[0003] Nevertheless, high-quality single-crystal SiC (c-SiC) substrates for the microelectronics industry are still expensive and difficult to supply in large sizes. Therefore, layer transfer solutions are advantageously used to manufacture composite structures that typically include a thin layer made of single-crystal SiC (derived from a high-quality c-SiC substrate) on a low-cost support substrate, for example made of polycrystalline SiC (p-SiC). Electronic components can then be manufactured on and / or in the thin layer.

[0004] A well-known thin layer transfer solution is the Smart Cut™ method, which is based on light ion implantation and direct bonding assembly between a single crystal donor substrate and a support substrate on the bonding interface.

[0005] Currently, p-SiC substrates are available on the market that can be used as support substrates, but their mechanical, electrical and even thermal properties are not necessarily optimal for obtaining high-quality composite structures from thin layer transfer techniques for power applications.

[0006] As mentioned above, power electronic applications require good vertical electrical conduction in the composite structure. For this, the monocrystalline thin layers can be doped, for example, N-type doped and doped to have a resistivity of 30 mOhm.cm or less, 10 mOhm.cm or less, or even less than 1 mOhm.cm, depending on the requirements of the application. However, it is also necessary to ensure good electrical conductivity to the support substrate of the composite structure. For this purpose, polycrystalline substrates are usually highly doped (especially N-type doped) to achieve a resistivity of less than 30 mOhm.cm. Furthermore, the assembly interfaces of the composite structure must be designed in such a way that the vertical electrical resistance is not increased (or is only slightly increased).

[0007] However, there are other applications that do not require vertical electrical conduction, but instead target a high resistivity support substrate. This is especially the case for radio frequency applications. Other characteristics of the support substrate (mechanical and even thermal), listed below, are required for these RF applications as well as for power applications.

[0008] Thin layer transfer methods based on direct molecular adhesive bonding rely heavily on the surface quality of the assembled substrates: in particular, a roughness (root-mean-square roughness) of 1 nm RMS or less is required for both the support and donor substrates, together with a very low level of surface defects (particles, holes, etc., or other irregularities that tend to give rise to bonding defects).

[0009] Perfect quality has proven difficult to achieve because the hardness of SiC and the presence of particles on the surface of the single crystal support substrate make surface preparation very complicated.

[0010] Finally, it is essential to use support substrates that exhibit low curvature or deformation. Curvature corresponds to deflection or "warping", which is equal to the algebraic difference of the deviation of the substrate with respect to a reference plane. A low curvature is required on the one hand so that these support substrates are suitable for good quality direct assembly and high bonding energy, and on the other hand so that high mechanical stresses are not likely to cause damage to the monocrystalline thin layer during or after the transfer method. A low curvature is also important to ensure the performance of the steps (e.g. photolithography) that fabricate components on / in the thin layer of the composite structure. The radius of curvature (proportional to the inverse of the warping) of the p-SiC support substrate is typically intended to be greater than about 25 m, i.e. a curvature ("warping") of less than or equal to 100 micrometers (micrometers are conveniently referred to as "microns" throughout the remainder of this document), for example for a substrate with a diameter of 150 mm.

[0011] Furthermore, it is often important that the supporting substrate ensures good thermal conductivity, in particular to efficiently remove heat generated by power components.

[0012] All these specifications are very complex to achieve on a p-SiC substrate.

[0013] US Patent No. 10934634 proposes a p-SiC substrate with a grain size variation between both sides of the substrate of less than 0.43% and resulting in a radius of curvature of more than 142 m. Furthermore, at least one side of the substrate exhibits an arithmetic mean roughness of less than 1 nm.

[0014] However, this method remains expensive and very energy and material intensive, as a large portion of the p-SiC initially deposited on the graphite substrate is removed and lost to obtain the proposed p-SiC substrate (typically 2 mm is initially deposited to form a 350 micron p-SiC substrate).

[0015] [Summary of the invention] The present invention proposes a composite structure comprising a thin layer made of monocrystalline material, in particular made of c-SiC, arranged on a p-SiC support substrate. The present invention also relates to a method for producing such a composite structure.

[0016] Brief description of the invention The present invention relates to a composite structure for the fabrication of microelectronic components, comprising a thin monocrystalline layer disposed on a support substrate made of polycrystalline silicon carbide, said support substrate having a preferred crystal orientation, wherein: C 422 The texture coefficient is less than 30%, especially less than 20%; C 220 The texture coefficient is greater than 60%, or C 111 +C 222 +C 511 The sum of the texture coefficients is more than 70%, especially more than 80%.

[0017] According to other advantageous, non-limiting features of the present invention, taken alone or according to any technically feasible combination, the supporting substrate having nitrogen doping and a resistivity of less than 30 mOhm.cm; The thin layer is composed of silicon carbide; The thin layer is made of diamond, The composite structure includes a continuous or discontinuous intermediate layer disposed between the thin layer and a supporting substrate and composed of at least one metallic or semiconducting material; the intermediate layer is comprised of silicon, silicon carbide, tungsten, and / or titanium; C 422 The texture coefficient is less than 15%, or even less than 10%, The thickness of the support substrate ranges between 50 microns and 800 microns, preferably between 60 microns and 500 microns; The composite structure includes electronic components on and / or within the thin layers, and optionally electrical contacts on the rear surface of the supporting substrate.

[0018] The invention also relates to a method for producing a composite structure comprising a thin monocrystalline layer arranged on a support substrate made of polycrystalline silicon carbide, the method comprising the steps of: a) providing a support substrate made of polycrystalline silicon carbide having a preferred crystal orientation, wherein during the crystal orientation: C 422 The texture coefficient is less than 30%, in particular less than 20%, C 220 Texture coefficient is greater than 60% or C 111 +C 222 +C 511 the sum of the texture coefficients is greater than 70%, in particular greater than 80%; b) providing a donor substrate made of a single crystal material; and c) transferring the thin layer from the donor substrate onto a support substrate.

[0019] According to other advantageous, non-limiting features of the present invention, taken alone or according to any technically feasible combination, The transferring step c) comprises: c1) forming a weakly buried plane in a donor substrate and defining a thin layer between said weakly buried plane and a front surface of the donor substrate; c2) assembling the donor substrate onto the support substrate by molecular adhesive bonding, either directly or via an intermediate layer; c3) performing separation along the weakly embedded plane and transferring the thin layer onto a supporting substrate, Step c2) includes, before assembling the two substrates, forming an intermediate layer on the donor substrate before or after step c1); and / or forming an intermediate layer on a supporting substrate; the intermediate layer (30) is formed of at least one metal or semiconductor material selected from the group consisting of silicon, silicon carbide, tungsten, and titanium; the single crystal material forming the donor substrate is silicon carbide; The method further includes fabricating electronic components on and / or in the thin layers of the composite structure; The manufacture of electronic components particularly involves steps of homoepitaxy or heteroepitaxy on thin layers.

[0020] Further features and advantages of the present invention will become apparent from the following detailed description of the invention, which is provided with reference to the accompanying drawings. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 shows a composite substrate according to the present invention. [Diagram 2] FIG. 1 shows a table listing 10 diffraction peaks, classified by increasing Miller indices (hkl), that have been investigated in a SiC substrate of the 3C polytype and that are measurable by X-ray diffraction, with the positions of the peaks and their theoretical intensities also shown. [Figure 3a] 1 shows photomicrographs (SEM) of support substrates manufactured under certain conditions and with certain preferred crystal orientations or textures implemented to fabricate composite structures according to the present invention. [Figure 3b] 1A-1C show micrographs (SEM) of support substrates manufactured under different conditions and with different preferred crystal orientations or textures implemented to fabricate composite structures according to the present invention. [Figure 3c] 13A-13C show photomicrographs (SEM) of support substrates manufactured under further conditions and with further preferred crystal orientations or textures implemented to fabricate composite structures according to the present invention. [Figure 4] FIG. 1 shows a composite substrate according to the present invention. [Figure 5a] 1 illustrates a step of a manufacturing method according to the present invention; [Figure 5b] 5A-5C illustrate different steps of the manufacturing method according to the invention. [Figure 5c] 5A-5C illustrate further steps of the manufacturing method according to the invention. [Figure 5c-2] (FIG. 5c') A diagram illustrating yet another step of the manufacturing method according to the invention. [Figure 5c-3](FIG. 5c'') A diagram showing yet another step of the manufacturing method according to the invention. [Figure 5d] FIG. 4 illustrates yet another step of the manufacturing method according to the present invention. [Figure 6] FIG. 1 shows the manufacturing conditions and related features of five types of support substrates, support substrates 2, 3 and 4 being suitable for the composite structure according to the invention.

[0022] The same reference numbers in the figures may be used for the same type of elements. Some of the figures are schematic diagrams that are not drawn to scale for ease of reading. In particular, the thicknesses of layers along the z-axis are not drawn to scale relative to the lateral dimensions along the x- and y-axes, and the relative mutual thicknesses of layers are not necessarily faithfully represented in the figures.

[0023] [Mode for carrying out the invention] The invention relates to a composite structure 100 particularly suitable for the manufacture of microelectronic components, comprising a thin monocrystalline layer 10, in particular made of silicon carbide, diamond, silicon, II-VI or III-V semiconductor compounds (e.g. AlN, GaN, etc.), or even gallium oxide (Ga2O3), arranged on a support substrate 20 made of polycrystalline silicon carbide (Figure 1).

[0024] In the main plane (x, y), the composite structure 100 is in the form of a circular wafer, preferably with a diameter of 100 mm, 150 mm, 200 mm or more. However, the composite structure can also be in any other form that allows subsequent processing for the fabrication of components. The thickness of the composite structure 100 extends along the z-axis in the figure.

[0025] The thickness of the thin layer 10 of the composite structure 100 typically ranges between a few tens of nm and a few hundreds of nm, for example between 50 nm and 800 nm. It will be seen hereinafter that, depending on the requirements of the electronic component to be produced, an epitaxy step can be carried out on the thin layer 10 either to thicken it (homoepitaxy) or to grow other materials (heteroepitaxy).

[0026] The thin layer 10 exhibits an electrical resistivity adapted to the application and the components for which it is intended. For example, in power components, the resistivity is typically less than 30 mOhm.cm, less than 10 mOhm.cm, or even less than 1 mOhm.cm with N-type doping (nitrogen dopant). For RF components, the resistivity can be greater than 100 Ohm.cm, or even greater than 10 kOhm.cm, for example, without any specific doping or with the addition of vanadium.

[0027] The support substrate 20, as its name suggests, corresponds to the mechanical support of the composite structure 100. The lateral dimensions of the support substrate 20 in its main plane (x, y), in particular its diameter, are the same as the lateral dimensions of the composite structure 100. It should be noted that the thin layer 10 may present slightly smaller lateral dimensions due to the transfer method. In fact, the peripheral ring of the support substrate 20 is usually devoid of the thin layer 10, since an edge flange or chamfer of the substrate 20 would prevent assembly and effective application of said layer 10.

[0028] In the composite structure 100, the thickness of the support substrate 20 is typically in the range of between several hundred microns and about 50 microns, for example between 800 microns and 50 microns, particularly between 500 microns and 60 microns, or even between 350 microns and 100 microns.

[0029] If good vertical electrical conductivity is required (power applications), the support substrate 20 has an electrical resistivity of less than 30 mOhm.cm, less than 15 mOhm.cm, or even less than 10 mOhm.cm. If the thin layer 10 is N-type, the doping type of the support substrate 20 is usually chosen to be the same, i.e. typically nitrogen doping. To achieve the aforementioned low resistivity, the nitrogen concentration (measurable by secondary ion mass spectrometry) is typically less than 5E19 atoms / cm. 3 More than 1E20 atoms / cm 3 or even 1.5E20 atoms / cm 3 That's all.

[0030] If a high resistivity is intended for the support substrate (greater than 100 Ohm.cm, or even greater than 10 kOhm.cm, or even higher), the p-SiC support substrate 20 is fabricated from very pure precursors (e.g., methyltrichlorosilane) and / or with the addition of impurities such as vanadium.

[0031] The support substrate 20 made of p-SiC of the 3C polytype also has a preferred crystal orientation, which in this case is characterized by various texture coefficients in specific ratios.

[0032] The texture index can be expressed as a percentage and quantifies the average preferred orientation of the crystallites of the support substrate 20 relative to the normal of the surface of said substrate. It should be noted that the texture index can be measured by the method described by G. Harris ("X. Quantitative measurement of preferred orientation in rolled uranium bars", Philosophical Magazine Series 7, 43:336, 113-123, 1952). In practice, the texture index is measured from the diffraction peaks collected by an X-ray diffractometer using the θ-2θ method over the angular range of 10° to 135° (2θ scale). Over this range, ten diffraction peaks can be considered for the 3C polytype of SiC substrate, listed in a table (shown in FIG. 2) and classified according to increasing Miller indices (hkl). Texture coefficient C hkl is the peak intensity I, which is proportional to the area under the sample peak hkl and the theoretical intensity I of the powder that can be obtained based on the theoretical percentage published by ICDD (International Center for Diffraction Data). 0 hkl The texture coefficient C is calculated based on hkl is expressed as follows: C hkl =(I hkl / I 0 hkl ) / (1 / N×Σ(I hkl / I 0 hkl )), where N is the number of peaks considered.

[0033] According to a first alternative embodiment, the preferred crystal orientation of the support substrate 20 is less than 30% C 422 Texture coefficient and C > 60% 220 It is characterized by texture coefficients.

[0034] According to a second alternative embodiment, the preferred crystal orientation of the support substrate 20 is less than 30% C 422 Texture coefficients, and C 111 +C 222 +C 511 It is characterized by the fact that the sum of the texture coefficients of is more than 70%.

[0035] Preferably, in any of the alternative embodiments specified, C 422 The texture factor is less than 20%, less than 15%, or even less than 10%.

[0036] Preferably, according to a second alternative embodiment, C 111 +C 222 +C 511 The sum of the texture coefficients is over 80%.

[0037] Figures 3a, 3b and 3c show three examples of textures of a support substrate 20 for a composite structure 100 according to the invention. The images are obtained by scanning electron microscopy (SEM) with backscattered electrons (EBSD) in cross-sections (y,z), i.e. in cross-sections (sections) of the support substrate 20. On the right side of Figures 3a and 3b, the triangular texture contains certain facets marked with various white symbols for information. Said symbols also apply to certain textures of the SEM images by way of example. On the right side of the three SEM images of Figures 3a, 3b and 3c, the percentage of the main texture coefficients of interest is indicated.

[0038] The preferred texture (according to the two alternative embodiments described above) combined with high doping (if vertical electrical conduction is required) is determined by the expected physical, mechanical and electrical specifications of the composite structure 100, namely: Excellent flatness (low curvature), Low electrical resistivity (if required for the application and components to be fabricated on the composite structure 100); and It makes it possible to obtain a support substrate 20 that has good thermal conductivity (especially in the case of the first specified alternative embodiment).

[0039] The radius of curvature of the support substrate 20 is greater than 25 m, advantageously greater than or equal to 50 m. By way of example, a support substrate 20 having a diameter of 150 mm has a curvature (i.e., "warping") of 100 microns, or even 50 microns or less, and a support substrate 20 having a diameter of 200 mm has a curvature (i.e., "warping") of 150 microns, or even 70 microns or less.

[0040] The range of the radius of curvature of the support substrate 20 makes said substrate perfectly suited to the specifications of the composite structure 100 provided with the monocrystalline thin layer 10, the method of manufacturing such a structure 100, and the subsequent manufacturing of microelectronic components on and / or in the thin layer 10. It should be noted that the curvature of the composite structure 100 remains close to that of the support substrate 20.

[0041] According to certain embodiments of the present invention, the composite structure 100 includes a continuous or discontinuous intermediate layer 30 disposed between the lamina 10 and the supporting substrate 20 and composed of at least one metallic or semiconducting material (FIG. 4). With reference to the method of fabricating the composite structure 100 as described below, the intermediate layer 30 can be formed on the side of the lamina 10, the side of the supporting substrate 20, or on both sides thereof prior to assembly along the bonding interface 40.

[0042] The intermediate layer 30 may be composed of, for example, silicon, silicon carbide, tungsten, and / or titanium. Typically, its thickness ranges between a few nm and a few hundred nm, preferably between 2 nm and 50 nm.

[0043] The present invention also relates to a method for fabricating the composite structure 100. The method comprises a first step a) of providing a support substrate 20 made of polycrystalline silicon carbide having a preferred crystal orientation, during which C 422 the texture factor is less than 30%, in particular less than 20%, less than 15% or even less than 10%, C 220 The texture coefficient is greater than 60%, or C 111 +C 222 +C 511 The sum of the texture coefficients is more than 70%, especially more than 80%.

[0044] Preferably, to address power electronic applications, the support substrate 20 has nitrogen doping that allows for the achievement of electrical resistivities of less than 30 mOhm.cm, less than 15 mOhm.cm, or even less than 10 mOhm.cm.

[0045] The radius of curvature of the support substrate 20 is greater than 25 m, advantageously 50 m or greater.

[0046] Step a) implements a chemical vapor deposition (CVD) technique. This technique requires a gas mixture that includes at least one silicon precursor gas (such as silane or chlorosilane), and / or at least one carbon precursor gas (such as alkane or alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated as MTCS), and, if necessary, at least one doping gas containing nitrogen (e.g., NH3, N2H4, N2). The doping gas can also be a carbon precursor and / or a silicon precursor (e.g., an amine, such as H2NCH3). These gases can be diluted in a carrier gas, which can be a reducing gas, such as hydrogen, and / or an inert gas, such as argon.

[0047] This gas mixture is placed in a high temperature reactor where the precursor gases decompose and react on the surface of preferably finely divided and purified isotropic graphite seeds to form a 3C-SiC polytype whose mechanical and thermal resistance properties, thermal expansion coefficient, and purity perfectly match the specifications of the composite structure 100. Furthermore, the 3C-SiC polytype is typically grown at temperatures of 1000° C. 20 atoms / cm 3 It can be doped with nitrogen to very high levels, thus exhibiting a resistivity of less than 30 mOhm.cm, without degrading the quality of the substrate and thereby adversely affecting the quality of the composite structure and subsequently the performance of the microelectronic components. Finally, the 3C-SiC polytype is a material capable of withstanding the high temperature processes that the support substrate 20 must be subjected to during the fabrication of the composite structure 100 and components.

[0048] The reactor temperature during the CVD deposition of SiC should be between about 1,000° C. and about 1,600° C., preferably between about 1,100° C. and about 1,400° C. Within this temperature range, the deposition rate can vary over a fairly wide range, from 1 micron / hour to more than 100 microns / hour. Advantageously, the total pressure in the reactor does not exceed 350 mbar, or even 300 mbar.

[0049] By modifying the CVD process parameters, such as temperature, partial pressure of precursors, and possibly the percentage of doping gas, the crystallographic orientation / texture of the deposited p-SiC layer can be changed.

[0050] After deposition, the graphite seeds coated with a thick SiC deposit are machined and then oxidized in air, typically at 900° C., to remove all graphite residues. It is noted that removal of the graphite seeds can also be performed by machining techniques alone, or even essentially by combustion / oxidation.

[0051] Raw p-SiC wafers are harvested face-by-face from the seed. Raw p-SiC wafers exhibit a curvature due to relaxation of the stresses in the deposited layers. This curvature can be measured using a confocal white light sensor that scans the surface of the p-SiC wafer.

[0052] The raw p-SiC wafer is then thinned by rough grinding and then fine grinding, and undergoes surface preparation by polishing to arrive at the p-SiC support substrate 20 having the key features described above in describing the composite structure 100. In particular, the purpose of the grinding step is to remove a sufficient thickness from the side of the wafer that was in contact with the graphite, thereby removing the initial crystal growth region and generating significant stresses.

[0053] It is important that the curvature of the raw p-SiC wafer remains within a reasonable range to enable the production of a support substrate 20 with low curvature from a raw wafer with an economically viable thickness. For example, the curvature ("warping") of a raw p-SiC wafer with a diameter of 150 mm and a thickness of less than 900 microns is targeted to be 250 microns or less. Thus, after grinding and polishing, it is possible to obtain a support substrate 20 with a thickness typically less than 500 microns and a curvature ("warping") of less than 100 microns, or less than 50 microns, or even less than 30 microns.

[0054] Figure 6 shows a table containing various p-SiC deposition conditions (temperature, precursor gas, pressure, mole fraction of doping gas) and the obtained mechanical, electrical and thermal properties. Samples 2, 3 and 4 represent the support substrate 20 for the composite structure 100 according to the invention, and their textures are illustrated in Figures 3c, 3a and 3b, respectively.

[0055] Samples 1 and 5 do not fall within the scope of the present invention as they do not achieve the specifications (resistivity, curvature) required to produce a high quality composite structure 100. The texture of these samples does not achieve low curvature, and the grains on surface 20a are larger and more non-uniform in size than samples 2, 3, and 4, making it more difficult to prepare the surface and obtain the surface finish required for direct assembly.

[0056] The surface 20a (FIG. 5a) of the support substrate 20 intended to receive the thin layer 10 preferably exhibits a roughness of 1 nm RMS or less (measured by atomic force microscope on a 20 micron×20 micron scan), even more preferably 0.5 nm RMS or less. The surface of the support substrate 20 intended to form the rear surface of the composite structure 100 may exhibit a higher surface roughness, for example of the order of 10 nm RMS.

[0057] Step a) of the method may optionally include a heat treatment applied to the support substrate 20 at a temperature above 1,500° C., typically between 1,500° C. and 2,000° C., so as to stabilise its polycrystalline structure. Indeed, these temperature ranges are likely to be applied at later stages in the method of fabricating the composite structure 100.

[0058] The manufacturing method according to the invention then comprises a step b) of providing a donor substrate 1 made of a monocrystalline material, from which a thin layer 10 is obtained (Figure 5a). As described above with reference to the composite structure 100, the monocrystalline material can be silicon carbide of the 4H, 6H or 3C polytype, diamond, silicon, II-IV or III-V semiconductor compounds (in particular GaN), etc. The donor substrate 1 is preferably in the form of a wafer with a diameter of 100 mm, 150 mm, 200 mm or more (the same as or very close to the diameter of the support substrate 20) and a thickness typically ranging between 300 microns and 800 microns. The donor substrate has a front surface 1a and a rear surface 1b. The surface roughness of the front surface 1a is advantageously chosen to be less than 1 nm RMS, or even less than 0.5 nm RMS, measured by atomic force microscope (AFM) in a 20 micron x 20 micron scan. The doping type and resistivity of the donor substrate 1 are defined as a function of the requirements of the components to be manufactured on and / or in the thin layer 10 of the composite structure 100 .

[0059] Finally, the method comprises a step c) of transferring the thin layer 10 originating from the donor substrate 1 onto a support substrate 20. There are various options for transferring the layer (mechanical, chemical or mechanochemical thinning, separation on a porous layer present in the donor substrate 1, etc.) known from the prior art and will not be described exhaustively here.

[0060] According to a preferred embodiment, step c) of the method comprises the injection of light entities and assembly by direct bonding according to the principles of the Smart Cut™ process.

[0061] A first step c1) corresponds to the introduction of a light entity into the donor substrate 1 in order to form a weakly embedded plane 11 which, together with the front surface 1a of the donor substrate 1, defines a thin layer 10 to be transferred (FIG. 5b). It should be noted that although the thin layer 10 to be transferred is shown as a continuous layer, it could also consist of discontinuous blocks, for example prepared on the surface of the donor substrate 1.

[0062] The light entities, preferably hydrogen, helium or a co-implant of these two entities, are implanted to a determined depth in the donor substrate 1 that corresponds to the target thickness of the thin layer 10. These light entities form, around the determined depth, microcavities distributed in a fine layer parallel to the free surface 1a of the donor substrate 1, which is parallel to the plane (x, y) in the figure. This fine layer is called weakly buried plane 11 for simplicity.

[0063] The implantation energy of the light entities is selected to reach a determined depth. For example, hydrogen ions are implanted at energy levels ranging between 10 keV and 250 keV, and at 50 keV to define a thin layer 10 with a thickness of about 100 nm to 1,500 nm. E 16 / cm 2 ~1 E 17 / cm 2 It should be noted that prior to the ion implantation step, a protective layer can be deposited on the front side 1a of the donor substrate 1. This protective layer can consist, for example, of a material such as silicon oxide or silicon nitride. The protective layer is removed prior to the next stage.

[0064] The transfer step c) then comprises a second stage c2) of assembling the donor substrate 1 on its front side 1a, on the support substrate 20 on its first side 20a, along the bonding interface 40 by molecular adhesion bonding (Figure 5c).

[0065] Optionally, an intermediate layer 30 can be formed on the front surface 1a of the donor substrate 1 before or after the step c1) of introducing the light entities, and in any case before the assembly step. This intermediate layer 30 can be made of a semiconductor material, for example silicon or silicon carbide, or of a metallic material, such as tungsten or titanium. The thickness of the intermediate layer 30 is advantageously typically limited to between a few nanometers and a few tens of nanometers.

[0066] If the intermediate layer 30 is formed before the first step c1), the injection energy (and possibly the dose) of the light entities is adjusted at the intersection point of this additional layer. If the intermediate layer 30 is formed after step c1), care is taken to form this layer by applying a thermal history lower than that of bubbling, which corresponds to the appearance of gas bubbles on the surface of the donor substrate 1 due to an excessively high growth and pressurization of the microcavities in the weakly embedded plane 11.

[0067] Optionally, an intermediate layer 30 can also be deposited on the face of the support substrate 20 to be assembled before the assembly stage and can be chosen to be of the same or different nature as the intermediate layer 4 mentioned for the donor substrate 1. The intermediate layer 30 can optionally be deposited on either one of the two substrates 1, 10 to be assembled.

[0068] The purpose of the intermediate layer(s) is primarily to facilitate the bonding energy, since the covalent bonding occurs at lower temperatures than would be the case for two directly assembled SiC surfaces (especially in the temperature range below 1,100° C.). Another benefit of this (these) intermediate layers may be to improve the vertical electrical conduction of the bonded interface 40.

[0069] The intermediate layer or layers 30 are intended to be embedded in the bonded assembly 50 after assembly (FIGS. 5c', 5c'') and ultimately in the composite structure 100. Even if the intermediate layer 30 is continuous when formed on one and / or the other of the substrates 1, 20, it may become segmented and assume a discontinuous nature during subsequent thermal treatments. This is essentially the case when the initial thickness of said layer is very thin, typically less than 10 nm.

[0070] With further reference to the description of the assembly step c2), as is known per se, direct molecular adhesive bonding does not require adhesive materials since the bond is established at the atomic level between the assembled surfaces. There are several types of molecular adhesive bonding, which differ especially in terms of temperature conditions, pressure conditions, atmospheric conditions or treatment before bringing the surfaces into contact. Mention may be made of room temperature bonding with or without prior plasma activation of the surfaces to be assembled, atomic diffusion bonding (ADB), surface activated bonding (SAB), etc.

[0071] The assembly step c2) may include a conventional sequence of chemical cleaning (e.g., RCA cleaning), surface activation (e.g., with oxygen or nitrogen plasma) or other surface preparation (such as cleaning (scrubbing) by brushing) prior to contacting the surfaces 1a, 20a to be assembled, which tend to promote the quality of the bonding interface 40 (low defects, high adhesion energy).

[0072] Finally, a third step c3) involves separation along the weakly embedded plane 11, whereby the thin layer 10 is applied onto a support substrate 20 (FIG. 5d).

[0073] The separation along the weakly embedded plane 11 is usually carried out by carrying out a heat treatment in the temperature range between 800 ° C. and 1,200 ° C. Such a heat treatment generates cavities and microcracks in the weakly embedded plane 11, which are pressurized by light entities present in gaseous form until a crack propagates along said weakly embedded plane 11. Alternatively, or jointly, a mechanical stress can be applied to the bonded assembly, in particular to the weakly embedded plane 11, so as to propagate or to assist the mechanical propagation of the crack that leads to the separation. When this separation is complete, a composite structure 100 is obtained, which comprises, on the one hand, the support substrate 20 and the transferred thin layer 10, and, on the other hand, the remainder 1' of the donor substrate. The level and type of doping of the thin layer 10 is determined by the choice of the characteristics of the donor substrate 1 or can be adjusted by known techniques for subsequent doping of semiconductor layers.

[0074] The free surface 10a of the thin layer 10 is usually rough after separation, for example exhibiting a roughness ranging between 5 nm and 100 nm RMS. In order to restore a good surface finish (typically a roughness of less than a few Angstroms RMS), cleaning and / or smoothing steps can be applied. In particular, these steps can include a mechanical-chemical smoothing treatment of the free surface of the thin layer 20. The removal of between 50 nm and 300 nm makes it possible to effectively restore the surface finish of said layer 10. Said steps can also include at least one heat treatment in a temperature range between 1,200 ° C. and 1,800 ° C. Such a heat treatment is carried out in order to remove residual light entities from the thin layer 10 and to promote the reconstruction of the crystal lattice of the thin layer 10. This also makes it possible to strengthen the bonding interface 40. The heat treatment may also include or correspond to epitaxy on the thin layer to increase the thickness of the thin layer 10 (e.g., homoepitaxy of c-SiC on the c-SiC thin layer 10, heteroepitaxy of GaN on the c-SiC thin layer 10, etc.).

[0075] Finally, it is noted that the transfer step c) may comprise a step of reconditioning the remainder 1' of the donor substrate in order to reuse it as a donor substrate 1 for a new composite structure 100. Mechanical and / or chemical treatments similar to those applied to the composite structure 100 may be performed on the front side 1'a of the remainder substrate 1'.

[0076] The resulting composite structure 100 is extremely resistant to very high temperature heat treatments that may be applied to improve the quality of the thin layer 10 or to fabricate components on and / or in said layer 10. The support substrate 20 in the composite structure 100 is stable and its curvature does not increase significantly during and after the high temperature heat treatments that the composite structure 100 is subjected to for its fabrication.

[0077] The composite structure 100 according to the invention is particularly suitable for manufacturing one or more high voltage microelectronic components, such as, for example, Schottky diodes, MOSFET transistors, etc. More generally, it is suitable for power microelectronic applications, as it allows excellent vertical electrical conduction, good thermal conductivity and results in high quality thin c-SiC layers.

[0078] The composite structure 100 may also be suitable for radio frequency applications when accompanied by a resistive supporting substrate 20 whose physical and possibly thermal characteristics are entirely suitable for the fabrication of RF electronic components.

[0079] Of course, the present invention is not limited to the embodiments and examples that have been described, and alternative embodiments can be added to the present invention without departing from the scope of the present invention, which is defined by the claims.

Claims

1. A composite structure for fabricating microelectronic components, comprising a thin monocrystalline layer (10) disposed on a support substrate (20) made of polycrystalline silicon carbide, said support substrate (20) having a preferred crystal orientation, wherein: C ４２２ The texture coefficient is less than 30%; C ２２０ Texture coefficient is greater than 60%, or C １１１ +C ２２２ +C ５１１ A composite structure (100) having a sum of texture coefficients of greater than 70%.

2. 10. The composite structure (100) of claim 1, wherein the support substrate (20) has nitrogen doping and a resistivity of less than 30 mOhm.cm.

3. 3. The composite structure (100) of claim 1 or 2, wherein the single crystal thin layer (10) is composed of silicon carbide.

4. 3. A composite structure (100) according to claim 1 or 2, wherein said thin single crystal layer (10) is made of diamond.

5. 3. The composite structure (100) of claim 1 or 2, comprising a continuous or discontinuous intermediate layer (30) disposed between the single crystal thin layer (10) and the support substrate (20) and composed of at least one metallic or semiconductor material.

6. The composite structure (100) of claim 5, wherein the intermediate layer (30) is comprised of silicon, silicon carbide, tungsten, and / or titanium.

7. Said C ４２２ A composite structure (100) according to claim 1 or 2, wherein the texture factor is less than 15%, or even less than 10%.

8. The composite structure (100) of claim 1 or 2, wherein the thickness of the support substrate (20) ranges between 50 microns and 800 microns.

9. 3. The composite structure (100) of claim 1 or 2, comprising electronic components on and / or within said single crystal thin layer (10), and optionally electrical contacts on a rear surface of said support substrate (20).

10. A method for manufacturing a composite structure (100) comprising a thin monocrystalline layer (10) disposed on a support substrate (20) made of polycrystalline silicon carbide, comprising: a) providing a support substrate (20) made of polycrystalline silicon carbide having a preferred crystal orientation; C ４２２ The texture coefficient is less than 30%; C ２２０ Texture coefficient is greater than 60%, or C １１１ +C ２２２ +C ５１１ the sum of the texture coefficients of the b) providing a donor substrate (1) made of a monocrystalline material; c) transferring the thin layer (10) from said donor substrate (1) onto said support substrate (20).

11. The transferring step c) c1) forming a weakly buried plane (11) in the donor substrate (1) and defining the single-crystal thin layer (10) between the weakly buried plane (11) and the front surface (1a) of the donor substrate (1); c2) assembling the donor substrate (1) on the support substrate (20) by molecular adhesive bonding, either directly or via an intermediate layer (30); c3) performing separation along the weakly buried plane (11) and transferring the single-crystal thin layer (10) onto the support substrate (20).

12. Before step c2) assembles the two substrates (1, 20), forming an intermediate layer (30) on the donor substrate (1) before or after step c1), and / or forming an intermediate layer (30) on the support substrate (20); The method of claim 11, wherein the intermediate layer (30) is formed of at least one metallic or semiconducting material selected from the group consisting of silicon, silicon carbide, tungsten, and titanium.

13. 13. The method of claim 11 or 12, wherein the monocrystalline material forming the donor substrate (1) is silicon carbide.

14. The method of claim 10 or 11, further comprising the step of fabricating electronic components on and / or in the single crystal thin layer (10) of the composite structure (100).

15. 15. The method of claim 14, wherein the manufacturing of the electronic component comprises a step of homoepitaxy or heteroepitaxy on the monocrystalline thin layer (10).

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