Single-threaded detection of valid synchronization headers

Abstract

An integrated circuit having an interface circuit is described. In operation, the interface circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the interface circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit, and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

Description

[Technical field]

[0001] The present disclosure relates to techniques for communicating using a serial communication protocol. [Background technology]

[0002] In serial communications, a recipient electronic device (sometimes called a "slave") that supports autobaud may need to extract the baud rate from a synchronization header in a frame. The synchronization header is usually constrained by the communication protocol to ensure detection or identification of a misinterpreted synchronization header without losing a valid synchronization header. For example, the Local Interconnect Network (LIN) is a single-wire serial communications protocol used to communicate between components in a vehicle. The LIN specification expects a slave to always detect a "break and sync" (or "break+sync") sequence or field in a synchronization header, which is sent by another electronic device (sometimes called a "master"). Moreover, a valid detection of the "break+sync" field may cause or enable the master to detect the baud rate at which it wishes to communicate. Furthermore, a frame in a LIN communication may be initiated by the master, where the frame begins with a break field followed by a synchronization byte field (which may include, for example, eight synchronization bits). This sequence is unique in the LIN communications protocol and may ensure that the slave detects the beginning of a new frame. FIG. 1 provides an example of existing break and sync (break+sync) fields in a frame conforming to the LIN communication protocol.

[0003] However, if for some reason the slave becomes confused (e.g., about whether it is currently detecting a "break+sync" field), it may miss a valid "break+sync" field that has a distinct starting point or time. This undesirable situation can also be caused by a transient short circuit to ground. In particular, a short circuit to ground can cause a dominant (or low) bit on the LIN bus for tens of milliseconds. This can confuse the slave, because, for example, an incorrect "break" field may be detected, and a subsequent real break may be confused with the start bit of the sync field.

[0004] To be able to recover from such a scenario and detect a valid "break+sync" field, a controller or control logic in the receiver circuit in the slave may start a thread with every dominant or extended low (e.g., "0") bit, which is considered a possible break field. The controller may then continue to verify the sync field until the sync verification fails, in which case the thread is released or terminated. From a hardware perspective, even though the maximum number of threads is a bounded problem, the cost of implementing a multithreading approach may be significantly higher than a single-threaded approach. Summary of the Invention [Means for solving the problem]

[0005] An embodiment of an integrated circuit is described. The integrated circuit includes an interface circuit for use with an electronic device. In operation, the interface circuit receives a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The interface circuit then calculates a set of conditions based at least in part on the received signal, and when valid, the set of conditions identifies a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the interface circuit determines a location of a synchronization field in the header relative to the identified first dominant bit, and calculates a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0006] It should be noted that the serial communication protocol may include a Local Interconnect Network (LIN) communication protocol.

[0007] Moreover, the dominant signal level may be less than the non-dominant signal level.

[0008] Further, the set of conditions may include a first instance of a first condition, where when valid, the first instance of the first condition may include a second dominant bit time of a second dominant bit in the binary bits having a dominant signal level being less than or equal to a first predefined multiple of a first dominant bit time of the first dominant bit, and the first dominant bit may precede the second dominant bit. For example, the first predefined multiple may include 1.25. Alternatively, the set of conditions may include a second condition, where when valid, the second condition may include a sum of the second dominant bit time and a first least dominant bit time of a first least dominant bit in the binary bits having a less dominant signal level being greater than or equal to a second predefined multiple of the first dominant bit time. It should be noted that the first least dominant bit may be between the first dominant bit and the second dominant bit.

[0009] In some embodiments, the second predefined multiple comprises a ratio of 2 to 11. Alternatively or additionally, the set of conditions may include a second instance of the first condition, where when enabled, the second instance of the first condition may include a third predefined bit time of a third predefined bit in the binary bits having a dominant signal level being less than or equal to a first predefined multiple of a second predefined bit time of the second predefined bit, and the second predefined bit may precede the third predefined bit. It is noted that the set of conditions may include a third condition, where when enabled, the third predefined condition may include a third predefined bit time being greater than or equal to a third predefined multiple of the second predefined bit time.

[0010] Additionally, a third predefined multiple may include 0.75.

[0011] Alternatively or additionally, the set of conditions may include a fourth condition. When effective, the fourth condition may include the sum of the second least probable bit time of the second least probable bit in the binary bits and the third most probable bit time is greater than or equal to a third predefined multiple of the average bit time of the pair of bits in the binary bits, and the sum is less than or equal to a first predefined multiple of the average bit time. Note that the third most probable bit may precede the second least probable bit, and the pair of bits may include the first least probable bit and a probable bit selected from the group including the first most probable bit, the second most probable bit, and the third most probable bit. In some embodiments, the first predefined multiple includes 1.25, and the third predefined multiple includes 0.75.

[0012] Another embodiment provides a vehicle including an integrated circuit.

[0013] Another embodiment provides a system including an integrated circuit.

[0014] Another embodiment provides a computer-readable storage medium having program instructions for use with an electronic device, the program instructions, when executed by the electronic device, causing the electronic device to perform at least some of the operations described above in one or more of the preceding embodiments.

[0015] Another embodiment provides a method for selectively calculating the baud rate of a received signal, the method including at least some of the operations being performed by an integrated circuit.

[0016] This summary is provided for the purpose of illustrating some exemplary embodiments so as to provide a basic understanding of some aspects of the subject matter described herein. It will therefore be appreciated that the features described above are examples and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following detailed description, drawings, and claims. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a timing diagram illustrating an example of existing break and sync (break+sync) fields in a frame conforming to the Local Interconnect Network (LIN) communications protocol. [Diagram 2] FIG. 11 is a timing diagram illustrating an example of not detecting a valid “break+sync” sequence or field when there is an undesired event, in accordance with some embodiments of the present disclosure. [Diagram 3] FIG. 2 illustrates an example of a state machine with state transitions that use predefined conditions, according to some embodiments of the present disclosure. [Figure 4] 4 illustrates an example of a synchronized (SYN) state in the state machine of FIG. 3 in accordance with some embodiments of the present disclosure. [Diagram 5] 4 is a timing diagram illustrating example received signals during LIN communication in accordance with some embodiments of the present disclosure. [Figure 6] 4 is a timing diagram illustrating example received signals during LIN communication in accordance with some embodiments of the present disclosure. [Figure 7] 4 is a timing diagram illustrating example received signals during LIN communication in accordance with some embodiments of the present disclosure. [Figure 8] 4 is a timing diagram illustrating example received signals during LIN communication in accordance with some embodiments of the present disclosure. [Figure 9] 4 is a timing diagram illustrating example received signals during LIN communication in accordance with some embodiments of the present disclosure. [Figure 10] 1 is a block diagram illustrating an example of an integrated circuit according to some embodiments of the present disclosure. [Figure 11] 4 is a flow diagram illustrating an example of a method for selectively calculating the baud rate of a received signal according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] It should be noted that like reference numbers refer to corresponding parts throughout the drawings. Moreover, multiple instances of the same part are designated by a common prefix separated by a dash from the instance number.

[0019] An integrated circuit for use with an electronic device is described. The integrated circuit may include an interface circuit. In operation, the interface circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the interface circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit, and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0020] By correctly identifying the location of the synchronization field and determining the baud rate, these circuit techniques may improve serial communications, for example, using the LIN communication protocol. In particular, these circuit techniques may enable a recipient electronic device using a serial communication protocol to recover from an undesirable state on the bus and detect a valid synchronization header (such as a "break+sync" sequence or field) in a frame. Thus, these circuit techniques may improve the reliability and performance of serial communications. Thus, these circuit techniques may make communications by electronic devices more robust and reliable, and thus facilitate the use of the integrated circuits in a wide variety of systems, electronic devices, and applications, such as in vehicles. For example, the integrated circuits may be used in vehicle assistance or automated (or autonomous) driving.

[0021] An embodiment of a circuit technique is now described. The circuit technique may enable an integrated circuit to selectively calculate a baud rate of a received signal. In operation, the integrated circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol (such as a LIN communication protocol), the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The integrated circuit may then calculate a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having a dominant signal level. Moreover, when the set of conditions is valid, the integrated circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit, and calculate the baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field.

[0022] The disclosed circuit techniques can ensure detection of a valid sync header despite undesirable state transitions on the LIN bus.

[0023] As mentioned above, a slave may need to detect a "break+sync" sequence or field to identify the start of a frame, as well as to subsequently determine or derive the baud rate of the current transmission. The LIN specification includes several conditions that may help a slave to successfully detect a "break+sync" sequence or field. In particular, a synchronization field (sometimes called a "sync field") follows a pause field. Moreover, the pause field may have a width or duration of at least 11 times the LIN bit time (thus, as per the LIN specification, there may be an upper limit on the length or duration of the pause field). (However, 11 is used as an illustrative example, and more generally, the width or duration may be M times the LIN bit time, where M is a non-zero integer). Furthermore, although not included in the LIN specification, the sync field bits may be compared to each other based at least in part on a LIN specified tolerance.

[0024] As expected in the LIN specification, a slave may detect a "break+sync" sequence or field in a variety of circumstances. In fact, integrated circuits conforming to the LIN specification are expected to guarantee detection of a "break+sync" sequence or field in a wide variety of scenarios. For example, one anomalous scenario may occur if a screwdriver shorts to ground on the LIN bus while being used to replace a part. This short to ground appears as a dominant bit on the LIN bus and may have a random width or duration. If the dominant bit is long (e.g., 10 ms) and is followed by a real or actual pause field (which for a 20k baud rate should have a duration longer than 550 μs), the slave may become confused and treat the short to ground pulse as a pause field and the actual pause field as the start bit of a sync field. In this scenario, the slave may assume that a sync byte (0x55) follows, least significant bit (LSB) first. In some implementations, the start bit of the sync field may be ignored and two sync bits (one dominant and one dominant) may be used in the comparison to check the validity of the "break+sync" sequence or field. In particular, two consecutive or adjacent bits of the sync field may be used together in the comparison to avoid rise and fall time differences of the receiving circuitry in the slave. For this comparison, the slave may use two bit times for the interrupt field to ensure that the interrupt field is at least 11 times the average sync bit time or duration. Note that some integrated circuits may use the start bit (or dominant bit) of the sync field and the first dominant bit (the least significant bit of the sync byte) to perform the comparison. In either scenario, it is realized during the reception of the sync field or byte that the short to ground was not an interrupt field. This is usually too late for the slave to revert to the actual interrupt and start considering the interrupt as the start of a "break+sync" sequence or field. Thus, in these scenarios, the slave may miss an entire frame.FIG. 2 shows a timing diagram illustrating an example of not detecting a valid "break+sync" sequence or field when there is an undesired event.

[0025] To address these issues, a slave may use multithreading. In particular, each dominant bit may be treated as if it were a break field, and subsequent bits may be evaluated as if they were part of the sync field. Moreover, a slave may continue to validate the sync field against the expected break field until a valid "break+sync" field is received. When this happens (and thus the validation fails), the thread may be freed for a new detection. Because there are six dominant bits in the "break+sync" field, a slave may need at least six threads to ensure that none of the dominant bits are lost in the break field.

[0026] Note that the multithreading scheme may be implemented using multiple instances of the receive circuit in the slave. Although incremental improvements may be made, the multithreading scheme may still require starting a new thread by assuming that each dominant bit is a potential interrupt field.

[0027] Alternatively, to address the above-mentioned problems, the slave may use improved single threading approaches. In these approaches, the slave may use one or more aspects or characteristics of the LIN communication protocol and a predefined comparison to achieve the desired results in a single thread. These approaches may reduce cost and complexity compared to multi-threading approaches.

[0028] In an improved single-threaded approach, it may be important to optimize the receiving circuitry without compromising the ability to detect the onset of the "break+sync" sequence or field. Moreover, in a single-threaded approach, one or more of the following aspects or characteristics of the LIN communication protocol may be used: An interrupt field may always precede a sync field. · In comparisons, the dominant bit should not be used alone as a representation of the LIN bit time. (In particular, the rise and fall times of the receiving circuitry can vary widely, so that the dominant or the non-dominant bit may be shorter or longer than expected, but each dominant bit may be used in comparisons between them, since rise and fall time differences within the receiving circuitry will affect each dominant bit in the same way.) The width or duration of the pause field may be at least 11 times the average LIN bit time received during the sync field. The duration or width of the new pair of bits (major and minor bits) in the sync field may remain within a predetermined amount or range of twice the average bit time. (More generally, twice may be replaced by N times, where N is an even non-zero integer. For example, the predetermined range may be ±25% or ±12.5%, depending on the system requirements. More generally, the predetermined range may be between 1+P and 1-P, where P is a decimal fraction between 0 and 0.4.) The dominant bit comparison may be sub-divided to evaluate potential interrupt fields when a "break+sync" detection fails in the same comparison period; and / or A storage unit may be used to hold previous or history information for detecting a valid "break+sync" field, so that autobaud detection can be optimized to use, for example, two storage units or registers. (Note, for example, that the information in the two storage units may be tracked by the same state machine that tracks the progress of the "break+sync" field detection.)

[0029] It should be noted that although the LIN communication protocol is used as an illustrative example in this discussion, the disclosed circuit techniques may be used with serial communication protocols other than the LIN communication protocol, in particular, the present circuit techniques may be used with other serial communication protocols in which detection of a synchronization pattern is desirable to avoid frame loss.

[0030] As mentioned above, a LIN-compliant slave may support autobaud detection or determination. This capability allows the slave to derive or determine the baud rate (or bit rate) of transmission from a detected "break+sync" field in the sync header of a frame. Moreover, the LIN specification restricts the sync bit to have a relationship with the interrupt field to help the slave detect a valid "break+sync" field. The current LIN specification does not limit the maximum duration of the interrupt field. This freedom constrains the controller or control logic in or associated with the receiving circuit in the slave to assume the dominant bit is an interrupt field and then proceed to verify subsequent sync bits as they are received. However, when there is a short circuit, the resulting signal glitch may be assumed to be an interrupt field and the controller may go ahead and verify the sync field. Thus, the glitch associated with the short circuit may be large enough to confuse the controller that a real or actual interruption is a sync bit. Thus, in this process, the controller may miss the real or actual interruption and therefore may miss the frame.

[0031] In some embodiments, the "break+sync" field detection is implemented using a state machine that tracks the incoming LIN bits and constantly searches for a valid "break+sync" field using predefined conditions, the conditions being: COND1: TLy+THy≧2 / 11 TLx; COND2:3 / 4 mean(T)≦Ty≦5 / 4 mean(T), COND3:TLy ≥ 3 / 4 TLx, and COND4:TLy≦5 / 4TLx, where x is the previous dominant or subordinate bit, y is the current dominant or subordinate bit, TLx is the previous dominant bit time, TLy is the current dominant bit time, THy is the current subordinate bit, Ty is the sum of TLy and THy or the sum of the most recent dominant bit time and the least recent subordinate bit time, and mean(T) is the average 2 bit times of the previous bit pairs in the sync field (1 dominant and 1 subordinate bit).

[0032] Note that COND1 can ensure that the width or duration of the pause field is at least 11 times one-half the sum of the start bit and the first least significant byte of the sync byte, which represents a LIN bit time. Moreover, COND2 can ensure that the sync field bits are within a bounded or predefined range of each other. Furthermore, COND3 can compare the current dominant bit to the previous dominant bit, which should ideally have the same width, and the inequality can be true when both dominant bits are from the sync field. However, when this comparison is false (or not true), the previous dominant bit x may have been the pause field and the current dominant bit y may be the start bit of the sync field. Furthermore, COND4 can compare the current dominant bit to the previous dominant bit, which should ideally have the same width, and the inequality can be true when both dominant bits are from the sync field. However, when this comparison is false (or not true), the current dominant bit y may be the pause field.

[0033] Figure 3 presents a diagram showing an example of a state machine with state transitions using the predefined conditions mentioned above. Note that RE is a rising edge, IDLE is the default state, BREAK is a possible interrupt that has been received, SYN is in the process of obtaining the sync field, and RECEIVED indicates that a valid break+sync has been received. Furthermore, note that the SYN state is a state machine that represents how much of the sync field is validated. Figure 4 presents a diagram showing an example of the SYN state in the state machine of Figure 3.

[0034] As shown in FIG. 3, if any of the predefined conditions evaluate to sync_fail, the state machine may transition to the BRK state, where the previously held abort field value is replaced with the most recently received dominant bit.

[0035] In some embodiments, the receiving circuit may include a counter that counts the dominant bit and the least significant bit width by the number of system clocks. In addition, there may be two registers, namely REG1 and REG2, which may be used to hold or store various values ​​during processing of the received signal to facilitate evaluation of predefined conditions (such as inequality checks) and to help determine the baud rate from the sync field when a valid "break+sync" field is received. In particular, REG1 may hold or store the potential break field count in IDL and SYN0, and at some time may hold or store the average of two bit times (one dominant bit and one least significant bit). Additionally, REG2 may hold or store the last received dominant bit.

[0036] Although example values ​​are given in the preceding discussion, different values ​​are used in other embodiments, and thus the values ​​provided are not intended to be limiting.

[0037] Timing diagrams are now presented along with examples illustrating various scenarios in which zero or more of the predefined conditions fail. In scenario 1, none of the predefined conditions fail (an ideal scenario). This scenario is illustrated in FIG. 5, which presents timing diagrams illustrating example received signals during LIN communication. In FIGS. 5-9, an instance of operation 510 involves checking COND1, an instance of operation 512 involves checking COND2, an instance of operation 514 involves checking COND3, and an instance of operation 516 involves checking COND4. Note that in FIG. 5, operation 510-1 detects the break which establishes that the break field is at least 11 bit times, in operation 512-1 the bit size is compared to the bit period and aggregated, operation 516-1 is a coarse check that this dominant bit is less than the previous one and the sequence is worthy of being considered as a break+sync bit in the sync field, and operations 514-1 and 516-2 are dominant bit comparisons to make sure they are the same size.

[0038] Additionally, in scenario 2, COND1 fails. This scenario is illustrated in Figure 6, which presents a timing diagram showing example received signals during LIN communication. Note that the failure of COND1 in operation 510-1 is essentially a sync_fail condition that puts the state machine into the BRK state, where the previous interrupt is replaced by the most recently received dominant bit.

[0039] Additionally, in scenario 3, COND2 fails. This scenario is illustrated in FIG. 7, which presents a timing diagram illustrating example received signals during LIN communication. Note that in operation 512-1, the failure of COND2 is essentially a sync_fail condition that places the state machine in the BRK state, where the previous interrupt is replaced with the most recently received dominant bit. Note also that in operation 516-3, the sync_fail condition places the state machine in the BRK state, where the previous interrupt is replaced with the most recently received dominant bit.

[0040] Additionally, in scenario 4, COND3 fails. This scenario is illustrated in Figure 8, which presents a timing diagram showing example received signals during LIN communication. At operation 514-1, the failure of COND3 causes the state machine to enter state SYN0, where the previous dominant bit becomes suspended and the current dominant bit acts as the start bit of the sync field.

[0041] In scenario 5, COND4 fails. This scenario is illustrated in Figure 9, which presents a timing diagram showing example received signals during LIN communication. In operation 516-3, the failure of COND4 is a sync_fail condition that puts the state machine into the BRK state, where the previous interrupt is replaced with the most recently received dominant bit.

[0042] As mentioned above, an integrated circuit may implement, at least in part, the circuit techniques. In particular, FIG. 10 presents a block diagram illustrating an example of an integrated circuit 1000. The integrated circuit may include an interface circuit 1010 including a receiver circuit 1012. In some embodiments, the receiver circuit 1012 may include an analog front end (such as a preamplifier), an analog-to-digital converter (ADC), one or more detection channels implementing one or more detection techniques, a clock, and control logic to configure and manage the detection circuit. It should be noted that among the one or more detection channels for measurements performed by a given integrated circuit, there may be dedicated detection channels. Alternatively or additionally, one or more detection channels may be shared when analyzing measurements performed by various integrated circuits.

[0043] 10 does not show all of the connections between components. Moreover, integrated circuit 1000 may include fewer or additional components, two or more components may be combined, a single component may be split into two or more components, and / or the location of one or more components may be changed.

[0044] Method embodiments will now be described. Figure 11 presents a flow diagram illustrating an example of a method 1100 for selectively calculating the baud rate of a received signal. The method may be implemented by an integrated circuit, such as an interface circuit.

[0045] During operation, the interface circuit may receive a signal corresponding to a header of a frame conforming to a serial communication protocol (operation 1110), the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels. The interface circuit may then calculate a set of conditions based at least in part on the received signal (operation 1112), the set of conditions identifying a first dominant bit in the binary bits having a dominant signal level when valid. Moreover, when the set of conditions is valid (operation 1114), the interface circuit may determine a location of a synchronization field in the header relative to the identified first dominant bit (operation 1116) and calculate a baud rate of the received signal based at least in part on a subset of the binary bits in the synchronization field (operation 1118). When not valid (operation 1114), the interface circuit may perform a return to operation 1110.

[0046] There may be additional or fewer operations in some embodiments of the method 1100. Moreover, the order of the operations may be changed and / or two or more operations may be combined into a single operation.

[0047] The disclosed integrated circuits and circuit techniques may be (or may be included in) any electronic device or system. For example, the electronic device may include a cellular phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an e-book device, a MiFi® device, a smart watch, a wearable computing device, a portable computing device, a consumer electronic device, a camera or image sensor, an access point, a router, a switch, communication equipment, test equipment, a vehicle, a drone, a boat, an airplane, a car, a truck, a bus, a motorcycle, manufacturing equipment, farm equipment, construction equipment, or another type of electronic device.

[0048] Although certain components are used to describe embodiments of an integrated circuit, in alternative embodiments, different components and / or subsystems may be present in the integrated circuit. Thus, embodiments of an integrated circuit may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more positions of one or more components may be changed, and / or there may be different types of components.

[0049] Moreover, the circuits and components in the integrated circuit embodiments may be implemented using any combination of analog and / or digital circuitry, including bipolar, PMOS and / or NMOS gates or transistors. Furthermore, the signals in these embodiments may include digital signals having approximately discrete values ​​and / or analog signals having continuous values. Furthermore, the components and circuits may be single-ended or differential, and the power supplies may be unipolar or bipolar. It should be noted that the electrical couplings or connections in the foregoing embodiments may be direct or indirect. In the foregoing embodiments, a single line corresponding to a route may refer to one or more single lines or routes.

[0050] As previously mentioned, an integrated circuit may implement some or all of the functionality of the present circuit technology. This integrated circuit may include hardware and / or software mechanisms used to implement the functionality associated with the present circuit technology.

[0051] In some embodiments, the output of a process for designing an integrated circuit, or a portion of an integrated circuit, including one or more of the circuits described herein, may be a computer-readable medium, such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuit configurations that may be physically instantiated as an integrated circuit or a portion of an integrated circuit. Although various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), OpenAccess (OA), or Open Artwork System Interchange Standard (OASIS). One skilled in the art of integrated circuit design can develop such data structures from schematic diagrams and corresponding descriptions of the type detailed above and encode the data structures in a computer-readable medium. One skilled in the art of integrated circuit fabrication can use such encoded data to manufacture integrated circuits including one or more of the circuits described herein.

[0052] Although some of the operations in the above-described embodiments have been implemented in hardware or software, in general, the operations in the above-described embodiments can be implemented in a wide variety of configurations and architectures. Thus, some or all of the operations in the above-described embodiments may be implemented in hardware, software, or both. For example, at least some of the operations in the present circuitry may be implemented using program instructions executed by a processor or in firmware in an integrated circuit.

[0053] Moreover, although example values ​​are given in the preceding discussion, different values ​​are used in other embodiments, and thus the values ​​provided are not intended to be limiting.

[0054] In the preceding description, reference is made to "some embodiments." It should be noted that "some embodiments" describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0055] The above description is intended to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Moreover, the above description of the embodiments of the present disclosure has been presented only for purposes of illustration and description. The above description is not intended to be exhaustive or to limit the disclosure to the disclosed form. Thus, many modifications and variations will be apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Moreover, the discussion of the foregoing embodiments is not intended to limit the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. [Explanation of symbols]

[0056] 1000 Integrated Circuits 1010 Interface circuit 1012 Receiver circuit

Claims

1. 1. An integrated circuit comprising an interface circuit, the interface circuit comprising: receiving a signal corresponding to a header of a frame conforming to a serial communications protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels; calculating a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having the dominant signal level; When said set of conditions is valid, determining a location of a synchronization field in the header relative to the identified first most significant bit; determining a baud rate of the received signal based at least in part on the subset of binary bits in the synchronization field; 4. An integrated circuit configured to:

2. 10. The integrated circuit of claim 1, wherein the serial communication protocol comprises a Local Interconnect Network (LIN) communication protocol.

3. The integrated circuit of claim 1 , wherein the dominant signal level is less than the dominant signal level.

4. the set of conditions includes a first instance of a first condition; When enabled, the first instance of the first condition includes a second dominant bit time of a second dominant bit among the binary bits having the dominant signal level being less than or equal to a first predetermined multiple of a first dominant bit time of the first dominant bit; The integrated circuit of claim 1 , wherein the first more significant bit precedes the second more significant bit.

5. The integrated circuit of claim 4 , wherein the first predetermined multiple comprises 1.

25.

6. the set of conditions includes a second condition; when enabled, the second condition includes a sum of the second most significant bit time and a first least significant bit time of a first least significant bit among the binary bits having the least significant signal level being greater than or equal to a second predetermined multiple of the first most significant bit time; 5. The integrated circuit of claim 4, wherein the first less-probable bit is between the first more-probable bit and the second more-probable bit.

7. The integrated circuit of claim 6 , wherein the second predetermined multiple comprises a ratio of 2 and 11.

8. the set of conditions includes a second instance of the first condition; When enabled, the second instance of the first condition includes a third dominant bit time of a third dominant bit among the binary bits having the dominant signal level being less than or equal to the first predetermined multiple of the second dominant bit time of the second dominant bit; 7. The integrated circuit of claim 6, wherein the second more significant bit precedes the third more significant bit.

9. the set of conditions includes a third condition, 9. The integrated circuit of claim 8, wherein, when valid, the third condition includes the third dominant bit time being greater than or equal to a third predetermined multiple of the second dominant bit time.

10. The integrated circuit of claim 9 , wherein the third predetermined multiple comprises 0.

75.

11. 11. The integrated circuit of claim 10, wherein the first predetermined multiple comprises 1.25 and the third predetermined multiple comprises 0.

75.

12. the set of conditions includes a fourth condition, When enabled, the fourth condition includes a sum of a second least significant bit time of a second least significant bit among the binary bits and the third most significant bit time being greater than or equal to the third predetermined multiple of an average bit time of a pair of bits among the binary bits and the sum being less than or equal to the first predetermined multiple of the average bit time; the third most significant bit precedes the second least significant bit; 10. The integrated circuit of claim 9, wherein the pair of bits includes the first less-probable bit and a more-probable bit selected from a group including the first more-probable bit, the second more-probable bit, and the third more-probable bit.

13. A non-transitory computer-readable storage medium for use with an electronic device, the computer-readable storage medium storing program instructions that, when executed by the electronic device, cause the electronic device to perform one or more operations, the operations including: receiving a signal corresponding to a header of a frame conforming to a serial communications protocol, the received signal including a time pattern of binary bits having instances of dominant and non-dominant signal levels; calculating a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having the dominant signal level; When said set of conditions is valid, determining a location of a synchronization field in the header relative to the identified first most significant bit; determining a baud rate of the received signal based at least in part on the subset of binary bits in the synchronization field; A non-transitory computer readable storage medium comprising:

14. 14. The non-transitory computer-readable storage medium of claim 13, wherein the serial communication protocol comprises a Local Interconnect Network (LIN) communication protocol.

15. 14. The non-transitory computer-readable storage medium of claim 13, wherein the dominant signal level is less than the dominant signal level.

16. the set of conditions includes a first instance of a first condition; When enabled, the first instance of the first condition includes a second dominant bit time of a second dominant bit among the binary bits having the dominant signal level being less than or equal to a first predetermined multiple of a first dominant bit time of the first dominant bit; 14. The non-transitory computer-readable storage medium of claim 13, wherein the first more significant bit precedes the second more significant bit.

17. 1. A method for selectively calculating a baud rate of a received signal, comprising: By electronic devices, receiving the signal corresponding to a header of a frame conforming to a serial communications protocol, the received signal including a time pattern of binary bits having instances of dominant and recessive signal levels; calculating a set of conditions based at least in part on the received signal, the set of conditions, when valid, identifying a first dominant bit in the binary bits having the dominant signal level; When said set of conditions is valid, determining a location of a synchronization field in the header relative to the identified first most significant bit; determining the baud rate of the received signal based at least in part on the subset of binary bits in the synchronization field; A method comprising:

18. 20. The method of claim 17, wherein the serial communication protocol comprises a Local Interconnect Network (LIN) communication protocol.

19. The method of claim 17 , wherein the dominant signal level is less than the minor signal level.

20. the set of conditions includes a first instance of a first condition; When enabled, the first instance of the first condition includes a second dominant bit time of a second dominant bit among the binary bits having the dominant signal level being less than or equal to a first predetermined multiple of a first dominant bit time of the first dominant bit; 20. The method of claim 17, wherein the first most significant bit precedes the second most significant bit.

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