Memory Organization for Multimode Support

Abstract

The memory package includes a first channel, a second channel, a third channel, and a fourth channel arranged consecutively in a clockwise direction on the memory package, each of the first channel, the second channel, the third channel, and the fourth channel having an access circuit and a memory array, and in a first mode, the first channel controls access to the memory array of the second channel, and the fourth channel controls access to the memory array of the third channel.

Description

[Background technology]

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on a bus that connects the DRAM to one or more data processors, such as a graphics processing unit (GPU) or a central processing unit (CPU). DRAM is typically inexpensive and dense, which allows for a large number of DRAMs to be integrated per device. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards that were popularized by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory subsystem that is relatively fast but also offers scalability. However, while these enhancements have improved the speed of DDR memory used for main memory in computer systems, further improvements are required.

[0002] One type of DDR DRAM, known as graphics double data rate (GDDR) memory, has pushed the boundaries of data transfer rates to accommodate the high bandwidth required for graphics applications. However, in addition to high bandwidth, it is important to allow a DRAM package to be configured for multiple applications. For example, a GDDR, version 6 (GDDR6) DRAM has two independent 16-bit channels, each of which can be configured in x16 mode or x8 mode. In x16 mode, the DRAM provides two 16-bit channels by selecting all 16 bits on each of the two channels. In x8 mode, each 16-bit system channel is provided by data from two DRAM packages, each of which contributes 8 bits by stacking the unused 8 bits to double the memory depth. The addresses of the grouped channels are bound together so that each executes the same command and operates in parallel in lockstep. In x8 mode, the number of DRAM packages and the memory depth are doubled.

[0003] Recently, JEDEC is considering a revision to the GDDR standard that will provide greater flexibility. According to this new revision, GDDR DRAMs will provide 4x8 channels. In the 4-channel mode, there is a single DRAM package and each of the system's four channels is provided by a selected one of the DRAM package's four channels. However, in the 2-channel mode, each DRAM package provides two of the system's four channels and the unused channel is stacked internally as an increased memory depth. The effect of the 2-channel mode is to double the number of DRAM packages and the memory depth. To implement this flexibility, the new GDDR DRAMs will be organized in an initiator-target configuration, where each initiator channel has its own memory and memory from its paired target channel available. Furthermore, this initiator-target configuration allows either a single package located on the top PCB surface, with each channel independently accessible in a four-channel (4CH) mode, or one package located on the top PCB surface and another on the bottom PCB surface in a so-called "clamshell" configuration to support a two-channel (2CH) mode. However, because the graphics controller and GDDR memory are large and power-hungry, the clamshell configuration requires backside cooling, increasing system cost. [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of a data processing system according to some embodiments. [Diagram 2] FIG. 1 is a block diagram of a memory package according to the prior art. [Diagram 3] 3 is a block diagram of a signal path diagram for a data processing system using the memory of FIG. 2. [Figure 4] FIG. 2 is a block diagram of a memory package according to some embodiments. [Diagram 5]5 is a block diagram of a circuit board layout using one memory package of FIG. 4 according to some embodiments. [Figure 6] FIG. 2 is a block diagram of a circuit board layout using two memory packages in a clamshell configuration according to some embodiments. [Figure 7] FIG. 2 is a block diagram of a circuit board layout using two memory packages in a two-channel single-sided configuration according to some embodiments. [Figure 8] FIG. 2 is a block diagram of a portion of a memory including an initiator channel, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0006] The memory package includes a first channel, a second channel, a third channel, and a fourth channel arranged consecutively in a clockwise direction on the memory package, each of the first channel, the second channel, the third channel, and the fourth channel having an access circuit and a memory array, and in a first mode, the first channel controls access to the memory array in the second channel, and the fourth channel controls access to the memory array in the third channel.

[0007] The layout of the circuit board includes a first memory package and a second memory package. Each of the first memory package and the second memory package includes a first channel, a second channel, a third channel, and a fourth channel arranged consecutively in a clockwise direction. Each of the first channel, the second channel, the third channel, and the fourth channel has a memory array. The first channel and the fourth channel include an initiator channel and exhibit vertical symmetry about a horizontal centerline. The second channel and the third channel include a target channel and exhibit vertical symmetry about the horizontal centerline. The first channel and the second channel exhibit horizontal symmetry about the vertical centerline. The third channel and the fourth channel further exhibit horizontal symmetry about the vertical centerline.

[0008] A method of operating a memory system by a processor includes selectively accessing a first memory channel, the processor accessing a first memory package mounted on a first side of a printed circuit board by communicating signals using first channel traces to a left side of the first memory package relative to a reference line of the printed circuit board, the first channel traces having a predetermined flat order from left to right. The method also includes selectively accessing a second memory channel, the processor accessing a second memory package mounted on the first side of the printed circuit board by communicating signals using second channel traces to a right side of the second memory package relative to a reference line of the printed circuit board, the second channel traces having the first flat order in a reverse order.

[0009] 1 is a block diagram of a data processing system 100 according to some embodiments. Data processing system 100 generally includes data processors in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 140.

[0010] The GPU 110 is a discrete graphics processor that has very high performance for optimized graphics processing, rendering and display, but requires high memory bandwidth to perform these tasks. The GPU 110 generally includes a set of command processors 111, a graphics single instruction multiple data (SIMD) core 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (DDR PHY) 115, and a GDDR PHY 116. Although a GPU is shown in this embodiment, the GPU 110 can be any of a variety of data processing elements, such as a machine learning parallel acceleration processor.

[0011] Command processor 111 is used to interpret high-level graphics instructions such as those specified in the OpenGL programming language. Command processor 111 has a bidirectional connection to memory controller 114 for receiving high-level graphics instructions such as OpenGL instructions, a bidirectional connection to cache 113, and a bidirectional connection to graphics SIMD core 112. In response to receiving the high-level instructions, command processor issues low-level instructions for rendering, geometric processing, shading, and rasterization of data such as frame data, using cache 113 as temporary storage. In response to the graphics instructions, graphics SIMD core 112 executes the low-level instructions on large data sets in a massively parallel manner. Command processor 111 and cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Cache 113 also has a bidirectional connection to graphics SIMD core 112 and a bidirectional connection to memory controller 114.

[0012] The memory controller 114 has a first upstream bidirectional port connected to the command processor 111, a second upstream bidirectional port connected to the cache 113, a first downstream bidirectional port to the DDR PHY 115, and a second downstream bidirectional port to the GDDR PHY 116. As used herein, the "upstream" port is the side of the circuitry towards the data processor and away from the memory, and the "downstream" port is in the direction away from the data processor and towards the memory. The memory controller 114 controls the timing and ordering of data transfers between the DDR memory 130 and the GDDR memory 140. DDR and GDDR memories have asymmetric access, i.e., access to open pages in the memory is faster than access to closed pages. The memory controller 114 stores memory access commands and processes them out of order for efficiency, for example, by prioritizing access to open pages while adhering to certain quality of service targets.

[0013] The DDR PHY 115 has an upstream bidirectional port connected to a first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. The DDR PHY 115 meets all specified timing parameters of a version of the DDR memory 130, such as DDR version 5 (DDR5), and performs timing calibration operations at the direction of the memory controller 114. Similarly, the GDDR PHY 116 has an upstream port connected to a second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 140. The GDDR PHY 116 meets all specified timing parameters of a version of the GDDR memory 140, and performs timing calibration operations at the direction of the memory controller 114. The GDDR memory 140 includes a set of mode registers 141 programmable on the GDDR PHY 116 to configure the GDDR memory 140 for operation.

[0014] In operation, data processing system 100 can be used as a graphics card or accelerator for high-bandwidth graphics processing required for graphics applications. Host CPU 120, running an operating system or application program, sends graphics processing commands to GPU 110 through DDR memory 130, which serves as a unified memory for GPU 110 and host CPU 120. It may send commands to the GPU interface, for example, using OpenGL commands or through any other host CPU. OpenGL is a cross-language, cross-platform application programming interface for rendering 2D and 3D vector graphics. Host CPU 120 interacts with GPU 110 using an application programming interface (API) to provide hardware accelerated rendering.

[0015] Data processing system 100 uses two types of memory. The first type of memory is DDR memory 130, which is accessible by both GPU 110 and host CPU 120. As part of the high performance of graphics SIMD core 112, GPU 110 uses high speed graphics double data rate (GDDR) memory.

[0016] 2 is a block diagram of a memory package 200 according to the prior art. The memory package 200 is divided into four channels 210, 220, 230, 240, which are in a quadrant defined by a vertical centerline 250 and a horizontal centerline 260. Channel 210 is known as channel "A" and is the initiator channel. Channel 220 is known as channel "B" and is the target channel. Channel 230 is known as channel "C" and is the initiator channel. Channel 240 is known as channel "D" and is the target channel. In 2CH mode, channel 210 steers memory access requests to either its data or data in channel 220 and returns data through the initiator's channel. Similarly, channel 230 steers memory access requests to either its data or data in target channel 240 and returns data through the initiator's channel. In an alternative configuration, initiator channel A may control access to target channel D, and initiator channel C may control access to target channel B.

[0017] Memory package 200 illustrates an organization of channels within a memory package that can support either a single memory package on one surface or dual memory packages in a clamshell configuration. However, providing two memory packages in a clamshell configuration requires backside cooling, increasing product cost.

[0018] Figure 3 is a block diagram of a signal path diagram for a data processing system 300 that uses memory package 200 of Figure 2 in a two channel, single sided configuration. Data processing system 300 includes memory packages 310 and 320 and a portion of a processor package 330. Figure 3 shows the channels having terminals on the underside for contacting a PCB, such as when implemented in a BGA package. In other embodiments, other package types, such as a quad flat pack (QFP), can be used.

[0019] Data processing system 300 uses the channel organization of memory package 200 of Figure 2, but orients the memory packages as follows: For memory package 310, initiator channel C is in the upper left corner and initiator channel A is in the lower right corner of memory package 310. Memory package 320 is rotated 180 degrees to an upright orientation, with initiator channel A in the upper left corner and initiator channel C in the lower right corner of memory package 310. Processor package 330 includes a first memory controller physical interface 331, a second memory controller physical interface 332, a third memory controller physical interface 333, and a fourth memory controller interface 334.

[0020] The signal path diagram shows that in the organization of memory package 200 shown in FIG. 2, there are significant signal crossovers that require one or more extra PCB layers, such as highlighted areas 341 and 342. Thus, users either implement more complex and expensive circuit board designs, or use a clamshell architecture but add backside cooling. In either case, implementing a two-channel mode with two memory packages significantly increases product costs.

[0021] It would be desirable to implement a mode capable of supporting two memory packages on the same PCB surface using the same memory controller organization without requiring extra PCB layers with crossover paths or backside cooling. According to various embodiments disclosed herein, a new memory package organization allows memory to be configured in two-channel or four-channel modes while avoiding these issues. For example, this organization allows for four memory channels using a single package on one side of the PCB, two channels on each side in a 2CH clamshell mode with two memory packages, and two channels on one side in a 2CH upper mode memory package, all using a common controller organization without adding complex crossover paths requiring one or more extra PCB layers.

[0022] 4 is a block diagram of a memory package 400 with two channel same side capability, according to some embodiments. The memory package 400 is divided into four channels 411, 412, 413, 414, which are in a quadrant defined by a vertical centerline 420 and a horizontal centerline 430. As shown in FIG. 4, the channels are chamfered, which identifies the reference point of the channel. A unique feature 415 in the center left of the memory package 400 can be used to identify the overall orientation of the memory package 400. In the illustrated embodiment, the unique feature is a reset pin that is used to reset all the channels, and there is only one reset pin per memory package.

[0023] Channel 411 is the "A" channel and is the initiator channel located in the upper left corner. Channel 412 is the "B" channel and is the target channel. Channel 413 is the "C" channel and is also the target channel. Channel 414 is the "D" channel and is the initiator channel. In 2CH mode, channel 411 controls memory access requests to both its data and the data in channel 412. Similarly, channel 414 controls memory access requests to both its data and the data in channel 413. Memory package 400 illustrates an organization of channels in a memory package that can support either a 4CH mode single memory package mode, a 2CH clamshell dual memory package mode, and a 2CH upper dual memory package mode aligned on the top (or bottom) surface of the PCB.

[0024] The memory package 400 exhibits both horizontal symmetry about a vertical centerline 420 and vertical symmetry about a horizontal centerline 430. Horizontal symmetry means that the initiator and target bytes have substantially the same circuitry mirrored about an axis of symmetry, in this example the vertical centerline 420. The channels are not necessarily identical, but have horizontal symmetry in the sense that corresponding signals have the same flat order but in opposite directions. Thus, signal terminals on the right side of channel 411 occur on the left side of channel 412. This feature can be used to provide substantial alignment of channel traces on the printed circuit board, with the host memory controller physical interface circuit (PHY) itself having the same flat order but laid out in a mirror image form on the processor package, to reduce or eliminate crossing signal paths. Unlike the known memory package 200 of FIG. 2, the memory package 400 does not have 180° rotational symmetry with respect to the initiator and target channel arrangements, as the initiator quadrants are adjacent to each other. This feature makes it possible to support a 2CH single-sided (top or bottom) dual memory package mode, thereby eliminating the need for backside cooling required for the 2CH clamshell mode.

[0025] 5 is a block diagram of a layout of a circuit board 500 using one memory package 400 of FIG. 4 in a four-channel mode, according to some embodiments. The circuit board 500 forms a data processing system and generally includes a memory package 510, a memory controller area 520, and non-crossing PCB paths 530 between the two. The memory package 510 is a memory package as shown in FIG. 4, with channel 411, an A channel located in the upper left corner, channel 412, a B channel located in the upper right corner, etc., with top and bottom specified relative to an edge of the memory package or relative to a reference line on the memory package. For example, the reference line may be rotated by −45° relative to an edge of the memory package.

[0026] Memory controller region 520 includes memory controller PHY channel 521 and memory controller PHY channel 522 in the left half of memory controller region 520, and memory controller PHY channel 523 and memory controller PHY channel 524 in the right half of memory controller region 520. The left and right halves of memory controller region 520 have terminal patterns that are compatible with the terminal patterns of corresponding channels 411, 412, 413, 414 of memory package 410. Memory controller PHY channels 521 and 523, and 522 and 524 need only have terminal patterns that match the flat ordering of the terminal patterns of channels 411 and 412, and 413 and 414, respectively, although in some embodiments their circuits may be identical, or possibly mirrored about a vertical centerline, to simplify design.

[0027] The data processing system supports a single memory package in a four channel mode. Flat ordering is maintained for this configuration with the channels exhibiting both horizontal and vertical symmetry through the example of three signals representing a number of signals exhibiting a pattern. Channel 411 has a read clock signal region labeled "RCK" to the left of the center of the channel, a data input / output signal region labeled "DQ" to the top right of the channel, and a command and address signal region labeled "CA" to the bottom right of the channel. Channel 414 has an RCK signal region in the center of the channel, but due to vertical symmetry with channel 411, a CA signal region to the top right of the channel and a DQ signal region to the bottom right of the channel. Channel 412 has a DQ signal region to the top left of the channel, a CA signal region to the bottom left of the channel, and an RCK signal region to the right of the center of the channel due to horizontal symmetry with channel 411. Channel 413 has a CA signal region on the top left side of the channel, a DQ signal region on the bottom left side of the channel, and an RCK signal region on the center right side of the channel, with vertical symmetry with channel 412 and horizontal symmetry with channel 414. This diagram illustrates the flat ordering problem with a very simple terminal example, but in various embodiments signals from RCK, DQ, CA and other signal groups can be mixed.

[0028] Thus, memory controller PHY channel 522 has a flat ordering with RCK, DQ, CA relative to channel 411, and memory controller PHY channel 524 has a flat ordering with the reversed order of CA, DQ, RCK relative to channel 411, allowing the same memory controller PHY channel for both to be used in a mirrored configuration without redesign. Memory controller PHY channel 521 has a flat ordering with RCK, CA, DQ relative to channel 414, and memory controller PHY channel 523 has a flat ordering with the reversed order of DQ, CA, RCK relative to channel 413, allowing the same memory controller PHY channel for both to be used in a mirrored configuration without redesign. The slightly different flat ordering for memory controller PHY channels 521 and 522, and 523 and 524 can be handled by package routing, allowing the same PHY design with mirroring to be used.

[0029] In summary, the unique ordering for each channel is A (RCK, DQ, CA), B (CA, DQ, RCK), C (DQ, CA, RCK), D (RCK, CA, DQ), where the flat ordering of A and B is mirrored, the flat ordering of C and D is mirrored, but A and D and B and C are not mirrored. Three signals are chosen in this example because this is the minimum needed to represent four unique flat orderings.

[0030] 6 is a block diagram of a layout of a circuit board 600 using two memory packages in a two-channel clamshell configuration, according to some embodiments. The circuit board 600 forms a data processing system and generally includes a memory package 610, a memory package 620, a memory controller area 630, and non-crossing PCB paths 640 between the two. The memory package 610 is a memory package on the top side of the PCB as shown in FIG. 4, with a channel 411, an A channel located in the top left corner, a channel 412, a B channel located in the top right corner, etc., with the top and bottom being relative to the edge of the PCB or a reference line on the PCB. The memory package 620 is a memory package on the bottom side of the PCB as shown in FIG. 4, with a channel 411, an A channel located in the top right corner, a channel 412, a B channel located in the top left corner, etc., with the top and bottom being relative to the edge of the PCB or a reference line on the PCB. Thus, memory package 620 is flipped horizontally relative to memory package 610 for mating to the backside of the PCB.

[0031] Memory controller region 630 includes memory controller PHY channel 631 and memory controller PHY channel 632 in the left half of memory controller region 630, and memory controller PHY channel 633 and memory controller PHY channel 634 in the right half of memory controller region 630. The left and right halves of memory controller region 630 are arranged horizontally symmetrically about a vertical centerline to generally align with the ball-outs of channels 414 and 411 of memory package 610 and channels 414 and 411 of memory package 620, and generally correspond to memory controller region 630. In the example shown in FIG. 6, memory controller PHY channels 631 and 633 have active signal paths to channel 414 on memory package 610 and channel 414 on memory package 620, respectively, using a first PCB layer, generally designated layer X. Memory controller PHY channels 632 and 634 have active signal paths to channel 411 on memory package 610 and channel 411 on memory package 620, respectively, using a second PCB layer, generally designated layer Y.

[0032] The data processing system supports dual memory packages in two-channel clamshell mode. The flat order for this configuration is the same as the four-channel mode, with the order for each channel being A, upper package (RCK, DQ, CA), A, lower package (CA, DQ, RCK), D, upper package (RCK, CA, DQ), D, lower package (DQ, CA, RCK).

[0033] FIG. 7 is a block diagram of a layout of a circuit board 700 using two memory packages in a two-channel single-sided configuration, according to some embodiments. The circuit board 700 forms a data processing system, a portion of which is formed on a PCB shown in FIG. 7, and has an edge 701 that forms a reference line along which the orientation of the memory packages can be described. The circuit board 700 generally includes a memory package 710, a memory package 720, a memory controller area 730, and non-crossing PCB paths 740 between the two. The memory package 710 is a memory package as shown in FIG. 4 on the top side of the PCB, with channel 411, an A channel located in the top left corner, channel 412, a B channel located in the top right corner, etc., with the top and bottom relative to the edge 701. 4, is the top memory package on the PCB rotated 180° relative to memory package 710, with channel 411, A channel located in the bottom right corner, channel 412, B channel located in the bottom left corner, etc., with the top and bottom being relative to edge 701 of the PCB. In other embodiments, a different reference line that is not parallel to edge 701 of the PCB can be used.

[0034] Memory controller region 730 includes memory controller PHY channel 731 and memory controller PHY channel 732 in the left half of memory controller region 730, and memory controller PHY channel 733 and memory controller PHY channel 734 in the right half of memory controller region 730. The left and right halves of memory controller region 730 are arranged horizontally symmetrically about a vertical centerline to generally align with the ball-outs of channels 411 and 414 of memory package 710 and channels 414 and 411 of memory package 720, and generally correspond to memory controller region 730. In the example shown in FIG. 7, memory controller PHY channels 731 and 733 have active signal paths to channel 414 on memory package 710 and channel 411 on memory package 720 using a first PCB layer, generally designated layer X. Memory controller PHY channels 732 and 734 have active signal paths to channel 411 on memory package 710 and channel 414 on memory package 720 using a second PCB layer, generally designated layer Y.

[0035] Memory packages 710 and 720 are placed side-by-side on the top side of the PCB, but memory package 720 is rotated 180 degrees relative to memory package 710. Because of the symmetry of DRAM, the flat order is based on the position of each channel, but not on the channels. Only the four outer channels retain their flat order, but because we are in two-channel mode, the asymmetric flat order of channels 412 and 413 does not affect operation or cause cross paths since they are not connected.

[0036] The data processing system supports dual memory packages in two-channel (2CH) single-sided mode. The flat order of this configuration is the same as in four-channel mode, with the order of each channel being A, left package (RCK, DQ, CA), D, right package (CA, DQ, RCK), D, left package (RCK, CA, DQ), A, right package (DQ, CA, RCK).

[0037] By changing the initiator channels to channels A and D instead of A and C, memory package 400 not only supports a four-channel single package mode and a two-channel clamshell mode, but also a new one-sided two-channel mode in which memory package 710 and memory package 720 can be placed on the same side of a printed circuit board. This new configuration improves the end product by avoiding the need for backside cooling or more PCB routing layers to accommodate crossover routing that would otherwise be required. In either case, system costs are reduced compared to the two-channel clamshell mode.

[0038] 8 is a block diagram of a portion of a memory 800 including an initiator channel, according to some embodiments. The memory 800 generally includes a control circuit 810, an address path 820, a set of memory arrays and page buffers 830, a data path 840, and a set of bond pads 850.

[0039] The control circuitry 810 includes a command decoder 811 and a mode register 812. The command decoder 811 decodes commands received from command and address pins (not shown in FIG. 8) into one of several supported commands defined by the memory's command truth table. One type of command decoded by the command decoder 811 is a mode register set (MRS) command. The MRS command causes the command decoder to provide a setting to the indicated mode register whose address input contains the setting. The MRS command has been known in the context of DRAM for quite some time and differs between different GDDR DRAM versions. The mode register 812 stores the programmed settings and in some cases outputs information about the GDDR DRAM.

[0040] The address path 820 receives multi-bit address signals and includes an input buffer 821 and an address latch 822 for each address signal, a set of row decoders 823, and a set of column decoders 824. The input buffer 821 receives and buffers a corresponding multi-bit address signal and provides a multi-bit buffered address signal in response. The address latch 822 has an input connected to the output of the input buffer 821, an output, and a clock input that receives a signal labeled "WCK". The address latch 822 latches bits of the buffered address on a particular clock edge, e.g., a rising edge, and serves as a write clock during write commands as well as a main clock used to capture commands. The row decoder 823 has an input connected to the output of the address latch 822, and an output. The column decoder 824 has an input connected to the output of the address latch 822, and an output.

[0041] The memory arrays and page buffers 830 are organized into sets of individual memory arrays known as separately addressable banks. For example, memory 800 may have a total of 16 banks. Each bank can have only one "open" page at a time, which has its contents read into the corresponding page buffer for faster read and write access. A row decoder 823 selects the row in the bank accessed during the activate command, and the contents of the indicated row are read into the page buffer and the row is ready for read and write access. A column decoder 824 selects a column of the row according to a column address.

[0042] The data path 840 includes a multiplexer 841, a demultiplexer 842, a data serializer and deserializer 843, and a data input / output (I / O) block 844. The multiplexer 841 has a first input connected to an output of the memory array and page buffer 830, a second input connected to another channel (not shown), a control input for receiving an initiator / target (I / T) bit, and an output. The demultiplexer 842 has an input, a first output connected to a data input of the memory array and page buffer 830, a control input for receiving the I / T bit, and an output connected to the other channel. The data serializer and deserializer 843 has an input connected to the output of the multiplexer 841, an output connected to an input of the demultiplexer 842, and a bidirectional data port. The data I / O block 833 has a first input for receiving a read clock pair RCK_t and RCK_c, a second input for receiving a write clock pair WCK_t and WCK_c, and a bidirectional connection connected to a data serializer and deserializer 843, and is connected to a group of data I / O terminals collectively labeled "DQ".

[0043] In operation, memory 800 allows for simultaneous operations on memory banks and channels. In one embodiment, memory 800 is compatible with any of the Double Data Rate (DDR) standards published by the Joint Electron Device Engineering Council (JEDEC), such as the Graphics DDR, version 6 (GDDR6) standard. The operation of many of the components within memory 800 is well known and will not be described in detail. However, certain features relevant to the present disclosure will now be described.

[0044] In general, to access data, a memory accessing agent, such as GPU 110, activates a row in a memory bank by issuing an activate (ACT) command. In response to the ACT command, data from memory cells along the selected row are stored in corresponding page buffers in the memory array and in page buffer 830. In DRAM, data reads are destructive to the contents of the memory cells, but a copy of the data is stored in the page buffer. After the memory controller 114 finishes accessing the data in the selected row of the bank, it closes the row by issuing a precharge (PRE) command (or a write or read command with automatic precharge, or a precharge all command). The PRE command causes the data in page buffer 124 to be rewritten to that row in the selected bank, and then allows another row to be activated. These operations are conventional in DDR memories, are described in various JEDEC standard documents, and will not be described further.

[0045] However, according to various embodiments disclosed herein, memory 800 is organized into channels, including two initiator channels and two target channels, to support 2CH mode. The channel shown in FIG. 8 is an initiator channel. It provides an address bit known as the "I / T" bit to select either it or its paired target channel, for example, in 2CH mode based on the upper address bit. The I / T signal also controls multiplexer 841 and demultiplexer 842 to route data on the narrow bus to or from the illustrated initiator channel or its paired target channel. It should be apparent that the dual mode architecture can be implemented in a variety of ways, and memory 800 represents only one exemplary way.

[0046] Each of the various components of the memory package 400 of FIG. 4 and the memory 800 of FIG. 8 and the circuit boards 500, 600, 700 of FIG. 5, 6 and 7, or any portion thereof, may be described or represented by a computer accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0047] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the memory package has been disclosed in the context of a graphics double data rate DRAM, but the present disclosure is applicable to other types of memory, such as SRAM and non-volatile memory, as well as other types of DRAM, such as high bandwidth memory (HBM), double data rate (DDR) DRAM, static random access memory (SRAM), various types of non-volatile memory, etc. Furthermore, the present disclosure contemplates various routing embodiments of a printed circuit board (PCB) in which signals from the memory channels have specific signals. For example, active signals may be routed between the memory controller and the memory on one or more layers, with other layers being used as power and ground planes. Also, while the embodiments have been described using examples of 4CH and 2CH modes, other organizations are possible. The vertical and horizontal symmetry of the channels has been described with respect to a reference line on the printed circuit board. In various embodiments, the reference line may correspond to an edge of the printed circuit board, or may be at any angle relative to the printed circuit board. The initiator and target channels have substantially the same circuitry, although not necessarily completely identical, such that there is horizontal symmetry such that the flat ordering of signals from the memory packages corresponds to the signals of the memory controller physical interface (PHY). Accordingly, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. 1. A memory package comprising: a first channel, a second channel, a third channel, and a fourth channel arranged consecutively in a clockwise direction on the memory package; each of the first channel, the second channel, the third channel, and the fourth channel includes an access circuit and a memory array; In a first mode, the first channel controls access to the memory array of the second channel, and the fourth channel controls access to the memory array of the third channel. Memory package.

2. the first channel, the second channel, the third channel, and the fourth channel have terminal patterns that exhibit horizontal symmetry about a vertical center line and vertical symmetry about a horizontal center line; The memory package of claim 1.

3. the first channel having a first plurality of signals in a first flat order from left to right; the second channel having a second plurality of signals corresponding to the first plurality of signals in reverse order; The memory package of claim 1.

4. the third channel having a third plurality of signals corresponding to the first plurality of signals in the first flat order from left to right; the fourth channel having a fourth plurality of signals corresponding to the first plurality of signals in reverse order; The memory package of claim 3.

5. the first plurality of signals includes a read clock signal, a data signal, and a command and address signal; The memory package of claim 3.

6. In a second mode, the first channel, the second channel, the third channel, and the fourth channel are independently accessible. The memory package of claim 1.

7. 1. A circuit board layout comprising: a first memory package and a second memory package; Each memory package is a first channel, a second channel, a third channel, and a fourth channel arranged successively in a clockwise direction; each of the first channel, the second channel, the third channel, and the fourth channel includes a memory array; the first channel and the fourth channel comprise an initiator channel and exhibit vertical symmetry about a horizontal centerline; the second channel and the third channel include a target channel and exhibit vertical symmetry about the horizontal centerline; the first channel and the second channel exhibit horizontal symmetry about a vertical centerline; the third channel and the fourth channel exhibit horizontal symmetry about the vertical centerline; In a first mode, the initiator channel and the target channel are independently accessible; In a second mode, the first channel controls access to the memory array of the second channel, and the fourth channel controls access to the memory array of the third channel. Circuit board layout.

8. the first memory package is arranged horizontally adjacent to the first memory package such that the first channel of the first memory package is located at an upper left position with respect to a reference line of the circuit board, and the second memory package is arranged horizontally adjacent to the first memory package such that the first channel of the first memory package is located at a lower right position with respect to the reference line of the circuit board; The circuit board of claim 7.

9. an integrated circuit processor die; the integrated circuit processor die a memory controller having a first memory controller physical channel interface and a second memory controller physical channel interface respectively coupled to the first channel and the fourth channel of the first memory package, and a third memory controller physical channel interface and a fourth memory controller physical channel interface respectively coupled to the fourth channel and the first channel of the second memory package; The circuit board of claim 7.

10. the integrated circuit processor die includes a graphics processing unit; The circuit board of claim 9.

11. non-intersecting paths between the first and second memory controller physical channel interfaces and the first and fourth channels of the first memory package, respectively; and non-intersecting paths between the third memory controller physical channel interface and the fourth memory controller physical channel interface and the fourth channel and the first channel of the second memory package, respectively. The circuit board of claim 9.

12. The method of claim 11, wherein the first channel of each of the first memory package and the second memory package has a first plurality of signals in a first flat order from left to right; the second channel of each of the first memory package and the second memory package has a second plurality of signals corresponding to the first plurality of signals in reverse order; The circuit board of claim 7.

13. The third channel of each of the first memory package and the second memory package has a third plurality of signals in a second flat order from left to right; the fourth channel of each of the first memory package and the second memory package has a fourth plurality of signals corresponding to the third plurality of signals in reverse order; The circuit board of claim 12.

14. The method of claim 13, wherein the first plurality of signals of each of the first memory package and the second memory package include a read clock signal, a data signal, and a command and address signal. The circuit board of claim 12.

15. 1. A method of operating a memory system by a processor, comprising: selectively accessing a first memory channel, the processor accessing the first memory package mounted on a first side of the printed circuit board by communicating signals to a left side of the first memory package relative to a reference line of the printed circuit board using first channel traces, the first channel traces having a first flat order from left to right; selectively accessing a second memory channel, the processor accessing the second memory package mounted on the first side of the printed circuit board by communicating signals using second signal traces to a right side of the second memory package relative to the reference line of the printed circuit board, the second signal traces having the first flat order in reverse order; method.

16. each of accessing the first memory package and accessing the second memory package includes selectively accessing either a respective first channel as a first initiator with a respective second channel as a first target, and a respective fourth channel as a second initiator with a respective third channel as a second target; 16. The method of claim 15.

17. accessing the first memory package includes accessing the first memory package having respective first, second, third, and fourth channels arranged consecutively in a clockwise direction around the first memory package; accessing the second memory package includes accessing the second memory package having respective first, second, third, and fourth channels arranged consecutively in a clockwise direction around the second memory package; 17. The method of claim 16.

18. accessing the first memory package includes accessing the respective first channel at an upper left portion relative to the reference line; accessing the second memory package includes accessing the respective first channel at a lower right portion relative to the reference line; 18. The method of claim 17.

19. the first memory package has the same circuitry as the second memory package; 17. The method of claim 16.

20. the reference line includes an edge of the printed circuit board; 17. The method of claim 16.

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