Silicon Lateral Etching

Abstract

1. A method for processing a substrate, the method comprising: placing the substrate in a plasma processing chamber, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the substrate including a recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; flowing a first process gas into the plasma processing chamber; pulsing a second process gas into the plasma processing chamber at a pulsing frequency while flowing the first process gas; applying power to power and bias electrodes of the plasma processing chamber while flowing the first process gas and pulsing the second process gas to generate a plasma in the plasma processing chamber; and exposing the substrate to the plasma to laterally etch a portion of the Si layer selective to the SiGe layer to form an indent between the SiGe layers.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority and the filing date of U.S. Non-Provisional Patent Application No. 17 / 713,723, filed April 5, 2022, which is incorporated by reference in its entirety herein.

[0002] The present invention relates generally to methods of processing a substrate, and in a specific embodiment, to lateral silicon etching. [Background technology]

[0003] Advances in integrated circuit (IC) manufacturing have been primarily driven by increasing device density to improve speed, performance, and manufacturing costs. Scaling to smaller node sizes has led to IC device architectures evolving from two-dimensional (2D) planar structures to three-dimensional (3D) vertical structures such as fin field-effect transistors (FinFETs). Further development of 3D device structures has led to the concept of gate-all around (GAA) devices, including nanosheet or nanowire structures. Nanosheet or nanowire (nanosheet / nanowire) transistors are expected to realize larger effective widths and improved device performance, and thus be promising candidates to replace FinFETs at the 5nm node and beyond.

[0004] Some of the unique features of nanosheet / nanowire transistor fabrication compared to FinFET fabrication are stacked sheet formation by epitaxy, internal spacer formation, dummy gate formation and subsequent channel release, and multi-threshold voltage processing. Due to these features, the fabrication process of nanosheet / nanowire transistors tends to be more complicated and tends to pose unprecedented challenges in assembly and material selection. Therefore, further development of fabrication processes for the implementation of nanosheet / nanowire transistors is needed. Summary of the Invention

[0005] According to one embodiment of the present invention, a method of processing a substrate includes placing the substrate in a plasma processing chamber, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the substrate including a recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; flowing a first process gas into the plasma processing chamber; pulsing a second process gas into the plasma processing chamber at a pulsing frequency while flowing the first process gas, the second process gas being different from the first process gas; applying power to power and bias electrodes of the plasma processing chamber while flowing the first process gas and pulsing the second process gas to generate a plasma in the plasma processing chamber; and exposing the substrate to the plasma to laterally etch a portion of the Si layer selective to the SiGe layer to form an indent between the SiGe layers.

[0006] According to one embodiment of the present invention, a method for processing a substrate includes forming a recess on a substrate, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; forming a passivation layer on a surface of the SiGe layer, the surface including the exposed sidewall of the SiGe layer; flowing a first component gas into a plasma processing chamber; and generating a first plasma in the plasma processing chamber. The above step of forming a passivation layer includes a step of exposing the substrate to a first plasma, and a step of laterally etching a portion of the Si layer to form an indent between the SiGe layer, the lateral etching step including the steps of flowing a second component gas into a plasma processing chamber, generating a second plasma in the plasma processing chamber, and exposing the substrate to the second plasma, the second plasma being different from the first plasma, and the passivation layer preventing etching of the SiGe layer by the second plasma.

[0007] According to one embodiment of the present invention, a method for processing a substrate comprises forming a plurality of vertical recesses in a layer stack, the layer stack being disposed on a substrate, the layer stack comprising alternating nanosheet layers comprising germanium (Ge) and sacrificial layers comprising silicon (Si), the substrate further comprising a dummy gate formed on the layer stack, the plurality of vertical recesses exposing sidewalls of the nanosheet layers and sidewalls of the sacrificial layers, and exposing the substrate to a plasma comprising nitrogen in a plasma processing chamber to induce nitridation of a portion of a surface of the nanosheet layers, the plasma being generated by flowing a first process gas comprising nitrogen into the plasma processing chamber. the steps of exposing the substrate to a plasma, pulsing a second process gas comprising fluorine into the plasma processing chamber while maintaining the plasma and while flowing the first process gas to supply fluorine to the plasma, where the fluorine-supplied plasma laterally etches a portion of the sacrificial layer to form a plurality of lateral recesses between adjacent nanosheets; depositing an interior sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the interior sidewall spacer layer to expose tips of the nanosheets, where remaining portions of the interior sidewall spacer layer form interior sidewall spacers.

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0009] [Figure 1A] 1A-1D show cross-sectional views of an exemplary substrate at various stages of a fabrication process including a lateral etching process according to various embodiments, showing a provided substrate including a layer stack of alternating nanosheets and sacrificial layers. [Figure 1B]1A-1D show cross-sectional views of an exemplary substrate at various stages of a fabrication process including a lateral etching process, according to various embodiments, showing the substrate after fin etch-back. [Figure 1C] 1A-1D depict cross-sectional views of an exemplary substrate at various stages of a fabrication process that includes a lateral etching process, according to various embodiments, illustrating the substrate during a passivation phase of the lateral etching process. [Figure 1D] 1A-1D show cross-sectional views of an exemplary substrate at various stages of a fabrication process that includes a lateral etching process, according to various embodiments, illustrating the substrate during an etching phase of the lateral etching process. [Figure 2A] 1A-1C show cross-sectional views of alternating nanosheets and sacrificial layers being exposed to plasma during a lateral etching process in a plasma processing chamber according to various embodiments, illustrating the formation of a passivation layer over the nanosheets. [Figure 2B] 1A-1C show cross-sectional views of alternating nanosheets and sacrificial layers being exposed to plasma during a lateral etching process in a plasma processing chamber according to various embodiments, illustrating how the sacrificial layers are laterally etched. [Diagram 3] 1 shows a cross-sectional view of alternating nanosheet and sacrificial layers during a lateral etching process in a plasma processing chamber with pitting, selectivity, and roughness issues. [Figure 4] 1 illustrates an exemplary device including nanosheet structures enabled by a lateral etching process, according to various embodiments. [Diagram 5] 4 illustrates an example timing diagram of various parameters of a lateral etch process in accordance with various embodiments. [Figure 6A] 1 shows an exemplary process flow diagram of a fabrication process including a lateral etching process, illustrating one embodiment. [Figure 6B]1 shows an exemplary process flow diagram of a fabrication process including a lateral etching process, illustrating another embodiment. [Figure 6C] 1 shows an exemplary process flow diagram of a fabrication process including a lateral etching process, illustrating yet another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] This application relates to the fabrication of semiconductor devices, e.g., 3D devices such as gate-all-around field effect transistors (GAAFETs), and in particular to lateral silicon etching. The fabrication of GAAFETs and other GAA devices typically involves the formation and fabrication of layer stacks of alternating nanosheets for the channel and sacrificial layers that separate the nanosheets. One of the key processes in this fabrication involves the formation of desired indents between the nanosheets by laterally etching portions of the sacrificial layers. However, conventional etching techniques face various problems, including low etch selectivity of the sacrificial layers relative to the nanosheets, pitting, and surface roughness of the formed indents. Thus, new methods of lateral etching while minimizing these problems may be needed.

[0011] The embodiments of the present application disclose a method for selective lateral etching. The lateral etching process in various embodiments includes a plasma process that combines a passivation phase and an etching phase. The passivation phase and the etching phase may be switched and repeated by dynamically controlling the composition of the plasma and other compositions of the plasma. For example, a fluorine agent may be pulsed to a plasma containing nitrogen and hydrogen to periodically switch between these two phases. A passivation layer formed during the passivation phase can protect the nanosheets during the etching phase that laterally etches the sacrificial layer. In various embodiments, the methods disclosed in the present application may be applied to lateral etching of silicon (Si) selective to silicon germanium (SiGe) alloy. Such embodiments can improve the etching selectivity and surface roughness characteristics without causing pitting, allowing the formation of indents between SiGe layers.

[0012] In the following, the steps of the fabrication process including the lateral etching process according to various embodiments are first described with reference to FIGS. 1A-1D. Two phases of the lateral etching process in a plasma processing chamber (i.e., a passivation phase and an etching phase) are illustrated in FIGS. 2A-2B in addition to FIGS. 1C-1D. For comparison, FIG. 3 illustrates the problems of low etching selectivity, pitting, and surface roughness according to the prior art. An example of a gate-all-around (GAA) device enabled by the fabrication process including the lateral etching process is illustrated with reference to FIG. 4. According to some embodiments, the pulsing of the second process gas while continuously flowing the first process gas in the lateral etching process is illustrated in the timing diagram shown in FIG. 5. An exemplary process flow diagram is illustrated in FIGS. 6A-6C. All figures in this disclosure are drawn for illustrative purposes only and are not drawn to scale, including the aspect ratio of the features. The following description in this disclosure is mainly directed to selective lateral etching of Si to SiGe, although other materials can be etched with the method in alternative embodiments.

[0013] 1A-1D show cross-sectional views of an exemplary substrate 100 at various stages of a fabrication process, including a lateral etching process, according to various embodiments. FIG 1A shows a cross-sectional view of an as-supplied substrate 100 with alternating stacks of nanosheets 110 and sacrificial layers 120.

[0014] In various embodiments, substrate 100 may be part of or may include a semiconductor device and may have undergone several processing steps (e.g., following conventional processing). Thus, substrate 100 may include layers of semiconductors useful in various microelectronics. For example, a semiconductor structure may include substrate 100 in which various device regions are formed. In some embodiments, substrate 100 is fabricated as a gate-all-around field effect transistor (GAAFET).

[0015] In one or more embodiments, the substrate 100 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In some embodiments, the substrate 100 may include silicon germanium, silicon carbide, gallium arsenide, gallium nitride, or other compound semiconductors. In other embodiments, the substrate 100 includes foreign layers such as silicon germanium-on-silicon, gallium nitride-on-silicon, silicon carbon-on-silicon, or even silicon-on-silicon layers or SOI substrates. In various embodiments, the substrate 100 is patterned or embedded with other components of a semiconductor device.

[0016] As further shown in FIG. 1A, the substrate 100 may include nanosheets 110 formed therein. Specifically, the nanosheets 110 are embedded in another material. The nanosheets 110 may be separated from one another by one of the sacrificial layers 120. Thus, the substrate 100 includes alternating layers of nanosheets 110 and sacrificial layers 120. Note that although FIG. 1A depicts three layers of nanosheets 110, the number of layers is not limited. In various embodiments, the nanosheets 110 will form a transistor channel at the end of fabrication, while the sacrificial layers 120 will be removed in a later step of fabrication to free up void space for the formation of a gate dielectric and a gate terminal. In various embodiments, the nanosheets 110 may include a silicon germanium alloy (SiGe), the sacrificial layers 120 may include silicon (Si), and a p-type field effect transistor (FET) may be formed using SiGe to enhance hole mobility. For example, the lateral etching process described below in FIGS. 1A-1D may be incorporated into the fabrication process to turn the nanosheets 110 into respective nanowires for the channel region of a GAAFET.

[0017] In some embodiments, the nanosheets 110 may comprise pure Ge. As a particular example, the SiGe used in the nanosheets 110 may be selected from a range of materials having the desired material properties (e.g., electrical properties for a desired application) or a ratio (e.g., SiGe / SiGe) suitable for the desired performance of the resulting semiconductor device. 0.7 Ge0.3 , Si 0.75 Ge 0.25 In some embodiments, nanosheets 110 may include SiGe alloys (mixtures) of germanium (SiGe, Ge, etc.). In some embodiments, nanosheets 110 may include 5-50% germanium. Nanosheets 110 may further include other elements such as dopants (e.g., N, B, and P) in addition to the primary components (e.g., Si and Ge). In some embodiments, all nanosheets 110 have the same composition. However, in other embodiments, each nanosheet 110 or some nanosheets 110 may have different compositions, as desired.

[0018] In various embodiments, nanosheet 110 has a thickness of a few nanometers to a few tens of nanometers, for example, in one embodiment, from about 1 nm to about 20 nm, and in another embodiment, the thickness of nanosheet 110 is from about 1 nm to about 10 nm.

[0019] In some embodiments, the stack of nanosheets 110 and sacrificial layers 120 may be formed by a deposition process, for example, epitaxially by chemical vapor deposition (CVD). In various embodiments, each layer of sacrificial layer 120 and nanosheet 110 may be a few nanometers to a few nanometers thick. In one embodiment, each layer of sacrificial layer 120 may be 5 nm to 20 nm thick, and each layer of nanosheet 110 may be 1 nm to 10 nm thick. Furthermore, each nanosheet 110 may be the same or different in thickness, each sacrificial layer 120 may be the same or different in thickness, and nanosheet 110 and sacrificial layer 120 may be the same or different in thickness.

[0020] Continuing with reference to FIG. 1A, a patterned hardmask layer 130 may be formed on the layer stack of the nanosheet 110 and the sacrificial layer 120. The hardmask used in the patterned hardmask layer 130 may include silicon oxide in one embodiment. In various embodiments, the hardmask may include silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxycarbide (SiOC). In alternative embodiments, the hardmask may include titanium nitride. Additionally, the hardmask may be a stacked hardmask, which includes, for example, two or more layers using two different materials. A first hardmask of the patterned hardmask layer 130 may include a metal-based layer (e.g., titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds), and a second hardmask may include a dielectric layer (e.g., SiO2, silicon nitride, SiCN, SiOC, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon). Deposition techniques that can be used to deposit the hardmask include, for example, vapor deposition techniques including chemical vapor deposition (CVD), physical vapor deposition (PVD), as well as other plasma processes (e.g., plasma enhanced chemical vapor deposition (PECVD)), sputtering, and other processes. The hardmask, in some embodiments, may have a thickness of about 5 nm to about 50 nm. Patterning of the hardmask may be performed by a conventional photolithography process. For example, such a conventional process may include spin-coating a photoresist onto the hardmask, performing a lithographic exposure to react portions of the photoresist for patterning, developing the photoresist to form a relief pattern, and transferring the relief pattern into the hardmask by anisotropic etching.

[0021] The substrate 100 shown in FIG. 1A is merely an example and may further include other layers useful for fabrication. For example, the substrate 100 may further include an optional dielectric blocking layer above the layer stack and below the hard mask. The dielectric blocking layer may include an oxide and may be used as an etch stop layer in one or more fabrication steps. In further embodiments, the substrate 100 may further include a dummy stack structure between the layer stack and the hard mask. The dummy stack may include a dummy gate, which in one embodiment includes polysilicon or amorphous silicon and a sidewall spacer (e.g., SiN).

[0022] FIG. 1B shows a cross-sectional view of the substrate 100 after the fin etch back.

[0023] In FIG. 1B, an anisotropic etch may be performed to form vertical recesses 135. Using the patterned hard mask layer 130 as an etch mask, portions of the nanosheet 110 and portions of the sacrificial layer 120 may be removed to form fin features that may form channel regions of transistors at the end of fabrication, the channel regions being separated by each vertical recess 135. The vertical recesses 135 expose the sidewalls of the nanosheet 110 and the sidewalls of the sacrificial layer 120. In various embodiments, this fin etch back process may include one or more wet etching processes, plasma etching processes (e.g., reactive ion etching (RIE) processes), or combinations of these or other etching processes. In some embodiments, a wet etch cleaning process or a dry etch cleaning process may be performed after the fin etch back process. In one embodiment, a dilute hydrofluoric acid (DHF) aqueous solution may be used in the cleaning process. Similar wet or dry cleaning processes may be performed at various stages of fabrication.

[0024] After the formation of the vertical recesses 135, indentations may be formed between the nanosheets 110 by etching away portions of the sacrificial layer 120 from both ends of the sacrificial layer 120 that are exposed at the sidewalls. To selectively etch the sacrificial layer 120 while preventing etching of the nanosheets 110, in various embodiments, a lateral etching process may be applied at this stage of fabrication.

[0025] Figure 1C shows a cross-sectional view of the substrate 100 during the passivation phase of a lateral etching process. Figure 2A shows a cross-sectional view of alternating nanosheets 110 and sacrificial layers 120 during the formation of a passivation layer 140 over the nanosheets 110 in a lateral etching process according to various embodiments.

[0026] At the start of the lateral etching process, the substrate 100 may first be exposed to a plasma generated from a first process gas, which forms the passivation layer 140, as shown in FIGS. 1C and 2A. In various embodiments, a first plasma 210 may be generated from the first process gas in a plasma processing chamber 200, as shown in FIG. 2A, and the surface of the sidewall of the nanosheet 110 may react to form the passivation layer 140. In some embodiments, the first plasma 210 may include nitrogen species 212 and hydrogen species 214 (FIG. 2A). The nitrogen species 212 and hydrogen species 214 may exist as atomic or molecular ions or atomic or molecular radicals, or combinations thereof. Thus, the first process gas may include nitrogen and hydrogen. In one or more embodiments, the first process gas may be N 2 and H 2 In another embodiment, the first process gas may include ammonia (NH 3 ), or NH 3 / H 2 / N 2 may include any combination of.

[0027] While the passivation layer 140 may be of any suitable thickness, in some embodiments, the passivation layer 140 may be relatively thin, for example, 2 nm or less. The passivation layer 140 may be, for example, a monolayer thick. In various embodiments, the passivation layer 140 may include a nitride formed by nitridation of the surface of the nanosheets 110 by nitrogen species 212 of the first plasma 210. This nitride-based passivation layer can advantageously increase etch selectivity while minimizing consumption of the nanosheets 110, as compared to other types of (e.g., oxide-based) passivation layers. Thus, in one or more embodiments, the first process gas and the first plasma 210 may be essentially oxygen-free. In some embodiments, the first process gas may also include a carrier gas, such as a noble gas (e.g., He, Ne, Ar, and Kr). In various embodiments, the first plasma 210 contains little or no etchant such that substantially no etching occurs. In one embodiment, the first process gas may be essentially fluorine-free. In various embodiments, a nitride may be formed as the passivation layer 140 by reaction between the surface of the nanosheet 110 (e.g., SiGe) and the nitrogen species 212 of the first plasma 210.

[0028] The reactivity of the nitrogen species 212 may be different between the surface of the nanosheet 110 (e.g., SiGe) and the surface of the sacrificial layer 120 (e.g., Si), which allows the selective formation of the passivation layer 140 only on the nanosheet 110. Note that in some embodiments, a similar reaction may occur on the surface of the sacrificial layer 120 during exposure to the first plasma 210 (i.e., during the passivation phase), and an additional layer may be formed on the sacrificial layer 120. The additional layer that may be formed on the sacrificial layer 120 may or may not be similar in composition to the passivation layer 140. In one embodiment, without wishing to be limited by any theory, it is believed that the additional layer may be similar in composition to the passivation layer 140, but has a thickness that is much smaller than the passivation layer 140, so that the selectivity in the etching phase is not nullified. In another embodiment, the difference in composition between the additional layer and the passivation layer 140 may be so large that the etching rate of the additional layer during the etching phase is significantly greater than the etching rate of the passivation layer 140. This may be possible due to the different surface chemistry during the passivation phase relative to the sacrificial layer 120 and the nanosheet 110. These two factors (i.e., thickness and composition) of the passivation layer 140 may play a role in influencing the etching selectivity, separately or in concert, with or without the additional layer. The inventors have confirmed that such an additional layer may be successfully removed during the etching phase. In a further embodiment, the exposure time to the first plasma 210 may be optimized so that the passivation layer 140 is formed and no excess of the additional layer is formed on the sacrificial layer 120. The exposure time to the first plasma 210 may be between 5 seconds and 5 minutes in one embodiment, and between 10 seconds and 30 seconds in another embodiment. In various embodiments, the time of exposure to the first plasma 210 may be optimized relative to the process time of the etching phase so that the subsequent lateral etching process can be efficient and selective.

[0029] Figure ID shows a cross-sectional view of the substrate 100 during the etching phase of the lateral etching process. Figure 2B shows a cross-sectional view of the alternating nanosheets 110 and the sacrificial layer 120 during the etching phase while the sacrificial layer 120 is being etched.

[0030] After the passivation layer 140 is formed, the etching phase of the lateral etching process may be initiated by achieving plasma conditions including an etchant. In FIGS. 1D and 2B, lateral recesses 145 are formed as indents between the nanosheets 110 by selectively removing portions of the sacrificial layer 120 from both ends of the sacrificial layer 120. In various embodiments, the lateral recesses 145 may have a lateral depth of 10 nm to 50 nm. In other embodiments, the lateral depth may be 20 nm to 200 nm. In some embodiments, the lateral recesses 145 may be formed by repeating the passivation and etching phases as part of a cyclic process. Each cycle of the cyclic process may laterally etch between a few monolayers to tens of nanometers of the nanosheets 110. During the etching phase, the passivation layer 140 protects the nanosheets 110 from etching. In various embodiments, the etching phase of the lateral etching process may be achieved by changing the plasma composition from the passivation phase of FIG. 2A, as shown in FIG. 2B. A second plasma 220, different in composition from the first plasma 210, may be generated in the plasma processing chamber 200 to provide an etchant to the sacrificial layer 120 to effect the etching phase. In some embodiments, the second plasma 220 may include nitrogen species 212, hydrogen species 214, and fluorine species 216 (FIG. 2B). Any of these species may exist as atomic or molecular ions or atomic or molecular radicals, or combinations thereof. Without wishing to be limited to any theory, for example, the fluorine species 216 (e.g., fluorine radicals) may be primarily responsible for etching the sacrificial layer. The second plasma 220 may be generated from a second process gas alone or from a combination of the second process gas and the first process gas. In various embodiments, the second process gas may include fluorine. In some embodiments, the second process gas may include nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), carbon tetrafluoride (CF 4 ), fluoroform (CHF 3), difluoromethane (CH 2 F 2 ), or fluoromethane (CH 3 In one or more embodiments, a second process gas (e.g., NF 3 ) while flowing a first process gas (e.g., N 2 and H 2 ) may be maintained. In some embodiments, the second process gas may also include a carrier gas, such as a noble gas (e.g., He, Ne, Ar, and Kr). In one or more embodiments, an optional purge step using an inert gas may be performed between the passivation phase and the etching phase of the lateral etching process. In an embodiment, the RF power applied to the first plasma 210 may be maintained, reduced, or turned off during such optional purge step.

[0031] In some embodiments, the lateral etching process may be based on using an oxygen-free plasma. Using an oxygen-free plasma for the lateral etching process may be advantageous because an oxide-based passivation layer for the nanosheet 110 may consume a significant portion of the nanosheet 110 (e.g., SiGe).

[0032] FIG. 3 shows a cross-sectional view of alternating nanosheets 110 and sacrificial layers 120 during a lateral etching process using another plasma 310 in a plasma processing chamber 200 that has problems with pitting, selectivity, and roughness.

[0033] As shown in FIG. 3, if lateral etching is performed without proper passivation of the nanosheet 110, the lateral recesses 145 formed may have poor surface morphology due to non-selective etching. Since the surface of the nanosheet 110 is not sufficiently protected, the reactive species (e.g., fluorine species 216) of the plasma 310 may etch both the nanosheet 110 and the sacrificial layer 120. This non-selective etching may result in slow etching of the sacrificial layer 120. This is because the reactive species are consumed by etching the nanosheet 110 as well as the sacrificial layer 120. The reactive species may also cause pits in the unprotected surface (i.e., pitting problems). Furthermore, etching by-products may significantly accumulate on the surface, which may deteriorate the surface morphology of the lateral recesses 145 (e.g., increase the surface roughness). These problems may be overcome by utilizing a passivation phase according to various embodiments in the lateral etching process. In one or more embodiments, the surface roughness (e.g., root mean square of height variation, roughness average, or peak-to-valley height) of the lateral recesses 145 may be reduced by employing a passivation phase in the lateral etching process. In some embodiments, the etch selectivity of silicon (Si) to silicon germanium (SiGe) may be between 5:1 and 90:1.

[0034] FIG. 4 illustrates an exemplary device 40 including nanosheet structures enabled by a lateral etching process, according to various embodiments.

[0035] At least a portion of device 40 may be formed using a lateral etching process in various embodiments. Device 40 includes a substrate 402, which includes a channel material 404 (e.g., Ge or SiGe) and a gate material 406 (e.g., Si). Channel material 404 may correspond to nanosheet 110 of FIGS. 1A-1D and 2A-2B. Thus, device 40 may be a gate-all-around (GAA) device as shown, or any other device (e.g., a Fin Field Effect Transistor (FinFET)). Device 40 may also include an isolation region 408. In some embodiments, isolation region 408 is a shallow trench isolation (STI).

[0036] Fabrication of device 40 may begin with heteroepitaxial growth of alternating Si and Ge or SiGe layers forming an alternating film stack 410 (which may correspond to the structure shown in FIG. 1A as the provided substrate 100). Alternating film stack 410 may then be patterned and recessed vertically to expose the sidewalls of the Ge or SiGe layers (FIG. 1B), after which lateral recesses may be formed (FIGS. 1C-1D).

[0037] After completion of the lateral etching process (e.g., FIGS. 1A-1D), subsequent processing may be performed to proceed with semiconductor device fabrication of device 40. In various embodiments, subsequent processing may include filling the lateral recesses with insulating material (i.e., forming inner spacers), epitaxially growing semiconductor regions (i.e., forming source / drains), removing remaining portions of the sacrificial layer (i.e., channel release), providing gate material 406 around channel material 404, and other related steps, all of which are provided by way of example only.

[0038] Application of the various embodiments described herein may advantageously be an optimal solution for the 5 nm node, 3 nm node, or below. For example, the GAA device architecture may be suitable for scaling beyond the 7 nm node. The GAA device architecture can address the short channel effect seen in some FinFET architectures by wrapping the gate around the entire channel, not just on three sides. This can reduce or prevent current leakage under the gate of the FinFET, thereby reducing power loss during inactivity.

[0039] In various embodiments, the passivation and etching phases of the lateral etching process may be advantageously repeated as part of a cyclic process to allow the passivation layer 140 to replenish and / or extend to the surface of the nanosheet 110 within the lateral recesses 145 (FIGS. 1D and 2B). In further embodiments, such cyclical embodiments may be achieved continuously by pulsing a second process gas into the plasma processing chamber while continuously flowing the first process gas and applying sufficient source power to maintain the plasma. In response to this pulsing, the plasma composition in the plasma processing chamber may dynamically switch between two states: the passivation phase when the flow of the second process gas is turned off, and the etching phase when the flow of the second process gas is turned on.

[0040] FIG. 5 illustrates an example timing diagram of various parameters of a lateral etching process in pulsing mode, according to various embodiments.

[0041] In FIG. 5, the four horizontal axes represent the progression of time. The four time axes are used to diagrammatically display plots of four process parameters versus time during the lateral etch process. The process time t 0 From 3The time period from the time of the lateral etch process to the time of the lateral etch process is shown. The four process parameters plotted in Fig. 5 are the gas flow rate of the first process gas, the gas flow rate of the second process gas, the source power, and the bias power. Although not specifically shown in Fig. 5, any other process parameter, such as temperature, may be independently controlled according to its own process recipe at any time during the lateral etch process.

[0042] In FIG. 5, a first process gas (e.g., N 2 and H 2 ) is t 0 may be flowed into the plasma processing chamber at a first flow rate and may remain constant for the duration of the process. In some embodiments, the flow rate of the first process gas may be between 50 and 200 sccm. In one or more embodiments, the first process gas is N 2 and H 2 and their flow rates are 40 to 160 sccm and 10 to 40 sccm, respectively. 1 At this stage, the source power and bias power are turned on and a plasma is generated in the plasma processing chamber. In one or more embodiments, a source power of 100-500 W and a bias power of 0-50 W may be applied. At this stage, there are only species from the first process gas in the plasma processing chamber, and the plasma cannot cause any etching but can cause passivation (i.e., it is the passivation phase). 1 From 2The time to passivation defines the duration of the initial passivation phase, and controlling the process time of the passivation phase can allow for the formation of a sufficient amount of passivation layer 140 on the nanosheet 110 while preventing or minimizing the formation of a layer on the sacrificial layer 120. In one or more embodiments, the process time of the initial passivation can be between 5 seconds and 5 minutes. In one embodiment, the process time of the initial passivation can be shorter than the process time of the etching phase. Starting the lateral etching process with passivation can advantageously ensure that the subsequent etching phase can be sufficiently selective to the nanosheet 110.

[0043] t 2 and a second process gas (e.g., NF 3 ) may be initiated at a pulsing frequency. The introduction of a second process gas (e.g., containing fluorine) into the plasma processing chamber provides an etchant to the plasma already present and being used for passivation, initiating the etching phase. In the example shown in FIG. 5, because the second process gas is provided as pulses, the concentration of the etchant in the plasma can vary significantly in response to the pulsing, thereby advantageously increasing the t 2 and 3 However, it should be noted that the off-phase of pulsing (e.g., t 2 and 3The plasma during the passivation phase between the first and second pulsing phases (passivation phase between the first and second pulsing phases) may or may not be completely etchant-free (e.g., fluorine radical-free). The actual concentration of various species in the plasma processing chamber depends on the lifetime of the species as well as various process parameters (e.g., pressure, pumping speed, and gas flow rate). In some embodiments, due to the high pressure and short lifetime of the species, the concentration of etchant (e.g., fluorine radical) depends on the residence time, which may be less than or equal to one second. Thus, after a few seconds of the off-phase of pulsing, the plasma processing chamber is considered to be substantially etchant-free, and this state continues until the next on-phase of pulsing. In one embodiment, the concentration of etchant may be up to 10%.

[0044] In various embodiments, the pulsing frequency of the second process gas may be between 0.005 and 50 Hz, and in other embodiments, between 0.01 and 1 Hz. The flow rate of the second process gas during the on-phase of pulsing may be between 5 and 50 sccm. In various embodiments, the duty cycle of the pulsing may be between 10 and 80%. The ratio of the flow rate of the first process gas to the flow rate of the second process gas may be between 5:1 and 100:1 in some embodiments.

[0045] In another embodiment, the start of pulsing of the second process gas (e.g., t 2 ) is the supply of power supply and bias power (e.g., t 1 ), or may precede it. For example, if these two steps are performed simultaneously, the first etching phase may precede the first passivation phase. Alternatively, the plasma may be generated after the start of the second process gas, which may advantageously ensure stability of the gas flow in the plasma processing chamber. In these embodiments, the first phase of the lateral etching process may be passivation or etching, depending on the timing of the plasma generation.

[0046] The process parameter conditions shown in FIG. 5 are only examples, and other process recipes with different conditions are possible. For example, a plasma can be sustained in the plasma processing chamber by applying a power pulse train of source power, bias power, or both. The source power and bias power can be changed at any time during the process, including during an optional purge step. In one embodiment, a first set of power conditions can be used for the passivation phase and a second set of power conditions can be used for the etching phase. In another embodiment, the power conditions can be adjusted as the lateral recess extends. The flow rates of the first and second process gases, as well as the gas composition, can be changed at any time during the process. In one embodiment, t 2 Then, once pulsing of the second process gas begins, the flow rate of the first process gas may be advantageously reduced such that the total gas flow rate (or the time average of the total gas flow rate) can remain unchanged. In another embodiment, the first process gas may be pulsed. In yet another embodiment, a component of the first process gas (e.g., NH 3 , H 2 , N 2 , or a combination thereof) with variable timing to vary the composition of the first process gas.

[0047] Various embodiments of the lateral etch process may be performed using any suitable type of plasma processing system, such as an inductively coupled plasma (ICP) tool, a capacitively coupled plasma (CCP) tool, a surface wave plasma (SWP) tool, a resonator (e.g., a helical resonator), etc. Although not described herein, embodiments of the present invention may also be applied to remote plasma systems, as well as batch systems.

[0048] 6A-6C show an example process flow diagram of a fabrication process including a lateral etching process, which can be followed in the figures mentioned above (FIGS. 1A-1D and 2A-2B) and will not be described again.

[0049] In the process flow 60 of FIG. 6A, a substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers and a recess in the layer stack may be placed in a plasma processing chamber (block 610, FIG. 1B). A first process gas may then be supplied to the plasma processing chamber (block 620), and a second process gas may then be pulsed into the plasma processing chamber while the first process gas is flowing (block 630). Power may then be applied to source and bias electrodes of the plasma processing chamber while the first process gas is flowing and the second process gas is pulsing to generate a plasma in the plasma processing chamber (block 640), and the substrate may be exposed to the plasma to laterally etch a portion of the Si layer selective to the SiGe layer to form an indent between the SiGe layers (block 650, FIGS. 1C-1D).

[0050] In the process flow 62 of FIG. 6B, a recess is first formed on a substrate including a layer stack of alternating Si and SiGe layers, exposing a sidewall of the Si layer and a sidewall of the SiGe layer (block 605, FIG. 1B). A passivation layer may then be formed on a surface of the SiGe layer (block 622, FIG. 1C) by flowing a first component gas into a plasma processing chamber (block 624), generating a first plasma in the plasma processing chamber (block 626), and then exposing the substrate to the first plasma (block 628). After passivation of the SiGe layer, a portion of the Si layer may be laterally etched (block 632, FIG. 1D) to form an indent between the SiGe layers by flowing a second component gas into the plasma processing chamber (block 634), generating a second plasma in the plasma processing chamber (block 636), and exposing the substrate to the second plasma (block 638).

[0051] In the process flow 64 of FIG. 6C, first, a vertical recess is formed in a layer stack of alternating Si-containing sacrificial layers and Ge-containing nanosheet layers on a substrate including a dummy gate (block 606, FIG. 1B). The substrate may then be exposed to a plasma including nitrogen in a first process gas in a plasma processing chamber to induce nitridation of a portion of the surface of the Ge-containing nanosheet layers (block 625, FIG. 1C). Next, while maintaining the plasma and flowing the first process gas, a second process gas including fluorine may be pulsed into the plasma processing chamber to laterally etch a portion of the sacrificial layers and form lateral recesses between adjacent nanosheets (block 635, FIG. 1D). After the lateral etching process, an interior sidewall spacer layer may be deposited (block 660) to fill the lateral recesses, and then etched back to expose the tips of the nanosheets (block 670) to complete the formation of the interior sidewall spacers. Thereafter, in some embodiments, process flow 64 may proceed to various additional steps (block 680), such as epitaxial growth of semiconductor regions (i.e., source / drain formation), removal of remaining portions of the sacrificial layer (i.e., channel release), and providing a gate material around the nanosheet.

[0052]

[0023] Illustrative embodiments of the present invention are summarized herein. Other embodiments may be seen from this entire specification, as well as the claims appended hereto.

[0053] Example 1. A method of processing a substrate, comprising: placing the substrate in a plasma processing chamber, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the substrate including a recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; flowing a first process gas into the plasma processing chamber; pulsing a second process gas into the plasma processing chamber at a pulsing frequency while flowing the first process gas, the second process gas being different from the first process gas; applying power to a power electrode and a bias electrode of the plasma processing chamber while flowing the first process gas and pulsing the second process gas to generate a plasma in the plasma processing chamber; and exposing the substrate to the plasma to laterally etch a portion of the Si layer selective to the SiGe layer to form an indent between the SiGe layers.

[0054] Example 2. The method of example 1, wherein the first process gas comprises nitrogen and the second process gas comprises fluorine.

[0055] Example 3. The first process gas is N 2 and H 2 or the first process gas comprises NH 3 The method according to any one of Examples 1 or 2, comprising:

[0056] Example 4. The second process gas is NF 3 ,SCIENCE FICTION 6 , C.F. 4 , CHF 3 , C.H. 2 F 2 , or C.H. 3 The method according to any one of Examples 1 to 3, comprising F.

[0057] Example 5. The method of any one of Examples 1-4, wherein the plasma forms a passivation layer on a surface of the SiGe layer, the surface of the SiGe layer including a sidewall of the SiGe layer.

[0058] Example 6. The method according to any one of Examples 1 to 5, wherein the pulsing frequency is 0.01 to 1 Hz.

[0059] Example 7. The method of any one of Examples 1-6, wherein the duty cycle of the pulsing is 10-80%.

[0060] Example 8. The method of any one of Examples 1-7, wherein the ratio of the flow rate of the first process gas to the flow rate of the second process gas is between 5:1 and 100:1.

[0061] Example 9. The method of any one of Examples 1-8, wherein applying power to the power electrode and the bias electrode to generate the plasma is performed while a second process gas is flowing into the plasma processing chamber.

[0062] Example 10. The method of any one of Examples 1-9, wherein the step of applying power to the power electrode and the bias electrode comprises applying a power pulse train.

[0063] Example 11. A method of processing a substrate, comprising forming a recess on a substrate, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer, forming a passivation layer on a surface of the SiGe layer, the surface including the exposed sidewall of the SiGe layer, flowing a first component gas into a plasma processing chamber, generating a first plasma in the plasma processing chamber, and passing the substrate through a first plasma. and laterally etching a portion of the Si layer to form an indent between the SiGe layer, the laterally etching step including the steps of flowing a second component gas into a plasma processing chamber, generating a second plasma in the plasma processing chamber, and exposing the substrate to the second plasma, the second plasma being different from the first plasma, and the passivation layer preventing etching of the SiGe layer by the second plasma.

[0064] Example 12. The first component gas is N 2 and H 2 and the second process gas comprises NF 3 ,SCIENCE FICTION 6 , C.F. 4 , CHF 3 , C.H. 2 F 2 , or C.H. 3 The method of example 11, comprising F.

[0065] Example 13. The method of any one of Examples 11 or 12, wherein the laterally etching further comprises continuously flowing the first component gas into the plasma processing chamber, and the flowing the second component gas into the plasma processing chamber is performed intermittently.

[0066] Example 14. The method of any one of Examples 11-13, wherein the step of exposing the substrate to the first plasma is performed for a duration of 5 seconds to 5 minutes.

[0067] Example 15. The method of any one of Examples 11-14, further comprising repeating the forming and laterally etching steps.

[0068] Example 16. A method of processing a substrate, comprising forming a plurality of vertical recesses in a layer stack, the layer stack being disposed on a substrate, the layer stack including alternating nanosheet layers including germanium (Ge) and sacrificial layers including silicon (Si), the substrate further including a dummy gate formed on the layer stack, the plurality of vertical recesses exposing a sidewall of the nanosheet layer and a sidewall of the sacrificial layer, and exposing the substrate to a plasma including nitrogen in a plasma processing chamber to induce nitridation of a portion of a surface of the nanosheet layer, the plasma being generated by flowing a first process gas including nitrogen into the plasma processing chamber. and, while maintaining the plasma and while flowing the first process gas, pulsing a second process gas comprising fluorine into the plasma processing chamber to supply fluorine to the plasma, where the fluorine supplied plasma laterally etches a portion of the sacrificial layer to form a plurality of lateral recesses between adjacent nanosheets; depositing an interior sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the interior sidewall spacer layer to expose tips of the nanosheets, where remaining portions of the interior sidewall spacer layer form interior sidewall spacers.

[0069] Example 17. The method of example 16, further comprising forming a multi-layer spacer over the dummy gate prior to forming the plurality of vertical recesses.

[0070] Example 18. The method of any one of Examples 16 or 17, further comprising, after etching a portion of the inner sidewall spacer layer, epitaxially growing a semiconductor region from the exposed tips of the nanosheets.

[0071] Example 19. The method of any one of Examples 16-18, wherein the nanosheet layer is a silicon germanium layer containing 5-50% germanium.

[0072] Example 20. The method of any one of examples 16-19, wherein the lateral recesses have a depth of 10-80 nm.

[0073] Although the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to this specification. It is therefore intended that the appended claims cover all such modifications or embodiments.

Claims

1. 1. A method for processing a substrate, comprising: placing a substrate in a plasma processing chamber, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the substrate including a recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; flowing a first process gas into the plasma processing chamber; pulsing a second process gas into the plasma processing chamber at a pulsing frequency while flowing the first process gas, the second process gas being different from the first process gas; applying power to power and bias electrodes of the plasma processing chamber while flowing the first process gas and pulsing the second process gas to generate a plasma in the plasma processing chamber; exposing the substrate to the plasma to laterally etch a portion of the Si layer selectively to the SiGe layer to form an indentation between the SiGe layers; The method includes:

2. 2. The method of claim 1, wherein the first process gas comprises nitrogen and the second process gas comprises fluorine.

3. The first process gas is N ２ and H ２ or the first process gas comprises NH ３ The method of claim 1 , comprising:

4. The second process gas is NF ３ , S.F. ６ , C.F. ４ , C.H.F. ３ , C.H. ２ F ２ , or C.H. ３ The method of claim 1 comprising F.

5. The method of claim 1 , wherein the plasma forms a passivation layer on a surface of the SiGe layer, the surface of the SiGe layer including the sidewalls of the SiGe layer.

6. The method of claim 1 , wherein the pulsing frequency is between 0.01 and 1 Hz.

7. The method of claim 1 , wherein the duty cycle of the pulsing is between 10 and 80%.

8. 2. The method of claim 1, wherein a ratio of a flow rate of the first process gas to a flow rate of the second process gas is between 5:1 and 100:

1.

9. 2. The method of claim 1, wherein the step of applying the power to the power electrode and the bias electrode to generate the plasma is performed while the second process gas is flowing into the plasma processing chamber.

10. The method of claim 1 , wherein the step of applying the power to the power electrode and the bias electrode comprises applying a power pulse train.

11. 1. A method for processing a substrate, comprising: forming a recess on a substrate, the substrate including a layer stack of alternating silicon (Si) and silicon germanium (SiGe) layers, the recess exposing a sidewall of the Si layer and a sidewall of the SiGe layer; forming a passivation layer on a surface of the SiGe layer, the surface including the exposed sidewalls of the SiGe layer; flowing a first constituent gas into a plasma processing chamber; generating a first plasma in the plasma processing chamber; exposing the substrate to the first plasma; forming the passivation layer, laterally etching a portion of the Si layer to form an indent between the SiGe layers; flowing a second constituent gas into the plasma processing chamber; generating a second plasma in the plasma processing chamber; exposing the substrate to the second plasma; the laterally etching step comprising: Including, the second plasma is different from the first plasma; the passivation layer prevents etching of the SiGe layer by the second plasma; method.

12. The first component gas is N ２ and H ２ The second component gas comprises NF ３ , S.F. ６ , C.F. ４ , C.H.F. ３ , C.H. ２ F ２ , or C.H. ３ The method of claim 11 comprising F.

13. 12. The method of claim 11 , wherein the laterally etching step further comprises the step of continuously flowing the first component gas into the plasma processing chamber, and the step of flowing the second component gas into the plasma processing chamber is performed intermittently.

14. The method of claim 11 , wherein the step of exposing the substrate to the first plasma is performed for a duration of between 5 seconds and 5 minutes.

15. The method of claim 11 , further comprising repeating the forming and laterally etching steps.

16. 1. A method for processing a substrate, comprising: forming a plurality of vertical recesses in a layer stack, the layer stack being disposed on the substrate, the layer stack including alternating nanosheet layers including germanium (Ge) and sacrificial layers including silicon (Si), the substrate further including a dummy gate formed on the layer stack, the plurality of vertical recesses exposing sidewalls of the nanosheet layers and sidewalls of the sacrificial layers; exposing the substrate to a plasma containing nitrogen in a plasma processing chamber to induce nitridation of a portion of a surface of the nanosheet layer, the plasma being generated by flowing a first process gas containing nitrogen into the plasma processing chamber; While maintaining the plasma and flowing the first process gas, pulsing a second process gas comprising fluorine into the plasma processing chamber to supply fluorine to the plasma, wherein the fluorine-supplied plasma laterally etches a portion of the sacrificial layer to form a plurality of lateral recesses between adjacent nanosheets; depositing an interior sidewall spacer layer to fill the plurality of lateral recesses; etching a portion of the interior sidewall spacer layer to expose tips of the nanosheets, with remaining portions of the interior sidewall spacer layer forming interior sidewall spacers; The method includes:

17. 17. The method of claim 16, further comprising forming a multi-layer spacer over the dummy gate prior to the step of forming the plurality of vertical recesses.

18. 17. The method of claim 16, further comprising, after said step of etching said portion of said inner sidewall spacer layer, epitaxially growing a semiconductor region from said exposed tips of said nanosheets.

19. The method of claim 16, wherein the nanosheet layer is a silicon germanium layer containing 5-50% germanium.

20. The method of claim 16, wherein the lateral recess has a depth of 10 to 80 nm.

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