Hybrid Patterning-Joining Semiconductor Tools

Abstract

The device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of the first wafer and the second wafer, including relative z-height values ​​of the first wafer and the second wafer. The stressor film deposition module is configured to form a first stressor film on the first wafer. The stressor film modification module is configured to modify the first stressor film based on a first modification map that defines an adjustment of an internal stress of the first wafer and is generated based on the wafer shape data. The second set of modules includes an alignment module configured to align the first wafer with the second wafer and a bonding module configured to bond the first wafer to the second wafer.

Description

[Technical field]

[0001] Incorporation by Reference This disclosure claims the benefit of U.S. Provisional Patent Applications Nos. 63 / 328,825 and 63 / 328,823, filed April 8, 2022, and U.S. Nonprovisional Patent Applications Nos. 17 / 885,097 and 17 / 885,038, filed August 10, 2022, each of which is incorporated by reference in its entirety.

[0002] The present disclosure relates generally to semiconductor manufacturing, and more particularly to wafer overlay control. [Background technology]

[0003] Semiconductor manufacturing involves multiple and varied steps and processes. One typical manufacturing process is known as photolithography (also called microlithography). Photolithography uses radiation, such as ultraviolet or visible light, to create fine patterns in semiconductor device designs. Semiconductor manufacturing techniques, including photolithography, etching, film deposition, surface cleaning, metallization, etc., can be used to construct a variety of semiconductor devices, such as diodes, transistors, and integrated circuits.

[0004] An exposure system (also called an exposure tool) is used to implement photolithography techniques. An exposure system typically includes an illumination system, a reticle (also called a photomask) or a spatial light modulator (SLM) for creating a circuit pattern, a projection system, and a wafer alignment stage for aligning a semiconductor wafer covered with a photosensitive resist. The illumination system illuminates an area of ​​the reticle or SLM with an illumination field of a (preferably) rectangular slot. The projection system projects an image of the illuminated area of ​​the reticle pattern onto the wafer. For accurate projection, it is important to expose a relatively flat or planar wafer, preferably with a height deviation of less than 10 microns, to the light pattern. Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure relates to a device for bonding wafers. [Means for solving the problem]

[0006] According to a first aspect of the present disclosure, a device for wafer bonding is provided. The device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of a first wafer and a second wafer. The wafer shape data includes relative z-height values ​​of the first wafer and the second wafer. The stressor film deposition module is configured to form a first stressor film on the first wafer. The stressor film correction module is configured to modify the first stressor film based on a first correction map that specifies an adjustment of an internal stress of the first wafer. The first correction map is generated based on the wafer shape data of the first wafer and the second wafer. The second set of modules includes an alignment module configured to align the first wafer with the second wafer and a bonding module configured to bond the first wafer to the second wafer.

[0007] In some embodiments, the stressor film deposition module is configured to form a first stressor film on the first wafer based on the first modification map.

[0008] In some embodiments, the first wafer has a front work surface and a back surface opposite the front work surface, and the stressor film deposition module is configured to form a first stressor film on the back side of the first wafer.

[0009] In some embodiments, the stressor film deposition module includes at least one of a spin-coating apparatus, a spray-coating apparatus, or an evaporation apparatus.

[0010] In some embodiments, the stressor film modification module includes a direct write exposure tool configured to expose the first stressor film to a pattern of electromagnetic radiation based on the first modification map.

[0011] In some embodiments, the stressor film modification module includes a developer configured to develop a photoresist layer of the first stressor film to form a relief pattern.

[0012] In some embodiments, the stressor film modification module includes an etcher configured to etch the shape-controlling layer of the first stressor film using the relief pattern as an etch mask.

[0013] In some embodiments, the stressor membrane modification module includes a hot plate with zoned temperature control.

[0014] In some embodiments, the stressor membrane modification module includes a thermal array having thermal zones with independent temperature control.

[0015] In some embodiments, the thermal array includes an array of resistors, each configured to generate a respective amount of heat based on a respective current passing through it.

[0016] In some embodiments, the at least one resistor is incorporated into a wafer chuck configured to hold the first wafer.

[0017] In some embodiments, the stressor film modification module includes a laser system configured to heat at least one of the first wafer or a wafer chuck configured to hold the first wafer.

[0018] In some embodiments, the controller is configured to generate a first correction map based on the wafer shape data of the first wafer and the second wafer.

[0019] In some embodiments, the controller is configured to receive input from and provide output to at least one module selected from the group consisting of a metrology module, a stressor film deposition module, a stressor film modification module, an alignment module, and a bonding module.

[0020] In some embodiments, the controller is configured to control at least one process selected from the group consisting of measuring wafer shape data, depositing a first stressor film, modifying the first stressor film, aligning the first wafer and the second wafer, and bonding the first wafer and the second wafer.

[0021] In some embodiments, the controller is configured to generate the first correction map based on historical data in addition to wafer shape data of the first wafer and the second wafer, where the historical data includes overlay information of the historical wafer.

[0022] In some embodiments, the stressor film deposition module is configured to form a second stressor film on a second wafer, and the stressor film modification module is configured to modify the second stressor film based on a second modification map that specifies an adjustment of an internal stress of the second wafer, the second modification map being generated based on wafer shape data of the first wafer and the second wafer.

[0023] In some embodiments, the alignment module and the bonding module are one integrated module so that there is no wafer transfer between alignment and bonding.

[0024] According to a second aspect of the present disclosure, a device for wafer bonding is provided. The device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of the first wafer and the second wafer. The wafer shape data includes relative z-height values ​​of the first wafer and the second wafer. The stressor film deposition module is configured to form a first stressor film on the first wafer based on a first correction map that specifies an adjustment of an internal stress of the first wafer. The first correction map is generated based on the wafer shape data of the first wafer and the second wafer. The second set of modules includes an alignment module configured to align the first wafer with the second wafer without correction of the first stressor film between the formation and the alignment. The bonding module is configured to bond the first wafer to the second wafer.

[0025] In some embodiments, the first modification map does not include a pattern.The stressor film deposition module is configured to form the first stressor film as a blanket film.

[0026] It should be noted that this Summary of the Invention section does not specify every embodiment and / or progressively novel aspect of the present disclosure or claimed invention. Instead, this Summary of the Invention only provides a preliminary discussion of different embodiments and corresponding points of novelty. For further details and / or anticipated aspects of the invention and embodiments, the reader is directed to the Detailed Description of the Invention section of this disclosure and corresponding figures, which are discussed further below. [Brief description of the drawings]

[0027] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, according to standard industry practice, various features are not drawn to scale, and in fact the dimensions of various features may be increased or decreased for clarity of discussion.

[0028] [Figure 1A] FIG. 2 is a plan view of a hybrid system according to some embodiments of the present disclosure. [Figure 1B] FIG. 1 is a perspective view of a hybrid system according to some embodiments of the present disclosure. [Figure 2A] 1 shows a simplified diagram of a process of wafer shape correction according to some embodiments of the present disclosure. [Figure 2B] 1 shows a schematic diagram of a process for wafer bonding according to some embodiments of the present disclosure. [Figure 3A] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 3B] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 3C] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 3D] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 3E] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 3F] 1A-1D show cross-sectional views of a wafer at various intermediate steps in its manufacture according to some embodiments of the present disclosure. [Figure 4A] 1 illustrates a top view of a thermal array according to one embodiment of the present disclosure. [Figure 4B] 1 illustrates thermal zones generated by a thermal array according to one embodiment of the present disclosure. [Figure 4C]13 illustrates thermal zones produced by a thermal array according to another embodiment of the present disclosure. [Diagram 5] 1 illustrates a flow chart of a process for wafer bonding according to an exemplary embodiment of the present disclosure. [Figure 6A] 1 shows an example of low-order wafer deformation. [Figure 6B] 1 shows an example of high order wafer deformation. [Figure 7] An example of a warped wafer test result is shown. [Figure 8A] An example of the raw joining error is shown. [Figure 8B] An example of a residual bonding error is shown. [Figure 8C] 4 shows another example of raw joining error. [Figure 8D] 4 shows another example of a residual bonding error. [Figure 9A] 1 illustrates a desired joint alignment according to one embodiment of the present disclosure. [Figure 9B] An example of a significant joint failure is shown below. [Figure 10] Experimental data on warped / bowed wafers and bond overlay error are presented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of components and arrangements are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purposes of brevity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of description, spatial relationship terms such as "top," "bottom," "lower," "below," "lower," "lower," "upper," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatial relationship terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein may likewise be interpreted accordingly.

[0030] The order of consideration of the different steps described herein is presented for clarity. In general, these steps can be performed in any suitable order. In addition, although different features, techniques, configurations, etc. herein may each be discussed in different parts of this disclosure, it is intended that each concept can be implemented independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0031] A typical semiconductor device may be composed of numerous layers, such as over 70 individual layers. At each level, multiple process steps are required to form the desired structures, including but not limited to thin film deposition, lithography, and etching. Non-uniform wafer stresses induced through these fundamental operations result from thin film patterning and are amplified through multiple temperature cycling processes, radically distorting the wafer grid.

[0032] These (wafer shape) distortions can appear as low-order global spherical deformations, as depicted in Figure 6A. Higher-order local height variations can be present as independent distortions or can be embedded in the global signature. An example of higher-order wafer deformation is presented in Figure 6B. The presented data is obtained from conventional semiconductor metrology equipment common in the industry. Both low-order and high-order wafer deformations can complicate the W2W (wafer-to-wafer) bonding process and negatively affect the yield, e.g., resulting in yield loss.

[0033] Wafer (grid) integrity is not only paramount to be able to handle the wafer as it moves through the modules of semiconductor manufacturing equipment, but it can also have a significant impact on yield during the bonding process. With the advent of 3D packaging, the semiconductor industry is entering a critical juncture where traditional bonding-based alignment corrections cannot account for nonlinear physical wafer effects induced through processing: stresses imposed on the wafer prior to the bonding operation impart global and local wafer shape distortions that can cause misalignments and compromise critical bonding metrics, directly resulting in significant yield loss in advanced packaging processes.

[0034] The purpose of a wafer bonding system is to connect (or bond) two constituent wafers in one mechanically stable package. As such, a W2W bonding platform consists of handling mechanisms and process modules for the top (upper) and bottom (lower) wafers. Its complexity is not relevant to this disclosure, except for the fact that alignment tolerances exist when integrating the wafers to produce a functioning device, which is mentioned in more detail below.

[0035] Wafer shape distortion can affect the most fundamental operation of a W2W system: wafer handling. If wafer warp (or wafer bow) prevents wafer transport and / or chucking, the effective yield of the bonding process will be zero. FIG. 7 clearly illustrates such failures in a HVM (high volume manufacturing) W2W bonding tool. As shown, wafers with compression-induced distortion (or wafer bow) greater than about 370 μm had significant handling failures that required manual recovery from the system. That is, the wafers in their current warped state prevented processing altogether. It should be noted that the wafer bow threshold that causes handling failures may vary depending on the specific tool. 370 μm is used as an example for illustration purposes herein.

[0036] On the (same) HVM W2W bonding tool (platform) used in FIG. 7, these wafers produced residual bonding errors as shown in FIG. 8A-8D. Specifically, FIG. 8A and FIG. 8B show the raw and residual errors of one wafer with a wafer bow of 100 μm. FIG. 8C and FIG. 8D show the raw and residual errors of another wafer with a wafer bow of 150 μm. It is noted that the residual errors are not correctable by the system components (e.g., HVM W2W bonding tool) and may show the best results even with feed-forward / backward correction applied. As understood by those skilled in the art, if the magnitude of these residual (overlay) errors is large enough, the residual errors may cause significant failures in electrical continuity and prevent devices from being produced. A simplified example is visualized in FIG. 9B, where the misalignment of the copper wiring between the top and bottom bonded wafers results in failure. Complex high-order wafer deformations, such as the high-order wafer deformation depicted in FIG. 6B, are expected to exacerbate the residual errors even further.

[0037] In FIG. 9B, the misaligned system 900B includes a bonded first wafer 910 (or top wafer) and a second wafer 920 (or bottom wafer). The first wafer 910 includes a first interconnect structure 913 (e.g., shown as 913a, 913b, and 913c), while the second wafer 920 includes a second interconnect structure 923 (e.g., shown as 923a, 923b, and 923c). The first interconnect structure 913 is misaligned with the second interconnect structure 923. In particular, the first interconnect structures 913a, 913b, and 913c are misaligned with the second interconnect structures 923a, 923b, and 923c, respectively. Therefore, the misaligned system 900B is faulty.

[0038] 9A illustrates an aligned system 900A, where a first interconnect structure 913 is aligned with a second interconnect structure 923. In particular, first interconnect structures 913a, 913b, and 913c are aligned with second interconnect structures 923a, 923b, and 923c, respectively. Although shown as seamlessly connected, there may be at least one interface or intermediate layer between the first interconnect structure 913 and the second interconnect structure 923.

[0039] Wafer distortion (or stress) can therefore lead to overlay errors and yield losses. These yield losses will only continue to worsen as alignment tolerances shrink in next-generation chip designs for advanced node semiconductor manufacturing. Therefore, especially as the semiconductor industry enters a critical juncture with the advent of 3D packaging and shrinking alignment tolerances for next-generation device designs, it is paramount that techniques exist to conveniently manipulate wafer shape to enable handling of highly distorted wafers through W2W bonding tools and provide compensation mechanisms for deficiencies present in bonder alignment systems that cannot effectively address wafer grid distortion. Such novel techniques are described herein.

[0040] Figure 10 shows experimental data that further illustrates the relationship between warped / bowed wafers and bonded overlay error. On the left side of Figure 10 is "Baseline", the standard baseline process. "Global Bow", "High Order Bow 1" and "High Order Bow 2" explore the response of global bow and higher order wafer distortions. It can be seen that the uncorrectable residual component of overlay is significantly worse than the baseline.

[0041] The technology disclosed herein provides the industry with a solution to combat process-induced wafer distortions, enabling the future of packaging solutions. The technology herein includes systems and hardware for manipulating wafer shape through a stress control layer (also called stressor film). The stress control layer may be locally enhanced by patterning and / or activation processes to provide additional degrees of freedom. Conventional wafer shape metrology tools and data from the semiconductor industry can be used as input functions to design the correct stress of the control layer and optimize the enhancement location for enhanced W2W (wafer-to-wafer) bonding performance. As a result of the integration of these methods, bond overlay residuals can be reduced, bond strength can be improved, and invalidations can be reduced, thereby providing commensurate yield improvements. An example of an embodiment includes combining lithography modules for coating, exposure, and development with modules for bonding wafers. The patterning capabilities of such tools are optimized to manipulate wafer shape through a stress control layer integrated on the wafer by using heat and / or electromagnetic radiation. Therefore, wafer-to-wafer bonding tools are equipped with shape correction capabilities to improve bonding yields. Note that in this disclosure, "wafer" and "substrate" are used interchangeably.

[0042] 1A and 1B are respectively a plan view and a perspective view of a hybrid system 100 according to some embodiments of the present disclosure. Initially, the hybrid system 100 includes a first set 150 of modules configured for wafer shape correction and a second set 160 of modules configured for wafer bonding. The hybrid system 100 may also include various wafer handling components and / or carriers. The carrier block 110 includes a stage 111 for receiving a wafer carrier 112. The wafer carrier 112 may accommodate multiple (semiconductor) wafers or substrates. A door 114 may be opened to access the multiple wafers in the wafer carrier 112. A first transfer arm 116 may transfer a substrate from the wafer carrier 112 to a shelf unit 121 in the processing block 120. A second transfer arm 123 may be positioned adjacent to the shelf unit 121 for forward and backward and vertical movement. The third transfer arm 125 can then access substrates from the shelf unit 121 or the second transfer arm 123 and move between modules, such as the first set of modules 150 and the second set of modules 160.

[0043] In this example, the first set of modules 150 (or wafer shape correction modules) includes modules 131, 132, 133, 134, 135, 136, 137, 138, and 139. Specifically, the modules 131 to 139 may include a metrology module 131, a deposition module 132, a coating module 133, a baking module 134, an image processing module 135, a development module 136, an etching module 137, a cleaning module 138, and a first inspection module 139.

[0044] Briefly, metrology module 131 may be configured to measure wafer shape data, such as the bow of the substrate, and generate bow measurements that map z-height deviations on the substrate relative to one or more reference z-height values. Deposition module 132 may be configured to deposit one or more films on the backside of the substrate (or on the front working surface of the substrate). Coating module 133 may be configured to coat the backside of the substrate (or on the front working surface of the substrate) with a radiation-sensitive material, such as a photoresist. Bake module 134 may be configured to bake the radiation-sensitive material. Image processing module 135 may be configured to expose the radiation-sensitive material to a pattern of actinic radiation based on an overlay correction pattern, which will be described below. Development module 136 may be configured to develop the radiation-sensitive material after exposure or image processing. Etching module 137 may be configured to use plasma or gas phase etching or wet etching. Cleaning module 138 may be configured to remove remaining (or residual) radiation-sensitive material from the substrate after the etching operation. The first inspection module 139 can be configured to inspect for defects after the overlay correction process. It should be noted that a brief description of the modules 131-139 is provided herein for illustrative purposes. A detailed description and examples of the modules 131-139 can be found in Applicant's issued U.S. Patent No. 10,475,657, which is incorporated herein by reference in its entirety.

[0045] Although the example of FIG. 1A is shown including all of modules 131-139, the first set of modules 150 may in other examples include only one or more of modules 131-139 depending on the specific design needs. In one embodiment, the first set of modules 150 may include modules 131-138 without the first inspection module 139. In another embodiment, the first set of modules 150 may include modules 131-135 without modules 136-138. In yet another embodiment, the first set of modules 150 may include modules 131-132 without modules 133-138. It should be noted that an external or outer tool may be used in place of at least one of modules 131-139. In some examples, wafer metrology is performed in an external metrology tool, and thus metrology module 131 is not required. In some embodiments, film formation is performed in an external or outer deposition tool, and thus deposition module 132 and / or coating module 133 are not required. Additionally, for a given one of modules 131-139, first set of modules 150 may include any number of the given module. For example, first set of modules 150 may include two metrology modules 131 such that two substrates can be characterized simultaneously. In alternative embodiments, two substrates may be characterized by one metrology module 131, either sequentially or simultaneously.

[0046] 1A , a second set of modules 160 (or wafer bonding modules) includes modules 161, 162, 163, 164, and 165. Specifically, modules 161-165 may include a surface treatment module 161, an alignment module 162, a (pre-) bonding module 163, a second inspection module 164, and an annealing module 165.

[0047] The surface treatment module 161 may be configured to prepare one or more substrate surfaces for subsequent bonding. For example, the surface treatment module 161 may include a plasma device configured to generate plasma and perform a plasma activation process on one or more substrates. The plasma activation process typically involves bombarding the substrate surface with plasma species to chemically activate the substrate surface. The surface treatment module 161 may further include a cleaning device configured to rinse the activated substrate surface with deionized water. It should be noted that the surface treatment module 161 may also be referred to as a cleaning module, an etching module, an activation module, a pre-treatment module, etc., depending on the given process performed by the surface treatment module 161.

[0048] The alignment module 162 can be configured to align the two substrates prior to bonding. For example, the two substrates may each include features such as alignment marks, and the alignment module 162 can be configured to align the alignment marks. Alignment modules are well known.

[0049] In this example, the (pre-)bonding module 163 can be configured to pre-bond or bond the two substrates. For example, the two substrates can be pre-bonded at a relatively low temperature, such as room temperature or around 25°C. The second inspection module 164 can be optionally configured to inspect the alignment after pre-bonding of the substrates, for example using infrared (IR) light transmission image processing. The annealing module 165 can be configured to anneal the two substrates at a relatively high temperature, for example in the range of 25-400°C, to further bond the two substrates. In the example of FIG. 1A, the alignment module 162 and the (pre-)bonding module 163 are shown to be two separate modules. In another example (not shown), the alignment module 162 and the (pre-)bonding module 163 can be one integrated module in which active alignment is performed just before the (pre-)bonding. That is, wafer alignment and (pre-)bonding can be performed consecutively in a single module (eg, a single tool, a single chamber, etc.) and there is no wafer transfer between alignment and (pre-)bonding.

[0050] Although the example of FIG. 1A is shown to include all of modules 161-165, second set of modules 160 may in other examples include one or more of modules 161-165 depending on specific design needs. For example, second set of modules 160 may include modules 161-163 and 165 without second inspection module 164. Furthermore, for a particular module of modules 161-165, second set of modules 160 may include any number of the particular module. For example, second set of modules 160 may include two surface treatment modules 161 such that two substrates may be prepared simultaneously. In alternative embodiments, two substrates may be prepared by one surface treatment module 161, either sequentially or simultaneously.

[0051] Additionally, the second set of modules 160 is configured to bond the two substrates via plasma activated bonding, and thus includes modules 161-165 in some embodiments. In other embodiments, the second set of modules 160 can be configured to bond the two substrates via another wafer bonding technique, such as fusion bonding, surface activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding, and the like. Thus, the second set of modules 160 may or may not include modules 161-165. For example, in the case of surface activated bonding, a surface treatment module (or cleaning module) may be configured to clean the two substrates via fast atom bombardment to atomically clean and activate the surfaces of the two substrates. The two substrates can then be aligned in the alignment module 162 and bonded in the bonding module. Thus, the second set of modules 160 may include three modules in a simple form (i.e., a surface treatment module, an alignment module 162 and a bonding module) or may further include additional modules such as an inspection module for inspecting the alignment after bonding. In the case of fusion bonding, the two silicon substrates may be cleaned by a surface treatment module (or an etching module) to achieve the cleanliness required for pre-bonding, which may be configured to perform a dry or wet etching process on the two silicon substrates. The surface treatment module may further rinse the two silicon substrates with deionized water to make the silicon surfaces hydrophilic. The two silicon substrates may then be aligned in an alignment module 162, pre-bonded in a (pre-)bonding module 163 (optionally inspected by a second inspection module 164) and annealed in an annealing module 165.

[0052] It should be noted that the first set of modules 150 and the second set of modules 160 may share one or more modules. For example, the first set of modules 150 and the second set of modules 160 may include a common cleaning module configured to remove remaining radiation-sensitive material after an etching operation and clean the two substrates prior to pre-bonding or bonding. In other words, the common cleaning module is configured to perform the functions of the cleaning module 138 and the surface treatment module 161. Furthermore, although the modules 131-139 and the modules 161-165 are shown in FIG. 1A as being arranged in two consecutive rows, it should be understood that the modules 131-139 and 161-165 may be arranged in any relative position and in any arrangement.

[0053] It should be noted that the deposition module 132 and the coating module 133, either in combination or alone, may be referred to as a stressor film deposition module. The bake module 134, the image processing module 135, the develop module 136, the etch module 137, the cleaning module 138, and the first inspection module 139, either in combination or alone, may be referred to as a stressor film modification module. Although the modules 131-139 and 161-165 are shown as being located within the processing block 120, it should be understood that one or more of the modules 131-139 and 161-165 may be located within another processing block, such as the processing block 130.

[0054] 1A, a controller 140 is connected to or included in the hybrid system 100. The controller 140 may be a computer processor located within the hybrid system 100 or a computer processor located remotely but in communication with components of the hybrid system 100. The controller 140 may be configured to receive wafer shape data (e.g., bow measurements) and generate a correction map (e.g., overlay correction pattern) based on the bow measurements. The bow measurements may be received from the metrology module 131 or a separate system. The overlay correction pattern prescribes an adjustment of the internal stress of the substrate (e.g., at a specific location on the substrate) based on the bow measurements. The overlay correction pattern may also be based on device parameters of the front working surface of the substrate in addition to the bow measurements. For example, a relatively deep memory array may require more stress correction compared to the early stages of building finFET devices for logic. The overlay correction pattern can be generated or calculated using any of a variety of computational methods, such as surface-to-surface deviation, z-height deviation from a reference plane, multi-order differential analysis of the location of interest, analysis of Zernike polynomials, pixelated basis function optimization, or spherical Bessel functions.

[0055] In the overlay correction pattern, a first given location on the substrate may be prescribed a different internal stress adjustment compared to a second given location on the substrate in the overlay correction pattern. In other words, the stress correction to be made may be specific to a location on the substrate surface. The location may be a point arrangement, an area or a region of the substrate. For example, the overlay correction pattern may prescribe an internal stress adjustment to provide a flat substrate (no curvature) or a slight selected curvature that is favorable for the subsequent patterning process. Such internal stress adjustment may be based on the type and thickness of a film deposited on the back surface of the substrate or the front working surface of the substrate.

[0056] In some embodiments, the controller 140 may be coupled to various components (e.g., modules) of the hybrid system 100 to receive inputs from and provide outputs to the various components. The controller 140 may be configured to control at least one module selected from the group consisting of modules 131-139 and 161-165. For example, the controller 140 may be configured to receive wafer shape data from the metrology module 131. The controller 140 may also be configured to adjust knob and control settings for the metrology module 131. Additionally, it should be understood that one or more of the functions described herein of the controller 140 may be implemented manually. For example, knob adjustments of the metrology module 131 may be performed manually.

[0057] Additionally, the components of the hybrid system 100 may be connected to and controlled by a controller 140. The controller 140 may optionally be connected to a corresponding memory storage unit and a user interface (all not shown). Various module operations may be performed via the user interface, and various process recipes and operations may be stored in the storage unit. Thus, a given substrate may be processed in the hybrid system 100 using a variety of micro-fabrication techniques.

[0058] The controller 140 can be implemented in a wide variety of ways. In one example, the controller 140 is a computer. In another example, the controller 140 includes one or more programmable integrated circuits programmed to provide the functionality described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), etc.), and / or other programmable integrated circuits can be programmed with software or other programming instructions to implement the functionality of a defined plasma process recipe. It is further noted that the software or other programming instructions can be stored on one or more non-transitory computer-readable media (e.g., memory storage devices, FLASH memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and that the software or other programming instructions, when executed by the programmable integrated circuit, cause the programmable integrated circuit to perform the processes, functions, and / or capabilities described herein. Other variations can also be implemented.

[0059] Additionally, bow measurements herein can include measuring the degree of convexity or concavity, or mapping z-height deviations on a substrate relative to one or more reference z-height values. In other words, the z-height deviations are spatially mapped, such as with coordinate positions, to identify the z-height deviations across the surface of the substrate. The bow and z-height deviations can be mapped with a variety of resolutions depending on the type of metrology equipment used and / or the desired resolution.

[0060] The bow measurements may include raw bow data and may also be expressed as a bow signature having a relative value. Note that in many embodiments, the reference z-height values ​​may all be close to zero and thus represent a wafer that is close to flat. For example, a wafer that is close to flat, or considered flat for purposes of overlay improvement herein, may be a wafer that has an average deviation of less than 10 microns.

[0061] Furthermore, the hybrid system 100 may include one or more processing modules (e.g., the first set of modules 150) having a substrate holder and substrate processing components configured to modify the internal stress of the substrate at a specific location on the substrate according to an overlay correction pattern, resulting in a bow of the substrate. The substrate with the modified bow has a modified overlay error. The modified overlay error is a reduced overlay error compared to the initial overlay error. The first set of modules 150 may be configured to differentially modify the internal stress in that one or more processing modules are configured to independently modify different locations on the substrate such that at least some of the different locations are modified differently compared to each other. Although a global or uniform / symmetric internal stress correction may be performed, the processing modules herein may be configured to modify stress by coordinate location on the substrate.

[0062] The first set of modules 150 can be configured to increase or reduce internal stress at locations on the substrate, modifying internal stress on either the front working surface or the back side. The first set of modules 150 can be configured to hold the substrate with the front working surface facing up (away from the gravitational force of the Earth) while physically modifying internal stress on the back side of the substrate.

[0063] The first set of modules 150 can be configured to modify the internal stress of the substrate by location-specific addition of material on the backside of the substrate in that a first given location on the substrate may have more material added compared to a second given location. For example, a backside deposition system may use chemical vapor deposition while projecting a light or heat pattern onto the backside. Because chemical vapor deposition may be surface temperature dependent, more or less material may be deposited based on the light or heat pattern projected onto the backside. Thus, differential amounts of material are deposited depending on the coordinate location. Upon completion of such a differential deposition process, the substrate has a modified bow that corrects or reduces overlay error.

[0064] In other embodiments, the first set of modules 150 can be configured to modify the internal stress of the substrate by location-specific removal of material on the backside of the substrate, in that a first given location on the substrate may have more material removed compared to a second given location. This can include selectively removing material from one or more films at given locations, such as by first adding one or more films to the backside of the substrate and then etching the backside using an etch mask. In other embodiments, the processing modules can be configured to modify the internal stress of the substrate by location-specific implantation of particles on the backside of the substrate, in that a first given location on the substrate may have more particles implanted compared to a second given location. For example, an ion implantation tool can implant particles on the working surface or backside to increase or decrease tensile / compressive forces, thereby altering the bow of the substrate. Such selective increase or decrease can depend on the type of surface material being treated and the type of particles being implanted. The processing modules can be configured to modify the internal stress of the substrate by location-specific temperature adjustment of the cured film. A given film being cured can develop stronger or weaker bonds based on the curing temperature. Temperature modulation can be achieved during curing by using heat or light projection, where individual projected pixels can be independently addressed or altered in intensity based on the overlay correction pattern.

[0065] The processing can be performed in one or more modules depending on the type of processing to be performed on the substrate to modify the stress. Thus, multiple modules can be used optionally. Although there are various mechanisms for modifying the stress (e.g., differential deposition, differential hardening, ion implantation, selective etching, etc.), for convenience in describing the embodiments, the present disclosure provides more example embodiments for selective etching.

[0066] An example of a wafer shape correction flow 200A is illustrated in FIG. 2A, where the top and bottom wafers intended for bonding undergo shape metrology to record their distortion signatures. The depicted flow (200A) performs sequential metrology prior to shape control layer application, but data (e.g., bow measurements) can be collected and fed forward at an earlier point in the line. Based on the integration, the target shape correction can be applied to both wafers or only one wafer. Using the metrology data (e.g., bow measurements), computational methods can be employed to generate a pattern to achieve the desired shape manipulation. This pattern can be recorded in the shape control layer to achieve the preferred shape. Once the shape is optimized, the two wafers (i.e., top and bottom wafers) then continue the normal integration flow through the W2W bonding process, resulting in a sample that is easier to handle / chuck by the bonder and results in improved bonding metrics.

[0067] Specifically, in SHAPE 201, wafers, such as process warped wafers, are provided. At least one wafer may have initial overlay errors resulting from one or more micro-fabrication steps performed to create at least a portion of a semiconductor device on a working surface of at least one wafer. For example, transistor gates may be complete or only partially complete.

[0068] Typically, a wafer has a front work surface and a back surface. The front work surface is the surface on which semiconductor devices such as transistors, diodes, gates, interconnects, etc. are fabricated. The back surface is typically opposite the front work surface, and in related examples is the surface that is typically clamped or chucked to a substrate holder. Techniques herein include back surface deposition of films to modify or tune internal stresses and alter wafer bow or primary curvature.

[0069] It should be noted that in this specification, the front working surface and the back side are used to refer to opposing sides of a wafer. In some microfabrication processes, a given wafer may have active devices or power delivery structures formed on both sides. That is, the back side may also be a working surface for forming semiconductor devices thereon. For purposes of explanation, this disclosure uses the back side of a wafer as an example to demonstrate wafer shape control.

[0070] The wafers provided in Shape 201 may include two wafers to be bonded, namely a first wafer and a second wafer. Shape 203 shows an example of a first wafer (the second wafer is omitted here for brevity). Block 210A shows an example of a wafer shape control module (or wafer shape correction module) configured to perform internal stress tuning on one or both of the two wafers. The internal stress tuning is configured to result in a flat wafer or a slight selected curvature that is advantageous for the subsequent patterning and / or bonding process. For example, the selected curvature may include two curvature profiles that may cancel each other out when the two wafers are bonded. The two curvature profiles may be inverse or symmetrical to each other. The selected curvature may also include two curvature profiles that are similar or identical to each other so that alignment / overlay errors can be cancelled out.

[0071] In SHAPE 211, wafer metrology is performed on the two wafers to obtain wafer shape data of the two wafers, such as bow measurements including relative z-height values. The wafer metrology can be implemented, for example, by the metrology module 131 or an external metrology tool. The control unit 212 can be configured to generate a first correction map based on the wafer shape data of the first wafer and the second wafer. The first correction map is configured to specify an adjustment of the internal stress of the first wafer. The control unit 212 can be implemented by the controller 140. In some embodiments, the control unit 212 can be configured to receive and / or store historical data, such as wafer shape data and / or other overlay information of historical wafers that have undergone shape correction and bonding. The historical data can be used alone or in conjunction with the wafer shape data of the first wafer and the second wafer to generate the first correction map.

[0072] In SHAPE 213, a stressor film, which may include a shape control layer, is applied or deposited on at least one of the two wafers. The stressor film may be deposited by a stressor film deposition module (i.e., deposition module 132 and / or coating module 133) or an outside film deposition tool. For example, a first stressor film may be deposited on the backside of the first wafer. The first stressor film may be deposited based on a first modification map. That is, the first modification map may include information about the first stressor film, such as material type, thickness, etc.

[0073] In shape 215, site-specific activation is performed, for example, by at least one module selected from the group consisting of bake module 134, image processing module 135, development module 136, and etching module 137. As a result, shape 205 shows an example of a first wafer after shape control or correction (the second wafer is omitted here for brevity). Shape 205 may have reduced bow or reduced overlay error compared to shape 203.

[0074] In some embodiments, the first stressor film is modified by exposing the first stressor film to a pattern of electromagnetic radiation based on the first modification map. Such exposure can be implemented by image processing module 135. The first stressor film can undergo crosslinking / decrosslinking to induce internal stress tuning by exposure. Optionally, the first stressor film is baked, for example in bake module 134. Such baking can further promote crosslinking / decrosslinking. Optionally, the photoresist layer of the first stressor film can be developed, for example in develop module 136, to form a relief pattern. Optionally, the shape control layer of the first stressor film can be etched, for example in etch module 137, using the relief pattern as an etch mask. In some embodiments, the first stressor film is modified by thermal treatment based on the first modification map. Optionally, the first stressor film can be subsequently developed and / or etched. In some embodiments, a relatively uniform blanket film (e.g., a spin-on material) can be deposited and selectively activated via UV and / or thermal treatment without the need for removal of the film.

[0075] It should be noted that since the first correction map is based on the wafer shape data of the two wafers, the first correction map may be specific to the two wafers. In other words, the first correction map may vary in the W2W flow. Thus, the image processing module 135 may include a programmable direct write exposure apparatus. As a result, the direct write exposure apparatus may be configured to expose the first stressor film to a pattern of electromagnetic radiation based on the (varying) first correction map. Further details regarding direct writing may be found in the applicant's pending U.S. patent application Ser. No. 17 / 703,072, filed Mar. 24, 2022, which is incorporated herein by reference in its entirety.

[0076] Furthermore, the first stressor film can be any combination of films such as oxide, nitride and / or spin-on films present on the front and / or back of the first wafer. The activation process can be the result of any combination of implantation, etching, radiation and / or temperature. An example of one such embodiment is depicted in Figures 3A-3F. In this embodiment, a CVD (Chemical Vapor Deposition) SiN film is used as the shape control layer of the first stressor film. The activation process includes applying a photosensitive layer, selectively exposing the resist (i.e., the photosensitive layer) with a matching wavelength, opening the exposed areas with a solvent development, and selectively removing the SiN with either a wet process or a RIE (Reactive Ion Etching) process to obtain the desired wafer shape. It should be noted that in some cases, activation may not be required at all and the desired performance may be achieved by using a native blanket control layer. For example, in Figures 3A-3F, the flow may end after the SiN (stress control) layer is deposited. In this case, the first correction map does not contain a pattern, so a layer of SiN is deposited and used as a blanket film.

[0077] Specifically, in FIG. 3A, a shape control layer 303 of the first stressor film is deposited on the backside of the first wafer 301. In this example, the shape control layer 303 is a SiN layer formed, for example, by CVD in the deposition module 132. In FIG. 3B, a photoresist layer 305 of the first stressor film is formed on the shape control layer 303, for example, by spin-on deposition in the coating module 133. In FIG. 3C, the photoresist layer 305 is exposed to a pattern of electromagnetic radiation based on a first correction map, for example, in the image processing module 135. In FIG. 3D, the photoresist layer 305 is developed, for example, in the development module 136, to form a relief pattern. In FIG. 3E, the shape control layer 303 is etched, for example, in the etching module 137, using the relief pattern as an etching mask. In FIG. 3F, the photoresist layer 305 is removed, for example, by an etching process in the etching module 137 and optionally a cleaning process in the cleaning module 138. Although not shown, the photoresist layer 305 can optionally be baked between Figures 3B and 3C and / or between Figures 3C and 3D, for example in bake module 134. Additionally, the photoresist layer 305 can be formed based on the first modification map.

[0078] As shown in Figures 3A-3F, the image processing module 135 may selectively activate the first stressor film via electromagnetic radiation, similar to conventional lithography practices in the industry. Alternatively, such patterning may be performed by locally heating the wafer with a hotplate (or thermal plate) with zoned temperature control, or a thermal array as illustrated in Figures 4A-4C. In some embodiments, wafer shape modification / correction may include using both electromagnetic radiation and heat as activation means.

[0079] 4A illustrates a plan view of a thermal array 400A according to one embodiment of the present disclosure. As illustrated, the thermal array 400A can include individual components, such as those shown at 410a', 410b', 410c', 410p', 410q', and 410r'. The individual components can be configured to generate heat independently of one another, thus allowing for thermal zones with independent temperature control. The size, location, and temperature of each thermal zone is determined by the respective individual component.

[0080] In some embodiments, the thermal array 400A includes an array of resistors. Each resistor can be configured to generate a respective amount of heat based on a respective current flowing through it. At least one resistor can be incorporated into a wafer chuck configured to hold a wafer, such as the first wafer. As a result, the at least one resistor can be in direct contact with the wafer. Alternatively, the at least one resistor can be placed in close proximity to the wafer such that the at least one resistor can efficiently heat the wafer without touching the wafer. For example, the distance between the at least one resistor and the wafer can be between 0 mm (in contact) and 5 mm. Of course, the thermal array 400A can include a combination of both types of resistors. Furthermore, multiple thermal arrays 400A can be implemented. For example, a lower thermal array can be implemented for a lower wafer chuck and an upper thermal array can be implemented for an upper wafer chuck. The lower thermal array and the upper thermal array can each have a configurable height position relative to the respective wafer chuck.

[0081] FIG. 4B illustrates a first pattern 400B of thermal zones generated by the thermal array 400A according to one embodiment of the present disclosure. Here, darker colors mean higher temperatures, while lighter colors mean lower temperatures. For example, zone 410a has a higher temperature than zone 410b, which has a higher temperature than zone 410c. A varied temperature distribution can be used to induce different degrees of internal stress modulation in the stressor film and thus the wafer. In particular, the first pattern 400B of thermal zones includes a line pattern 420, whose zones have the same temperature as each other. Zone 410c can represent a background temperature, for example, where no heat is being generated. The resistors of the thermal array 400A can locally heat the wafer, thus selectively activating the stressor film in a location-specific manner.

[0082] 4C shows a second pattern 400C of thermal zones generated by thermal array 400A according to another embodiment of the present disclosure. Similarly, darker colors represent higher temperatures, while lighter colors represent lower temperatures. For example, zone 410p is hotter than zone 410q, which is hotter than zone 410r.

[0083] It should be noted that zones 410a, 410b, 410c, 410p, 410q, and 410r correspond to individual components 410a', 410b', 410c', 410p', 410q', and 410r', respectively. In this example, the thermal array 400A is generally shaped like a circular wafer, although the thermal array 400A may have other shapes. The individual components of the thermal array 400A may also have any shape. The individual components may each include multiple resistors. Thus, the size of the individual components need not be on the same order as the patterning resolution. For example, the individual components 410a' may be on the order of 33 mm by 26 mm, while the individual components 410a' may include smaller resistors, such as microresistors and / or nanoresistors.

[0084] In addition, the thermal array 400A can be included in the hybrid system 100 as a separate heating module (not shown), by the bake module 134, or by the deposition module 132. When the thermal array 400A is included by the deposition module 132, the deposition module 132 can enable patterning during deposition to form a patterned film as deposited. Modifications to such patterned films may not be necessary after film formation and before future wafer alignment. For example, CVD is temperature dependent. Independent deposition rate control of the first stressor film can be achieved by the thermal zones of the thermal array 400A.

[0085] Although not shown, a laser system can also be used to directly heat the wafer chuck and / or wafer. Wavelengths can be selected that are absorbent in the wafer chuck and / or wafer to cause heating.

[0086] Referring back to FIG. 2A, a first wafer is used as an example to explain the wafer shape correction flow 200A, while a second wafer is omitted for brevity. In one embodiment, the second wafer is characterized by wafer metrology of shape 211, but does not undergo the process shown in shapes 213 and 215. That is, the internal stress adjustment is performed only for the first wafer. In another embodiment, the second wafer is characterized by wafer metrology of shape 211, and undergoes the process shown in shapes 213 and 215. A detailed description is provided above and is omitted here for brevity. In brief, the internal stress adjustment is performed for both the first wafer and the second wafer. A second stressor film is formed on the second wafer, and the internal stress of the second wafer can be adjusted based on a second correction map that specifies the adjustment. The second correction map can be generated based on the wafer shape data of the first wafer and the second wafer.

[0087] The hardware to perform the processing required to achieve the wafer shape control detailed in this disclosure requires modules not present in commercially available semiconductor wafer-to-wafer bonding tools. The use of the wafer shape correction methods disclosed herein to optimize the wafer bonding process requires offline wafer shape correction before reaching the bonder tool. This is undesirable as inserting another tool into the integrated flow would have a significant impact on manufacturing throughput and induce redundancies in wafer handling. The embodiments disclosed herein maintain the core functionality of a bonding tool (e.g., plasma activation, hydrophilization, alignment, bonding, etc.) but also include patterning modules that enable wafer shape control such as, but not limited to, bow metrology, coating, exposure and development, or other stress activation processes. By creating a hybrid bonding-patterning tool, the yield improvements gained through wafer shape control can be realized without the throughput degradation induced from offline processing.

[0088] An example embodiment and configuration is depicted in FIG. 2B. The embodiment includes an integrated platform or stand-alone tool for wafer-to-wafer bonding that modifies the wafer shape of at least one wafer of a pair of wafers to be bonded. Such a system includes a wafer shape modification module (e.g., first set of modules 150) and a bonding module (e.g., second set of modules 160). An example system (e.g., hybrid system 100) can also include a conventional wafer handling robot for moving wafers between modules and sub-modules.

[0089] Thus, example embodiments include a semiconductor tool that maintains the core functionality of a conventional W2W bonding platform, and further integrates patterning modules (e.g., coating, exposing, developing, etc.) into the bonder to facilitate wafer topography manipulation. Exposure, image processing, or activation modules may include electromagnetic radiation and / or site-specific thermal expansion. The semiconductor tool can access both the front and back sides of the wafer for processing. The semiconductor tool may include integrated metrology to evaluate incoming wafer topography. The semiconductor tool may include integrated metrology to evaluate post-bonding alignment metrics.

[0090] In a preferred embodiment, the stress control (or wafer shape control) is deposited in-tool, but the semiconductor tool can accept wafers with externally applied films on different platforms. Preferably, spin-on stress control films (spin-on stressor films) are used for wafer shape modification. CVD film deposition is an alternative film deposition technique that includes patterning of such films.

[0091] As shown in FIG. 2B, process 200B includes block 210B configured for wafer shape control / correction and block 220 configured for wafer alignment and bonding. Identical components in FIG. 2A and FIG. 2B are labeled with identical numbers, e.g., 201, 203, 205, 211, 212, and 213. Block 210B may include an example of block 201A. Specifically, the location-specific activation of shape 215 is now achieved by a corrective image exposure of shape 217 and a corrective image development of shape 219. Such a corrective image may be, for example, a first correction map. Similarly, internal stress adjustments may be made to the first wafer but not to the second wafer. Alternatively, internal stress adjustments may be made to both the first and second wafers.

[0092] In block 220, the first and second wafers can be (pre-)bonded. In shape 211, a plasma activation process is performed on the first and second wafers, for example by the surface treatment module 161. In shape 223, deionized water (DIW) is used to rinse the first and second wafers, for example by the surface treatment module 161. In shape 225, the first and second wafers are aligned, for example by the alignment module 162, and (pre-)bonded, for example by the (pre-)bonding module 163. In shape 227, the (pre-)bonded wafers are inspected, for example using IR light transmission imaging by the second inspection module 164. In shape 207, the (pre-)bonded wafers can be stripped and cleaned, for example by the cleaning module 138 and / or the surface treatment module 161. The (pre-)bonded wafers can be further bonded, for example by the annealing module 165. It should be understood that the first wafer and the second wafer may alternatively be bonded by other processes or techniques, as previously described, in the second set of modules 160. Block 220 may include shape 207 in some embodiments.

[0093] FIG. 5 shows a flowchart of a process 500 for wafer bonding according to some embodiments of the present disclosure. The process 500 starts at step S510, where a first correction map is generated based on wafer shape data of a first wafer and a second wafer. The first correction map specifies an adjustment of the internal stress of the first wafer. The process 500 then proceeds to step S520 by correcting the first wafer shape of the first wafer by forming a first stressor film on the first wafer based on the first correction map. In step S530, after step S520, the first wafer is aligned with the second wafer. In step S540, the first wafer is bonded to the second wafer.

[0094] In the above description, specific details have been described, such as the specific geometry of the processing system and a description of the various components and processes used. However, it should be understood that the technology described herein may be practiced in other embodiments that differ from these specific details, and such details are for the purpose of explanation, not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numerical values, materials, and configurations have been described to provide a sufficient understanding. However, the embodiments may be practiced without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and redundant descriptions may be omitted.

[0095] To facilitate understanding of various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed as though the operations are necessarily order dependent. In fact, the operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0096] As used herein, "substrate" or "wafer" refers generally to an object to be processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but rather is intended to include any such layer or base structure and any combination of layers and / or base structures. Although the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0097] The substrate may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0098] Those skilled in the art will also appreciate that many variations may be made in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Thus, the above description of several embodiments of the present invention is not intended to be limiting. Rather, limitations to the embodiments of the present invention are presented in the following claims.

Claims

1. 1. A device for bonding wafers, said device comprising: a first set of modules configured for wafer shape correction, the first set of modules comprising: a metrology module configured to measure wafer shape data of a first wafer and a second wafer, the first wafer having a front work surface and a back surface opposite the front work surface; a stressor film deposition module configured to form a first stressor film on the backside of the first wafer; a stressor film modification module configured to modify the first stressor film based on a first modification map that defines an adjustment of an internal stress of the first wafer, the first modification map being generated based on the wafer shape data of the first wafer and the second wafer; a first set of modules comprising: a second set of modules configured for bonding the first wafer and the second wafer, the second set of modules comprising: an alignment module configured to align the first wafer with the second wafer; a bonding module configured to bond the front working surface of the first wafer to the second wafer; a second set of modules comprising: Equipped with the stressor film deposition module is configured to form the first stressor film on the backside of the first wafer based on the first modification map; The stressor film modification module comprises a thermal array having thermal zones with independent temperature control, each of the thermal zones comprising a microresistor or nanoresistor, each of the microresistors or nanoresistors configured to generate a respective amount of heat based on a respective current flowing through it.

2. The device of claim 1 , wherein the stressor film deposition module comprises at least one of a spin coating apparatus, a spray coating apparatus, or an evaporation apparatus.

3. 10. The device of claim 1, wherein the stressor film modification module comprises a direct write exposure tool configured to expose the first stressor film to a pattern of electromagnetic radiation based on the first modification map.

4. The device of claim 3 , wherein the stressor film modification module comprises a developer configured to develop a photoresist layer of the first stressor film to form a relief pattern.

5. 5. The device of claim 4, wherein the stressor film modification module comprises an etcher configured to etch a shape-controlling layer of the first stressor film using the relief pattern as an etch mask.

6. The device of claim 1 , wherein the stressor membrane modification module comprises a hotplate with zoned temperature control.

7. The device described in claim 1, wherein at least one of the microresistors or nanoresistors is incorporated into a wafer chuck configured to hold the first wafer.

8. 10. The device of claim 1, wherein the stressor film modification module comprises a laser system configured to heat at least one of the first wafer or a wafer chuck configured to hold the first wafer.

9. The device of claim 1 , further comprising: a controller configured to generate the first correction map based on the wafer shape data of the first wafer and the second wafer.

10. 10. The device of claim 9, wherein the controller is configured to receive input from and provide output to at least one module selected from the group consisting of the metrology module, the stressor film deposition module, the stressor film modification module, the alignment module, and the bonding module.

11. 11. The device of claim 10, wherein the controller is configured to control at least one process selected from the group consisting of measuring the wafer shape data, depositing the first stressor film, modifying the first stressor film, aligning the first wafer and the second wafer, and bonding the first wafer and the second wafer.

12. 10. The device of claim 9, wherein the controller is configured to generate the first correction map based on historical data in addition to the wafer shape data of the first wafer and the second wafer, the historical data including overlay information of historical wafers.

13. the stressor film deposition module is configured to form a second stressor film on the second wafer; 2. The device of claim 1, wherein the stressor film modification module is configured to modify the second stressor film based on a second modification map that defines an adjustment of an internal stress of the second wafer, the second modification map being generated based on the wafer shape data of the first wafer and the second wafer.

14. The device of claim 1 , wherein the alignment module and the bonding module are one integrated module such that there is no wafer transfer between the alignment and the bonding.

15. 1. A device for bonding wafers, said device comprising: a first set of modules configured for wafer shape correction, the first set of modules comprising: a metrology module configured to measure wafer shape data of a first wafer and a second wafer, the first wafer having a front work surface and a back surface opposite the front work surface; a stressor film deposition module configured to form a first stressor film on the backside of the first wafer based on a first correction map that specifies an adjustment of an internal stress of the first wafer, the first correction map being generated based on the wafer shape data of the first wafer and the second wafer; a first set of modules comprising: a second set of modules configured for aligning and bonding the first wafer and the second wafer, the second set of modules comprising: an alignment module configured to align the first wafer with the second wafer without modification of the first stressor film between the forming and aligning; a bonding module configured to bond the front working surface of the first wafer to the second wafer; a second set of modules comprising: Equipped with the stressor film deposition module is configured to form the first stressor film on the backside of the first wafer based on the first modification map; The stressor film modification module comprises a thermal array having thermal zones with independent temperature control, each of the thermal zones comprising a microresistor or nanoresistor, each of the microresistors or nanoresistors configured to generate a respective amount of heat based on a respective current flowing through it.

16. the first correction map does not include a pattern; The device of claim 15 , wherein the stressor film deposition module is configured to form the first stressor film as a blanket film.

17. The device described in claim 1, further comprising an inspection module configured to inspect the first wafer and the second wafer bonded to each other.

18. The device described in claim 17, wherein the inspection module is configured to inspect the first wafer and the second wafer bonded to each other by infrared light transmission imaging.

19. A method for bonding a first wafer to a second wafer, comprising: The method comprises: generating a first correction map that defines an adjustment of internal stress of the first wafer based on wafer shape data of the first wafer and the second wafer; modifying a first wafer shape of the first wafer by forming a first stressor film on the first wafer based on the first modification map; aligning the first wafer with the second wafer after the modification; and bonding the first wafer to the second wafer.

20. The method described in claim 19, wherein modifying the first wafer shape of the first wafer further includes modifying the first stressor film based on the first modification map.

21. The method described in claim 20, wherein modifying the first stressor film includes exposing the first stressor film to a pattern of electromagnetic radiation based on the first modification map.

22. The method of claim 21, further comprising developing the photoresist layer of the first stressor film to form a relief pattern.

23. The method of claim 22, further comprising etching a shape control layer of the first stressor film using the relief pattern as an etching mask.

24. The method of claim 21, wherein the first stressor film is exposed to the pattern of electromagnetic radiation by direct writing.

25. The method of claim 20, wherein modifying the first stressor film includes applying heat to the first stressor film.

26. The method described in claim 25, wherein the heat is applied to the first stressor film using a thermal array having thermal zones with independent temperature control.

27. ​​The method of claim 26, further comprising passing a respective current through each resistor of the thermal array, causing each resistor to generate a respective amount of heat.

28. The method of claim 25, wherein the heat is applied to the first stressor film using a laser system configured to heat at least one of the first wafer or a wafer chuck configured to hold the first wafer.

29. The method of claim 20, wherein modifying the first stressor film includes implanting ions into the first stressor film.

30. The method of claim 19, further comprising maintaining the first stressor film unmodified between forming the first stressor film and aligning the first wafer with the second wafer.

31. The method of claim 30, wherein forming the first stressor film includes forming the first stressor film as a blanket film.

32. The first wafer has a front work surface and a back surface opposite the front work surface, 20. The method of claim 19, wherein the first stressor film is formed on a backside of the first wafer.

33. Generating a second correction map that specifies an adjustment of internal stress of the second wafer based on the wafer shape data of the first wafer and the second wafer; 20. The method of claim 19, further comprising: modifying a second wafer topography of the second wafer by forming a second stressor film on the second wafer based on the second modification map.

34. The method described in claim 33, wherein modifying the second wafer shape of the second wafer further includes modifying the second stressor film based on the second modification map.

35. The method of claim 19, further comprising measuring the wafer shape data of the first wafer and the second wafer using one or more metrology tools.

36. The method described in claim 35, wherein measuring the wafer shape data includes measuring relative z-height values ​​of the first wafer and the second wafer by warp measurement.

37. The method described in claim 19, wherein the first correction map is generated based on historical data in addition to the wafer shape data of the first wafer and the second wafer, and the historical data includes overlay information of the historical wafer.

38. A method for bonding a first wafer to a second wafer, said method comprising: receiving wafer shape data for the first wafer and the second wafer from one or more metrology tools; generating a first correction map and a second correction map based on the wafer shape data of the first wafer and the second wafer, the first correction map specifying an adjustment of internal stress of the first wafer, and the second correction map specifying an adjustment of internal stress of the second wafer; modifying a first wafer shape of the first wafer by forming a first stressor film on the first wafer based on the first modification map; modifying a second wafer shape of the second wafer by forming a second stressor film on the second wafer based on the second modification map; aligning the first wafer with the second wafer after modifying the first wafer shape and after modifying the second wafer shape; and bonding the first wafer to the second wafer.

Images