Power Factor Correction System

Abstract

In some examples, the apparatus includes a lamp generating circuit (1002) having a lamp control input (1003b) and a lamp output (1003e), the lamp control input being coupled to a power factor correction (PFC) output terminal, a comparator (630) having a comparator output and first and second comparator inputs, the first comparator input being coupled to the lamp output and the second comparator input being coupled to the PFC switch current sense terminal, and a pulse width modulation (PWM) generating circuit (634) having a PWM control input and a PWM output, the PWM control input being coupled to the comparator output and the PWM output being coupled to the PFC switch control terminal.

Description

[Technical field]

[0001] A power supply system may transfer power from an alternating current (AC) source to a load. The power supply system may rectify the AC voltage to generate a direct current (DC) voltage. The power supply system may also include a power converter, such as a switch mode power converter, to regulate the DC voltage to a target DC voltage and provide the regulated DC voltage to the load. The power supply system may use various techniques to improve power transfer, such as reducing the phase delay between the AC voltage and the AC current drawn from the AC source and reducing power losses during switching of the power converter. Summary of the Invention

[0002] The apparatus includes a ramp generating circuit, a comparator, and a pulse width modulation (PWM) generating circuit. The ramp generating circuit has a ramp control input and a ramp output, the ramp control input coupled to a power factor correction (PFC) output terminal. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the ramp output and the second comparator input coupled to the PFC switch current sense terminal. The PWM generating circuit has a PWM control input and a PWM output, the PWM control input coupled to the comparator output and the PWM output coupled to the PFC switch control terminal.

[0003] The apparatus includes a power factor correction (PFC) circuit, a current measurement circuit, a voltage measurement circuit, and a controller. The PFC circuit has a PFC input and a PFC output, the PFC circuit including an inductor, a switch, and a diode, the inductor coupled between the PFC input and a current terminal of the switch, and the diode coupled between the current terminal and the PFC output. The current measurement circuit is magnetically coupled to the current terminal and has a current measurement output. The voltage measurement circuit is coupled to the PFC output and has a voltage measurement output. The controller has a first control input, a second control input, and a control output, the first control input coupled to the current measurement output, the second control input coupled to the voltage measurement output, and the control output coupled to a control terminal of the switch. The controller also includes a ramp generation circuit, a comparator, and a PWM generation circuit. The ramp generation circuit has a ramp control input coupled to the second control input and a ramp output. The comparator has a comparator output and first and second comparator inputs, the first comparator input coupled to the ramp output and the second comparator input coupled to the first control input. The PWM generator circuit has a PWM control input and a PWM output, the PWM control input coupled to the comparator output and the PWM output coupled to the control output.

[0004] The method includes receiving a first voltage from an output of a power factor correction (PFC) circuit, determining a first ramp voltage for a ramp signal based on the first voltage, and generating a ramp signal that decreases from the first ramp voltage to a second ramp voltage. The method also includes providing a pulse width modulated (PWM) signal having a first state to a control terminal of a switch of the PFC circuit. The method also includes receiving a second voltage representative of a current through the switch of the PFC circuit when the PWM signal is in the first state, and comparing the second voltage to the ramp signal to generate a decision. The method also includes switching the PWM signal from the first state to a second state to disable the switch in response to a decision indicating that the second voltage crosses the ramp signal. [Brief description of the drawings]

[0005] [Figure 1]1 is a schematic diagram of an example power transfer system.

[0006] [Diagram 2] 2 is a waveform diagram showing an example of an input voltage and an input current of the power transmission system of FIG. 1.

[0007] [Diagram 3] FIG. 2 is a schematic diagram of an example power supply system including a power factor correction (PFC) circuit that may be part of the power transmission system of FIG.

[0008] [Figure 4] 4 includes waveform diagrams illustrating an example PFC operation of the power supply system of FIG. 3. [Diagram 5] 4 includes waveform diagrams illustrating an example PFC operation of the power supply system of FIG. 3.

[0009] [Figure 6] FIG. 4 is a schematic diagram of example internal components of a controller of the PFC circuit of FIG.

[0010] [Figure 7] 7 includes waveforms illustrating an example PFC operation supported by the example controller of FIG. 6.

[0011] [Figure 8] FIG. 2 is a schematic diagram of an example power supply system including a PFC circuit that may be part of the power transfer system of FIG.

[0012] [Figure 9] 9 includes waveform diagrams illustrating an example PFC operation supported by the PFC circuit of FIG. 8.

[0013] [Figure 10] FIG. 9 is a schematic diagram of example internal components of a controller of the PFC circuit of FIG. [Figure 11] FIG. 9 is a schematic diagram of example internal components of a controller of the PFC circuit of FIG.

[0014] [Figure 12] FIG. 2 is a schematic diagram of an example power supply system including a PFC circuit that may be part of the power transfer system of FIG.

[0015] [Figure 13] 13 includes waveform diagrams illustrating an example operation of the PFC circuit of FIG. 12.

[0016] [Figure 14] FIG. 13 is a schematic diagram of example internal components of a controller of the PFC circuit of FIG.

[0017] [Figure 15] 1 is a flowchart of an example method of controlling a PFC circuit in accordance with various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] 1 is a schematic diagram of an example power transfer system 100. The system 100 may include an AC power source 102, a power supply system 104, and a load 106. The power supply system 104 may include a positive input 105a, a negative input 105b, a positive output 107a, and a negative output 107b. The AC power source 102 provides an AC input voltage signal 108 (V in The AC input voltage signal 108 may provide a positive half-cycle when the voltage signal is positive (e.g., between T0 and T1 and between T2 and T3) and a negative half-cycle when the voltage signal is negative (e.g., between T1 and T2). During the positive half-cycle, the positive input 105a may receive a higher voltage than the negative input 105b, and during the negative half-cycle, the polarity is reversed and the positive input 105a may receive a lower voltage than the negative input 105b. The AC input current signal 110 (I in A current signal (denoted as (t)) may also flow into the positive input 105a and return to the AC power source 102 from the negative input 105b during a positive half-cycle of the AC input voltage signal 108. The AC input current signal may also flow into the negative input 105b and return to the AC power source 102 from the positive input 105a during a negative half-cycle of the AC input voltage signal 108.

[0019] From an AC input voltage signal 108, the power supply system 104 produces a DC output voltage signal 112 (V out The positive output 107a may provide a positive power rail and the negative output 107b may provide a negative power rail. The power supply system 104 may provide a DC output voltage signal 112 to a load 106, which may include electrical components that operate on a DC voltage. The power supply system 104 also generates a DC output current signal 114 (I out System 100 may provide a DC output voltage signal 112 and a DC output current signal 114, which may be a capacitor current signal 117 (denoted as I(t)) flowing through capacitor 118. System 100 may include a capacitor 118 that performs a filtering operation to reduce ripple in DC output voltage signal 112 and DC output current signal 114. DC output current signal 114 may be a capacitor current signal 117 (denoted as I(t)) flowing through capacitor 118. C (t)) and a load current signal 119 (I load (t)) The DC output current signal 114, the capacitor current signal 117, and the load current signal 119 may be related by the following equation: I out (t)=I C (t)+I load (t) (Equation 1)

[0020] To generate the DC output voltage signal 112 from the AC input voltage signal 108, the power supply system 104 may include a rectifier circuit 120 and a power converter circuit 122. The rectifier circuit 120 may perform a rectification operation to convert the AC input voltage signal 108 to a DC input voltage signal 130. As part of the rectification operation, the rectifier circuit 120 may pass the positive voltage of the AC input voltage signal 108 as the DC input voltage signal 130 during the positive half cycle. The rectifier circuit 120 may also block the negative voltage of the AC input voltage signal 108 during the negative half cycle in a half-wave rectification operation, or convert the negative voltage to a positive voltage in a full-wave rectification operation, and generate the pulsating DC input voltage signal 130. The power converter circuit 122 may then generate the DC output voltage signal 112 from the DC input voltage signal 130 based on a conversion ratio. In examples where power converter circuit 122 is a step-up converter (e.g., a boost converter), the conversion ratio may be higher than 1 and the DC output voltage signal 112 may be higher than the DC input voltage signal 130. In examples where power converter circuit 122 is a step-down converter (e.g., a buck converter), the conversion ratio may be lower than 1 and the DC output voltage signal 112 may be lower than the DC input voltage signal 130.

[0021] In addition to generating the DC output voltage signal 112, the power converter circuit 122 may include a power factor correction (PFC) circuit 124 to perform a PFC operation. The PFC circuit 124 may receive a DC input voltage signal 130 and generate a PFC output voltage signal 132, which may then be converted to the DC output voltage signal 112 by the power converter circuit 122. A power factor (PF) may be defined as the ratio of the real power, measured in watts (W), consumed by the load 106 divided by the total apparent power, measured in volt-amperes (VA), circulating between the AC source 102 and the load 106. A high PF (e.g., close to or equal to 1) may indicate that a large proportion of the power supplied by the AC source 102 (apparent power) is delivered to and consumed by the load 106. A PFC operation may be performed to increase the PF up to 1.

[0022] PF is determined by the phase relationship φ between the AC input voltage signal 108 and the AC input current signal 110 and the amount of total harmonic distortion (THD) present in the AC input current signal according to the following equation: TIFF2025514168000002.tif624 (Formula 2)

[0023] 2 illustrates example charts 202, 204, and 206 of the AC input voltage signal 108 and the AC input current signal 110, where the AC input voltage signal 108 includes a sinusoidal signal having a fundamental frequency. In chart 202, the AC input voltage signal 108 and the AC input current signal 110 have a zero phase difference, which may result in a PF of 1. In chart 204, the AC input voltage signal 108 and the AC input current signal 110 have a phase difference of φ, which may result in a PF less than 1. Also, in chart 206, the AC input current signal 110 includes pulses and is not sinusoidal. The AC input current signal 110 may have substantial THD, which may result in a PF less than 1. The THD may reduce the spectral content of the AC input current signal 110 related to the fundamental frequency.

[0024] 2, when the PF is equal to 1, the maximum values ​​of the AC input current signal 110 and the AC input voltage signal 118 may coincide. Thus, the amount of power transferred from the AC source 102 to the load 106 may be increased as compared to examples where the PF is lower than 1, such as the examples of the AC input current signal 110 and the AC input voltage signal 118 shown in charts 204 and 206. A higher PF may also indicate reduced harmonic distortion (e.g., reduced THD) in the AC input current signal 110. Reducing harmonic distortion may also increase the amount of power transferred from the AC source 102 to the load 106 because harmonic distortion may reduce the spectral content of the AC input current signal 110 related to the fundamental frequency of the AC input voltage signal 108.

[0025] 3 is a schematic diagram of an example power supply system 104 including a rectifier circuit 120 and a PFC circuit 124. Referring to FIG. 3, the power supply system 104 may include diodes 302a, 302b, 302c, and 302d coupled between a positive input 105a and a negative input 105b to form a diode bridge 304. The diode bridge 304 may be part of the rectifier circuit 120 and may perform a full-wave rectification operation to generate a pulsating DC input voltage signal 130 from an AC input voltage signal 108. The PFC circuit 124 may also include an inductor 306, a switch 308, and a diode 310 and may be coupled to a controller 312 that controls the switch 308. The inductor 306, the switch 308, and the diode 310 may be coupled at a node 314, and the switch 308 may be coupled between the node 314 and the negative output 107b. The voltage at node 314 may switch between the positive and negative power rails within a switching cycle and may be a switching node. In FIG. 3, the negative output 107b may be coupled to ground. In another example, the negative output 107b may be coupled to a low impedance voltage source to provide a reference voltage and provide a return path for the DC output current signal 114.

[0026] The inductor 306, the switch 308, and the diode 310 may be part of the PFC circuit 124. The switch 308 may control the flow of the AC input current signal 110 through the inductor 306 to store magnetic energy in the inductor. The diode 310 may act as a rectifier. When the switch 308 is disabled, the voltage at the node 314 becomes the output voltage V out When the inductor 306 is higher than the output voltage V out(t), the diode 310 may be reverse biased and may block current flow from the load 106 back to the inductor 306. The inductor 306 may charge and the inductor current may flow through the enabled switch 308. The switch 308 may include a transistor such as a silicon field effect transistor (FET) or a gallium nitride (GaN) high electron mobility transistor (HEMT). In some examples, the power system 104 may include another transistor configured as a synchronous rectifier (SR) switch, the body diode of which may be the diode 310. When the switch 308 is disabled, the transistor may be enabled, and vice versa.

[0027] The controller 312 may generate a control signal 330 for enabling / disabling the switch 308 in each switching cycle. The control signal 330 may be in the form of a multi-cycle pulse width modulated (PWM) signal. Each cycle of the PWM signal may have a pulse where the PWM signal is in a first state to enable the switch 308 and in a second state to disable the switch 308 for the remainder of the cycle. If the switch 308 is an NFET, the first state may be an asserted state (e.g., logic 1) and the second state may be a deasserted state (e.g., logic 0). Also, if the power supply system 104 includes an SR switch, the controller 312 may generate a control signal (not shown) for the SR switch having an opposite state to the control signal 330.

[0028] The controller 312 receives the PFC output voltage signal 132 (V out_pfc (t)) and the DC input voltage signal 130 (V in,dc 3, a measurement signal 350 of the PFC output voltage (V ref3 , the current measurement circuit 372 may include a shunt resistor 374 coupled across a return path of the AC input current signal 110 and may generate a voltage signal reflective of the magnitude of the current signal 110. The current measurement circuit 372 may also include a measurement circuit 376 to generate the measurement signal 370.

[0029] In some examples, the power supply system 104 may also include a current measurement circuit 380 that is magnetically coupled to a current terminal of the switch 308. The current measurement circuit 380 may be part of the PFC circuit 124 or may be external to the PFC circuit 124 and measures a switch current signal 382 (I in FIG. 3 ) flowing through the switch 308. sw (t)) and generate a measurement signal 384 of the switch current signal 382. The current measurement circuit 380 may include a current transformer (CT) sensor that may include a primary coil 386 coupled between the node 314 and a current terminal of the switch 308, a secondary coil 388 magnetically coupled to the primary coil 386, and a measurement circuit 390. When the switch 308 is enabled, the inductor current (and the AC input current signal 110) increases over time and flows through the switch 308 as the switch current signal 382. Through magnetic coupling, a current signal 392 that tracks the switch current signal 382 may be induced in the secondary coil 388. The measurement circuit 390 may include circuitry for measuring the current signal 392 and generate the measurement signal 384. For example, the measurement circuit 390 may include a resistor to convert the current signal to a voltage signal and provide the voltage signal as the measurement signal 384.

[0030] In some examples, the voltage measurement circuits 342 and 352 and the current measurement circuits 372 and 380 may include sample-and-hold (S / H) circuits for generating samples of the voltage signals. In some examples, these circuits may also include analog-to-digital converters (ADCs) for converting the sampled voltage signals to digital values.

[0031] The controller 312 may implement a voltage feedback loop in which the controller 312 receives the measurement signals 340 and 350 and V ref 3. Adjust the control signal 330 based on the PFC output voltage signal 132 and V ref Controller 312 may also implement a current feedback loop in which controller 312 may adjust control signal 330 based on measurement signal 370 or measurement signal 384 to reduce the phase difference between AC input voltage signal 108 and AC input current signal 110, reducing harmonic distortion in AC input current signal 110 and improving the PF.

[0032] 4 includes waveform diagrams illustrating an example operation of the PFC circuit 124 of FIG. 4 includes graphs 402, 404, 406, and 408. Graph 402 illustrates the time variation of the control signal 330 over multiple switching cycles, including switching cycles sw(0), sw(1), and sw(2). Graph 404 illustrates the time variation of the AC input current signal 110 (I in ) over time. Graph 406 also shows the current through diode 310 (I out ) over time, while graph 408 shows the current through capacitor 118 (I C ) is shown.

[0033] The first switching cycle (sw(1)) begins at time T0. At T0, the inductor current and the AC input current are I in_init Depending on the type of PFC operation supported by the controller 312, as described below, the value of Iin_init may be zero or may have a positive value. Between T0 and T1 is a first charging interval, during which the controller 312 may provide a pulse having a first state for the control signal 330. When the switch 308 is enabled, the voltage at the node 314 may be brought close to ground, and the output voltage V out , and diode 310 may be reverse biased and prevent current from flowing from load 106 / capacitor 118 back to switch 308 and ground. Thus, between T0 and T1, diode 310 (I out ) may be zero. Also, the capacitor 118 may be connected to the load current I load to supply the load 106, and thus the capacitor current I C can be negative.

[0034] Also, between T0 and T1, an increasing positive charging current may flow from inductor 306 through switch 308 to ground, charging inductor 306. L The voltage across inductor 306, denoted as V in,dc ) when the inductor 306 has an inductance L, the AC input current signal 110 (I in (t)) which can be equal to the inductor current I L may be increased based on the following formula: TIFF2025514168000003.tif538

[0035] In Equation 3, the DC input voltage signal 130 (V in,dc ) is positive, so the inductor current dI L The slope of / dt is also positive, and the inductor current increases between time T0 and T1. The switch current I sw t on During time T0 to T1, the inductor current may be equal to IL. The positive inductor current may reach a peak at time T1. The duration between times T0 to T1 may be t on, which is equal to the pulse width of the control signal 330 in switching cycle sw(0) and represents the charging interval during which the switch 308 is enabled. Within the switching cycle sw(0), the positive peak inductor current at time T1 (I in,pk (denoted as V) is calculated based on the following formula: in,dc , t on , and I in_init Related to. I in_pk =I in_init +(V in,dc / L)×t on (Formula 4)

[0036] The duration between T1 and T2 may be a portion of the discharge interval, and the controller 312 may terminate the pulse and set the control signal 330 to a second state to disable the switch 308. off Disabling switch 308 may disconnect inductor 306 from ground, causing the voltage at node 314 to equal the output voltage V out The switch current I sw may be zero. Diode 310 may be forward biased. Inductor 306 may dissipate the stored magnetic energy to provide a discharge current to load 106 and capacitor 118, generating a DC output current signal 114 (I out (t)) can be equal to the inductor current and the capacitor current I C (t) and load current I load (t) and the voltage of the switching node 314 is V out_pfc Then, the inductor voltage V L V in,dc -V out_pfc and the rate of change of the inductor current may be: TIFF2025514168000004.tif15126

[0037] V in,dc V out_pfc If lower than V Lcan become negative, discharging the inductor 306 and providing current to the load 106 and the capacitor 118. The inductor current is proportional to the input current I in As in (t), negative dI L A positive peak inductor current (I in,pk Depending on the type of PFC operation, the inductor current may drop to a positive value, zero, or a negative value as the final inductor current of the first switching cycle, which also represents the initial inductor current I for the next switching cycle (e.g., sw(2)). in_init The average inductor current in the first switching cycle sw(1) can be I in,avg and the peak inductor current I in,pk , the initial and final inductor currents of the first switching cycle, and the inductor (t on and t off The inductor current may be based on the duration of charging and discharging I in_init can be achieved.

[0038] The charging and discharging of inductor 306 may then be repeated for subsequent switching cycles, including switching cycle sw(1) between T2 and T4 and switching cycle sw(2) between T4 and T6. In the example of FIG. 4, switching cycles sw(0), sw(1), and sw(2) charge and discharge inductor (t on and t off ) charging and discharging for the same duration, with the same peak inductor current I in,pk , the same average inductor current I in,avg , and the same initial inductor current I in_init may have:

[0039] To implement PFC operation, the controller 312 varies the DC input voltage signal 130 (V in,dc (t)) measurement signal 350 for a switching cycle t on and / or t offis adjusted based on the measurement signal 350 to obtain the peak inductor current I in,pk and the average inductor current I in,avg , and adjusts the THD and AC input current signal 110 (I in ) and AC input voltage signal 108(V in ) and increase the PF. Figure 5 shows the inductor current (I L Graph 502 illustrates continuous conduction mode (CCM) operation, graph 504 illustrates critical conduction mode (CrCM) operation, and graph 506 illustrates discontinuous conduction mode (DCM) operation.

[0040] Referring to graph 502, the initial and final inductor currents of a switching cycle in CCM operation may be non-zero. The controller 312 measures the average inductor current, input voltage, and output voltage of a switching cycle and adjusts the pulse width of the control signal 330 based on the measurements so that the average inductor current may vary over a switching cycle to track the input voltage. Thus, in CCM operation, each switching cycle may have a fixed duration, and the duration of the charging period t on And the duty cycle may vary over the switching cycle.

[0041] Also, referring to graph 504, the initial and final inductor current of a switching cycle in CrCM operation may be zero. The controller 312 measures the output voltage and adjusts the duration of the charging period t so that the output voltage is constant over the switching cycle. on The controller 312 may also measure the inductor current and initiate a new switching cycle and charging period in response to the inductor current dropping to zero. Thus, in CrCM operation, the controller 312 may set the pulse width (and duration of the charging period t on ) may be constant over the cycle. However, the cycle period and t offmay vary over a switching cycle, and the average inductor current may also vary depending on the input voltage.

[0042] Also, referring to graph 506, in DCM operation, the initial and final inductor current of a switching cycle may be zero. on and t off In addition, a switching cycle includes the duration t during which the inductor current is zero. zero The controller 312 measures the output voltage and determines the duration of the charging period t so that the output voltage is constant over the switching cycle. on The controller 312 may also set t on , t off , and t zero If the peak inductor current varies over the switching cycle, the average inductor current may also vary to track the input voltage.

[0043] 6 is a schematic diagram of the controller 312. The controller 312 may implement a voltage feedback loop for adjusting the DC output voltage signal 112 based on a reference DC output voltage signal 360 and a current feedback loop for adjusting the input current signal 110 based on the AC input voltage signal 108 to improve the PF. Referring to FIG. 6, the controller 312 may include a first amplifier 602, a square generator circuit 604, a processing circuit 606, a second amplifier 608, and a PWM generating circuit 610. The first amplifier 602 may be an error amplifier of the voltage feedback loop. The first amplifier 602 outputs the PFC output voltage signal 132 (V out_pfc ) measurement signal 340 and the reference PFC output voltage signal 360 (V ref ), generate a voltage error signal 612 that represents the difference between the DC output voltage (or a scaled version thereof) and the reference voltage, and provide the voltage error signal 612 to the processing circuitry 606. The square generator circuit 604 may also receive the DC input voltage signal 130 (V in,dc) measurement signal 350, generate a squared version of the DC input voltage signal 130 (e.g., the root mean square (rms) of the voltage signal), and provide the squared voltage signal to processing circuit 606. Voltage measurement circuits 342 and 352 may generate their respective measurement signals 340 and 350 by sampling the signal at any time within a switching cycle. Processing circuit 606 may also receive parameter values ​​614. Processing circuit 606 may generate a reference current signal 616 based on the following equation: TIFF2025514168000005.tif18125

[0044] In Equation 6, I ref where ω represents the reference current signal 616, G represents a voltage loop function implemented by the first amplifier 602 to generate a voltage error signal 612 based on the DC output voltage and a reference voltage, and C represents a parameter value 614. The reference current may include information of the voltage error signal 612 based on which the controller 312 may set the DC output voltage as part of a voltage feedback loop. The reference current may also include information of the DC input voltage signal 130 based on which the controller 312 may set the AC input current as part of a current feedback loop.

[0045] In some examples, the processing circuit 606 receives the parameter values ​​614, a squared version of the DC input voltage signal 130, and a voltage error signal 612 in the form of a digital value, and calculates I ref The processing circuit 606 may calculate a digital value of I ref 6. In some examples, the processing circuit 606 also receives the parameter value 614, a squared version of the DC input voltage signal 130, and a voltage error signal 612 in the form of an analog voltage signal, and derives I from the received signals. ref A separate analog voltage signal representing

[0046] The second amplifier 608 may be an error amplifier in a current feedback loop. The second amplifier 608 receives a reference current signal 616 from the processing circuit 606 and a switching cycle (I in_avg ) of the switching cycle. Current measurement circuit 372 may generate measurement signal 370 by sampling AC input current signal 110 at any time within a switching cycle. Also, current measurement circuit 380 may receive measurement signal 370 or 384 that represents an average of AC input current signal 110 during the charging period (t on ) at the midpoint of the switch current signal 382 (I sw ) to measure the average inductor current within a switching cycle and generate a measurement signal 384. The second amplifier 608 may generate a current error signal 620 representing the difference between the average AC input current and a reference current and provide the current error signal 620 to the PWM generation circuit 610.

[0047] The PWM generator circuit 610 generates the control signal 330 to determine the charging period duration (t on ) may be set. The PWM generating circuit 610 may include a comparator 630, a reference signal generator 632, and a timing logic circuit 634. The reference signal generator 632 may generate a periodic ramp reference signal 640, and the period of the reference signal 640 may define the cycle period of the switching cycle and the control signal 330. The comparator 630 may compare the current error signal 620 with the reference signal 640 to generate a decision signal 642. The timing logic circuit 634, which may include an SR latch, may generate the control signal 330 as a PWM signal and modulate the pulse width of the PWM signal based on the state of the decision signal 642. The controller 600 may include a gate driver circuit (not shown in FIG. 6) for generating a drive signal for the switch 308 in response to the control signal 330.

[0048] FIG. 7 includes waveform diagrams illustrating an example PFC operation of the PFC circuit 124 under the control of the controller 312 of FIG. 6. FIG. 7 includes graphs 702, 704, 706, 708, 710, and 712. Graph 702 illustrates the time variation of the DC input voltage signal 130, which may be a sinusoidal signal in FIG. 7. Graph 704 illustrates the time variation of the AC input current signal 110, which may also represent the inductor current of the inductor 306. Graph 706 illustrates the time variation of the average inductor current of each of the switching cycles sw(0)-sw(7). Graph 708 also illustrates the time variation of the periodic ramp reference signal 640, and graph 710 illustrates the time variation of the current error signal 620. Graph 712 also illustrates the time variation of the control signal 330. The example PFC operation illustrated in FIG. 7 may be a CCM operation.

[0049] Referring to graphs 708 and 710, at the beginning of switching cycle sw(0), the reference signal 640 is at the low voltage V low At the end of sw(0), a high voltage V high The reference signal 640 then follows a repeating ramp pattern to fall to V low At the end of sw(1), it goes back to V high 6. Also, at the beginning of each switching cycle, the reference signal 640 may be lower than the current error signal 620, and the comparator 630 may generate an asserted decision signal 642 to set the SR latch of the timing logic circuit 634. In response to the SR latch being set, the timing logic circuit 634 may generate an asserted control signal 330 to initiate the pulse. When the reference signal 640 exceeds the current error signal 620, the comparator 630 may trip and generate a de-asserted decision signal 642, thereby releasing the set signal of the SR latch. The reference signal 640 may also reset the SR latch. In response to the SR latch being reset, the timing logic circuit 634 may generate a de-asserted control signal 330 to stop the pulse and terminate the duration of the charging period t on The control signal 330 may terminate the discharge period duration toff may remain deasserted for the remainder of the switching cycle corresponding to

[0050] Duration of the charging period t on and the duration of the discharge period t off may reflect the magnitude of the current error signal 620. Specifically, for a high current error signal 620, it may take longer for the reference signal 640 to cross and exceed the current error signal 620. Thus, as the current error signal 620 increases, t on increases, and t off may decrease. Also, for a low current error signal 620, it may take less time for the reference signal 640 to cross and exceed the current error signal 620. Thus, as the current error signal 620 decreases, t on decreases, and t off may increase.

[0051] In each switching cycle, the controller 312 generates the PFC output voltage signal 132 (V out_pfc ) measurement signal 340, DC input voltage signal 130 (V in,dc ), a measurement signal 370 of the AC input current signal 110, and a reference PFC output voltage signal 360 (V ref ) for each switching cycle and generate a current error signal 620 for that switching cycle. on A measurement signal 370 may be received that is sampled at the midpoint of the switching cycle t on The inductor current sampled at the midpoint of t may be close to the average inductor current of the switching cycle. s (0), t s (1), t s (2) T s (3) T s (4) T s (5) T s (6), and s (7), which are respectively the ton (0), t of switching cycle sw(1) on (1), t of switching cycle sw(2) on (2), t of switching cycle sw(3) on (3), t of switching cycle sw(4) on (4), t of switching cycle sw(5) on (5), t of switching cycle sw(6) on (6), and t of the switching cycle sw(7) on (7). In some examples, the controller 312 may be configured to calculate the t on Based on the t of the current switching cycle (which is yet to be determined), on For example, the controller 312 may estimate the midpoint of t on When these are almost equal, t on Based on the switching cycle sw(1), on The midpoint of may be determined.

[0052] The controller 312 then determines the t on and determining a current error signal 620 for the switching cycle based on a measurement signal sampled at a midpoint of the switching cycle and determining a current error signal 620 for the switching cycle based on comparing the current error signal 620 to a reference signal 640 for the switching cycle. on With such an arrangement, the controller 312 can determine the average inductor current (I in_avg ) for that switching cycle, in_avg and based on the current error signal 620, determines t on and t off can be adjusted.

[0053] Although the power supply system 104 of Figure 3 may have an improved PF with the controller 312 implementing CCM operation by sensing the average inductor current, the current measurement circuit 372 may introduce significant power loss into the power supply system 104. Specifically, referring back to Figure 3, the current measurement circuit 372 includes a shunt resistor 374 in the return path of the inductor current to measure the inductor current. However, directing the inductor current through the resistor 374 may cause significant power loss (especially when the inductor current is large) and reduce the power efficiency of the power supply system 104.

[0054] In contrast, the current measurement circuit 380 measuring the switch current signal 382 via magnetic coupling may reduce power loss incurred in the current measurement operation and improve power efficiency of the power supply system 104. Specifically, the current measurement circuit 380 measures the switch current signal 382 during the t off 3. Thus, the average current flowing through the primary coil 386 during a switch cycle may be reduced relative to the current measurement circuit 372, reducing the power loss incurred by the current measurement circuit. Power loss may be further reduced by decreasing the rotation ratio between the secondary coil 388 and the primary coil 386, such that the current signal 392 may be a scaled-down version of the switch current signal 382. Such an arrangement may further reduce the average current flowing through the measurement circuit 390 during a switch cycle, further reducing power loss.

[0055] Also, sensing the inductor current via magnetic coupling may create an isolation boundary between the PFC circuit 124 and the measurement circuit 390. The PFC circuit 124 (e.g., the inductor 306, the switch 308, and the diode 310 coupled at node 314) may be on the primary side of the isolation boundary (coupled to the primary coil 386), and the measurement circuit 390 may be on the secondary side of the isolation boundary (coupled to the secondary coil 388). The isolation boundary may improve safety and prevent short circuits between the AC power source 102 (which may be on the primary side) and other electrical components that may be on the secondary side, such as the power converter circuit 122 of FIG. 1.

[0056] Although the current measurement circuit 380 may reduce power loss and improve safety, the sampling operation by the current measurement circuit is subject to timing uncertainties that may introduce distortions and errors into the PFC operation. Specifically, as described above, the current measurement circuit 380 may sample the switch current at the midpoint of the charging period of the switching cycle to measure the average inductor current in the switching cycle. However, due to a sampling time offset, the switch current may vary from t on Therefore, the current error signal 620 may not represent the true difference between the reference current signal 616 and the average inductor current over a switching cycle, and the measurement signal 384 may not be sampled at the exact midpoint of t. on Adjusting Vref may introduce an error component into the inductor current.

[0057] The sampling time offset may be caused by various sources of timing uncertainty, such as jitter in the clock signal provided to the sampling circuit. The sampling time offset may also vary over a switching cycle, and the magnitude of the error component caused by the sampling time offset may also vary over a switching cycle. Specifically, referring to FIG. 7, the inductor current increases with a shorter t on (e.g., sw(4)) in a switching cycle with a longer ton (e.g., sw(0)). Thus, the same sampling time offset can be achieved with a shorter t on In a switching cycle with a longer t on The varying error component can increase harmonic distortion in the inductor current (and the AC input current signal 110) and degrade the PF of the power supply system 104.

[0058] 8 is a schematic diagram of an example power supply system 104 that may address at least some of the problems discussed above. With reference to FIG. 8, the power supply system 104 may include a controller 822. In a switching cycle, the controller 822 generates a ramp reference signal that may ramp over a ramp signal range in the switching cycle, compares the ramp reference signal to a measurement signal 384 (of the switch current signal 382), and adjusts the t of the control signal 330 for that switching cycle based on the comparison. on The measurement signal 384 may be set as t on t on The ramp signal range may include multiple samples of the switch current signal 382 or the induced current signal 392 sampled within a switching cycle. The ramp signal range may reflect the target / reference peak current for that switching cycle, which also reflects the DC input voltage signal 130 for that switching cycle. As part of the PFC operation, the controller 822 varies the ramp signal range to vary the t of the control signal 330 over a switching cycle. on , and the switch currents can be modulated by t on At the end of the period, the target / reference peak current may be reached.

[0059] The controller 822 may be part of an integrated circuit, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microcontroller, or a general purpose central processing unit (CPU). In some examples, the controller 822 may be integrated in the same integrated circuit package with one or more of the inductor 306, the switch 308, the voltage measurement circuits 342 and 352, and the current measurement circuit 380. In some examples, the controller 822 may be a separate integrated circuit chip from one or more of the inductor 306, the switch 308, the voltage measurement circuits 342 and 352, and the current measurement circuit 380.

[0060] Figure 9 includes waveform diagrams illustrating an example PFC operation of the PFC circuit 124 under the control of the controller 822 of Figure 8. Figure 9 includes graphs 902, 904, and 906. Graph 902 illustrates the time variation of the ramp reference signal generated by the controller 822, graph 904 illustrates the time variation of the measurement signal 384 (of the switch current 804), and graph 906 illustrates the control signal 330.

[0061] At time T0, the mth switching cycle sw(m) of the ramp reference signal and the mth ramp cycle begin. The ramp reference signal is V low (which can be 0 volts) and V high The ramp reference signal may have a ramp signal range between V high (m), at the end of the mth lamp cycle at T2, V low The m-th switching cycle sw(m) also ends at T2. on (m) may start at T0. on During (m), the inductor current increases as the inductor 306 charges. Because the switch 308 is enabled, the switch current 804 may be equal to the inductor current, and the measurement signal 384 increases over time. For CCM operation, the switch current 804 has a non-zero initial current I in_init(m), the measurement signal 384 starts increasing at the corresponding initial voltage V init (m) For CCrM and DCM operation, the inductor current and measurement signal 384 may start increasing from zero.

[0062] After the start of the mth switching cycle at T0, the controller 822 may compare between the voltages of the measurement signal 384 and the ramp reference signal to generate a determination, and if the determination indicates that the measurement signal 384 has a lower voltage than the ramp reference signal, the controller 822 may set the control signal 330 to an asserted state and extend the pulse. If the determination indicates that the measurement signal 384 crosses or exceeds the ramp reference signal, the controller 822 may set the control signal 330 to a deasserted state and extend the pulse and t on In the example of FIG. 9, the measurement signal 384 may be V peak At (m) the ramp reference signal crosses and V peak (m) is the peak current I in_pk (m) The peak current I in_pk (m) is the input DC voltage V in,dc can be tracked.

[0063] The duration between T1 and T2 is the t of the mth switching cycle during which the controller 822 keeps the control signal 330 in a deasserted state. off (m). Because switch 308 is disabled, switch current 804 may also be zero. Inductor 306 supplies capacitor current signal 117 (I C (t)) and the load current signal 119 (I load (t)) can be discharged and provided.

[0064] At time T3, the nth switching cycle sw(n) of the ramp reference signal and the nth ramp cycle begin. The ramp reference signal is V low and V high (n) may have a ramp signal range between V high (n) is V high(m) to reflect an increased target / reference peak current for the nth switching cycle. Also, t on (n) may begin at T3, and the controller 822 may set the control signal 330 to an asserted state to enable the switch 308. The measurement signal 384 (which represents the switch current and the inductor current) may on V between (n) init (n) and crosses the ramp reference signal at T4. In response to the measurement signal 384 crossing (or exceeding) the ramp reference signal, the controller 822 sets the control signal 330 to a deasserted state and pulses t on (n) may be terminated.

[0065] V high As (n) increases, it may take longer for the measurement signal 384 to cross the ramp reference signal. Thus, t on The duration of (n) is t on The crossing voltage V of the measurement signal 384 at T4 may be longer than the duration of peak (n) is V peak (m), and the corresponding peak current I in_pk (n) is the peak current I in_pk (m). Therefore, V high By varying the ramp signal range, the controller 822 can adjust t on And the inductor current (and AC input current signal 110) may be modulated to support PFC operation.

[0066] 10 and 11 illustrate examples of internal components of the controller 822. Referring to FIG. 10, the controller 822 may include a reference ramp signal generator circuit 1002, a memory 1004, a comparator 630, and a timing logic circuit 634 to generate the control signal 330. The memory 1004 may include volatile and / or non-volatile memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, erasable programmable read-only memory (EPROM), etc. The controller 822 may include a gate driver circuit (not shown in FIG. 10) that generates a drive signal for the switch 308 in response to the control signal 330. In some examples, the reference ramp signal generator circuit 1002 may have a control input 1003a, PFC inputs 1003b and 1003c, a timing input 1003d, and a ramp output 1003e. The reference ramp signal generator circuit 1002 may also include a ramp voltage range determining circuit 1012 , a DAC 1014 , and a counter 1016 .

[0067] Within a switching cycle, the reference ramp signal generator circuit 1002 may provide a ramp reference signal 1020 at a ramp output 1003e. The ramp reference signal 1020 may ramp over a ramp signal range determined by a ramp voltage range determination circuit 1012 within a switching cycle, as shown in graph 902 of FIG. 9. The ramp voltage range determination circuit 1012 has a scaling factor 1018 (denoted as S in FIG. 10) via a control input 1003a and a ramp voltage range (V out_pfc ) measurement signal 340, and V out_pfc and S. The scaling factor 1018 may be based on the voltage error signal 612 (the output of the voltage feedback loop) or a parameter. The comparator 630 may compare the ramp reference signal 1020 with the measurement signal 384 (the switch current 804 (I sw) to generate a decision signal 1022. The comparator 630 may receive the ramp reference signal 1020 and the measurement signal 384 as a continuous analog voltage signal, a sampled analog voltage signal, or a digital value. The timing logic 634 may include an SR latch that may be set by the decision signal 1022 and reset by the ramp reference signal 1020, where the reset may be active low. With the ramp reference signal 1020 having a higher voltage than the measurement signal 384 at the beginning of a switching cycle, the comparator 630 may provide an asserted decision signal 1022 to set the SR latch. In response to the SR latch being set, the timing logic 634 may generate an asserted control signal 330 to initiate a pulse. When the measurement signal 384 exceeds the ramp reference signal 1020, the comparator 630 may trip and generate a de-asserted decision signal 1022, thereby releasing the set signal of the SR latch. The ramp reference signal 1020 may also reset the SR latch. In response to the SR latch being reset, the timing logic circuit 634 generates a deasserted control signal 330 to stop the pulse and end the duration of the charging period t on The control signal 330 may terminate the duration of the discharge period t off may remain deasserted for the remainder of the switching cycle corresponding to

[0068] Prior to a switching cycle, the ramp signal range determination circuit 1012 determines the ramp voltage range 1030 (or V low If is constant, the peak lamp voltage V high ) and provide a ramp voltage range 1030 to the DAC 1014. The DAC 1014 also receives a count value 1032 from a counter 1016, which may receive a clock signal and sweep through a range of count values ​​in a ramp cycle in response to the clock signal. The DAC 1014 may determine a ramp voltage range 1030 to the DAC 1014 in response to changes in the count value 1032. high From tV lowA ramp reference signal 1020 may be generated that ramps down in steps to

[0069] 11 illustrates an example of the internal components of a DAC 1014. With reference to FIG. 11, the DAC 1014 may include a programmable current source 1102, a resistor ladder 1104, and a multiplexer circuit 1106. The programmable current source 1102 may be coupled between a first terminal 1110 of the resistor ladder 1104 and a voltage source 1112, and a second terminal 1114 of the resistor ladder 1104 may be coupled between a V low The programmable current source 1102 may be programmed based on the lamp voltage range information 1030 to couple the voltage at the first terminal 1110 to a ground that provides V high , where the current can reflect the lamp voltage range. A number of tap points of resistor ladder 1104 are each set to V high ~V low and coupled to an input of a multiplexer circuit 1106, a select input of which may receive the count value 1032. As the counter 1016 sweeps through a range of count values ​​in a switching cycle, the multiplexer 1106 may output different voltages from the resistor ladder 1104 as the ramp reference signal 1020 at different times in the switching cycle.

[0070] Referring again to FIG. 10, the ramp signal range determination circuit 1012 also receives t on 10, the PFC output voltage signal 132 may receive a duration 1040 of S (which may be a parameter or may be based on the voltage error signal 612) and a measurement signal 340 (V out_pfc ) and t on Based on the duration 1040 of high), all of which may be for the current or previous switching cycle (e.g., the mth cycle). The lamp voltage range determination circuit 1012 may receive the duration 1040 from the memory 1004, which may store the time when the decision signal 1022 is in the switching cycle t on In response to indicating the end of the ramp period (when the measurement signal 384 crosses the reference ramp signal 1020), the counter 1016 may store a count value 1032. For CCM and CCrM operation, the ramp voltage range determination circuit 1012 may determine the V high (m+1) can be determined. TIFF2025514168000006.tif10147

[0071] In Equation 7, V high where m+1 represents the peak ramp signal voltage for the m+1 switching cycle, and S may be a scaling factor 1018, which may be based on the voltage error signal 612 or another parameter, and V out_pfc (m) represents the sampled PFC output voltage in the mth switching cycle, and t on (m) is the t of the mth switching cycle on represents the duration of V for the current switching cycle, L represents the inductance of the inductor 306, and R represents the resistance of a resistor in the measurement circuit 390 for converting the sensed switch current 804 (or a scaled version of it) to a voltage. high V of the preceding switching cycle to determine out_pfc and t on Using V out_pfc , and t on may be based on the duration of being approximately constant between successive switching cycles.

[0072] Equation 7 may also be expanded to cover DCM operation as well. For DCM operation, the lamp voltage range determination circuit 1012 determines V in_dc, and receives a measurement signal 350 of V for the (m+1)th switching cycle as follows: high (m+1) can be determined. TIFF2025514168000007.tif17155 (Formula 8)

[0073] In Equation 8, t on (m) is the t of the mth switching cycle on t represents the duration of each switching cycle / lamp cycle, and T represents the cycle period of each switching cycle / lamp cycle. In some examples, the lamp voltage range determination circuit 1012 determines t based on the range of the count value 1032. on can be determined.

[0074] The measurement signal 384 (I sw ) is set according to Equation 7. high By comparing it with a ramp reference signal having avg DC input voltage signal 130 (V in_dc ) and can be shown to follow the shape of

[0075] t of a switching cycle on During this time, switch 308 is enabled and the voltage across inductor 306 rises to V in_dc , the inductor current (and switch current 804, I sw ) is I in_init (For example, T0 / T3 in Figure 9) to I in_pk (e.g., T1 / T4 in FIG. 9). Equation 4 above can be rewritten as follows: TIFF2025514168000008.tif13106

[0076] In addition, in CCM and CCrM operation modes, the average current I avg can be written as follows: in_init and I in_pk may be related to. I avg =(I in_init +I in_pk ) / 2 (Equation 10)

[0077] Combining Equations 9 and 10: I avg =I in_pk -(V in,dc ×t on ) / 2×L (Equation 11)

[0078] Also, the reference ramp signal 1020 changes over time to V high From V low V low is equal to zero, the crossing voltage V between the measurement signal 384 and the ramp reference signal 1020 is peak is expressed as follows: peak , t off and the switching / ramp cycle period T. (I in_pk ×R) / V high =t off / T (Formula 12)

[0079] In Equation 12, V peak I in_pk ×R, where R is the same as in Equation 7 and represents the resistance of a resistor in measurement circuit 390 for converting the sensed current to a voltage.

[0080] For CCM and CCrM in steady state, the DC input voltage signal 130 and the PFC output voltage signal 130 are expressed as follows: off and the switching / lamp cycle period T. V in_dc / V out pfc =t off / T (Formula 13)

[0081] Combining Equations 12 and 13: TIFF2025514168000009.tif17109

[0082] Equations 7, 9, 11, and 14 are substituted according to Equation 7. high Combine with terms. TIFF2025514168000010.tif20144 (Formula 15)

[0083] Equation 15 can be rewritten as follows: TIFF2025514168000011.tif11136 (Formula 16)

[0084] Also, equation 16 can be simplified to: I avg =(S × V in_dc ) / R (Equation 17)

[0085] Referring to Equation 17, S may be constant over a switching cycle, such as when the voltage control loop reaches a steady state and the voltage error signal 612 is approximately constant. Thus, the average current I avg is V in_dc This may improve the PF and reduce harmonic distortion in the AC input current since the PF may be proportional to and follow the shape of

[0086] The following derivation gives the measurement signal 384 (I sw (representing the V high By comparing it with a ramp reference signal having avg DC input voltage signal 130 (V in_dc ) can be shown to be proportional to and follow the shape of

[0087] In DCM mode, the average current in a switching cycle is t zero This can be determined by the following formula, which may be based on the formula and reason for zero current during the duration: TIFF2025514168000012.tif537 (Formula 18)

[0088] At steady state, the inductor volt-seconds are balanced over the switching cycle, so: V in,dc ×t on =(V out_pfc -V in,dc )×toff (Formula 19)

[0089] Equations 18 and 19 can be combined as follows: TIFF2025514168000013.tif15166

[0090] In the case of DCM, Equation 12 becomes: TIFF2025514168000014.tif1789

[0091] For DCM, Equations 8 and 12 are combined. TIFF2025514168000015.tif17163

[0092] Combining Equations 20 and 21: TIFF2025514168000016.tif10162

[0093] Also, equation 22 can be simplified to equation 17.

[0094] The controller 312 controls the return path current (or inductor current) at t on 7, where the controller 822 samples the switch current 804 at midpoints to determine the average current and generate the current error signal 620 for the switching cycle. The controller 822 receives the measurement signal 384 as a continuous analog voltage signal, compares the measurement signal 384 to a reference ramp signal 1020 to generate a decision signal 1022, and generates a current error signal 620 in response to the decision signal 1022 indicating that the switch current has reached the target peak current for that switching cycle. on With such an arrangement, the PFC operation of FIG. 9 may be less susceptible to clock jitter that may introduce variable sampling time offsets and increase harmonic distortion in the AC input current as in the PFC operation of FIG.

[0095] Also, for CCM and CrCM operation, the comparator 630 and timing logic 634 control the switch current I sw Based on the measurement signal 384 of on The measurement signal 340 may be generated from a measurement circuit on the secondary side of the isolation boundary between the primary coil 386 and the secondary coil 388. Thus, for CCM and CrCM operation, the controller 822 may modulate V in_dc 1. There is no need to cross an isolation boundary to receive the measurement signal 350. Such an arrangement may facilitate integration of the controller 822 with other circuitry, such as that which may be on the secondary side, such as the power converter circuit 122 of FIG.

[0096] FIG. 12 illustrates another example PFC circuit 124 that may perform PFC operation based on the techniques described in FIG. 8-FIG. 11. Referring to FIG. 12, the PFC circuit 124 of the power supply system 104 may include an inductor 306, switches 1202 and 1204, and diodes 1206 and 1208. The switches 1202, 1204, and the inductor 306 are coupled at a node 1214, and the switches 1202 and 1204 are coupled in series between the positive output 107a and the negative output 107b. The node 1214 may switch between the positive and negative power rails and may be a switching node. Also, the diodes 1206 and 1208 are coupled at a node 1220, and the diodes 1206 and 1208 are also coupled in series between the positive output 107a and the negative output 107b. Inductor 306 is coupled between positive input 105a and node 1214, and node 1220 between diode 1206 and diode 1208 is coupled to negative input 105b. In some examples, each of switches 1202 and 1204 may include a transistor such as an NFET or a GaN HEMT. In some examples, each of diodes 1206 and 1208 may be a body diode of a respective NFET. Switch 1202 may have a body diode 1216, and switch 1204 may have a body diode 1226.

[0097] The power supply system 104 also includes a controller 1230 coupled to the switches, the voltage measurement circuits 342 and 352, and the current measurement circuits 380a and 380b. A primary coil 386 of the current measurement circuit 380a may be coupled between the switch 1202 and the node 1214, and a primary coil 386 of the current measurement circuit 380b may be coupled between the switch 1204 and the node 1214. In some examples, the switches 1202 and 1204, the diodes 1206 and 1208, and the inductor 306 may be configured as a totem pole rectifier. The controller 1230 may generate control signals 1240 (denoted as VG1) and 1242 (denoted as VG2) to enable / disable the switches 1202 and 1204, respectively, to perform rectification and PFC operation. The controller 1230 may generate the control signals based on the measurement signals 340, 350, 384a, and 384b from the voltage measurement circuits 342 and 352 and the current measurement circuits 380a and 380b, respectively. The controller 1230 may be part of an integrated circuit, such as an ASIC, FPGA, or general purpose CPU, and may be integrated or separate from one or more of the inductor 306, the diodes 1206 and 1208, the switches 1202 and 1204, the voltage measurement circuits 342 and 352, and the current measurement circuits 380a and 380b.

[0098] Figure 13 illustrates an example operation of the PFC circuit 124 of Figure 12. Diagram 1302 illustrates the operation of the PFC circuit 124 during a positive half-cycle and diagram 1304 illustrates the operation of the PFC circuit 124 during a negative half-cycle of the AC input voltage signal 108. In diagrams 1302 and 1304, diodes 1206 and 1208 are labeled Q2 and Q1, respectively, and switches 1202 and 1204 are labeled Q4 and Q3, respectively.

[0099] Referring to figure 1302, V inDuring the positive half-cycle of the negative input 105b, when the negative input 105b receives a lower voltage than the positive input 105a, Q2 (diode 1206) is forward biased and Q1 (diode 1208) is reverse biased. The forward biased Q2 may connect the negative output 107b to the negative input 105b, and the reverse biased Q1 may disconnect the positive output 107a from the negative input 105b. During the charging interval, the controller 1240 may disable Q3 and enable Q4 to allow the inductor 306 to charge, and the inductor current 1310 may flow from the positive input 105a through the inductor 306 and Q4 and back to the negative input 105b. The inductor current (which is equal to the switch current through Q4) may increase over time, similar to the switch current 804 shown in graph 904 of FIG. 9. Also, during the discharge interval, the controller 1240 may enable Q3 (switch 1204) and disable Q4 (switch 1202). The switch current through Q4 may be zero. An inductor current 1312 may flow from the positive input 105a through the inductor 306 and switch 1204 to the capacitor 118 and the load 106, and the positive output 107a (and the positive power rail) may be connected to the positive input 105a. Thus, during the positive half-cycle, the positive output 107a may have a positive polarity and the negative output 107b may have a negative polarity.

[0100] Referring to diagram 1304, the negative input 105b receives a higher voltage than the positive input 105a. inDuring the negative half-cycle of the positive input 105b, Q2 is reverse biased and Q1 is forward biased. The forward biased Q1 may connect the negative input 105b to the positive output 107a, and the reverse biased Q2 may disconnect the negative input 105b from the negative output 107b. During the charging interval, the controller 1240 may enable Q3 and disable Q4 to allow the inductor 306 to charge, and an inductor current 1320 (which is equal to the switch current through Q3) may flow from the negative input 105b through Q3 and the inductor 306 back to the positive input 105a. The inductor current may increase over time, similar to the switch current 804 shown in the graph 904 of FIG. 9. Also, during the discharging interval, the controller 1240 may enable Q4 and disable Q3. The inductor current 1322 may flow from the negative input 105b through the capacitor 118 and the load 106, and back through Q4 and the inductor 306, and the positive output 107a (and the positive power rail) may be connected to the negative input 105b. Thus, during the negative half-cycle, the positive output 107a may also have a positive polarity, and the negative output 107b may also have a negative polarity.

[0101] 14 illustrates an example of the internal components of the controller 1230. With reference to FIG. 14, the controller 1230 may include components of the controller 822, such as the reference ramp signal generator 1002, the memory 1004, the comparator 630, and the timing logic 634. In addition, the controller 1230 may also include a multiplexer 1402, an inverter 1403, and a control signal router 1406. The multiplexer 1402 may receive the measurement signals 384a and 384b from the respective current measurement circuits 380a and 380b, and may output a signal to the V in Based on the measurement signal 350, the multiplexer 1402 may selectively forward one of them as the measurement signal 1404. Specifically, if the measurement signal 350 indicates a positive half cycle, the multiplexer 1402 may forward the measurement signal 384a (representing the switch current of the switch 1202) as the measurement signal 1404. Also, if the measurement signal 350 indicates a negative half cycle, the multiplexer 1402 may forward the measurement signal 384b (representing the switch current of the switch 1204) as the measurement signal 1404.

[0102] Controller 1230 may also provide complementary control signals 1240 and 1242 such that when switch 1202 is enabled, switch 1204 is disabled, and vice versa. Controller 1230 may include an inverter 1403, which may be coupled to the output of timing logic 634 to generate inverted control signal 330. Control signal router 1406 may be connected to V in 12. Specifically, when the measurement signal 350 indicates a positive half cycle, the control signal router 1406 may send the control signal 330 as the control signal 1240 to the switch 1202 and the inverted control signal 330 as the control signal 1242 to the switch 1204. When the measurement signal 350 indicates a negative half cycle, the control signal router 1406 may send the control signal 330 as the control signal 1242 to the switch 1204 and the inverted control signal 330 as the control signal 1240 to the switch 1202.

[0103] FIG. 15 includes a flow chart of an example method 1500 of controlling a PFC circuit, such as the PFC circuit 124 of FIG. 8 and FIG. 12. The PFC circuit 124 may have a PFC input terminal and a PFC output terminal. With reference to FIG. 8, the PFC circuit 124 may be coupled to the rectifier circuit 120 and may include an inductor 306, a switch 308, and a diode 310, where the inductor 306 is coupled between the PFC input terminal and a current terminal of the switch 308, and the diode 310 is coupled between the current terminal and the PFC output terminal. With reference to FIG. 12, the PFC circuit 124 may include the inductor 306, the switches 1202 and 1204, and the diodes 1206 and 1208 configured as a totem pole rectifier. The method 1500 may be implemented by a controller, such as the controller 822 of FIG. 8 and the controller 1230 of FIG. 12.

[0104] In step 1502, the controller receives a first voltage from the output of the PFC circuit. The first voltage is represented by the PFC output voltage signal 132 (V out_pfc(t)). The controller may represent V out_pfc A measurement signal 340 representative of (t) may be received. The first voltage may be sampled during a first switching cycle, which also coincides with a first lamp cycle.

[0105] In step 1504, the controller may determine a first ramp voltage for the ramp signal based on the first voltage.

[0106] Specifically, the controller calculates the t on Receive the duration and, after the first ramp cycle, the first ramp voltage (V high The controller may determine t on The duration information may be stored in a memory (e.g., memory 1004) and the information may be retrieved from the memory. The controller may also receive a scaling factor S, which may be a parameter or may be based on the voltage error signal 612 from the voltage control loop.

[0107] For CCM and CCrms operation, the controller determines the PFC output voltage and the t on Based on the duration, the controller may determine the first ramp voltage according to Equation 7. For DCM operation, the controller also determines the first ramp voltage during the first switching cycle (V in_dc Or V in ) and a measurement signal 350 representing the input voltage to the PFC circuit 124 at t off It receives the duration of the switching cycle (T) and the input voltage, the PFC output voltage, t on , t off , and T duration, the first ramp voltage may be determined according to Equation 8.

[0108] In step 1506, the controller may generate a ramp signal that decreases from a first ramp voltage to a second ramp voltage. The controller may include a DAC 1014 and a counter 1016. The counter 1016 may provide a set of count values ​​to the DAC 1014, which may provide an analog voltage as the ramp signal and decrease the analog voltage from the first ramp voltage to a second ramp voltage (e.g., zero) in response to the count value during the second ramp cycle.

[0109] In step 1508, the controller may provide a pulse-width modulated (PWM) signal having a first state to a control terminal of a switch of the PFC circuit.

[0110] Specifically, the controller provides a PWM signal in a second switching cycle that coincides with the second lamp cycle. From the beginning of the second switching cycle, a charging interval t on starts, and the PWM signal may be in a first state (e.g., asserted state). The switch receiving the PWM signal may be switch 308 of FIG. 8, switch 1202 of FIG. 12 during the positive half cycle, or switch 1204 of FIG. 12 during the negative half cycle. The switch may be enabled to provide a return path for the inductor current back to the AC power source 102, allowing the inductor 306 to charge.

[0111] In step 1510, the controller may receive a second voltage representing across the switch when the PWM signal is in the first state. Referring again to FIG. 9, the second voltage may represent the switch current, which is equal to the inductor current and increases over time within the charging interval of the second switching cycle. The second voltage may be the measurement signal 384 from the current measurement circuit 380 of FIG. 8 or the measurement signal 380a / 380b from the respective current measurement circuit 380a / 380b of FIG. 12.

[0112] At step 1512, the controller may compare the second voltage to the ramp signal to generate a determination, and at step 1514, in response to the determination indicating that the second voltage crosses the ramp signal, the controller may switch the PWM signal from the first state to the second state to disable the switch.

[0113] Specifically, referring back to FIG. 9 , the controller maintains the PWM signal in the first state and starts t of the second switching cycle when the decision signal 1022 indicates that the second voltage remains lower than the ramp signal. on When the decision signal 1022 indicates that the second voltage crosses or exceeds the ramp signal, the controller may extend t by switching the PWM signal from the first state to a second state (e.g., a deasserted state). on Exit off The switch (switch 308 in FIG. 8, switch 1202 in FIG. 12 during the positive half cycle, or switch 1204 in FIG. 12 during the negative half cycle) may be disabled until the end of the second switching cycle.

[0114] Any of the methods described herein may be implemented in whole or in part using a computing system including one or more processors that may be configured to perform the steps. Thus, embodiments may be directed to a computing system configured to perform the steps of any of the methods described herein, with possibly different components performing each step or each group of steps. Although steps are presented as numbered, steps of the methods described herein may be performed simultaneously or in different orders. Also, some of the steps may be used with some of other steps from other methods. Also, all or some of the steps may be optional. Also, any steps of any method may be implemented using a module, unit, circuit, or other means for performing those steps.

[0115] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, (a) in a first example, device A is directly coupled to device B, or (b) in a second example, device A is coupled to device B via an intervening component C, such that device B is controlled by device A via a control signal provided by device A, where the intervening component C does not substantially change the functional relationship between device A and device B.

[0116] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, or via the configuration and / or layout of hardware components, device interconnections, or a combination thereof.

[0117] Circuits or devices described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit elements or devices. For example, a structure described herein as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and be adapted to be coupled to at least some of the passive elements and / or sources, thereby forming the described structure, either at the time of manufacture or at a time thereafter, e.g., by an end user and / or a third party.

[0118] Although certain components are described as being of a particular process technology, these components may be interchangeable with other process technologies. The circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to that available prior to the replacement of the components. Unless otherwise noted, a component shown as a resistor generally represents any one or more elements coupled in series or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series or parallel between the same two nodes as a single resistor or capacitor, respectively.

[0119] Use of the term "ground" in this description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other type of ground connection applicable or appropriate to the teachings of this description. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means + / - 10 percent of that parameter.

[0120] Modifications in the described examples are possible, and other examples are possible, within the scope of the claims.

Claims

1. It is a device, A lamp generation circuit having an input and an output, A comparator having a first comparator input coupled to the output of the lamp generation circuit, a second comparator input configured to be coupled to the output of the current measurement circuit, and a comparator output, A pulse-width modulation (PWM) generation circuit having a pulse-width modulation (PWM) control input coupled to the comparator output and a first switch control output, A memory having a memory input coupled to the comparator output and a memory output, configured to store a value indicating the duration of the PWM signal, Includes, The apparatus wherein the lamp generation circuit is configured to provide a first lamp voltage for a second lamp cycle based on a value stored in the memory.

2. The apparatus according to claim 1, The input of the lamp generation circuit is connected to the power factor correction (PFC) output terminal. The lamp generation circuit, The first lamp voltage is determined based on the first voltage at the input of the lamp generation circuit. The lamp signal is provided that decreases from the first lamp voltage to the second lamp voltage. It is configured in such a way, The comparator is configured to provide a determination signal to the comparator output by comparing the lamp signal and the current measurement output with a second comparator input. An apparatus in which the PWM generation circuit is configured to change the state of the PWM signal at the first switch control output in response to the determination signal indicating that the signal at the output of the current measurement circuit crosses with the lamp signal.

3. The apparatus according to claim 2, A device wherein, when the PWM signal is in a first state, the signal at the output of the current measurement circuit reflects the current through the PFC switch.

4. The apparatus according to claim 3, The apparatus further includes a current transformer that is magnetically coupled to the current terminal of the PFC switch, and is configured to generate the signal at the output of the current measuring circuit by detecting the current.

5. The apparatus according to claim 3, The lamp signal decreases from the first lamp voltage to the second lamp voltage during the lamp cycle period. The PWM signal has a switching cycle period during which the PWM signal switches from the first state to the second state. A device in which the switching cycle period is equal to the ramp cycle period.

6. The apparatus according to claim 5, The lamp generation circuit further has a timing input coupled to the memory output, The lamp generation circuit, The value is read from the memory via the timing input. The first ramp voltage for the ramp signal of the second ramp cycle is determined after the first ramp cycle which corresponds to the first switching cycle. In the second ramp cycle, the ramp signal is provided. A device further configured in this way.

7. The apparatus according to claim 2, The lamp generation circuit, A lamp voltage range determination circuit having a processing input coupled to the input of the lamp generation circuit and a lamp voltage range output, wherein the lamp voltage range determination circuit is configured to provide a lamp voltage range signal to the lamp voltage range output based on the first voltage, A digital-to-analog converter (DAC) having a ramp voltage range input coupled to the ramp voltage range output, a digital input, and an analog output, The first lamp voltage is determined based on the lamp voltage range signal. The lamp signal, which is gradually reduced from the first lamp voltage to the second lamp voltage in response to a change in the state of the digital input, is provided to the analog output. The DAC is configured as follows, A counter having a clock input and a counter output coupled to the digital input, A device including a device.

8. The apparatus according to claim 2, The lamp generation circuit further has a control input, and the lamp generation circuit is further configured to determine the first lamp voltage based on a signal at the control input.

9. The apparatus according to claim 8, The apparatus further includes an amplifier having an amplifier output, a first amplifier input coupled to the PFC output terminal, and a second amplifier input coupled to a reference terminal.

10. The apparatus according to claim 9, A device in which the amplifier is part of a voltage feedback loop for adjusting the first voltage based on a reference voltage at the reference terminal.

11. The apparatus according to claim 2, The lamp generation circuit has an input that is a first PFC input, and the lamp generation circuit further has a second PFC input that is coupled to the PFC input terminal. The apparatus further comprises a lamp generation circuit configured to determine the first lamp voltage based on the duration of the switching cycle period of the PWM signal and a third voltage at the PFC input terminal.

12. The apparatus according to claim 2, The PWM generation circuit further has a second switch control output, and the PWM generation circuit is configured to provide a second PWM signal to the second switch control output. The aforementioned device A first current transformer magnetically coupled to the first current terminal of a first PFC switch, the first current transformer having a first current measuring output, A second current transformer magnetically coupled to the second current terminal of a second PFC switch, the second current transformer having a second current measuring output, A multiplexer having a first multiplexer input coupled to the first current measurement output, a second multiplexer input coupled to the second current measurement output, a first selection input coupled to the PFC input terminal, and a multiplexer output coupled to the second comparator input, A control signal routing circuit having a first control signal input coupled to the control output of the first PFC switch, a second control signal input coupled to the control output of the second PFC switch, a second selection input coupled to the PFC input terminal, a first control signal output coupled to the first control terminal of the first PFC switch, and a second control signal output coupled to the second control terminal of the second PFC switch, In response to the second selection input having the first state, the first control signal input is connected to the first control signal output, and the second control signal input is connected to the second control signal output. In response to the second selection input having a second state, the second control signal input is connected to the first control signal output, and the first control signal input is connected to the second control signal output. The control signal routing circuit is configured as follows: A device that further includes the following.

13. It is a method, Receiving a first voltage from the output of the power factor correction (PFC) circuit, Determining a first lamp voltage for a lamp signal based on the first voltage, To generate the lamp signal that decreases from the first lamp voltage to the second lamp voltage, A pulse-width modulation (PWM) signal having a first state is provided to the control terminal of the switch of the PFC circuit, When the PWM signal is in the first state, a second voltage representing the current through the switch of the PFC circuit is received, To generate a determination, the second voltage and the lamp signal are compared, In response to the determination indicating that the second voltage crosses the lamp signal, the PWM signal is switched from the first state to the second state in order to disable the switch, Determining the duration of the PWM signal in the first state, The memory stores the duration of the PWM signal in the first state, The first ramp voltage of the second ramp cycle is determined based on the duration of the PWM signal in the first state stored in the memory, Methods that include...

14. The method according to claim 13, The lamp signal decreases from the first lamp voltage to the second lamp voltage during the lamp cycle period. The PWM signal has a switching cycle period during which the PWM signal switches from the first state to the second state. A method wherein the switching cycle period is equal to the ramp cycle period.

15. The method according to claim 14, In the first switching cycle, the duration of the PWM signal having the first state is determined, Determining the first ramp voltage for the ramp signal of the second ramp cycle after a first ramp cycle that coincides with the first switching cycle, In the second ramp cycle, the ramp signal is provided, Methods that further include the above.

16. The method according to claim 15, A method in which the first ramp voltage for the ramp signal in the second ramp cycle is determined based on the first voltage in the first switching cycle.

17. The method according to claim 13, Receiving a voltage error signal from a voltage control loop that adjusts the first voltage based on a reference voltage, The first lamp voltage is determined based on the voltage error signal, Methods that further include the above.

18. The method according to claim 13, Receiving a third voltage from the input of the PFC circuit, The first ramp voltage is determined based on the third voltage and the duration of the switching cycle period of the PWM signal, Methods that further include the above.

19. It is a device, A power factor correction (PFC) circuit having a power factor correction (PFC) input and a PFC output, the PFC circuit comprising a switch having a current terminal coupled to the PFC output and an inductor coupled between the PFC input and the current terminal of the switch, A current measuring circuit coupled to the current terminal of the switch, the current measuring circuit having a current measuring output, A voltage measurement circuit coupled to the PFC output, the voltage measurement circuit having a voltage measurement output, A controller having a first control input coupled to the current measurement output, a second control input coupled to the voltage measurement output, and a control output coupled to the control terminal of the switch, A lamp generation circuit having a PFC input coupled to the second control input and a lamp output, A comparator having a first comparator input coupled to the lamp output, a second comparator input coupled to the first control input, and a comparator output, A PWM generation circuit having a PWM control input coupled to the comparator output and a PWM output coupled to the control output, A memory having a memory input coupled to the comparator output and a memory output, The controller includes, A device including a device.

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