VOT compensation-based single-phase interleaving CRM PFC digital control system and method

Abstract

The invention relates to the technical field of electronics, and discloses a VOT compensation-based single-phase interleaved CRM PFC digital control system and method, and the system comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator, and a driver. An EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module are integrated in the DSP controller, a 2P2Z controller, a voltage feedforward operation unit, a current detection verification unit and a temperature protection unit are further arranged in the DSP controller, the TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is provided with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase and two-phase staggered Boost topology, and the two Boost circuits are staggered and connected in parallel at a 180-degree initial phase and are jointly connected to the same PFC bus. According to the invention, the circuit design is simplified, the dynamic stability of inductive current interleaving is optimized, and the THD index of the power supply is improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a single-phase interleaved CRM PFC digital control system and method based on VOT compensation. Background Technology

[0002] According to the IEC 61000-3-2 standard, power factor requirements are specified for industrial electrical equipment with a power consumption of 75W or higher. A lower power factor increases the system's power consumption, places higher demands on the system's power capacity, and causes harmonic pollution to the power grid due to poor input current waveforms, affecting the overall power quality and the EMC performance of the equipment. Therefore, power consumption in laboratory instruments, communication equipment, home appliances, and rail transportation all require the addition of PFC circuits to achieve power factor correction.

[0003] Currently, the mainstream single-phase PFC circuit topology on the market is the bridged BOOST topology. Considering factors such as power expansion and THD optimization, two-way hardware interleaving is generally chosen for medium-power single-phase AC mains power supply scenarios. The two BOOST topologies are connected in parallel and interleaved at 180°, achieving the same power output with smaller inductance and capacitance values. The circuit topology is as follows: Figure 1 As shown. Figure 1 The topology can select multiple operating modes, which can be divided into DCM (discontinuous conduction mode), CCM (continuous conduction mode), and CRM (critical conduction mode) according to the inductor current state. In DCM mode, the power factor is low and the EMI characteristics are poor, so it has almost no applications.

[0004] CCM mode control is simple, and there are mature analog ICs available for selection, making development difficult. For example, TI's UCC28070 control chip can be used as a controller. The circuit operates in CCM mode, but it suffers from problems such as low efficiency, temperature drift in loop parameters, and inflexible control.

[0005] In CRM mode, the inductor current increases linearly from 0 in each switching cycle, then decreases linearly after a constant on-time, ending a switching cycle when it reaches 0. The average inductor current is half of its peak value, and the total input current is formed by the superposition of the two-phase inductor currents. The boost diode has no reverse recovery loss and is highly efficient. However, during the resonant decrease of the drain-source voltage of the switching transistor, a reverse inductor current discharges the parasitic capacitance of the switching transistor. The presence of this reverse inductor current causes the inductor current in each switching cycle to no longer be a standard triangular wave. The average inductor current cannot perfectly track the sinusoidal input voltage signal, especially at the zero-crossing point of the power frequency, resulting in severe crossover distortion. Summary of the Invention

[0006] Based on this, this application provides a single-phase interleaved CRM PFC digital control system and method based on VOT compensation. By segmenting the on-time of the switching transistor within the power frequency cycle, it improves the zero-crossing distortion at the power frequency; by optimizing the dynamic stability of the inductor current interleaving through adaptive interleaved phase control; and by constructing a zero-crossing detection signal through simple hardware and signal logic, it simplifies circuit design and improves THD performance and system efficiency.

[0007] This application discloses a single-phase interleaved CRM PFC digital control system based on VOT compensation, which includes: The system includes a DSP controller, a first power loop, a second power loop, a first external comparator, a second external comparator, and a driver. The DSP controller integrates an EPWM driver module, an ADC sampling module, an on-chip DC digital comparator module, and a TZ trigger interrupt module. It also includes a 2P2Z controller, a voltage feedforward arithmetic unit, a current detection and verification unit, and a temperature protection unit. The TZ trigger interrupt module has TZ2 and TZ3 pins. The EPWM driver module is configured with a first comparator register CMPA, a period register TBPRD, and a second comparator register CMPB. The first power circuit and the second power circuit form a single-phase two-phase interleaved Boost topology. The two Boost circuits are connected in parallel with 180° initial phase interleaving and are connected to the same PFC bus to jointly complete the main power conversion for power factor correction. The first power circuit and the second power circuit output their respective inductor current signals and switch drain-source voltage signals to the sampling port of the ADC sampling module and the corresponding off-chip comparator to provide feedback for control and detection. The ADC sampling module acquires the AC live wire voltage. AC neutral line voltage PFC bus voltage First power circuit inductor current Second power circuit inductor current Switching transistor temperature Ambient temperature The analog state quantities are converted into digital quantities and then transmitted to the corresponding functional units inside the DSP controller, where the AC live wire voltage is... AC neutral line voltage PFC bus voltage The digital value is used to calculate the reference conduction time, which is then combined with the inductor current of the first power circuit. Second power circuit inductor current The digital determination of the balance state of the two inductor currents and the AC live wire voltage AC neutral line voltage The extracted instantaneous value of the AC input voltage is used to complete the segmented compensation of the conduction time, and the compensated conduction time is obtained. The value of the time base counter TBCTR captured by the on-chip DC digital comparator module is used to calculate the interleaved phase angle adjustment parameter. The DSP controller synchronously updates the compensated conduction time and interleaved phase angle adjustment parameters to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs two-phase switch drive signals corresponding to the first power circuit and the second power circuit according to the parameters in the register. After being amplified by the driver, the signals are sent to the control terminals of the switch tubes in the first power circuit and the second power circuit respectively to control the switching tubes to turn on and off. The first external comparator and the second external comparator compare the drain-source voltage of the switching transistor with the voltage divider of the PFC bus, and send the comparison result to the TZ2 and TZ3 pins of the DSP controller after a logical AND operation to provide the inductor current zero-crossing trigger signal. The on-chip DC digital comparator module interacts with the TZ trigger interrupt module to achieve time base synchronization and time base counter value capture based on the zero-crossing trigger signal, and feeds back the capture result to the register configuration terminal of the EPWM drive module to dynamically adjust the interleaved phase angle of the two-phase drive signals.

[0008] Furthermore, AC live wire voltage AC neutral line voltage The digital value is transmitted to the voltage feedforward arithmetic unit to provide a voltage reference for input voltage feedforward control and conduction time calculation. The voltage feedforward arithmetic unit is also used to extract the instantaneous value of AC input voltage. PFC bus voltage The digital signal is transmitted to the 2P2Z controller to provide bus voltage feedback for the voltage loop closed-loop control, used for calculating the reference conduction time; the inductor current of the first power loop... Second power circuit inductor current The digital quantity is transmitted to the current detection and verification unit to provide current basis for current balance state determination, inductor current zero-crossing detection and verification, and interleaved phase control. Switching transistor temperature Ambient temperature The digital data is transmitted to the temperature protection unit to provide temperature data for system overheat protection and temperature compensation. The EPWM drive module includes a first drive channel EPWM1A, a second drive channel EPWM2A, a first complementary drive channel EPWM1B, and a second complementary drive channel EPWM2B. The output terminals of EPWM1A and EPWM2A are both connected to the driver input terminals, and the driver output terminals are respectively connected to the control electrodes of the switching transistors of the first power circuit and the second power circuit. EPWM1B and EPWM2B respectively output complementary drive signals that are inverses of the corresponding main drive signals, and their output terminals are respectively connected to a logic AND operation circuit composed of AND gates.

[0009] Furthermore, the non-inverting input of the first external comparator is connected to the PFC bus voltage divider detection signal COMP+, and the inverting input is connected to the drain-source voltage divider detection signal COMP1- of the switching transistor in the first power circuit. The first external comparator compares the voltages of the two voltage divider signals and outputs a comparison signal. This comparison signal is then connected to the TZ2 pin after a logical AND operation with EPWM1B to form the first inductor current zero-crossing detection signal. The non-inverting input of the second external comparator is connected to COMP+, and the inverting input is connected to COMP2-, the drain-source voltage divider detection signal of the second power circuit. The second external comparator compares the voltage of the two voltage divider signals and outputs a comparison signal. This comparison signal is connected to the TZ3 pin after a logical AND operation with EPWM2B to form the second inductor current zero-crossing detection signal. The on-chip DC digital comparator module is connected to the TZ2 and TZ3 pin signals respectively. According to the trigger timing of the two inductor current zero-crossing detection signals, it captures the time base counter value at the trigger moment and sends the phase adjustment information to the register configuration terminal of the EPWM drive module in real time, so that the EPWM drive module can adaptively adjust the interleaved phase of the two-phase drive signals according to the input voltage conditions, and at the same time realize the time base synchronization of the EPWM drive module. The current detection and verification unit will detect the inductor current of the first power circuit. Second power circuit inductor current The digital value is compared with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the inductor current zero-crossing detection.

[0010] This application also discloses a single-phase interleaved CRM PFC digital control method based on VOT compensation, applicable to the system described above, which includes: The DSP controller configures the internal EPWM drive module, initializes the initial values ​​of CMPA, TBPRD, and CMPB, and enables EPWM1A and EPWM2A to output the main drive signals corresponding to the first and second power loops, respectively, while EPWM1B and EPWM2B output the corresponding complementary drive signals. The main drive signals are amplified by the driver and drive the switching transistors of the corresponding power loops. The complementary drive signals are connected to the logic AND operation circuit. The output signals of the first and second external comparators and the corresponding complementary drive signals are ANDed and then sent to the TZ2 and TZ3 pins, respectively, to construct the inductor current zero-crossing detection path.

[0011] Furthermore, it also includes: The DSP controller configures its internal EPWM drive module in single-increment counting mode: when the time base counter counts to 0, the main drive signal is set high; when the count reaches the compensated on-time value in the first comparator register, the main drive signal flips low; when the count reaches the value corresponding to the interleaved phase angle adjustment parameter in the period register, the switching cycle is restarted; the period register value corresponds to the switching frequency of the current switching cycle; the DSP controller configures the initial switching frequency to the minimum switching frequency and associates the on-chip DC digital comparator module with the signals of pins TZ2 and TZ3, using pins TZ2 and TZ3 as trigger sources to trigger corresponding interrupt events, achieving synchronization between the zero-crossing signal and the drive cycle; the DSP controller initializes the internal temperature protection unit and current detection and verification unit, setting... , The overheat protection threshold, and , The current balance determination threshold and zero-crossing detection verification logic.

[0012] Furthermore, it also includes steps for analog signal acquisition, conversion, and digital signal parsing and allocation: The ADC sampling module inside the DSP controller synchronously acquires data through each sampling port. , , , , , , The analog signal is converted into a digital value and then transmitted to the voltage feedforward arithmetic unit, the 2P2Z controller, the current detection and verification unit, and the temperature protection unit, respectively. Voltage feedforward arithmetic unit extraction , The instantaneous value of the digital AC input voltage is obtained and the feedforward calculation is completed; Will , The digital value is transmitted to the voltage feedforward arithmetic unit to extract the instantaneous value of the AC input voltage and complete the input voltage feedforward calculation. The 2P2Z controller calculates iteratively using the voltage loop differential equation. The digital quantity is used to obtain the reference conduction time, and the output of the voltage loop differential equation is the load condition characterization value. The current detection and verification unit will , The digital value is compared and verified in real time with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the zero-crossing detection and to detect the balance state of the two inductor currents. Temperature protection unit will , The digital value is compared with the preset threshold in real time to determine the temperature status of the switching transistor and the system, and it only participates in overheat protection and temperature compensation.

[0013] Furthermore, it also includes the calculation steps for the compensated conduction time: The DSP controller compensates for the reference conduction time using a segmented compensation method based on the instantaneous value of the AC input voltage, load conditions, and the balance state of the two inductor currents. The compensation formula is as follows:

[0014] in, The compensated conduction time, As the reference conduction time, The segmented adjustment value is for experimental verification, i.e., the conduction time compensation amount; The segmented compensation counteracts the influence of the reverse inductor current, reducing the current crossover distortion at the zero-crossing point of the AC input voltage to optimize the current waveform. If the temperature protection unit determines that an overheating state has occurred, it synchronously triggers the temperature compensation strategy to adjust the conduction time and switching frequency.

[0015] Furthermore, it also includes the calculation of the interleaved phase angle adjustment parameters and the dynamic output steps of the drive signal: The DSP controller calculates the interleaved phase angle adjustment parameters based on the time base counter values ​​obtained by the on-chip DC digital comparator modules of EPWM1 ​​and EPWM2 channels. The compensated on-time and staggered phase angle adjustment parameters are synchronously updated to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs the appropriate two-phase switch drive signal according to the timing rules of the single-increment counting mode, based on the timing of setting the main drive signal high and turning low according to the CMPA, and based on the timing of restarting the switching cycle according to the TBPRD. At the zero-crossing point of the AC input voltage, maintain the minimum switching frequency, reduce the interleaved phase angle, and synchronize the two-phase drive signals. As the instantaneous value of the AC input voltage increases, adjust the CMPA value of the next switching cycle, gradually increasing the interleaved phase angle to 180° to achieve a fixed phase-shifted working state for the first power circuit and the second power circuit. This keeps the two-phase inductor currents stable and interleaved, canceling the single-phase inductor current ripple, while maintaining the balance of the two inductor currents. This optimizes the interleaved stability of the inductor current under AC input voltage fluctuations and load changes. Configure the CMPB value for the EPWM drive module so that the CMPB value is equal to the CMPA value plus the compensation value determined by debugging. This compensation value is set according to the PFC design operating frequency and circuit parasitic parameters. The EPWM drive module controls the complementary drive signal to be high at the CMPB counting time and low when TBCTR equals TBPRD according to the CMPB value.

[0016] Furthermore, it also includes soft-switching implementation and harmonic suppression steps: The complementary drive signal, in conjunction with the output signals of the first and second external comparators, performs a logical AND operation to construct an inductor current zero-crossing detection signal. This enables the inductor current zero-crossing trigger and synchronized updating of the switching cycle, allowing the system to achieve zero-voltage soft switching and valley-level turn-on. The current detection and verification unit then... , The digital quantity is used to verify the inductor current operating characteristics in the soft-switching state in real time, providing a basis for fine-tuning the register parameters; When the AC input voltage Vin is greater than the difference between the PFC bus output voltage Vout and Vin, the segmented compensation for the reference conduction time is stopped, and the following is set: The compensated on-time is updated to the reference on-time and written into the CMPA, and the system only achieves valley-level turn-on; at the zero-crossing point of the AC input voltage, the on-time compensation is increased. The new compensated on-time is calculated and updated to CMPA to enhance the cancellation effect on reverse inductor current, reduce the distortion effect of reverse inductor current on current waveform, and reduce total harmonic distortion.

[0017] Furthermore, it also includes system overheat protection procedures: If the temperature protection unit determines or If the digital value exceeds the preset overheat protection threshold, the overheat protection action is immediately triggered. The CMPA and TBPRD parameters of the EPWM drive module are adjusted to reduce the switching frequency or reduce the conduction time until the system temperature returns to a safe range, thereby achieving temperature protection for the switching transistor and the system.

[0018] Due to the adoption of the above technical solution, this application has the following advantages: 1. By using segmented compensation with varying conduction time, the influence of reverse inductance current is effectively offset, significantly improving crossover distortion at power frequency zero crossing.

[0019] 2. Adaptive staggered phase control is adopted to replace the traditional fixed 180° stagger, thereby improving the dynamic stability of inductor current stagger.

[0020] 3. A zero-crossing detection signal is constructed using complementary drive signals and an external comparator, eliminating the need for additional hardware and simplifying circuit design.

[0021] 4. Achieve ZVS+ valley-level turn-on composite soft switching, with a system peak efficiency of up to 98.3% and THD as low as 2.5%, performance indicators far exceeding those of CCM mode and traditional CRM mode PFC power supplies.

[0022] 5. Flexible digital control with adaptive parameter adjustment, suitable for 3kW medium-power single-phase PFC scenarios, outperforming traditional CCM and CRM solutions. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0024] Figure 1 This is a two-phase parallel interleaved Boost topology diagram according to an embodiment of this application; Figure 2 This is a diagram showing the relationship between inductor current ripple and duty cycle under 180° parallel interleaving conditions according to an embodiment of this application. Figure 3 This is a schematic diagram of on-chip resource configuration according to an embodiment of this application; Figure 4 This is a block diagram illustrating the digital control principle of an embodiment of this application; Figure 5 This is a timing diagram of the EPWM1A and EPWM1B signals in an embodiment of this application; Figure 6 This is a timing diagram of the inductor current zero-crossing detection signal according to an embodiment of this application; Figure 7 This is a block diagram of the working logic of a digital comparator according to an embodiment of this application; Figure 8 This is a waveform diagram of the power frequency zero-crossing inductor current in an embodiment of this application; Figure 9 This is a waveform diagram of the inductor current at the power frequency peak point according to an embodiment of this application; Figure 10 This is a waveform diagram of the inductor current after variable conduction time compensation according to an embodiment of this application; Figure 11 This is a diagram illustrating the effect of ZVS (zero voltage turn-on) near the zero-crossing point of the power frequency in an embodiment of this application. Figure 12 This is a diagram illustrating the effect of switching on (VS) near the power frequency peak value in an embodiment of this application. Detailed Implementation

[0025] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0026] See Figure 1 This application provides an embodiment of a single-phase interleaved CRM PFC digital control method based on VOT compensation, which includes: The system comprises a DSP controller, a first power loop, a second power loop, a first external comparator, a second external comparator, and a driver. The DSP controller integrates an EPWM driver module, an ADC sampling module, an on-chip DC digital comparator module (DC sub-module), and a TZ trigger interrupt module (TZ sub-module). It also includes a 2P2Z controller, a voltage feedforward arithmetic unit, a current detection and verification unit, and a temperature protection unit. The TZ trigger interrupt module has a TZ2 pin (second trigger interrupt pin) and a TZ3 pin (third trigger interrupt pin). The EPWM driver module is configured with a first comparator register (CMPA), a period register (TBPRD), and a second comparator register (CMPB). The first power circuit and the second power circuit form a single-phase two-phase interleaved Boost topology. The two Boost circuits are connected in parallel with 180° initial phase interleaving and are connected to the same PFC bus to jointly complete the main power conversion for power factor correction. The first power circuit and the second power circuit output their respective inductor current signals and switch drain-source voltage (VDS) signals to the sampling port of the ADC sampling module and the corresponding off-chip comparator to provide feedback for control and detection. The ADC sampling module acquires the AC live wire voltage. AC neutral line voltage PFC bus voltage First power circuit inductor current Second power circuit inductor current Switching transistor temperature Ambient temperature The analog state quantities are converted into digital quantities and then transmitted to the corresponding functional units inside the DSP controller, where the AC live wire voltage is... AC neutral line voltage PFC bus voltage The digital value is used to calculate the reference conduction time, which is then combined with the inductor current of the first power circuit. Second power circuit inductor current The digital determination of the balance state of the two inductor currents and the AC live wire voltage AC neutral line voltage The extracted instantaneous value of AC input voltage is used to perform segmented compensation of conduction time to obtain the compensated conduction time. The value of the time base counter (TBCTR) captured by the on-chip DC digital comparator module is used to calculate the interleaved phase angle adjustment parameter. The DSP controller synchronously updates the compensated conduction time and interleaved phase angle adjustment parameters to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs two-phase switch drive signals corresponding to the first power circuit and the second power circuit according to the parameters in the register. After being amplified by the driver, the signals are sent to the control terminals of the switch tubes in the first power circuit and the second power circuit respectively to control the switching tubes to turn on and off. The first external comparator and the second external comparator compare the drain-source voltage (VDS) of the switching transistor with the voltage divider of the PFC bus, and send the comparison result to the TZ2 and TZ3 pins of the DSP controller after a logical AND operation to provide the inductor current zero-crossing trigger signal. The on-chip DC digital comparator module interacts with the TZ trigger interrupt module to achieve time base synchronization and capture the time base counter (TBCTR) value based on the zero-crossing trigger signal, and feeds back the capture result to the register configuration terminal of the EPWM drive module to dynamically adjust the interleaved phase angle of the two-phase drive signals.

[0027] The embodiments of this application can employ a DSP controller of model LS-Z22PQMS. This controller is a general-purpose hardware platform, and under the premise that the hardware model and circuit structure remain unchanged, various different method steps described in this application can be implemented by loading different software algorithms and executing different control programs.

[0028] Optionally, AC live wire voltage AC neutral line voltage The digital value is transmitted to the voltage feedforward arithmetic unit to provide a voltage reference for input voltage feedforward control and conduction time calculation. The voltage feedforward arithmetic unit is also used to extract the instantaneous value of AC input voltage. PFC bus voltage The digital signal is transmitted to the 2P2Z controller to provide bus voltage feedback for the voltage loop closed-loop control, used for calculating the reference conduction time; the inductor current of the first power loop... Second power circuit inductor current The digital quantity is transmitted to the current detection and verification unit to provide current basis for current balance state determination, inductor current zero-crossing detection and verification, and interleaved phase control. Switching transistor temperature Ambient temperature The digital data is transmitted to the temperature protection unit to provide temperature data for system overheat protection and temperature compensation. The EPWM drive module includes a first drive channel (EPWM1A), a second drive channel (EPWM2A), a first complementary drive channel (EPWM1B), and a second complementary drive channel (EPWM2B). The output terminals of EPWM1A and EPWM2A are both connected to the driver input terminals, and the driver output terminals are respectively connected to the control electrodes of the switching transistors of the first power circuit and the second power circuit. EPWM1B and EPWM2B respectively output complementary drive signals that are inverses of the corresponding main drive signals, and their output terminals are respectively connected to a logic AND operation circuit composed of AND gates.

[0029] Optionally, the non-inverting input of the first external comparator is connected to the PFC bus voltage divider detection signal COMP+, and the inverting input is connected to the drain-source voltage divider detection signal COMP1- of the switching transistor in the first power circuit. The first external comparator compares the voltages of the two voltage divider signals and outputs a comparison signal. This comparison signal is then connected to the TZ2 pin after a logical AND operation with EPWM1B to form the first inductor current zero-crossing detection signal. The non-inverting input of the second external comparator is connected to COMP+, and the inverting input is connected to COMP2-, the drain-source voltage divider detection signal of the second power circuit. The second external comparator compares the voltage of the two voltage divider signals and outputs a comparison signal. This comparison signal is connected to the TZ3 pin after a logical AND operation with EPWM2B to form the second inductor current zero-crossing detection signal. The on-chip DC digital comparator module is connected to the TZ2 and TZ3 pin signals respectively. According to the trigger timing of the two inductor current zero-crossing detection signals, it captures the time base counter (TBCTR) value at the trigger moment and sends the phase adjustment information to the register configuration terminal of the EPWM drive module in real time. This enables the EPWM drive module to adaptively adjust the interleaved phase of the two-phase drive signals according to the input voltage conditions, and at the same time realizes the time base synchronization of the EPWM drive module. The current detection and verification unit will detect the inductor current of the first power circuit. Second power circuit inductor current The digital value is compared with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the inductor current zero-crossing detection.

[0030] This application also provides an embodiment of a single-phase interleaved CRM PFC digital control method based on VOT compensation, applicable to the system described in the above embodiment, which includes: The DSP controller configures the internal EPWM drive module, initializes the initial values ​​of CMPA, TBPRD, and CMPB, and enables EPWM1A and EPWM2A to output the main drive signals corresponding to the first and second power loops, respectively, while EPWM1B and EPWM2B output the corresponding complementary drive signals. The main drive signals are amplified by the driver and drive the switching transistors of the corresponding power loops. The complementary drive signals are connected to the logic AND operation circuit. The output signals of the first and second external comparators and the corresponding complementary drive signals are ANDed and then sent to the TZ2 and TZ3 pins, respectively, to construct the inductor current zero-crossing detection path.

[0031] Optionally, it also includes: The DSP controller configures its internal EPWM drive module in single-increment counting mode: when the time base counter (TBCTR) counts to 0, the main drive signal is set high; when the count reaches the compensated on-time value in the first comparator register (CMPA), the main drive signal flips low; when the count reaches the value corresponding to the interleaved phase angle adjustment parameter in the period register (TBPRD), the switching cycle is restarted; the period register (TBPRD) value corresponds to the switching frequency of the current switching cycle; the DSP controller configures the initial switching frequency to the minimum switching frequency and associates the on-chip DC digital comparator module with the signals of pins TZ2 and TZ3, using pins TZ2 and TZ3 as trigger sources to trigger corresponding interrupt events, achieving synchronization between the zero-crossing signal and the drive cycle; the DSP controller initializes the internal temperature protection unit and current detection and verification unit, setting... , The overheat protection threshold, and , The current balance determination threshold and zero-crossing detection verification logic.

[0032] Optionally, it also includes steps for analog signal acquisition, conversion, and digital signal parsing and allocation: The ADC sampling module inside the DSP controller synchronously acquires data through each sampling port. , , , , , , The analog signal is converted into a digital value and then transmitted to the voltage feedforward arithmetic unit, the 2P2Z controller, the current detection and verification unit, and the temperature protection unit, respectively. Voltage feedforward arithmetic unit extraction , The instantaneous value of the digital AC input voltage is obtained and the feedforward calculation is completed; Will , The digital value is transmitted to the voltage feedforward arithmetic unit to extract the instantaneous value of the AC input voltage and complete the input voltage feedforward calculation. The 2P2Z controller calculates iteratively using the voltage loop differential equation. The digital quantity is used to obtain the reference conduction time ( The output of the voltage loop difference equation is a load condition characterization value. The current detection and verification unit will , The digital value is compared and verified in real time with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the zero-crossing detection and to detect the balance state of the two inductor currents. Temperature protection unit will , The digital value is compared with the preset threshold in real time to determine the temperature status of the switching transistor and the system, and it only participates in overheat protection and temperature compensation.

[0033] Optionally, it also includes a step for calculating the compensated conduction time: The DSP controller uses a segmented compensation method to adjust the reference conduction time based on the instantaneous value of the AC input voltage, load conditions, and the balance state of the two inductor currents. Compensation will be provided, and the compensation formula is as follows:

[0034] in, The compensated conduction time, The segmented adjustment value is for experimental verification, i.e., the conduction time compensation amount; The segmented compensation counteracts the influence of the reverse inductor current, reduces the current crossover distortion at the zero-crossing point of the AC input voltage, and optimizes the current waveform. If the temperature protection unit determines that an overheating state has occurred, it synchronously triggers the temperature compensation strategy to adjust the conduction time and switching frequency.

[0035] Optionally, it also includes the calculation of interleaved phase angle adjustment parameters and the dynamic output of the drive signal: The DSP controller calculates the interleaved phase angle adjustment parameters based on the time base counter (TBCTR) values ​​obtained by the on-chip DC digital comparator module capture function (DCCAP) of the EPWM1 ​​and EPWM2 channels. The compensated on-time and staggered phase angle adjustment parameters are synchronously updated to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs the appropriate two-phase switch drive signal according to the timing rules of the single-increment counting mode, based on the timing of setting the main drive signal high and turning low according to the CMPA, and based on the timing of restarting the switching cycle according to the TBPRD. At the zero-crossing point of the AC input voltage, maintain the minimum switching frequency, reduce the interleaved phase angle, and synchronize the two-phase drive signals. As the instantaneous value of the AC input voltage increases, adjust the CMPA value of the next switching cycle, gradually increasing the interleaved phase angle to 180° to achieve a fixed phase-shifted working state for the first power circuit and the second power circuit. This keeps the two-phase inductor currents stable and interleaved, canceling the single-phase inductor current ripple, while maintaining the balance of the two inductor currents. This optimizes the interleaved stability of the inductor current under AC input voltage fluctuations and load changes. Configure the CMPB value for the EPWM drive module so that the CMPB value is equal to the CMPA value plus the compensation value determined by debugging. This compensation value is set according to the PFC design operating frequency and circuit parasitic parameters. The EPWM drive module controls the complementary drive signal to be high at the CMPB counting time and low when TBCTR equals TBPRD according to the CMPB value.

[0036] Optionally, it also includes soft-switching implementation and harmonic suppression steps: The complementary drive signal, in conjunction with the output signals of the first and second external comparators, performs a logical AND operation to construct the inductor current zero-crossing detection signal. This enables the inductor current zero-crossing trigger and synchronous update of the switching cycle, allowing the system to achieve zero-voltage soft switching (ZVS) and valley-to-turn (VS). The current detection and verification unit... , The digital quantity is used to verify the inductor current operating characteristics in the soft-switching state in real time, providing a basis for fine-tuning the register parameters; When the AC input voltage Vin is greater than the difference between the PFC bus output voltage Vout and Vin, the reference conduction time is stopped. The segmented compensation makes The compensated on-time is updated to the reference on-time and written into the CMPA, and the system only achieves valley-level turn-on; at the zero-crossing point of the AC input voltage, the on-time compensation is increased. The new compensated on-time is calculated and updated to CMPA to enhance the cancellation effect on reverse inductor current, reduce the distortion effect of reverse inductor current on current waveform, and reduce total harmonic distortion (THD).

[0037] Optionally, it also includes system overheat protection steps: If the temperature protection unit determines or If the digital value exceeds the preset overheat protection threshold, the overheat protection action is immediately triggered. The CMPA and TBPRD parameters of the EPWM drive module are adjusted to reduce the switching frequency or reduce the conduction time until the system temperature returns to a safe range, thereby achieving temperature protection for the switching transistor and the system.

[0038] like Figure 1 The single-phase interleaved BOOST circuit shown operates in CRM mode. By segmenting the on-time of the switching transistor within the power frequency cycle, it improves the crossover distortion problem of PFC at the zero-crossing point of the power frequency. At the same time, it proposes a simple and effective digital generation method for the drive signal and the zero-crossing detection signal, which simplifies the circuit design, optimizes the dynamic stability of the inductor current interleaving, and improves the power supply THD index.

[0039] For ease of understanding, this application provides more specific embodiments: Example 1: The LS-Z22PQMS DSP product was selected as the controller, and embedded software code development was completed on the CCS12.4 platform. Traditional CRM PFCs often use two channels, EPWM1A and EPWM1B, to generate 180° complementary drive signals, which is simple to configure and implement. The reason for choosing 180° complementary interleaved drive is that, under this operating condition with a duty cycle of 0.5, the inductor current ripple is minimized. Figure 2 As shown, the vertical axis represents the total inductor current. Peak-to-peak value of single-phase inductor current The ratio. However, near the zero-crossing point of the power frequency, due to the low input voltage, the conduction time... If the switching duty cycle is too long, the switching duty cycle d will be much greater than 0.5, resulting in poor inductor current interleaving and severe crossover distortion. In addition, it is difficult to construct a zero-crossing detection signal, making it difficult to achieve a soft-switching effect and leading to low power supply efficiency.

[0040] This application selects two channels, EPWM1A and EPWM2A, to generate drive signals. A minimum switching frequency is set at the zero-crossing point of the AC power frequency, and the interleaving angle is reduced. Simultaneously, conduction time compensation is added to offset the influence of reverse inductor current, improving crossover distortion and enhancing THD performance. A zero-crossing detection signal is constructed and associated with the drive signal to achieve synchronous updates of conduction time and counting period, and adaptive adjustments are made in response to changes in input voltage. The specific design process is as follows: a) On-chip resource allocation Two channels, EPWM1A and EPWM2A, generate drive signals (EPWM1A corresponds to power loop 1 (first power loop), and EPWM2A corresponds to power loop 2 (second power loop), which will not be elaborated further). Two channels, EPWM1B and EPWM2B, generate complementary drive signals. The positive input of external comparator 1 (the first external comparator) is connected to the PFC bus voltage divider detection signal COMP+, and the negative input is connected to the power loop 1 switch transistor DS voltage divider detection signal COMP1-. The comparator output pin COMP1 and the EPWM1B signal complete an AND operation, and the signal is sent to pin TZ2 of the DSP. Similarly, the positive input of external comparator 2 (the second external comparator) is connected to the PFC bus voltage divider detection signal COMP+, and the negative input is connected to the power loop 2 switch transistor DS voltage divider detection signal COMP2-. The comparator output pin COMP2 and the EPWM2B signal complete an AND operation, and the signal is sent to pin TZ3 of the DSP. The on-chip resource configuration is as follows... Figure 3 As shown.

[0041] Figure 3 The components in the middle are LS-Z22PQMS (DSP), XL74LS08 (4 groups of 2-input AND gates), and SGM8741 (comparator). Figure 3 The hardware configuration enables the inductor current zero-crossing detection function.

[0042] b) EPWM module initialization configuration The EPWM1 ​​and EPWM2 channels are configured in single-increment counting mode. When TBCTR=0 (time base counter is zero), the EPWM1A output is high; it toggles low at TBCTR=CMPA; and the counting cycle restarts at TBCTR=TBPRD (TBPRD is the EPWM channel time base counting period, corresponding to the switching frequency of the current switching cycle). The initial switching frequency information (i.e., the minimum switching frequency) and output action are configured. The DSP's on-chip DC (digital comparator) module is used, with TZ2 and TZ3 signals as trigger sources, to trigger the corresponding interrupt events.

[0043] c) Initialization and configuration of the ADC digital comparator module Complete the acquisition of control-related status variables and configure sampling port resources, such as... Figure 2 As shown, it is necessary to collect the live wire voltage, neutral wire voltage, PFC bus voltage, and inductor current of power loop 1 (see power loop description). Figure 1 Information such as power circuit 2 inductor current, switching transistor temperature, and ambient temperature.

[0044] Complete the acquisition of control-related status variables and configure sampling port resources, such as... Figure 4 As shown, it is necessary to collect the live wire voltage. Neutral line voltage PFC bus voltage Power circuit 1 inductor current (See power circuit description) Figure 1 ), Power circuit 2 inductor current Switching transistor temperature Information such as ambient temperature .

[0045] d) Iterate the voltage loop difference equation to calculate the conduction time. By introducing input voltage feedforward to track the bus voltage setpoint, the voltage loop output represents the load magnitude and can calculate the initial conduction time of the next switching cycle. .

[0046] e) Segmented compensation for conduction time Actual conduction time under different loads and input conditions The initial value can be calculated by step d). Adjusted values ​​verified by experiments The summation is represented in segments, as in formula (1): (1) f) Switch information refresh Based on the actual conduction time obtained in the previous step, real-time Update the CMPA values ​​of both EPWM1 ​​and EPWM2 channels, reset the TBCTR value based on the zero-crossing detection signal, and output the drive signal. The entire digital control process is as follows: Figure 4 .

[0047] exist Figure 4 middle, This is the sampled value of the live wire voltage. This is the sampled value of the neutral line voltage. For PFC bus voltage sampling value, For the sampled value of the inductor current in power circuit 1, For the inductor current sampling value of power circuit 2, For the temperature sampling value of the switching transistor, This is the ambient temperature sample value; This is the drive signal for power circuit 1. This is the drive signal for power circuit 2, which is connected to the driver for subsequent driving. Figure 1 The switching transistors Q1 and Q2 in the middle.

[0048] The key points of this application are mainly twofold: firstly, the construction of the zero-crossing detection signal, and secondly, the implementation of an adaptive interleaved drive signal based on the input voltage change, rather than a fixed 180° interleaving.

[0049] a) Construction of zero-crossing detection signal The LS-Z22PQMS has a main frequency of 50MHz and a 20ns time interval between each counting point. For each PWM channel, CMPB=80+CMPA is configured. The EPWMnB signal is set high at CMPB and toggles low at TBCTR=TBPRD. The voltage divider values ​​on the non-inverting input sides of the two external comparators are relatively low. The TZ2 and TZ3 signals are the zero-crossing detection signals for the inductor current of power loop 1 and power loop 2, respectively. Figure 5 , Figure 6 As shown.

[0050] Figure 6 The signal correspondence of the oscilloscope is shown in Table 1.

[0051] Table 1 Signal Correspondence

[0052] b) Interleaved drive signal implementation The first step is register configuration during the initialization phase.

[0053] Configure TZ and DC digital comparator modules for EPWM1 ​​channel: Epwm1Regs.TZSEL.bit.DCAEVT2 = TURE; Epwm1Regs.TZCTL.all = 0xFFFE; Epwm1Regs.TZDCSEL.all = 0x009A; Epwm1Regs.DCTRIPSEL.all = 0x0281; Epwm1Regs.DCACTL.all = 0x0008; Epwm1Regs.DCFCTL.all = 0x0012; Epwm1Regs.DCCAPCTL.all = 0x0003; Event triggering correspondence: "TZ3 is associated with DCBH and DCBEVT1"; "COMP1 is associated with DCAL and DCBEVT2"; "TZ2 is associated with DCAH and DCAEVT1". This can be understood as TZ2 triggering EPWM1 ​​time base synchronization to start a new counting cycle; TZ3 triggering DCCAP to capture the current TBCTR of the EPWM1 ​​channel for adjusting the interleaved phase angle.

[0054] Configure TZ and DC digital comparator modules for EPWM2 channel: Epwm2Regs.TZSEL.bit.DCAEVT2 = TURE; Epwm2Regs.TZCTL.all = 0xFFFE; Epwm2Regs.TZDCSEL.all = 0x009A; Epwm2Regs.DCTRIPSEL.all = 0x0192; Epwm2Regs.DCACTL.all = 0x0008; Epwm2Regs.DCFCTL.all = 0x0012; Epwm2Regs.DCCAPCTL.all = 0x0003; Event triggering correspondence: “TZ2 is associated with DCBH and DCBEVT1”; "COMP2 is associated with DCAL and DCBEVT2"; "TZ3 is associated with DCAH and DCAEVT1". This can be understood as TZ3 triggering EPWM2 time base synchronization to start a new counting cycle; TZ2 triggering DCCAP to capture the current TBCTR of the EPWM2 channel for adjusting the interleaved phase angle.

[0055] The working logic block diagram of the DSP's digital comparator block (DC submodule) is as follows: Figure 7 As shown.

[0056] In the interrupt service routine code, the CMPA value is compensated in segments based on the input voltage magnitude, and the interleaved phase angle is adjusted. At the zero-crossing point of the power frequency, the EPWM1A and EPWM1B signals are synchronized. As the instantaneous value of the input voltage increases, the CMPA for the next switching cycle is adjusted based on the DCCAP values ​​of the two channels, gradually achieving the phase reversal effect. At any given moment, the DS voltage cannot fully resonate to 0, only achieving valley-level switching. The switching frequency is relatively high, eliminating the need for CMPA compensation. The specific control effect waveform is shown below. Figure 8 , Figure 9 As shown.

[0057] Figure 8 , Figure 9 The correspondence between oscilloscope signals is shown in Table 2.

[0058] Table 2 Signal Correspondence

[0059] Example 2: In this embodiment, the hub beam micro DSP chip LS-Z22PQMS is selected as the controller, and the control software is developed on the CCS12.4 platform to realize 3kW single-phase interleaved CRMPFC digital control.

[0060] 1. Allocation of hardware and software resources EPWM1A and EPWM2A generate two main drive signals; EPWM1B and EPWM2B generate complementary drive signals. The non-inverting input of the first external comparator is connected to the PFC bus voltage divider, and the inverting input is connected to the drain-source voltage divider of the first power circuit switching transistor. The output is logically ANDed with EPWM1B and then connected to the TZ2 pin. The non-inverting input of the second external comparator is connected to the PFC bus voltage divider, and the inverting input is connected to the drain-source voltage divider of the second power circuit switching transistor. The output is logically ANDed with EPWM2B and then connected to the TZ3 pin.

[0061] 2. EPWM module initialization Configure EPWM1 ​​and EPWM2 in single-increment counting mode: the drive signal is set high when TBCTR=0, toggles low when the first comparator register value is reached, and restarts the cycle when the cycle register value is reached. Configure the initial switching frequency to the minimum switching frequency and associate the on-chip DC digital comparator module with the TZ2 and TZ3 signals.

[0062] 3. ADC Acquisition Configuration Collect AC input voltage, PFC bus voltage, two-phase inductor current, switching transistor temperature, and ambient temperature.

[0063] 4. Calculation and compensation of conduction time Input voltage feedforward is introduced, and the reference conduction time is calculated iteratively using the voltage loop differential equation. Segmented compensation is performed according to the following formula: Compensated conduction time = Reference conduction time + Experimental verification adjustment value. The compensation amount is increased at the power frequency zero crossing point to offset the reverse inductance current and improve crossover distortion.

[0064] 5. Adaptive Interleaved Control The minimum switching frequency is set at the zero-crossing point of the power frequency to reduce the interleaved phase angle and drive synchronously; the interleaved angle is gradually increased as the input voltage increases to achieve stable phase shifting.

[0065] 6. Zero-crossing detection and soft switching Configure the second comparator register value to be 80 + the first comparator register value, so that the complementary drive signal is set high / flipped at the corresponding time, and forms a reliable zero-crossing detection signal in conjunction with the external comparator to achieve ZVS+ valley turn-on.

[0066] 7. Experimental Results This application implements parallel interleaved digital control function and achieves soft switching effect with ZVS+ valley turn-on. The power supply has a peak efficiency of 98.3%, THD=2.5%, smooth inductor current waveform with no obvious crossover distortion, and good soft switching effect. Its performance indicators far exceed those of PFC power supplies in CCM mode and traditional CRM mode.

[0067] This application implements parallel interleaved digital control functionality. The hardware and software configuration is described above, and the measured waveform is as follows. Figure 10 , Figure 11 , Figure 12 . Figure 10 The effect of VOT (variable conduction time) compensation is clearly visible in the data. Figure 11 , Figure 12 In the diagram, dark blue represents the DS voltage of power circuit 1, light blue represents the DSP output port drive signal of power circuit 1, and purple represents the inductor current of power circuit 1. The effect of zero-crossing detection of inductor current can be clearly seen. ZVS / VS can be achieved at different power frequencies, achieving the best achievable soft-switching effect.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A single-phase interleaved CRM PFC digital control system based on VOT compensation, characterized in that, include: The system includes a DSP controller, a first power loop, a second power loop, a first external comparator, a second external comparator, and a driver. The DSP controller integrates an EPWM driver module, an ADC sampling module, an on-chip DC digital comparator module, and a TZ trigger interrupt module. It also includes a 2P2Z controller, a voltage feedforward arithmetic unit, a current detection and verification unit, and a temperature protection unit. The TZ trigger interrupt module has TZ2 and TZ3 pins. The EPWM driver module is configured with a first comparator register CMPA, a period register TBPRD, and a second comparator register CMPB. The first power circuit and the second power circuit form a single-phase two-phase interleaved Boost topology. The two Boost circuits are connected in parallel with 180° initial phase interleaving and are connected to the same PFC bus to jointly complete the main power conversion for power factor correction. The first power circuit and the second power circuit output their respective inductor current signals and switch drain-source voltage signals to the sampling port of the ADC sampling module and the corresponding off-chip comparator to provide feedback for control and detection. The ADC sampling module acquires the AC live wire voltage. AC neutral line voltage PFC bus voltage First power circuit inductor current Second power circuit inductor current Switching transistor temperature Ambient temperature The analog state quantities are converted into digital quantities and then transmitted to the corresponding functional units inside the DSP controller, where the AC live wire voltage is... AC neutral line voltage PFC bus voltage The digital value is used to calculate the reference conduction time, which is then combined with the inductor current of the first power circuit. Second power circuit inductor current The digital determination of the balance state of the two inductor currents and the AC live wire voltage AC neutral line voltage The extracted instantaneous value of the AC input voltage is used to complete the segmented compensation of the conduction time, and the compensated conduction time is obtained. The value of the time base counter TBCTR captured by the on-chip DC digital comparator module is used to calculate the interleaved phase angle adjustment parameter. The DSP controller synchronously updates the compensated conduction time and interleaved phase angle adjustment parameters to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs two-phase switch drive signals corresponding to the first power circuit and the second power circuit according to the parameters in the register. After being amplified by the driver, the signals are sent to the control terminals of the switch tubes in the first power circuit and the second power circuit respectively to control the switching tubes to turn on and off. The first external comparator and the second external comparator compare the drain-source voltage of the switching transistor with the voltage divider of the PFC bus, and send the comparison result to the TZ2 and TZ3 pins of the DSP controller after a logical AND operation to provide the inductor current zero-crossing trigger signal. The on-chip DC digital comparator module interacts with the TZ trigger interrupt module to achieve time base synchronization and time base counter value capture based on the zero-crossing trigger signal, and feeds back the capture result to the register configuration terminal of the EPWM drive module to dynamically adjust the interleaved phase angle of the two-phase drive signals.

2. The system according to claim 1, characterized in that, AC live wire voltage AC neutral line voltage The digital value is transmitted to the voltage feedforward arithmetic unit to provide a voltage reference for input voltage feedforward control and conduction time calculation. The voltage feedforward arithmetic unit is also used to extract the instantaneous value of AC input voltage. PFC bus voltage The digital signal is transmitted to the 2P2Z controller to provide bus voltage feedback for the voltage loop closed-loop control, used for calculating the reference conduction time; the inductor current of the first power loop... Second power circuit inductor current The digital quantity is transmitted to the current detection and verification unit to provide current basis for current balance state determination, inductor current zero-crossing detection and verification, and interleaved phase control. Switching transistor temperature Ambient temperature The digital data is transmitted to the temperature protection unit to provide temperature data for system overheat protection and temperature compensation. The EPWM drive module includes a first drive channel EPWM1A, a second drive channel EPWM2A, a first complementary drive channel EPWM1B, and a second complementary drive channel EPWM2B. The output terminals of EPWM1A and EPWM2A are both connected to the driver input terminals, and the driver output terminals are respectively connected to the control electrodes of the switching transistors of the first power circuit and the second power circuit. EPWM1B and EPWM2B respectively output complementary drive signals that are inverses of the corresponding main drive signals, and their output terminals are respectively connected to a logic AND operation circuit composed of AND gates.

3. The system according to claim 1, characterized in that, The non-inverting input of the first external comparator is connected to the PFC bus voltage divider detection signal COMP+, and the inverting input is connected to the drain-source voltage divider detection signal COMP1- of the switching transistor in the first power circuit. The first external comparator compares the voltage of the two voltage divider signals and outputs a comparison signal. This comparison signal is then connected to the TZ2 pin after a logical AND operation with EPWM1B to form the first inductor current zero-crossing detection signal. The non-inverting input of the second external comparator is connected to COMP+, and the inverting input is connected to COMP2-, the drain-source voltage divider detection signal of the second power circuit. The second external comparator compares the voltage of the two voltage divider signals and outputs a comparison signal. This comparison signal is connected to the TZ3 pin after a logical AND operation with EPWM2B to form the second inductor current zero-crossing detection signal. The on-chip DC digital comparator module is connected to the TZ2 and TZ3 pin signals respectively. According to the trigger timing of the two inductor current zero-crossing detection signals, it captures the time base counter value at the trigger moment and sends the phase adjustment information to the register configuration terminal of the EPWM drive module in real time, so that the EPWM drive module can adaptively adjust the interleaved phase of the two-phase drive signals according to the input voltage conditions, and at the same time realize the time base synchronization of the EPWM drive module. The current detection and verification unit will detect the inductor current of the first power circuit. Second power circuit inductor current The digital value is compared with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the inductor current zero-crossing detection.

4. A single-phase interleaved CRM PFC digital control method based on VOT compensation, applicable to the system described in any one of claims 1-3, characterized in that, include: The DSP controller configures the internal EPWM drive module, initializes the initial values ​​of CMPA, TBPRD, and CMPB, and enables EPWM1A and EPWM2A to output the main drive signals corresponding to the first and second power loops, respectively, while EPWM1B and EPWM2B output the corresponding complementary drive signals. The main drive signals are amplified by the driver and drive the switching transistors of the corresponding power loops. The complementary drive signals are connected to the logic AND operation circuit. The output signals of the first and second external comparators and the corresponding complementary drive signals are ANDed and then sent to the TZ2 and TZ3 pins, respectively, to construct the inductor current zero-crossing detection path.

5. The method according to claim 4, characterized in that, Also includes: The DSP controller configures its internal EPWM drive module in single-increment counting mode: when the time base counter counts to 0, the main drive signal is set high; when the count reaches the compensated on-time value in the first comparator register, the main drive signal flips low; when the count reaches the value corresponding to the interleaved phase angle adjustment parameter in the period register, the switching cycle is restarted; the period register value corresponds to the switching frequency of the current switching cycle; the DSP controller configures the initial switching frequency to the minimum switching frequency and associates the on-chip DC digital comparator module with the signals of pins TZ2 and TZ3, using pins TZ2 and TZ3 as trigger sources to trigger corresponding interrupt events, achieving synchronization between the zero-crossing signal and the drive cycle; the DSP controller initializes the internal temperature protection unit and current detection and verification unit, setting... , The overheat protection threshold, and , The current balance determination threshold and zero-crossing detection verification logic.

6. The method according to claim 4, characterized in that, It also includes the steps of analog signal acquisition, conversion, and digital signal parsing and allocation: The ADC sampling module inside the DSP controller synchronously acquires data through each sampling port. , , , , , , The analog signal is converted into a digital value and then transmitted to the voltage feedforward arithmetic unit, the 2P2Z controller, the current detection and verification unit, and the temperature protection unit, respectively. Voltage feedforward arithmetic unit extraction , The instantaneous value of the digital AC input voltage is obtained and the feedforward calculation is completed; Will , The digital value is transmitted to the voltage feedforward arithmetic unit to extract the instantaneous value of the AC input voltage and complete the input voltage feedforward calculation. The 2P2Z controller calculates iteratively using the voltage loop differential equation. The digital quantity is used to obtain the reference conduction time, and the output of the voltage loop differential equation is the load condition characterization value. The current detection and verification unit will , The digital value is compared and verified in real time with the zero-crossing detection signals of the TZ2 and TZ3 pins to determine the validity of the zero-crossing detection and to detect the balance state of the two inductor currents. Temperature protection unit will , The digital value is compared with the preset threshold in real time to determine the temperature status of the switching transistor and the system, and it only participates in overheat protection and temperature compensation.

7. The method according to claim 4, characterized in that, It also includes the steps for calculating the conduction time after compensation: The DSP controller compensates for the reference conduction time using a segmented compensation method based on the instantaneous value of the AC input voltage, load conditions, and the balance state of the two inductor currents. The compensation formula is as follows: in, The compensated conduction time, As the reference conduction time, The segmented adjustment value is for experimental verification, i.e., the conduction time compensation amount; The segmented compensation counteracts the influence of the reverse inductor current, reducing the current crossover distortion at the zero-crossing point of the AC input voltage to optimize the current waveform. If the temperature protection unit determines that an overheating state has occurred, it synchronously triggers the temperature compensation strategy to adjust the conduction time and switching frequency.

8. The method according to claim 4, characterized in that, It also includes the calculation of interleaved phase angle adjustment parameters and the dynamic output steps of the drive signal: The DSP controller calculates the interleaved phase angle adjustment parameters based on the time base counter values ​​obtained by the on-chip DC digital comparator modules of EPWM1 ​​and EPWM2 channels. The compensated on-time and staggered phase angle adjustment parameters are synchronously updated to the CMPA and TBPRD of the EPWM drive module. The EPWM drive module outputs the appropriate two-phase switch drive signal according to the timing rules of the single-increment counting mode, based on the timing of setting the main drive signal high and turning low according to the CMPA, and based on the timing of restarting the switching cycle according to the TBPRD. At the zero-crossing point of the AC input voltage, maintain the minimum switching frequency, reduce the interleaved phase angle, and synchronize the two-phase drive signals. As the instantaneous value of the AC input voltage increases, adjust the CMPA value of the next switching cycle, gradually increasing the interleaved phase angle to 180° to achieve a fixed phase-shifted working state for the first power circuit and the second power circuit. This keeps the two-phase inductor currents stable and interleaved, canceling the single-phase inductor current ripple, while maintaining the balance of the two inductor currents. This optimizes the interleaved stability of the inductor current under AC input voltage fluctuations and load changes. Configure the CMPB value for the EPWM drive module so that the CMPB value is equal to the CMPA value plus the compensation value determined by debugging. This compensation value is set according to the PFC design operating frequency and circuit parasitic parameters. The EPWM drive module controls the complementary drive signal to be high at the CMPB counting time and low when TBCTR equals TBPRD according to the CMPB value.

9. The method according to claim 4, characterized in that, It also includes soft-switching implementation and harmonic suppression steps: The complementary drive signal, in conjunction with the output signals of the first and second external comparators, performs a logical AND operation to construct an inductor current zero-crossing detection signal. This enables the inductor current zero-crossing trigger and synchronized updating of the switching cycle, allowing the system to achieve zero-voltage soft switching and valley-level turn-on. The current detection and verification unit then... , The digital quantity is used to verify the inductor current operating characteristics in the soft-switching state in real time, providing a basis for fine-tuning the register parameters; When the AC input voltage Vin is greater than the difference between the PFC bus output voltage Vout and Vin, the segmented compensation for the reference conduction time is stopped, and the following is set: The compensated on-time is updated to the reference on-time and written into the CMPA, and the system only achieves valley-level turn-on; at the zero-crossing point of the AC input voltage, the on-time compensation is increased. The new compensated on-time is calculated and updated to CMPA to enhance the cancellation effect on reverse inductor current, reduce the distortion effect of reverse inductor current on current waveform, and reduce total harmonic distortion.

10. The method according to claim 4, characterized in that, It also includes system overheat protection steps: If the temperature protection unit determines or If the digital value exceeds the preset overheat protection threshold, the overheat protection action is immediately triggered. The CMPA and TBPRD parameters of the EPWM drive module are adjusted to reduce the switching frequency or reduce the conduction time until the system temperature returns to a safe range, thereby achieving temperature protection for the switching transistor and the system.

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