Bump bonding structure for multi-chip bonding.

Abstract

A method of forming a multi-chip system is disclosed. The method includes forming one or more bumps on respective conductive contact pads of a first electronic device, forming one or more mini-bumps on respective conductive contact pads of a second electronic device, and aligning the respective one or more mini-bumps with the respective one or more bumps. The method further includes performing a bump bonding process that applies a compressive force to one or both of the first electronic device and the second electronic device to compress the one or more mini-bumps into the one or more bumps to form one or more bump bond structures that bond the second electronic device to the first electronic device.

Description

[Technical field]

[0001] The present invention relates generally to chip bonding, and more particularly to a bump bond structure for multi-chip bonding. [Background technology]

[0002] In many large-scale electronic applications, it is desirable to connect integrated circuit (IC) devices together to add functionality and / or increase capacity. These IC devices are typically connected to each other via bump bonds. Bump bonding is a common technique in the industry for packaging integrated circuits. Gold is used not only for electrical signal transfer between devices, but also for thermal transfer of heat between devices. Typical industrial processes employ large bump bonds (50-100 μm in diameter / thickness), and high temperatures of 300-450 °C combined with high pressure to obtain a strong metallurgical bond. However, in certain low-temperature applications, high temperatures can damage certain components on the IC. Therefore, these gold bonding processes are not compatible with these types of devices. Summary of the Invention

[0003] In one example, a method of forming a multi-chip system is disclosed. The method includes forming one or more bumps on respective conductive contact pads of a first electronic device, forming one or more mini-bumps on respective conductive contact pads of a second electronic device, and aligning the respective one or more mini-bumps with the respective one or more bumps. The method further includes performing a bump bonding process that applies a compressive force to one or both of the first electronic device and the second electronic device to compress the one or more mini-bumps into one or more bumps forming one or more bump bond structures and bond the second electronic device to the first electronic device.

[0004] In yet another example, a multi-chip system is disclosed that includes a first electronic device having a plurality of first conductive contact pads disposed on a top surface of the first electronic device and a second electronic device having a plurality of second conductive contact pads disposed on a bottom surface of the second electronic device, the multi-chip system further including a plurality of bump bonding structures, a given bump bonding structure coupling a respective one of the plurality of first conductive contact pads to a respective one of the plurality of second conductive contact pads to bond the first electronic device to the second electronic device, each of the plurality of bump bonding structures including a mini-bump compressed within the bump. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a perspective view of a multi-chip system. [Diagram 2] FIG. 2 is a schematic cross-sectional view of a bump bonding structure. [Diagram 3] FIG. 3 is a cross-sectional view of a multi-chip system in an early stage of manufacture, with the mini-bumps of the second electronic device aligned with the conductive bumps of the first electronic device. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating the mini-bumps of a second electronic device being moved into contact with the conductive bumps of a first electronic device while undergoing a bump bonding compression process. [Diagram 5] FIG. 5 is a schematic cross-sectional view illustrating how the mini-bumps are partially compressed into the conductive bump when a compressive force is continued to be applied to the top surface of the second electronic device. [Figure 6] FIG. 6 is a schematic cross-sectional view showing how the mini-bump is fully compressed into the conductive bump to form the bump bond structure. [Figure 7] FIG. 7 is a schematic cross-sectional view of a multi-chip system including both a bump bonding structure and a low-temperature bump bonding structure coupling a second electronic device to a first electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] The present disclosure relates to forming a multi-chip system from two or more electronic devices (e.g., integrated circuits). The two or more electronic devices are electrically and / or mechanically coupled to one another via bump bond structures (e.g., gold, copper). The bump bond structures can be conductive or non-conductive. The bump bond structures can carry electrical signals or can function as standoffs that do not carry signals but bond the electronic devices to one another. In one example, each bump bond structure is formed with mini-bumps compressed into a bump via a low-temperature thermo-compression flip-chip bonding process. In certain applications, the circuits may be temperature sensitive or may include low-temperature solder interconnects (e.g., indium or indium alloys) that limit the upper process temperature to about 50° C. to about 250° C. (e.g., 150° C.) and / or may include architectures that do not support large bump bonds. The present disclosure addresses the limitations of bump bonding using high process temperatures (e.g., 300° C. to 450° C.) and / or very large bump bond structures that are not compatible with temperature sensitive circuits or circuits requiring fine pitch interconnects. In one example, the structure and process allows for the formation of gold interconnects alongside indium or indium alloy interconnects in the same flip chip bonding process with low temperature requirements (eg, below 150° C.).

[0007] In one example, one or more mini-bumps are fabricated on a first electronic device (e.g., top integrated circuit chip) and one or more respective regular bumps are fabricated on a second electronic device (e.g., bottom substrate / integrated circuit chip). The first electronic device is placed above the second electronic device, and one or more mini-bumps are pressed into one or more respective bumps by compression during the bump bonding process to form a uniform connection between the first electronic device and the second electronic device. Additionally, one or more low melting point bumps may be fabricated on one of the first electronic device and / or the second electronic device to provide an electrical connection between the electronic devices. Low melting point bump bonding is defined as a bump bond with a melting point of about 50°C to about 250°C (e.g., 150°C). This process allows for simultaneous flip-chip bump bonding of two entirely different interconnects composed of different materials: bumps (e.g., gold or copper) and low melting point bumps (e.g., indium / indium alloy bumps).

[0008] In yet another example, the bump bond structure consists of a conductive pad or bump about 3 μm thick and about 10 μm×10 μm in area on the lower substrate compression bonded to a mini-bump about 2 μm thick and about 2 μm×2 μm in area on the upper chip. The mini-bump is compressed into the conductive pad or bump with sufficient compressive force applied in the bonding process to form a robust mechanical bond and low resistance electrical contact, for example, via cold welding. The bonding process can be performed at or below 150° C., which can be beneficial to protect temperature sensitive devices. This structure and bonding process is not only applicable to conductive materials such as gold or copper, but can also be used with other conductive or non-conductive materials.

[0009] FIG. 1 is a perspective view of an example of a multi-chip system 10. FIG. 2 is a schematic cross-sectional view of an example bump bonding structure 30 of the multi-chip system 10. The multi-chip system 10 includes a first electronic device 12 (e.g., a lower or main device) connected to a second electronic device 22 (e.g., an upper or auxiliary device) via multiple bump bonding structures 30. Although a single electronic device is shown as the upper device, multiple upper devices can be coupled to one lower or main device. The electronic devices can be substrate wafers, packaged devices for passing signals to another device, integrated circuits (ICs), or various other types of electronic devices.

[0010] The first electronic device 12 includes a plurality of first conductive contact pads 16 disposed on a top surface of the first electronic device 12. Each of the plurality of first conductive contact pads 16 is coupled to a respective conductive line 14 that electrically couples each of the respective first conductive contact pads 16 to other electrical elements, such as vias and / or circuits, within the first electronic device 12. The second electronic device 22 includes a plurality of second conductive contact pads 26 disposed on a bottom surface of the second electronic device 22. Each of the plurality of second conductive contact pads 26 is coupled to a respective conductive line 24 that electrically couples each of the respective second conductive contact pads 26 to other electrical elements, such as vias and / or circuits, within the second electronic device 22. The first electronic device 12 is electrically and mechanically coupled to the second electronic device 22 by a plurality of bump bonding structures 30 that bond the devices to each other via corresponding conductive contact pads of the first electronic device 12 and the second electronic device 22, respectively.

[0011] 2, a given bump bond structure of the plurality of bump bond structures 30 is formed of a mini-bump 32 compressed within a (larger) bump 20. The bump bond structure 30 covers a first UBM layer 18 at the end of the bump 20 and a second UBM layer 28 at the end of the mini-bump 32. The first UBM layer 18 covers a given first conductive contact pad of the plurality of first conductive contact pads 16, and the second UBM layer 28 covers a given second conductive contact pad of the plurality of second conductive contact pads 26. The first UBM layer 18 and the second UBM layer 28 are optional based on the material of the bump bond structure and may be formed from one or more metals, including but not limited to gold, titanium, chromium, platinum, or combinations thereof, to promote adhesion and / or act as a barrier layer to prevent the formation of native oxides that naturally occur on most metals. The bump bond structure 30 may be formed of a conductive metal, such as gold or copper, or may be formed of a non-conductive material if not used to transfer electrical or thermal energy. The bump bond structure 30 may be configured for mechanical attachment and / or to transfer electrical signals and / or thermal energy.

[0012] In one example, the first UBM layer 18 and the second UBM layer 28 may each have a thickness of 100 Å (10 nm) to about 5000 Å (500 nm). In one example, the first UBM layer 18 and the second UBM layer 28 may each be formed of a 350 Å (35 nm) / 3000 Å (300 nm) thick titanium / gold stack. The bump bond structure 30 may be formed of gold. Prior to compression bonding, the bump 20 may have a size of 10 μm×10 μm (surface area of ​​100 μm 2 ), and 3 μm high. The mini-bumps 32 are 2 μm×2 μm (surface area 4 μm 2), and may be 2 μm high. This provides a surface area ratio of about 25:1 between the bump 20 and the mini-bump 32. In one example, the second electronic device 22 and the first electronic device 12 may be bonded using a thermal compression flip chip process at 150° C. or less, where a large bonding force is applied first to compress the mini-bump 32 into the larger bump 20. Once the mini-bump 32 is fully compressed and / or crushed into the larger bump 20, the increased surface contact area with the larger bump 20 reduces the force applied per unit area by about 25 times, thus avoiding compression of the larger bump 20. Here, the larger bump 20 acts as a stop to maintain a fixed separation between the first electronic device 12 and the second electronic device 22.

[0013] In this example, a surface area of ​​approximately 25:1 is shown, however other surface area ratios (e.g., 10:1, 20:1, 30:1, 40:1, 50:1) may be employed based on the compressive force applied in the flip chip bonding process. Additionally, the thickness of the mini-bumps and larger bumps may vary based on the particular design and temperature.

[0014] Fabrication will now be described with reference to Figures 3-6 in connection with forming a bump bond structure similar to that shown in Figures 1-2. It should be understood that this example is described with reference to a process flow for forming a bump bond structure for bonding two electronic devices together. The process flow begins with providing a first electronic device (e.g., a wafer having a plurality of first ICs, the first IC) with a top surface of conductive contact pads, and providing a second electronic device (e.g., the second IC) with a bottom surface of conductive contact pads. This example is further described with reference to depositing a UBM metal layer on the conductive contact pads to provide an adhesion layer between the conductive contact pads and the bonding layer of the bump bond structure.

[0015] FIG. 3 is a cross-sectional view of a multi-chip system at an early stage of fabrication. The multi-chip system includes a first electronic device 50 (e.g., a first IC or a first substrate wafer) that may include conventional and / or conductive circuits for performing multiple circuit functions. A portion of the circuit or vias may be connected to one or more first conductive contact pads 52 via one or more conductive lines (not shown) to share functions and / or signals with a second electronic device 60. The one or more conductive contact pads 52 may be formed of a conductive metal, including but not limited to gold or copper. The first electronic device 50 may be a first substrate wafer having a plurality of first ICs cut into individual first ICs from the first substrate wafer, or the first electronic device 50 may be a first IC. For ease of explanation, the explanation refers to the first electronic device 50 rather than the first IC or the first substrate wafer.

[0016] The second electronic device 60 (e.g., a second IC or a second substrate wafer) may include conventional and / or conductive circuitry for performing multiple circuit functions. Portions of the circuitry may be connected to one or more conductive contact pads 62 via one or more conductive lines (not shown) for sharing functions and / or signals with one or more other ICs. The one or more conductive contact pads 62 may be formed of a conductive metal such as gold or copper. The second electronic device 60 may be a second substrate wafer that may include multiple second ICs that are cut into individual second ICs from the second substrate wafer, or may be a second IC.

[0017] The one or more conductive contact pads 52 on the top surface of the first electronic device 50 each include an overlying first UBM layer 54. The first UBM layer 54 may be a metal layer having a thickness of about 100 Å (10 nm) to about 5000 Å (500 nm) to promote adhesion and / or act as a barrier to prevent the formation of native oxides that naturally occur in most metals. In addition, the first UBM layer 54 may be formed from metals including, but not limited to, gold, titanium, chromium, platinum, or combinations thereof. The thickness of the first UBM layer 54 may be selected such that the first UBM layer 54 can have similar conductive properties as the one or more conductive contact pads 52. The first UBM layer 54 may be deposited using standard contact material deposition methods such as evaporation or sputtering.

[0018] The one or more conductive contact pads 62 on the bottom surface of the second electronic device 60 each include an underlying second UBM layer 64. The second UBM layer 64 may be one or more metal layers having a total thickness of about 100 Å (10 nm) to about 5000 Å (500 nm) to promote adhesion and / or act as a barrier to prevent the formation of native oxides that naturally occur with most metals. In addition, the second UBM layer 64 may be formed from one or more metals including, but not limited to, gold, titanium, chromium, platinum, or combinations thereof. The thickness of the second UBM layer 64 may be selected such that the second UBM layer 64 can have similar conductive properties as the one or more conductive contact pads 62. The second UBM layer 64 may be deposited using standard contact material deposition methods such as evaporation or sputtering.

[0019] The bump bonding process forms multiple bump bond structures, but in this example, a single bump bond structure is formed for ease of explanation. Although this process can be used for non-conductive bump bond structures forming spacers or standoffs, this example refers to a conductive bump bond structure. The first electronic device 50 includes a conductive bump 56 that resides on a first UBM layer 54, and the second electronic device 60 includes a conductive mini-bump 66 that resides below or on and in contact with a second UBM layer 64. The surface area of ​​the conductive bump 56 to the surface area of ​​the conductive mini-bump 66 has a surface area ratio of about 10:1 to about 50:1 (e.g., about 25:1). The conductive bump 56 can have a height (e.g., 3 μm) that is greater than the height of the conductive mini-bump 66 (e.g., 2 μm).

[0020] Next, as shown in FIG. 4, the first electronic device 50 and the second electronic device 60 undergo a bump bonding process in which the outer bottom surface of the conductive mini-bump 66 of the second electronic device 60 is brought into contact with the outer top surface of the conductive bump 56 of the first electronic device 50. This can be accomplished in a relatively low temperature environment, e.g., about 50° C. to about 250° C. (e.g., 150° C.), compared to the typical bonding temperatures (e.g., 300° C. to 450° C.) of the conductive materials (e.g., gold, copper) of the conductive bump 56 and the conductive mini-bump 66. As shown in FIG. 4, a compressive force 100 is applied to the top surface of the second electronic device 60 to begin compressing the conductive mini-bump 66 into the conductive bump 56. The compressive force may be in the range of about 50 Newtons to about 250 Newtons (e.g., 150 Newtons). Alternatively, the compressive force may be applied from the bottom of the first electronic device 50 , or may be a combination of forces exerted from both the top surface of the second electronic device 60 and the first electronic device 50 .

[0021] FIG. 5 shows the conductive mini-bump 66 being partially compressed into the conductive bump 56 as a compressive force 100 continues to be applied to the top surface of the second electronic device 60. As the conductive mini-bump 66 is compressed, the surface area of ​​the conductive mini-bump 66 increases relative to the conductive bump 56, resulting in a redistribution of the pressure over the increased surface area. Finally, as shown in FIG. 6, the conductive mini-bump 66 is fully compressed into the conductive bump 56 to form the bump bond structure 68, resulting in a redistribution of the pressure from a surface area ratio of about 25:1 to a surface area ratio of about 1:1. As a result, the conductive bump 56 acts as a stop if the compressive force 100 is selected such that the conductive bump 56 is not compressed when the conductive mini-bump 66 is fully compressed. The final structure is the bump bond structure 68, which is a cold weld between the conductive mini-bump 66 and the conductive bump 56.

[0022] The compression bonding process of forming the bump bond structure 68 from the combination of the conductive mini-bumps 66 and the conductive bumps 56 can be combined with other bump bond structures and processes. For example, the bump bond structure 68 and process can be combined with a bump bonding process that forms a low melting point bump bond structure.

[0023] 7 is a cross-sectional view of a multi-chip system 75 that uses both bump bond structures and low melting point bump bond structures. The multi-chip system 75 includes a first electronic device 80 (e.g., a bottom or main device) connected to a second electronic device 96 (e.g., a top or auxiliary device) via a plurality of bump bond structures 82 and a plurality of low melting point bump bond structures 84. Although the second electronic device 96 is shown as a top device, multiple top devices can be bonded to one bottom or main device. The electronic devices can be substrate wafers, packaged devices for passing signals to another device, integrated circuits (ICs), or various other types of electronic devices.

[0024] Each of the bump bond structures 82 is formed of a mini-bump compressed into a bump, as shown in Figures 2 and 6. Each of the low melting point bump bond structures 84 is formed of a first UBM layer 88 covering a first contact pad 86, a second UBM layer 94 covering a second contact pad 92, and a low melting point bump layer 90 bonding the first UBM layer 88 to the second UBM layer 94. The first UBM layer 88 and the second UBM layer 94 promote adhesion and / or act as barrier layers to prevent the formation of native oxides that naturally occur with most metals, and may be formed from metals including, but not limited to, gold, titanium, chromium, platinum, or combinations thereof.

[0025] In one example, the low melting point bump bond structure 84 is formed of indium. The indium bump bond structure can easily bond the first electronic device 80 and the second electronic device 96 at temperatures of about 150° C. or less, and can be bonded at the same time that the bump bond structure 82 is formed by compressing the mini-bumps into a larger bump, as described in the process shown in FIGS. 3-6. The bump bond structure can be formed of conductive or non-conductive materials, such as gold or copper. Additionally, multiple other materials and low melting point materials can be used to provide the bump bond structure and low melting point bump bond structure as shown in FIG. 7.

[0026] For ease of explanation, the terms "place over," "on top," "place under," and "under" (and derivatives) are used throughout this disclosure to indicate the relative position of two adjacent surfaces in a selected orientation. Additionally, the terms "top" and "bottom" used throughout this disclosure indicate opposite surfaces in a selected orientation. Similarly, the terms "above" and "below" indicate relative positions in a selected orientation for purposes of explanation. Indeed, the examples used throughout this disclosure show one selected orientation. However, in the examples described, the selected orientation is arbitrary, and other orientations (e.g., upside down, rotated 90 degrees, etc.) are possible within the scope of this disclosure.

[0027] The above are examples of the present disclosure. Of course, it is not possible to describe every conceivable combination of components or methods for purposes of describing the present disclosure, but one skilled in the art will recognize that many further combinations and permutations of the present disclosure are possible. Therefore, the present disclosure is intended to embrace all such changes, modifications, and variations that fall within the spirit and scope of the appended claims. In addition, when the present disclosure or claims recite "a," "first," or "another" element, or the equivalent thereof, it should be construed as including one or more such elements, and does not require or exclude two or more such elements. Furthermore, to the extent that the term "comprises" is used in either the detailed description or the claims, such term is intended to be inclusive, in the same manner as the term "comprises" is construed when employed as a transitional term in the claims. Finally, the term "based on" is construed to mean based at least in part on.

Claims

1. 1. A method of forming a multi-chip system, comprising: forming one or more bumps on each conductive contact pad of the first electronic device; forming one or more mini-bumps on each conductive contact pad of the second electronic device; aligning each of the one or more mini-bumps with each of the one or more bumps; performing a bump bonding process applying a compressive force to one or both of the first electronic device and the second electronic device to compress the one or more mini-bumps into the one or more bumps to form one or more bump bond structures that bond the second electronic device to the first electronic device. A method comprising:

2. 10. The method of claim 1, wherein the temperature of the bump bonding process is less than or equal to 150 degrees Celsius.

3. The method of claim 1 , wherein each of the one or more bumps and the one or more mini-bumps is formed from a material selected from the group including gold, copper, or a non-conductive material.

4. 2. The method of claim 1, wherein an initial surface area of ​​a given bump of the one or more bumps to a given mini-bump of the one or more mini-bumps prior to performing the bump bonding process ranges from about 10:1 to about 50:

1.

5. 5. The method of claim 4, wherein an initial surface area ratio of the given bump of the one or more bumps to the given mini-bump of the one or more mini-bumps prior to performing the bump bonding process is approximately 25:

1.

6. 2. The method of claim 1, wherein the compression force of the bump bonding process is selected to enable each of the one or more bumps to act as a compression stop when the respective one or more mini-bumps are substantially compressed into the respective one or more bumps.

7. 10. The method of claim 1, further comprising forming a first under bump metallization (UBM) layer between each of the one or more bumps and their respective conductive contacts, and forming a second UBM layer between each of the one or more mini-bumps and their respective conductive contact pads.

8. 8. The method of claim 7, wherein the first UBM layer and the second UBM layer each have a thickness of about 100 Å to about 5000 Å to promote adhesion and provide similar properties to an underlying conductive contact pad.

9. 8. The method of claim 7, wherein each of the first UBM layer and the second UBM layer may be formed of a 350 Å / 3000 Å thick titanium / gold stack.

10. 8. The method of claim 7, wherein each of the first UBM layer and the second UBM layer is formed from one or more conductive materials selected from the group including gold, titanium, chromium, and platinum.

11. 10. The method of claim 1, further comprising forming one or more low melting point bump bond structures between the first electronic device and the second electronic device simultaneously with forming the one or more bump bond structures.

12. The method of claim 11 , wherein each of the one or more low melting point bump bond structures is formed from indium.

13. 1. A multi-chip system, comprising: a first electronic device having a plurality of first conductive contact pads disposed on a top surface of the first electronic device; a second electronic device having a plurality of second conductive contact pads disposed on a bottom surface of the second electronic device; Multiple bump bonding structures a given bump bonding structure couples a respective one of the plurality of first conductive contact pads to a respective one of the plurality of second conductive contact pads to bond the first electronic device to the second electronic device, each of the plurality of bump bonding structures including a mini-bump compressed within a bump.

14. 14. The system of claim 13, wherein the bumps and mini-bumps of each of the plurality of bump bonding structures are selected from a group including gold, copper, or a non-conductive material.

15. 14. The system of claim 13, wherein an initial surface area of ​​a given bump of the plurality of bump bonding structures to a given mini-bump of the plurality of bump bonding structures before each mini-bump is compressed into a respective bump ranges from about 10:1 to about 50:

1.

16. 14. The system of claim 13, further comprising: a first under bump metallization (UBM) layer disposed between a bump bonding surface of each of the plurality of bump bonding structures and its respective conductive contact; and a second UBM layer disposed between a mini-bump surface of each of the plurality of bump bonding structures and its respective conductive contact pad.

17. 17. The system of claim 16, wherein the first UBM layer and the second UBM layer each have a thickness of about 100 Å to about 5000 Å to promote adhesion and provide similar properties to an underlying conductive contact pad.

18. 17. The system of claim 16, wherein the first UBM layer and the second UBM layer are formed from one or more conductive materials selected from the group including gold, titanium, chromium, and platinum.

19. The system of claim 13 , further comprising one or more low melting point bump bond structures coupling the first electronic device and the second electronic device.

20. 20. The system of claim 19, wherein each of the one or more low melting point bump bond structures is formed from indium.

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