Apparatus and method for fabricating switched-capacitor circuits - Patents.com

Abstract

Disclosed embodiments may include an apparatus having a first device layer having a first switch, a second device layer having a second switch, and a third device layer disposed between the first device layer and the second device layer. The third device layer has a first capacitor. The first switch and the second switch are interconnected with the first capacitor to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 364,569, filed May 12, 2022, and U.S. Provisional Patent Application No. 63 / 364,674, filed May 13, 2022, the entire contents of which are incorporated herein by reference for all purposes.

[0002] The present disclosure relates generally to power electronic devices and, more particularly, to power converters. [Background technology]

[0003] Today's central processing units (CPUs) are evolving to provide greater computational performance, such as artificial intelligence (AI) processing and cloud computing applications, which in turn increases the demand for power from the power supply. As a result, the power converters in the power supply may occupy significant space to meet the increasing current requirements of the CPU. Therefore, designing compact, high-density power converters to reduce the required circuit area while meeting the increased current and space requirements has become a challenge in the field. Summary of the Invention

[0004] An embodiment of the present disclosure provides an apparatus having a first device layer having a first switch, a second device layer having a second switch, and a third device layer disposed between the first device layer and the second device layer. The third device layer has a first capacitor. The first switch and the second switch are interconnected with the first capacitor to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch.

[0005] An embodiment of the present disclosure provides an apparatus. The apparatus includes a cell and a phase device cell. Each of the cells includes a capacitor and a first switch. The phase device cell includes a second switch. The cells are stacked vertically above the phase device cell. The capacitor and the first switch in each cell are interconnected with the second switch to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the second switch in each cell.

[0006] An embodiment of the present disclosure provides a method of fabricating a switched-capacitor circuit, the method including the steps of providing a first device layer, disposing a third device layer on the first device layer, interconnecting a first capacitor in the third device layer with a first switch in the first device layer, disposing a second device layer on the third device layer, and interconnecting a second switch in the second device layer with the first capacitor.

[0007] An embodiment of the present disclosure provides a method for fabricating a switched capacitor circuit, the method comprising the steps of providing a phase device cell including a phase switch of the switched capacitor circuit, and vertically stacking the cells on the phase device cell, each of the cells having a capacitor and a stack switch, the capacitor and stack switch in each of the cells being interconnected with the phase switch.

[0008] Additional features and advantages of the disclosed embodiments will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the embodiments. The features and advantages of the disclosed embodiments may be realized and attained by means of the elements and combinations recited in the claims. [Brief description of the drawings]

[0009] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and the accompanying drawings. It should be noted that, according to industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. [Figure 1] FIG. 1 illustrates an example power converter in accordance with some embodiments of the present disclosure. [Figure 2A] ~ [Figure 2B] FIG. 2 illustrates an example switched-capacitor circuit in accordance with some embodiments of the present disclosure. [Figure 3A] ~ [Figure 3D] FIG. 1 illustrates an exemplary structure according to some embodiments of the present disclosure. [Figure 4A] ~ [Figure 4C] FIG. 2 illustrates an exemplary passive device layer according to some embodiments of the present disclosure. [Figure 4D] FIG. 2 illustrates an exemplary active device layer with a shaped interconnect substrate according to some embodiments of the present disclosure. [Diagram 5] FIG. 2 illustrates an example switched-capacitor circuit in accordance with some embodiments of the present disclosure. [Figure 6A] FIG. 1 illustrates an exemplary structure according to some embodiments of the present disclosure. [Figure 6B] FIG. 2 illustrates an example sub-structure according to some embodiments of the present disclosure. [Figure 7] FIG. 1 illustrates an exemplary structure according to some embodiments of the present disclosure. [Figure 8A] ~ [Figure 8B] 1A-1C each illustrate an example cell, according to some embodiments of the present disclosure. [Figure 9] 8B illustrates an example structure of the cell of FIG. 8A according to some embodiments of the present disclosure. [Figure 10] FIG. 2 illustrates another example cell, according to some embodiments of the present disclosure. [Figure 11A]1A-1C are cross-sectional views of exemplary portions of LC networks according to some embodiments of the present disclosure. [Figure 11B] 1 is a cross-sectional view of an exemplary portion of another LC network according to some embodiments of the present disclosure. [Figure 12] FIG. 1 illustrates an example power converter in accordance with some embodiments of the present disclosure. [Figure 13] FIG. 2 illustrates an exemplary power converter package according to some embodiments of the present disclosure. [Figure 14] 1 is a flowchart of a method for fabricating a switched-capacitor circuit according to some embodiments of the present disclosure. [Figure 15] 4 is a flowchart of another method of fabricating a switched-capacitor circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The following disclosure provides many different exemplary embodiments or examples for implementing different features of the provided subject matter. To explain the present disclosure, certain simplified examples of components and devices are described below. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0011] The terms used herein generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples herein, including examples of any term discussed herein, is illustrative only and does not limit in any way the scope and meaning of the disclosure or any exemplified term. Similarly, the disclosure is not limited to the various embodiments provided herein.

[0012] Terms such as "first", "second", etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the embodiment. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0013] Additionally, spatially relative terms such as "lower," "below," "bottom," "upper," "top," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature illustrated in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] As used herein, the term “connected” can also be referred to as “electrically connected,” and the term “coupled” can also be referred to as “electrically coupled.” “Connected” and “coupled” can also be used to indicate that two or more elements cooperate or interact with each other.

[0015] Various embodiments of the present disclosure are described with respect to embodiments in a particular context, namely, in charge pump circuits. As used in this disclosure, the term "charge pump" refers to a switched capacitor network configured to convert an input voltage to an output voltage. Examples of such charge pumps include cascade multiplier, Dickson, ladder, series-parallel, Fibonacci, and Doubler switched capacitor networks, all of which may be configured as multi-phase or single-phase networks.

[0016] However, the concepts in this disclosure may be applied to other types of power converters. A power converter that converts a higher input voltage source to a lower output voltage level is commonly known as a step-down converter or buck converter because the converter is "bucking" the input voltage. A power converter that converts a lower input voltage source to a higher output voltage level is commonly known as a step-up converter or boost converter because the converter is "boosting" the input voltage. Additionally, some power converters, commonly known as "buck-boost converters," may be configured to convert an input voltage source to a wide range of output voltages, where the output voltage may be higher or lower than the input voltage. In various embodiments, the power converter may be bidirectional and may be either a boost or a buck converter depending on how the power source is connected to the converter. An AC-DC power converter may be constructed from a DC-DC power converter, for example, by first rectifying the AC input voltage to a DC voltage and then applying the DC voltage to the DC-DC power converter.

[0017] High density integrated switched capacitor power converters may be desirable in applications including, but not limited to, data centers, portable electronic devices such as tablets, cell phones or handheld computers, and Internet of Things (IoT) devices. In particular, modern high performance microprocessors may include billions of transistors switching at several gigahertz and / or consuming hundreds of amps of current at relatively low voltages (e.g., less than 1.0 V in some situations). Furthermore, the power consumption characteristics of modern microprocessors are growing along with increased computing performance, creating challenges for on-board point-of-load (PoL) converters and / or data center power supplies. High efficiency, high power density, and high bandwidth PoL converters may be required to support hundreds of amps of current (e.g., more than 50.0 A in some situations) delivered at relatively low voltages (e.g., less than 1.0 V). Such PoL converters may operate at relatively high voltage conversion ratios (e.g., greater than 10:1) to support current and / or future high performance microprocessors. The data center industry may also be migrating from 12V bus architectures to 48V buses due to increasing server power consumption, which may enable overall efficiency improvements and / or lower costs. Providing power at 48V may also leverage, for example, the existing 48V telecom power ecosystem. Drawing energy from a relatively high wide range of input voltages (e.g., between 40.0V-60.0V) may be advantageous for supporting high performance microprocessors and / or for supporting telecom loads, while power converters capable of providing lower voltage outputs (e.g., less than 1.0V) may be regulated with a relatively high bandwidth. The size, cost, and / or performance advantages offered by integration make it desirable to design modular and / or compact dc-dc converters that can be relatively easily sized and / or tailored for a variety of applications having different voltage and / or current needs.

[0018] Please refer to FIG. 1. FIG. 1 is a diagram illustrating an example power converter 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the power converter 100 can include a device 110a that provides a power module. As used herein, a power module can refer to a physical unit or apparatus that includes power and electronic components of a power conversion circuit. The device 110a includes a switched capacitor circuit 112 (also known as a charge pump circuit) and a controller circuit 114 configured to control the operation of the switched capacitor circuit 112. In particular, the controller circuit 114 can include, among other components, a control circuit, a timing circuit, a protection circuit, and a gate driver configured to operate a switch, which can change the electrical configuration of the capacitor of the switched capacitor circuit 112 between a first mode / state or a second mode / state.

[0019] In the embodiment of FIG. 1, the power converter 100 is configured to receive energy from an input voltage source 102 at an input voltage V1 and deliver the energy to an output load 104 at an output voltage V2. In some embodiments, the input voltage V1 may be higher than the output voltage V2. The switched capacitor circuit 112 is configured to convert the input voltage V1 to the output voltage V2. In some embodiments, multiple power modules can be placed in parallel within the power converter 100 to achieve a higher power rating based on low-cost and low-rated devices. Thus, the modular design also provides flexibility and scalability of the power conversion circuit to meet various needs of the power supply system in various applications.

[0020] In various embodiments, the controller circuit 114 in the device 110a may be an internal master controller or a slave controller configured to communicate with a master controller in the power system. In some other embodiments, the switched capacitor circuit 112 in the device 110a may also be controlled by an external master controller connected to the device 110a. The controller circuit 114 may be fabricated on a semiconductor substrate such as silicon, gallium nitride (GaN), silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-on-glass (SOG), silicon-on-quartz (SOQ), among others, using semiconductor processing techniques corresponding to complementary metal oxide semiconductor (CMOS) fabrication. The controller circuit 114 may be physically integrated with the switches in the switched capacitor circuit 112, either on the same substrate (e.g., an on-chip configuration) or as an off-chip component configured to operate the switches in the switched capacitor circuit 112.

[0021] 1, in some embodiments, the input terminals V1p, V1n are connected to the input voltage source 102 to receive the input voltage V1, and the output terminals V2p, V2n are connected to the output load 104 to output the output voltage V2. In addition, some input terminals of the controller circuit 114, such as a PG terminal for receiving a "Power Good" signal or a CLK terminal for receiving a clock signal, can be connected to other external circuits or devices for receiving a PG signal and a clock signal. Similarly, the IO pins of the device 110a can be connected to the output load 104 to receive an output voltage V2. in and I.O. out may also be connected to a corresponding circuit or device to facilitate operation of the circuit. In this disclosure, the terms "node" and "terminal" may be used interchangeably.

[0022] FIG. 2A illustrates an exemplary switched-capacitor circuit 200a according to some embodiments of the present disclosure. As shown in FIG. 2A, in some embodiments, the switched-capacitor circuit 200a may be a multi-phase switched-capacitor circuit, such as a two-phase variant of a Dickson charge pump, also known as a cascaded multiplier. In some embodiments, the switched-capacitor circuit 200a of FIG. 2A may be used for the switched-capacitor circuit 112 in the device 110a of FIG. 1, although the present disclosure is not limited thereto. It is understood that in various embodiments, the switched-capacitor circuit may also be a single-phase circuit or a multi-phase circuit and may be designed based on a desired conversion ratio. In the embodiment of FIG. 2A, a conversion ratio of 4:1 may be obtained. In general, in a Dickson topology, different conversion ratios V1 / V2 (e.g., a 3:1 conversion ratio, a 5:1 conversion ratio, etc.) may be obtained by using different numbers of capacitors and different numbers of switches. As the magnitude of the desired conversion ratio increases, the number of capacitors and switches used in the power converter may increase.

[0023] In the embodiment of FIG. 2A, the switched capacitor circuit 200a includes a stack switch 210 for a first phase, a stack switch 220 for a second phase, a phase switch 230 shared by both phases, a first set of capacitors 240 associated with the first phase and having first capacitors C1A, C2A, and C3A connected to the stack switch 210, and a second set of capacitors 250 associated with the second phase and having second capacitors C1B, C2B, and C3B connected to the stack switch 220. The stack switch 210 associated with the first phase includes switches S1A, S2A, S3A, and S4A. The stack switch 220 associated with the second phase includes switches S1B, S2B, S3B, and S4B. The phase switch 230 includes switches S5, S6, S7, and S8. Thus, switched capacitor circuit 200a provides a switching network that transitions between a first state and a second state depending on which of the switches are open and which are closed. The first switch configuration transitions the switched capacitor network from the first state to the second state. The second switch configuration transitions the switched capacitor network from the second state to the first state. As the switches switch the switched capacitor network between these states, capacitors 240 and 250 are charged or discharged in a charge pump cycle to complete the power conversion and transfer power from the source to the load.

[0024] In the design shown in FIG. 2A, the switching network has two switch chains, i.e., switches connected in series. In particular, stack switches S1A, S2A, S3A, and S4A form one switch chain associated with a first phase, while stack switches S1B, S2B, S3B, and S4B form another switch chain associated with a second phase. The stack switches S1A, S2A, S3A, and S4A are connected to the positive terminals of first capacitors C1A, C2A, and C3A associated with the first phase, respectively, via corresponding dc nodes. Similarly, the stack switches S1B, S2B, S3B, and S4B are connected to the positive terminals of second capacitors C1B, C2B, and C3B associated with the second phase, respectively, via corresponding dc nodes.

[0025] The phase switches S5 and S6 are connected to the negative terminals of the first and second capacitors C1B, C2A, and C3B via a first phase node P1, while the phase switches S7 and S8 are connected to the negative terminals of the first and second capacitors C1A, C2B, and C3A via a second phase node P2. In other words, the first phase node P1 is connected to the negative terminals of a first subset of the first capacitors (e.g., capacitor C2A) and a first subset of the second capacitors (e.g., capacitors C1B and C3B), while the second phase node P2 is connected to the negative terminals of a second subset of the first capacitors (e.g., capacitors C1A and C3A) and a second subset of the second capacitors (e.g., capacitor C2B).

[0026] In operation, the switches S1A, S2B, S3A, S4B, S6, and S7, shown as group 1 in FIG. 2A, and the switches S1B, S2A, S3B, S4A, S5, and S8, shown as group 2 in FIG. 2A, may be in complementary states. For example, in a first state, in response to a command from the controller circuit, the switches S1A, S2B, S3A, S4B, S6, and S7 may be open, and the switches S1B, S2A, S3B, S4A, S5, and S8 may be closed. In a second state following the first state, in response to a command from the controller circuit, the switches S1A, S2B, S3A, S4B, S6, and S7 may be closed, and the switches S1B, S2A, S3B, S4A, S5, and S8 may be open. Furthermore, a dead time interval may exist between the first state and the second state. During the dead time, all switches are open, thereby ensuring a clean transition between the two switch states. It will be appreciated that the present disclosure is not limited to such ratios or types of conversion circuits. In various embodiments, the buck or boost configurations can be applied to all possible charge pump ratios.

[0027] 2B is a diagram illustrating another exemplary switched-capacitor circuit 200b according to some embodiments of the present disclosure. As shown in FIG. 2B, in some embodiments, the switched-capacitor circuit 200b may further include a first set of inductors 260 having first inductors L1A, L2A, and L3A associated with a first phase and connected between corresponding capacitors C1A, C2A, and C3A and the phase switch 230, respectively, and a second set of inductors 270 having second inductors L1B, L2B, and L3B associated with a second phase and connected between corresponding capacitors C1B, C2B, and C3B and the phase switch 230, respectively.

[0028] As shown in Figure 2B, various circuit topologies can be used in the present disclosure to form different types of power converters, such as hybrid converters, resonant switched capacitor converters, or multilevel power converters having transistors, capacitors, and one or more inductors as energy storage elements, or converters with LC filters connected with switched capacitor networks to facilitate adiabatic charging or discharging, etc. In particular, hybrid converters, such as multilevel power converters or series capacitor buck converters, also include switched capacitor circuits combined with different topologies.

[0029] FIG. 3A illustrates an exemplary structure 300a according to some embodiments of the present disclosure. The structure 300a can be used to implement the switched-capacitor circuit 200a shown in FIG. 2A. As shown in FIG. 3A, multiple layers 310-350 are stacked vertically, i.e., along the z-direction perpendicular to the substrate, on top of each other in the structure 300a. In particular, the structure 300a includes active device layers 310, 330, and 350 and passive device layers 320 and 340. The stacking configuration can include alternating stacking of the active device layers 310, 330, and 350 and the passive device layers 320 and 340, although the present disclosure is not limited thereto.

[0030] In some embodiments, the active device layers 310, 330, and 350 may comprise, but are not limited to, switching elements (e.g., switches 210, 220, and 230 of FIG. 2A) fabricated on a semiconductor substrate, such as bulk silicon, doped silicon, GaN, GaAs, or SOI. The stack switches 210 and 220 and the phase switch 230 may be implemented by field effect transistors, bipolar junction transistors, diodes, or other electrical devices. In some embodiments, one or more of the active device layers 310, 330, and 350 may further comprise control circuitry (e.g., controller circuit 114 of FIG. 1) fabricated on the same semiconductor substrate as the switching elements, such that the controller circuitry 114 is physically integrated with the switches. In some embodiments, the passive device layers 320 and 340 may comprise passive devices including capacitors (e.g., capacitors 240 and 250 of FIG. 2A) or resistors fabricated on the substrate. The substrate may include, but is not limited to, glass, quartz, silicon, SOI, SOS, SOG, SOQ, ceramic (alumina, aluminum nitride, sapphire), or composite materials, among other substrate materials.

[0031] In the structure 300a, the passive device layer 320 is disposed between the active device layer 310 and the active device layer 330. Specifically, the passive device layer 320 is stacked above the active device layer 310, which may be a bottom layer. The active device layer 330 is stacked above the passive device layer 320. In some embodiments, the active device layer 310 comprises a first switch (e.g., stack switch 210 of FIG. 2A associated with the first phase). The passive device layer 320 comprises a first capacitor (e.g., capacitor 240 of FIG. 2A associated with the first phase). The active device layer 330 comprises a second switch (e.g., phase switch 230 of FIG. 2A shared by the first and second phases). By providing conductive features (e.g., contacts), the stack switches 210 in the active device layer 310 and the phase switches 230 in the active device layer 330 can be interconnected with the capacitors 240 in the passive device layer 320 to form a switched capacitor circuit for the first phase shown in Figure 2A. As previously described in Figure 2A, the switched capacitor circuit transitions between at least two states in response to switching of the stack switches 210 and the phase switches 230.

[0032] Similarly, the passive device layer 340 is disposed between the active device layer 330 and the active device layer 350 to form a switched capacitor circuit for the second phase shown in FIG. 2A. Thus, the phase switch 230 in the active device layer 330 may be shared by the two phases and interconnected with both the capacitors 240 and 250. Specifically, the passive device layer 340 is stacked above the active device layer 330, and the active device layer 350, which may be the top layer, is stacked above the passive device layer 340. As used herein, the "bottom" layer is the layer closest to the substrate providing the electrical interface, and the "top" layer is the layer furthest from the substrate.

[0033] The active device layer 350 includes a third switch (e.g., stack switch 220 of FIG. 2A associated with the second phase). The passive device layer 340 includes a second capacitor (e.g., capacitor 250 of FIG. 2A associated with the second phase). By providing conductive features (e.g., contacts), the stack switch 220 in the active device layer 350 and the phase switch 230 in the active device layer 330 can be interconnected with the capacitor 250 in the passive device layer 340 to form a switched capacitor circuit for the second phase shown in FIG. 2A.

[0034] Thus, the structure 300a can form a multi-phase switched capacitor circuit (e.g., the two-phase switched capacitor circuit 200a of FIG. 2A) that transitions between at least two states depending on switching of the stack switches 210, 220 and the phase switch 230 located in different active device layers. In this embodiment, the first switch in the bottom layer (e.g., the active device layer 310) may be the stack switch 210 associated with the first phase. The third switch in the top layer (e.g., the active device layer 350) may be the stack switch 220 associated with the second phase. A second switch in the intermediate layer (e.g., active device layer 330) is a phase switch 230 for both the first phase and the second phase and couples (connects) a first capacitor in one layer (e.g., passive device layer 320) stacked below the intermediate layer and a second capacitor in another layer (e.g., passive device layer 340) stacked above the intermediate layer to a shared phase node of the switched capacitor circuit (e.g., phase nodes P1 and P2 in FIG. 2A ).

[0035] It should also be noted that in other embodiments, structure 300a may have multiple passive device layers stacked on a single active device layer, or multiple active device layers stacked on a single passive device layer, or a stack including at least one of a passive device layer, an interconnect layer, and an active device layer. For example, structure 300a may further include an interconnect layer to provide electrical connection between the active device layer and the passive device layer, or an interconnect layer to provide electrical connection between devices in the active device layer via metal lines.

[0036] 3B illustrates another exemplary structure 300b according to some embodiments of the present disclosure. Compared to the embodiment of FIG. 3A, as shown in FIG. 3B, a controller layer 360 having the circuitry of the controller circuit 114 can be disposed as a bottom layer, and the device layers 310-350 are stacked above the controller layer 360. The controller circuit 114 in the controller layer 360 can connect with the switches in the device layers 310, 330, and 350 through contacts and vias, thereby providing control signals for controlling the stack switches and phase switches per phase. Thus, the structure 300b can be used to implement the device 110a shown in FIG. 1.

[0037] 3C is a diagram illustrating another exemplary structure 300c according to some embodiments of the present disclosure. Compared with the embodiment of FIG. 3A and FIG. 3B, in the structure 300c, the device layers 310, 330, and 350 can each include a corresponding control circuit for controlling the switching of the stack switches or phase switches in the same device layer. In some embodiments, the control circuits in these device layers 310, 330, and 350 can communicate with each other through contacts and vias, and can collectively perform the operation of the controller circuit 114 to provide control signals for each phase. Thus, the structure 300c can also be used to implement the device 110a shown in FIG. 1.

[0038] 3D illustrates another exemplary structure 300d according to some embodiments of the present disclosure. Compared with the embodiment of FIGS. 3A-3C, the structure 300d further includes additional passive device layers 370 and 380. The passive device layers 370 and 380 are inductor layers including the inductors 260 and 270 of FIG. 2B, respectively. For example, the passive device layer 370 can be stacked between the passive device layer 320 and the active device layer 330, so that the inductors in the passive device layer 370 (e.g., the first inductors L1A, L2A, and L3A of FIG. 2B) are coupled (connected) between the corresponding capacitors in the passive device layer 320 (e.g., the first capacitors C1A, C2A, and C3A of FIG. 2B) and the phase switch 230 in the active device layer 330.

[0039] Similarly, the passive device layer 380 is stacked between the passive device layer 340 and the active device layer 330, so that the inductors in the passive device layer 380 (e.g., the second inductors L1B, L2B, and L3B in FIG. 2B) are coupled (connected) between the corresponding capacitors in the passive device layer 340 (e.g., the second capacitors C1B, C2B, and C3B in FIG. 2B) and the phase switch 230 in the active device layer 330. Thus, the structure 300d can also be used to implement the switched capacitor circuit 200b shown in FIG. 2B. It should be noted that in other alternative embodiments, the passive device layer 370 can be stacked between the passive device layer 320 and the active device layer 310, and the passive device layer 380 can be stacked between the passive device layer 340 and the active device layer 350. The structure 300d in FIG. 3D is an example and is not intended to limit the present disclosure.

[0040] In various embodiments, the passive device layers 320 and 340 can be implemented in different ways to provide vertical capacitors that couple between the phase switches and stack switches, reducing routing distances and reducing parasitic inductances in the circuit. FIGS. 4A-4C are diagrams illustrating exemplary passive device layers 400a, 400b, and 400c, according to some embodiments of the present disclosure. In some embodiments, the capacitors C1, C2, C3-Cn embedded in each passive device layer 400a, 400b, or 400c may be multi-layer ceramic capacitors (MLCCs). MLCCs can store electrical energy in multiple ceramic layers with high dielectric constants. For example, Barium Titanate (BaTiO 3 ) can be selected as the dielectric. In the construction of MLCCs, multiple metal electrodes and ceramic layers are stacked alternately within the capacitor. The internal electrodes are arranged in an interdigitating pattern, with adjacent electrodes extending to opposite terminals while non-adjacent electrodes extend to the same terminal. On each terminal, a metallized coating applied to the outer surface, called an end termination, electrically connects the exposed electrode edges. MLCCs exhibit high capacitance, small size, low cost, high reliability, and excellent high frequency characteristics, and can be widely used in different applications.

[0041] As shown in FIG. 4A, in some embodiments, the positive terminals of the capacitors C1, C2, C3-Cn are connected to corresponding contacts located on a first surface 402 of the passive device layer 400a, and the negative terminals of the capacitors C1, C2, C3-Cn are connected to corresponding contacts located on a second surface 404 of the passive device layer 400a opposite the first surface 402. The passive device layer 400a is stacked with a layer having stack switches via the first surface 402 and with a layer having phase switches via the second surface 404. Thus, the stack switches can be connected to the positive terminals of the capacitors C1, C2, C3-Cn via dc nodes, and the phase switches can be connected to the negative terminals of the capacitors C1, C2, C3-Cn via corresponding phase nodes. It will be appreciated that in different arrangements, the first surface 402 can be either a top surface or a bottom surface, since the stack switches can be stacked below or above the passive device layer 400a. In the embodiment of FIG. 4A, the multilayer ceramic capacitors C1, C2, C3-Cn are embedded in the substrate, and the long edge of each multilayer ceramic capacitor C1, C2, C3-Cn is substantially perpendicular to the top or bottom surface of the passive device layer 400a, but the present disclosure is not limited thereto.

[0042] As shown in the passive device layer 400b of FIG. 4B, the multilayer ceramic capacitors C1, C2, C3-Cn are also embedded in the substrate, with the long edge of each multilayer ceramic capacitor C1, C2, C3-Cn being substantially parallel to the top or bottom surface of the passive device layer 400b. As in the embodiment of FIG. 4A, the positive terminals of the capacitors C1, C2, C3-Cn are connected to corresponding contacts located on the first surface 402, while the negative terminals of the capacitors C1, C2, C3-Cn are connected to corresponding contacts located on the second surface 404 opposite the first surface 402. As shown in the passive device layer 400c of FIG. 4C, in some embodiments, the multilayer ceramic capacitors C1, C2, C3-Cn can also be vertically embedded in a molded composite material 406, such as molded plastic or other electrical insulator material, to form the passive device layer 400c. It will be appreciated that the passive device layer may be realized by other approaches and the embodiments shown in Figures 4A-4C are merely examples and are not meant to limit the present disclosure.

[0043] In some embodiments, the active device layers 310, 330, and 350 and / or the passive device layers 320 and 340 in the structure 300a of Figure 3A may be formed using a molded interconnect substrate (MIS), and one or more of the stack switches 210, 220, the phase switch 230, and the capacitors 240, 250 may be embedded in the molded interconnect substrate (MIS). A molded interconnect substrate is a packaging technology built on a leadframe substrate that supports a single die or multi-die configuration.

[0044] 4D illustrates an exemplary active device layer 400d with molded interconnect substrate, according to some embodiments of the present disclosure. In the active device layer 400d, one or more IC dies 410 including active elements (e.g., switches) are attached to a leadframe 420 with a thermally conductive material 430 disposed between the IC die 410 and the leadframe 420. Conductive pillars (e.g., Cu pillars) 440 and 450 are disposed to couple the IC die 410 or the leadframe 420 to a MIS 460 having a pre-molded structure. The MIS 460 may include one or more layers pre-configured with copper plating or interconnects to provide electrical connections.

[0045] FIG. 5 illustrates an exemplary switched capacitor circuit 500 according to some embodiments of the present disclosure. As shown in FIG. 5, in some embodiments, the switched capacitor circuit 500 includes multiple single-phase switched capacitor networks 510, 520, and 530 connected in parallel for three different phases. For example, as shown in FIG. 5, the switched capacitor network 510 can be implemented by a 4:1 Dickson switched capacitor network having switches S1A-S8A and capacitors C1A, C2A, and C3A. Similarly, the switched capacitor networks 520 and 530 can be implemented by a 4:1 Dickson switched capacitor network having respective switches S1B-S8B, S1C-S8C, and capacitors C1B-C3B, C1C-C3C. The switches S1A-S8A, S1B-S8B, and S1C-S8C can be controlled in response to commands from a controller circuit 540 connected to the switched capacitor networks 510, 520, and 530.

[0046] The switched capacitor network 510 includes a stack switch 512 and a phase switch 514 for the first phase and a capacitor 516 associated with the first phase. The stack switch 512 associated with the first phase includes switches S1A, S2A, S3A, and S4A forming a switch chain. The phase switch 514 includes switches S5A, S6A, S7A, and S8A. In the design shown in FIG. 5, the stack switches S1A, S2A, S3A, and S4A are connected to the positive terminals of the capacitors C1A, C2A, and C3A, respectively, through corresponding dc nodes. The phase switches S5A and S6A are connected to the negative terminals of the capacitors C1A and C3A through one phase node, while the phase switches S7A and S8A are connected to the negative terminal of the capacitor C2A through another phase node. Similarly, the switched capacitor networks 520 and 530 each include stack switches 522, 532 and phase switches 524, 534 for the second or third phase, and capacitors 526, 536 associated with the second or third phase. The arrangement of circuit components in the switched capacitor networks 520 and 530 is similar to that in the switched capacitor network 510, and therefore further details are omitted for brevity. Compared to the embodiment of FIG. 2A, in the switched capacitor circuit 500, the switched capacitor networks 510, 520 and 530 do not share phase nodes and phase switches. The capacitors 516, 526 and 536 are connected to respective sets of phase switches 514, 524 and 534 for different phases.

[0047] Similar to the embodiment of FIG. 2A, in response to commands from the controller circuit 540, each of the switched capacitor networks 510, 520, and 530 transitions between a first state and a second state depending on which of the switches are open and which are closed. Thus, a charge pumping action occurs as the switches cause the switched capacitor networks to switch between these states. In some embodiments, the controller circuit 540 can output corresponding control signals such that the switched capacitor networks 510, 520, and 530 operate 120 degrees out of phase with each other. The topology shown in FIG. 5 can be further modified to combine N phases in parallel such that they are 360 / N degrees out of phase with each other, where N is any integer greater than 1. With such an arrangement, the switched capacitor circuit 500 reduces output voltage ripple and improves output power handling capability.

[0048] Figure 6A illustrates an example structure 600, in accordance with some embodiments of the present disclosure, which can be used to implement the switched-capacitor circuit 500 shown in Figure 5. As shown in Figure 6A, the structure 600 includes substructures 610, 620, 630, and 640 stacked vertically on one another along the z-direction perpendicular to the substrate.

[0049] Each of the substructures 610, 620, and 630 is associated with a corresponding phase of the switched-capacitor circuit 500 of Figure 5. For example, substructure 610 corresponds to the switched-capacitor network 510 for the first phase, substructure 620 corresponds to the switched-capacitor network 520 for the second phase, and substructure 630 corresponds to the switched-capacitor network 530 for the third phase. Substructure 640, which may be the bottom layer beneath substructures 610, 620, and 630, comprises controller circuitry 540.

[0050] As shown in Figure 6A, each of the substructures 610, 620, and 630 includes a first device layer (e.g., layer 612, 622, or 632) having a stack switch (e.g., stack switch 512, 522, or 524), a second device layer (e.g., layer 614, 624, or 634) having a phase switch (e.g., phase switch 514, 524, or 534), and a third device layer (e.g., layer 616, 626, or 636) having a capacitor (e.g., capacitor 516, 526, or 536) stacked between the first and second device layers. By providing contacts and vias within each layer of the structure 600, the substructures 610, 620, and 630 can be stacked on top of each other to connect the switched capacitor networks 510, 520, and 530 in parallel to form the switched capacitor circuit 500 of Figure 5. Additionally, the controller circuit 540 in the bottom layer can connect to the switches in the substructures 610, 620 and 630 through these contacts and vias, thereby providing control signals to control the stack switches and phase switches for each phase.

[0051] FIG. 6B illustrates an example substructure 610 according to some embodiments of the present disclosure. It will be understood that substructures 620 and 630 may include the same or similar features as substructure 610 of FIG. 6B. In FIG. 6B, a passive device layer 616 is stacked above an active device layer 614, and an active device layer 612 is stacked above the passive device layer 616. Substructure 610 provides a bottom contact 611 on a bottom surface and a top contact 615 on a top surface opposite the bottom surface for electrical connection with other substructures stacked above or below substructure 610. One or more through vias 613 may be formed through active device layer 612, passive device layer 616, and active device layer 614 and extend in a height direction. As shown in FIG. 6B, through vias 613 may be configured to couple corresponding bottom contacts 611 and top contacts 615.

[0052] With the stacked structure shown in Figure 3A or Figure 6A, a switched capacitor power converter can be formed with its stack switches, capacitors, and phase switches stacked vertically in different layers. Thus, the horizontal surface area required for the power converter can be reduced. The structures 300a and 600 disclosed in Figures 3A and 6A are suitable for various devices or systems such as power converters used in modern data centers, but the present disclosure is not limited thereto. The disclosed embodiments can also be used in other power applications or scenarios where package height is less critical.

[0053] FIG. 7 illustrates an example structure 700 according to some embodiments of the present disclosure. The structure 700 can be used to implement a single-phase switched capacitor network. As shown in FIG. 7, the structure 700 includes two sets of cells 710 and 720, and a phase device cell 730. The cells 710 and 720 are stacked vertically on each other and stacked on top of the phase device cell 730 along the z-direction perpendicular to the substrate. As shown in FIG. 7, each cell 710 or 720 includes a top contact located on a top surface and a bottom contact located on a bottom surface for connecting to a contact of another cell stacked above or below the cell.

[0054] Each of the cells 710 and 720 includes at least one capacitor (e.g., one of the capacitors C1-C5) and a first switch (e.g., one of the switches S1-S5) connected to the positive terminal of the corresponding capacitor. The first switches S1-S5 in the stacked cells 710 and 720 are connected in series as stack switches of a single-phase switched capacitor network. The phase device cell 730 includes second switches S6, S7, S8, and S9, which are phase switches of the single-phase switched capacitor network and are connected to the negative terminal of the corresponding capacitors C1-C5. By stacking the cells 710 and 720 on the phase device cell 730, the capacitors C1-C5 and the first switches S1-S5 in each cell 710 or 720 are interconnected with the second switches S6, S7, S8, and S9 to form a single-phase switched capacitor network. As with the previous embodiments, the switched-capacitor circuit shown in FIG. 7 can be configured to transition between at least two states depending on the switching of the first switches S1-S5 and the second switches S6-S9 in each cell 710 or 720.

[0055] In structure 700, cells 710 and 720 are alternately stacked to connect capacitors C1-C5 to corresponding phase nodes 732 or 734. In particular, in each cell 710, a capacitor (e.g., capacitor C1, C3, or C5) is connected to a first subset of second switches (e.g., switches S8 and S9) at a first phase node 732 of the switched capacitor circuit, and in each cell 720, a capacitor (e.g., capacitor C2 or C4) is connected to a second subset of second switches (e.g., switches S6 and S7) at a second phase node 734 of the switched capacitor circuit.

[0056] As in the previous embodiment, in a switch chain having first switches S1-S5, adjacent switches are in complementary states. In other words, in operation, in a first state, in response to a command from the controller circuit, the first switch in each cell 710, e.g., switches S1, S3, and S5, may be on, and the first switch in each cell 720, e.g., switches S2 and S4, may be off. In a second state following the first state, in response to a command from the controller circuit, the first switch in each cell 710 may be off, and the first switch in each cell 720 may be on.

[0057] In some embodiments, each of the first switches S1-S5 may be a field effect transistor having a source terminal and a drain terminal connected to one of the top contacts and one of the bottom contacts, respectively. Each of the capacitors C1-C5 is connected between the source terminal of the corresponding field effect transistor and the first phase node 732 or the second phase node 734 of the switched capacitor circuit through corresponding contacts and / or vias in the cells 710 and 720.

[0058] 8A and 8B are diagrams illustrating example cells 710 and 720, respectively, according to some embodiments of the present disclosure. As shown in FIG. 8A and 8B, each of the cells 710 and 720 has top contacts T1-T5 located on a top surface and bottom contacts B1-B5 located on a bottom surface. The top contacts T1, T2, T4, and T5 are connected to bottom contacts B1, B2, B4, and B5, respectively, to provide electrical connection between the stacked cells 710 and 720.

[0059] In the cells 710 and 720, the source terminal S of the transistor 712 or 722 is connected to the bottom contact B3, and the drain terminal D of the transistor 712 or 722 is connected to the top contact T3. For the cell 710 of FIG. 8A, the gate terminal G of the transistor 712 is connected to the top contact T1 and the bottom contact B1. For the cell 720 of FIG. 8B, the gate terminal G of the transistor 722 is connected to the top contact T2 and the bottom contact B2. Thus, when the cells 710 and 720 are alternately stacked, the gate terminals of the transistor 712 in the cell 710 are electrically connected to each other to receive a first control signal, while the gate terminals of the transistor 722 in the cell 720 are electrically connected to each other to receive a second control signal. Thus, adjacent switches in the switch chain can operate in a complementary state.

[0060] For the cell 710 of FIG. 8A, the capacitor 714 is connected between the source terminal S of the transistor 712 and a node 716. The node 716 is connected to the top contact T5 and the bottom contact B5, and would be electrically connected to a first phase node (e.g., phase node 732 in FIG. 7) of the switched capacitor circuit through an electrical connection between the stacked cells 710 and 720. Meanwhile, for the cell 720 of FIG. 8B, the capacitor 724 is connected between the source terminal of the transistor 722 and a node 726. The node 726 is connected to the top contact T4 and the bottom contact B4, and would be electrically connected to a second phase node (e.g., phase node 734 in FIG. 7) of the switched capacitor circuit through an electrical connection between the stacked cells 710 and 720. Thus, when the cells 710 and 720 are alternately stacked, the capacitor 714 and the capacitor 724 in adjacent cells are connected to different subsets of the phase switches to form the single-phase switched capacitor network shown in FIG. 7.

[0061] FIG. 9 illustrates an exemplary structure of the cell 710 of FIG. 8A, according to some embodiments of the present disclosure. As shown in FIG. 9, the top contacts T1-T5 and the bottom contacts B1-B5 can be disposed at corresponding positions on opposite sides of the cell 710, such that the top contacts T1-T5 can be coupled to corresponding contacts of the adjacent cell 720 stacked above the cell 710, and the bottom contacts B1-B5 can be coupled to corresponding contacts of the adjacent cell 720 stacked below the cell 710. The transistor 712 and the capacitor 714 in the cell 710 can be arranged to optimize the electrical connections between the components, the top contacts T1-T5, and the bottom contacts B1-B5. A similar structure can be applied to the cell 720 of FIG. 8B, but will not be repeated here for brevity.

[0062] FIG. 10 illustrates another exemplary cell 1000 according to some embodiments of the present disclosure. As shown in FIG. 10, the transistors 712 and 722 operating in a complementary manner and the capacitors 714 and 724 can also be integrated into a single cell to form a switched capacitor network. Thus, the single-phase switched capacitor network illustrated in FIG. 7 can be formed by stacking one or more cells 1000 instead of the pair of one cell 710 and one cell 720. In FIG. 10, the cell 1000 includes transistors 712 and 722 and capacitors 714 and 724. Similar to the embodiment of FIG. 8A and FIG. 8B, the capacitor 714 is connected between the source terminal S1 of the transistor 712 and a node 716 connected to the top junction T5 and the bottom junction B5, while the capacitor 724 is connected between the source terminal S2 of the transistor 722 and a node 726 connected to the top junction T4 and the bottom junction B4.

[0063] Transistors 712 and 722 are connected in series between top junction T3 and bottom junction B3. In particular, drain terminal D1 of transistor 712 is connected to top junction T3, drain terminal D2 of transistor 722 is connected to source terminal S1 of transistor 712, and source terminal S2 of transistor 722 is connected to bottom junction B3. Gate terminal G1 of transistor 712 is connected to top junction T1 and bottom junction B1, while gate terminal G2 of transistor 722 is connected to top junction T2 and bottom junction B2.

[0064] It should be noted that while cell 1000 includes two stack switches (e.g., transistors 712 and 722) and two capacitors 714 and 724 in a single cell, the disclosure is not so limited. In other embodiments, a cell may include any number of stack switches connected in series and corresponding capacitors connected to the stack switches. In other words, in some embodiments, at least one of the stacked cells may include multiple capacitors and multiple stack switches interconnected with a phase switch to form a switched capacitor circuit.

[0065] In the embodiments of Figures 7-10, by stacking multiple stackable cells 710, 720 and / or 1000 on top of the phase device cell 730, a switched capacitor power converter can be formed with its electrical components stacked vertically. As with the embodiments of Figures 2A-6D, the horizontal surface area required for the power converter can be reduced, which is desirable for various power applications or scenarios where package height is less critical. Furthermore, the conversion ratio of the switched capacitor network can be easily changed by stacking different numbers of cells, thereby providing modularity and flexibility for the design of power converters to meet different power requirements in different applications at low cost.

[0066] It will be appreciated that the structures 300a-300d, 600 and 700 of the present disclosure can also be modified and applied to other types of power converters having different implementations, arrangements and / or topologies. For example, the structures disclosed herein can form a resonant switched capacitor converter including a transistor, a capacitor and one or more inductors as an energy storage element, or a multilevel power converter, or a converter with an LC filter coupled with a switched capacitor to facilitate adiabatic charging or discharging.

[0067] In such implementations, the capacitors and inductors can be located in the same passive device layer or in separate passive device layers. Referring again to FIG. 3A, in some embodiments, the passive device layer 320 or 340 can further include one or more inductors connected with one or more of the capacitors 240 or 250 in the same layer. Alternatively, as shown in FIG. 3D, the structure 300d can include one or more additional inductor layers, i.e., passive device layers 370 and 380 stacked vertically adjacent to the passive device layer 320 or 340. The passive device layers 370 and 380 comprise one or more inductors connected with one or more of the capacitors 240 or 250 in the passive device layer 320 or 340.

[0068] 11A and 11B, which show one or more additional inductor layers stacked vertically adjacent to a passive device layer having a capacitor. FIG. 11A shows a cross-sectional view of an example portion of an LC network 1100a, according to some embodiments of the present disclosure. As shown in FIG. 11A, the LC network 1100a can include a capacitor layer 1110 and an inductor layer 1120, with contacts and / or vias configured to enable electrical connection of the inductor layer 1120 and the capacitor layer 1110 in series. The LC network 1100a can be fabricated by bonding a bottom surface of the capacitor layer 1110 to a top surface of the inductor layer 1120. In some embodiments, the bond can include a hybrid bond such that a metal-to-metal bond and an oxide-to-oxide bond are formed between the bonding surfaces of the capacitor layer 1110 and the inductor layer 1120.

[0069] FIG. 11B illustrates a cross-sectional view of an exemplary portion of another LC network 1100b according to some embodiments of the present disclosure. In FIG. 11B, the LC network 1100b can include two inductor layers 1120 and 1130 and a capacitor layer 650 connected between the two inductor layers 1120 and 1130 with contacts and / or vias configured to allow a series electrical connection. As an example, the LC network 1100b can be used in a resonant switched capacitor converter. It will be understood that the relative arrangement of the inductor layers 1120 and 1130 and the capacitor layer 1110 shown in FIGS. 11A and 11B is a non-limiting example and other arrangements may be possible. In various embodiments, the LC network can include one or more inductor layers, one or more capacitor layers, one or more through vias, and electrical contact pads, as desired.

[0070] Reference is now made to FIG. 12. FIG. 12 illustrates an exemplary power converter 1200 according to some embodiments of the present disclosure. Compared to the embodiment of FIG. 1, the power converter 1200 may include multiple devices 110a, 110b, and 110c connected to each other, with each device providing a power module. In a preferred embodiment, the power module may include one or more of the devices 110a, 110b, and 110c. It should be noted that the number of the devices 110a, 110b, and 110c may be different in different embodiments, and FIG. 12 is a simplified example and is not meant to limit the present disclosure. In the embodiment of FIG. 12, by using multiple power modules (e.g., including multiple devices 110a, 110b, and 110c) having input terminals V1p and V1n of a switched capacitor circuit connected to each other in the power converter 1200 and output terminals V2p and V2n of a switched capacitor circuit connected to each other, the power converter 1200 can achieve a higher power rating based on low-cost and low-rated devices. Therefore, the modular design also provides flexibility and scalability of the power conversion circuit to meet different needs of the power supply system in different applications.

[0071] In some embodiments, devices 110a, 110b, and 110c may each include a corresponding switched capacitor circuit 112 and a separate controller circuit 114, although the disclosure is not limited thereto. In some embodiments, the switched capacitor circuits 112 in devices 110a, 110b, and 110c may be controlled by an external master controller connected to devices 110a, 110b, and 110c. In some other embodiments, power converter 1200 may include an internal master controller (e.g., controller circuit 114 in device 110a) and one or more slave controllers (e.g., controller circuit 114 in devices 110b and 110c) configured to communicate with the internal master controller. Additionally, one or more of the power modules in power converter 100 may support a Power Management Bus (PMBUS) communication protocol, while the remaining power modules are “light” power modules having a simpler design without PMBUS and / or telemetry circuitry.

[0072] 12, in some embodiments, the input terminals V1p, V1n and output terminals V2p, V2n of the switched capacitor circuit 112 in each of the devices 110a, 110b, and 110c are connected in parallel. In addition, some input terminals of the controller circuit 114, such as the PG terminal or the CLK terminal, are also connected in parallel, so that the devices 110a, 110b, and 110c receive the same PG signal and the same clock signal. in and I.O. out Some other terminals, such as , may be connected in series to facilitate operation of the circuit.

[0073] In various embodiments of the present disclosure, for applications where the size of the circuit is important, the devices 110a, 110b, and 110c with the charge pump circuitry can be stacked vertically in a package to provide high power density to the power converter 1200. For example, a central processing unit (CPU) in a laptop or data center can provide sufficient height margin (e.g., about 2-9 mm or about 7-22 mm) to allow low-profile charge pump power modules to be stacked vertically in the z-direction. Thus, as the package height increases, the area occupied by the charge pump circuitry on the horizontal plane (i.e., the xy plane) can be reduced, with corresponding savings in footprint.

[0074] Compared with the charge pump power module of the present embodiment, the buck converter power module typically has a relatively high-profile inductor, such as a wire-wound inductor. In particular, the inductor is usually the largest and tallest component in a conventional module, and is a bottleneck that reduces the height of the module in the z-direction. Conventional buck converters cannot be stacked due to the large inductor height, and such vertically stacked buck converter power modules are not desirable for power supply applications for laptops or CPUs in data centers because they exceed the height constraint. On the other hand, in the case of the switched capacitor architecture of the present embodiment, the low-profile (e.g., about 1 mm) charge pump power module is suitable for stacking in various power supply applications.

[0075] FIG. 13 illustrates an exemplary power converter package 1300 according to some embodiments of the present disclosure. The power converter package 1300 includes multiple integrated circuit packages (e.g., devices 110a, 110b, and 110c) stacked vertically to increase power density without increasing the overall package area. As shown in FIG. 13, the bottom layer device 110a may be a bottom package providing a bottom bond contact 1312a on one side (e.g., the bottom side) and a top bond contact 1314a on another side (e.g., the top side) opposite the side having the bottom bond contact 1312a. One or more through vias 1316a of the device 110a couple the corresponding bottom bond contact 1312a to the corresponding top bond contact 1314a.

[0076] Similarly, the middle layer device 110b may be a middle package providing a bottom bond contact 1312b on its bottom surface and a top bond contact 1314b on its top surface opposite the bottom surface, with one or more through vias 1316b connecting the corresponding bottom bond contact 1312b to the corresponding top bond contact 1314b. The top layer device 110c may be a top package providing a bottom bond contact 1312c on its bottom surface. Alternatively stated, in the embodiment of FIG. 13, the bottom bond contact on one surface of the package provides a connection to a substrate or adjacent lower package stacked below the package, and the top bond contact on the opposite surface provides a connection to an adjacent upper package stacked above the package.

[0077] It should be noted that in some embodiments, the top package may be a stackable package or a non-stackable package. In other words, the top layer device 110c may provide a top bonding contact on a top surface, while in some other embodiments, the device 110c may provide only a bottom bonding contact 1312c. It should also be noted that in various embodiments, depending on the application, the orientation of the non-stackable and stackable packages may vary in the power converter package 1300.

[0078] As shown in FIG. 13, devices 110a, 110b, and 110c are stacked together via joints 1320a, 1320b, and 1320c, which may be electrical joints (e.g., bumps), thermo-compression joints, or hybrid joints between two adjacent packages. In some embodiments, joints 1320a, 1320b, and 1320c may comprise electrically conductive bumps that conduct both thermal and electrical signals, and thermally conductive bumps dedicated to thermal conduction only. In particular, joint 1320a is configured to join bottom joint contacts 1312a in the bottom layer to a substrate, such as a main printed circuit board (PCB) 1310. Joints 1320b and 1320c are configured to join top joint contacts located on a top surface of a package in one layer to corresponding bottom joint contacts located on a bottom surface of another package in an adjacent layer. The joints 1320a, 1320b, and 1320c and the through vias 1316a and 1316b provide electrical connections between the stacked devices 110a, 110b, and 110c. Thus, the stacked devices 110a, 110b, and 110c of Figure 13 can form the power converter 1200 of Figure 12, in which the switched capacitor circuits in different modules are electrically connected in parallel with each other.

[0079] As described above, one or more controller circuits configured to control the operation of the switched-capacitor circuits may be disposed within devices 110a, 110b, 110c. In some embodiments, a master controller circuit may be disposed within a bottom package (e.g., device 110a) and a slave controller circuit may be disposed within one or more middle packages (e.g., device 110b) or within a top package (e.g., device 110c). The slave controller circuits may be electrically connected to the master controller circuit disposed within the bottom package via corresponding bottom bonding contacts 1312a-c and top bonding contacts 1314a and 1314b of the integrated circuit packages.

[0080] FIG 14 is a flow chart of a method 1400 of fabricating a switched-capacitor circuit according to some embodiments of the present disclosure. It is understood that additional operations may be performed before, during, and / or after the method 1400 shown in FIG 14, and some other processes are only briefly described herein. The method 1400 may be performed to fabricate the structure 300a of FIG 3A for fabricating integrated circuits for power converter applications, such as the power converter 100 of FIG 1 and the power converter 1200 of FIG 12. The method 1400 includes operations 1410-1490.

[0081] In operation 1410, a first device layer (e.g., active device layer 310 of FIG. 3A) is provided. In operation 1420, a third device layer (e.g., passive device layer 320 of FIG. 3A) is disposed on the first device layer. In operation 1430, a first capacitor in the third device layer (e.g., capacitor 240 of FIG. 3A) is interconnected with a first switch in the first device layer (e.g., stack switch 210 of FIG. 3A). A bottom contact of the third device layer can be coupled with a corresponding top contact of the first device layer to connect a positive terminal of the first capacitor to a corresponding first switch.

[0082] In operation 1440, a second device layer (e.g., active device layer 330 of FIG. 3A) is disposed on a third device layer. In operation 1450, a second switch (e.g., phase switch 230 of FIG. 3A) in the second device layer is interconnected with the first capacitor. A bottom contact of the second device layer can be coupled with a corresponding top contact of the third device layer to connect the negative terminal of the first capacitor to the corresponding second switch.

[0083] In operation 1460, a fifth device layer (e.g., passive device layer 340 of FIG. 3A) is disposed on the second device layer. In operation 1470, a second capacitor in the fifth device layer (e.g., capacitor 250 of FIG. 3A) is interconnected with a second switch. A bottom contact of the fifth device layer can be coupled with a corresponding top contact of the second device layer to connect a negative terminal of the second capacitor to a corresponding second switch.

[0084] In operation 1480, a fourth device layer (e.g., active device layer 350 of FIG. 3A) is disposed on the fifth device layer. In operation 1490, a third switch (e.g., stack switch 220 of FIG. 3A) in the fourth device layer is interconnected with the second capacitor. A bottom contact of the fourth device layer can be coupled with a corresponding top contact of the fifth device layer to connect a negative terminal of the second capacitor to a corresponding third switch.

[0085] In some embodiments, in operation 1420 or 1460, one or more inductor layers (e.g., inductor layers 1120 and / or 1130 of FIGS. 11A and 11B) may be vertically stacked adjacent to a passive device layer (e.g., capacitor layer 1110 of FIGS. 11A and 11B) before or after stacking of a third device layer. The inductor layer may comprise one or more inductors that couple (connect) with one or more first capacitors in the passive device layer to form an LC network.

[0086] As described above, in method 1400, the first and fifth device layers can be formed by vertically embedding a multilayer ceramic capacitor in a substrate, with one or more contacts connected to a positive terminal of the multilayer ceramic capacitor located on a first surface and one or more contacts connected to a negative terminal of the multilayer ceramic capacitor located on a second surface opposite the first surface. In some other embodiments, the first and fifth device layers can be formed by embedding a multilayer ceramic capacitor in a molded composite material. In some other embodiments, one or more of the active or passive device layers can be formed by embedding switches and / or capacitors with a molded interconnect substrate.

[0087] By the above described operations 1410-1490, a structure having multiple layers vertically stacked on each other (e.g., structure 300a of FIG. 3A) can be obtained for implementing a switched capacitor circuit. A switched capacitor power converter can thus be formed with its stack switches, capacitors, and phase switches vertically stacked on different layers, and the horizontal surface area required for the power converter can be reduced.

[0088] 15 is a flow chart of another method 1500 of fabricating a switched-capacitor circuit according to some embodiments of the present disclosure. It is understood that additional operations may be performed before, during, and / or after the method 1500 shown in FIG. 15, and that some other processes are only briefly described herein. The method 1500 may be performed to fabricate the structure 700 of FIG. 7 for fabricating integrated circuits for power converter applications, such as the power converter 100 of FIG. 1 and the power converter 1200 of FIG. 12. The method 1500 includes operations 1510 and 1520.

[0089] In operation 1510, a phase device cell (e.g., phase device cell 730 of FIG. 7) including a phase switch (e.g., switches S6-S8 of FIG. 7) of a switched capacitor circuit is provided. In operation 1520, a plurality of cells (e.g., cells 710 and 720 of FIG. 7) are vertically stacked on the phase device cell. Each of the cells includes a capacitor (e.g., one of capacitors C1-C5) and a stack switch (e.g., one of switches S1-S5). The capacitor and stack switch of each of the cells are interconnected with the phase switch. In each cell, the capacitor is connected between corresponding bottom and top contacts, and the stack switch is connected between corresponding bottom and top contacts.

[0090] The process of stacking the cells in operation 1520 may include connecting a bottom contact located on the bottom surface of each cell (e.g., bottom contacts B1-B5 in Figures 8A and 8B) to a contact of another cell stacked below the cell, and connecting a top contact located on the top surface of each cell (e.g., top contacts T1-T5 in Figures 8A and 8B) to a contact of another cell stacked above the cell.

[0091] In some embodiments, in operation 1520, one or more cells in one set (e.g., cell 710 in FIG. 7 ) and one or more cells in another set (e.g., cell 720 in FIG. 7 ) are stacked alternately. In each cell 710, a capacitor is connected to a first subset of phase switches (e.g., switches S8 and S9 in FIG. 7 ) at a first phase node (e.g., phase node 732 in FIG. 7 ) of the switched capacitor circuit. In each cell 720, a capacitor is connected to a second subset of phase switches (e.g., switches S6 and S7 in FIG. 7 ) at a second phase node (e.g., phase node 734 in FIG. 7 ) of the switched capacitor circuit.

[0092] By operations 1510 and 1520 described above, a structure (e.g., structure 700 of FIG. 7) can be obtained for implementing a switched capacitor circuit, and a switched capacitor power converter can thus be formed with its electrical components stacked vertically, reducing the horizontal surface area required for the power converter. By applying method 1500 to fabricate a switched capacitor circuit as described above, the transformation ratio of the switched capacitor network can be easily changed by stacking different numbers of cells, thereby providing modularity and flexibility for the design of power converters to meet different power requirements in different applications at low cost.

[0093] In summary, in various embodiments of the present disclosure, switches and capacitors can be stacked vertically in different ways to build single-phase or multi-phase switched capacitor networks, which can be applied in various power conversion circuits, such as charge pump circuits, resonant switched capacitor converter circuits, multi-level power converter circuits, etc., to increase power density per unit area. Thus, the total area required for a power converter can be reduced, which is desirable for data center power supplies and other power applications. It is noted that the switched capacitor circuits and / or power converters of the present disclosure can be realized in various topologies depending on the desired voltage conversion ratio and the allowed switching voltages.

[0094] In the above specification, the embodiments have been described with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications of the described embodiments may be made. Other embodiments may become apparent to those skilled in the art upon consideration of the specification and practice of the disclosure disclosed herein. Additionally, the order of steps depicted in the figures is intended for illustrative purposes only and is not intended to be limited to any particular order of steps. Thus, those skilled in the art may understand that these steps may be performed in different orders while performing the same method.

[0095] It is understood that certain features herein that are described for clarity in the context of separate embodiments can also be provided in combination in a single embodiment. Conversely, various features herein that are described for brevity in the context of a single embodiment can also be provided separately or in any suitable subcombination, or in any other described embodiment herein as appropriate. Certain features described in the context of various embodiments are not to be construed as essential features of those embodiments, unless the embodiment is inoperable without those elements.

[0096] The embodiments can be further described using the following clauses. 1. A first device layer having a plurality of first switches; a second device layer having a plurality of second switches; a third device layer disposed between the first device layer and the second device layer, the third device layer having a plurality of first capacitors; Equipped with the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; the switched-capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches. 2. The plurality of first switches are stack switches connected to the positive terminals of the plurality of first capacitors via a plurality of DC nodes; Item 2. The apparatus of item 1, wherein the plurality of second switches are phase switches connected to the negative terminals of the plurality of first capacitors via a first phase node or a second phase node. 3. The apparatus of claim 2, wherein the first phase node is connected to a negative terminal of a first subset of the plurality of first capacitors, and the second phase node is connected to a negative terminal of a second subset of the plurality of first capacitors. 4. A fourth device layer having a plurality of third switches; a fifth device layer disposed between the second device layer and the fourth device layer, the fifth device layer having a plurality of second capacitors; Further equipped with the switched capacitor circuit is a multi-phase switched capacitor circuit, the plurality of second switches are phase switches for a first phase and a second phase for connecting the plurality of first capacitors and the plurality of second capacitors to a shared phase node of the switched-capacitor circuit; the plurality of first switches are stacked switches associated with the first phase; 4. The apparatus according to any one of items 1 to 3, wherein the plurality of third switches are stack switches associated with the second phase. 5. The device described in any one of items 1 to 4, wherein positive terminals of the plurality of first capacitors are connected to corresponding contacts located on a first surface of the third device layer, and negative terminals of the plurality of first capacitors are connected to corresponding contacts located on a second surface of the third device layer opposite the first surface. 6. The device according to any one of items 1 to 5, wherein the plurality of first capacitors are multilayer ceramic capacitors. 7. The apparatus of claim 6, wherein the multilayer ceramic capacitors are embedded in a substrate and a long edge of each multilayer ceramic capacitor is substantially perpendicular to a top surface of the third device layer. 8. The apparatus of claim 6, wherein the multilayer ceramic capacitors are embedded in a substrate, and a long edge of each multilayer ceramic capacitor is substantially parallel to a top surface of the third device layer. 9. The device of claim 6, wherein the multilayer ceramic capacitor is vertically embedded in a molded composite material. 10. The device described in any one of items 1 to 9, wherein one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded using a molded interconnect substrate. 11. The apparatus described in any one of paragraphs 1 to 10, wherein the third device layer further comprises an inductor connected to one or more of the first capacitors to form a resonant switched capacitor converter or a multilevel converter. 12. The device described in any one of clauses 1 to 11, further comprising an inductor layer vertically stacked adjacent to the third device layer, the inductor layer comprising an inductor connected to one or more of the plurality of first capacitors to form a resonant switched capacitor converter or a multilevel converter. 13. The apparatus of any one of clauses 1 to 12, comprising a plurality of substructures vertically stacked on one another, each substructure associated with a corresponding phase of the switched-capacitor circuit, the apparatus comprising the first device layer, the second device layer, and the third device layer. 14. The apparatus of claim 13, wherein the plurality of substructures form a multi-phase switched capacitor circuit having n phases that are 360 / n degrees out of phase with each other, where n is any integer greater than 1. 15. A plurality of cells, each cell comprising a capacitor and a first switch; a phase device cell having a plurality of second switches, the plurality of cells being vertically stacked on the phase device cell; and An apparatus comprising: the capacitor and the first switch in each cell are interconnected with the plurality of second switches to form a switched capacitor circuit; the switched-capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the plurality of second switches in each cell. 16. The apparatus of claim 15, wherein the plurality of cells comprises two sets of cells stacked vertically alternately, and in one cell of the set, the capacitor is connected to a first subset of the plurality of second switches at a first phase node of the switched capacitor circuit, and in the other cell of the set, the capacitor is connected to a second subset of the plurality of second switches at a second phase node of the switched capacitor circuit. 17. During a first state of the switched-capacitor circuit, each first switch in one set of cells is on and each first switch in another set of cells is off; Item 17. The apparatus of item 16, wherein during a second state of the switched-capacitor circuit, each first switch in one set of cells is off and each first switch in another set of cells is on. 18. Each cell is a top contact located on a top surface of the cell, the top contact being coupled to a contact of another cell stacked above the cell; Item 18. The device according to any one of items 15 to 17, wherein a bottom contact located on the bottom surface of the cell is connected to a contact of another cell stacked below the cell. 19. The apparatus of claim 18, wherein a first phase node of the switched capacitor circuit is electrically connected to one of the top contacts and one of the bottom contacts, and a second phase node of the switched capacitor circuit is electrically connected to another one of the top contacts and another one of the bottom contacts. 20. The device described in paragraph 18 or 19, wherein each first switch of each cell comprises a field effect transistor having a source terminal and a drain terminal respectively connected to one of the top contacts and one of the bottom contacts of the cell. 21. The device described in item 20, wherein in each cell, the capacitor is connected between the source terminal of the field effect transistor and one of the first phase node or the second phase node of the switched capacitor circuit. 22. The device described in any of items 15 to 21, wherein at least one of the cells comprises a plurality of capacitors and a plurality of first switches interconnected with the plurality of second switches to form the switched capacitor circuit. 23. The device described in any one of items 15 to 22, wherein at least one of the cells further comprises an inductor. 24. A method of manufacturing a switched-capacitor circuit, comprising the steps of: providing a first device layer; disposing a third device layer over the first device layer; interconnecting a plurality of first capacitors in the third device layer with a plurality of first switches in the first device layer; disposing a second device layer over the third device layer; interconnecting a plurality of second switches in the second device layer with the plurality of first capacitors; A method comprising: 25. disposing a fifth device layer on the second device layer; interconnecting a plurality of second capacitors in the fifth device layer with the plurality of second switches; disposing a fourth device layer on the fifth device layer; interconnecting a plurality of third switches in the fourth device layer with the plurality of second capacitors; 25. The method of claim 24, further comprising: 26. The method of claim 24 or 25, further comprising the step of coupling a bottom contact of the third device layer with a corresponding top contact of the first device layer to connect a positive terminal of one of the plurality of first capacitors to one of the plurality of first switches. 27. The method of any of paragraphs 24 to 26, further comprising the step of coupling a bottom contact of the second device layer with a corresponding top contact of the third device layer to connect a negative terminal of one of the plurality of first capacitors to one of the plurality of second switches. 28. The method further includes vertically embedding a multilayer ceramic capacitor into a substrate to form the third device layer; one or more contacts connected to a positive terminal of the multilayer ceramic capacitor located on the first surface of the third device layer; 28. The method of any one of items 24 to 27, wherein one or more contacts are connected to a negative terminal of the multilayer ceramic capacitor located on a second surface of the third device layer opposite the first surface. 29. The method of any one of paragraphs 24 to 27, further comprising embedding a multilayer ceramic capacitor within a molded composite material to form the third device layer. 30. The method of any one of paragraphs 24 to 29, further comprising embedding one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors with a molded interconnect substrate. 31. A method according to any one of paragraphs 24 to 30, further comprising a step of vertically stacking an inductor layer adjacent to the third device layer, the inductor layer comprising an inductor connected to one or more of the plurality of first capacitors. 32. A method for manufacturing a switched-capacitor circuit, comprising the steps of: providing a phase device cell including a plurality of phase switches of a switched capacitor circuit; vertically stacking a plurality of cells on the phase device cell, each of the cells including a capacitor and a stack switch; Including, The capacitor and the stack switch of each of the plurality of cells are interconnected with the plurality of phase switches. 33. The step of stacking the plurality of cells comprises: 33. The method of claim 32, comprising vertically stacking one or more cells in one set and one or more cells in another set, wherein in each cell in the one set, the capacitor is connected to a first subset of the plurality of phase switches at a first phase node of the switched capacitor circuit, and in each cell in the other set, the capacitor is connected to a second subset of the plurality of phase switches at a second phase node of the switched capacitor circuit. 34. The step of stacking the plurality of cells comprises: connecting, for each cell, a bottom contact located on a bottom surface of the cell to a contact of another cell stacked below the cell; connecting, for each cell, a top contact located on a top surface of the cell to a contact of another cell stacked above the cell; Item 34. The method according to item 32 or 33, comprising: 35. The method of claim 34, wherein in each cell, the capacitor is connected between corresponding bottom and top contacts. 36. The method of claim 34 or 35, wherein in each cell, the stack switch is connected between corresponding bottom and top contacts.

[0097] The above summarizes the features of some embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to carry out the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. a first device layer having a plurality of first switches; a second device layer having a plurality of second switches; a third device layer disposed between the first device layer and the second device layer, the third device layer having a plurality of first capacitors; Equipped with the plurality of first switches and the plurality of second switches are interconnected with the plurality of first capacitors to form a switched capacitor circuit; the switched-capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches.

2. the plurality of first switches are stack switches connected to positive terminals of the plurality of first capacitors via a plurality of DC nodes; 2. The apparatus of claim 1, wherein the plurality of second switches are phase switches connected to negative terminals of the plurality of first capacitors via a first phase node or a second phase node.

3. 3. The apparatus of claim 2, wherein the first phase node is connected to a negative terminal of a first subset of the plurality of first capacitors and the second phase node is connected to a negative terminal of a second subset of the plurality of first capacitors.

4. a fourth device layer having a plurality of third switches; a fifth device layer disposed between the second device layer and the fourth device layer, the fifth device layer having a plurality of second capacitors; Further equipped with the switched capacitor circuit is a multi-phase switched capacitor circuit, the plurality of second switches are phase switches for a first phase and a second phase for connecting the plurality of first capacitors and the plurality of second capacitors to a shared phase node of the switched-capacitor circuit; the plurality of first switches are stacked switches associated with the first phase; The apparatus of any one of claims 1 to 3, wherein the plurality of third switches are stacked switches associated with the second phase.

5. 5. The apparatus of claim 1, wherein positive terminals of the first capacitors are connected to corresponding contacts located on a first face of the third device layer and negative terminals of the first capacitors are connected to corresponding contacts located on a second face of the third device layer opposite the first face.

6. The apparatus of any one of claims 1 to 5, wherein the plurality of first capacitors are multi-layer ceramic capacitors.

7. 7. The apparatus of claim 6, wherein the multi-layer ceramic capacitors are embedded in a substrate, with a long edge of each multi-layer ceramic capacitor being substantially perpendicular to a top surface of the third device layer.

8. 7. The apparatus of claim 6, wherein the multi-layer ceramic capacitors are embedded in a substrate, with a long edge of each multi-layer ceramic capacitor being substantially parallel to a top surface of the third device layer.

9. The device of claim 6 , wherein the multilayer ceramic capacitor is vertically embedded in a molded composite material.

10. The apparatus of any preceding claim, wherein one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors are embedded with a molded interconnect substrate.

11. 11. The apparatus of claim 1, wherein the third device layer further comprises an inductor coupled with one or more of the first capacitors to form a resonant switched capacitor converter or a multi-level converter.

12. 12. The apparatus of claim 1, further comprising an inductor layer vertically stacked adjacent to the third device layer, the inductor layer comprising an inductor connected with one or more of the first plurality of capacitors to form a resonant switched capacitor converter or a multi-level converter.

13. 13. The apparatus of claim 1, comprising a plurality of substructures vertically stacked on one another, each substructure associated with a corresponding phase of the switched-capacitor circuit, comprising the first device layer, the second device layer, and the third device layer.

14. 14. The apparatus of claim 13, wherein the plurality of substructures form a multi-phase switched capacitor circuit having n phases that are 360 / n degrees out of phase with each other, where n is any integer greater than 1.

15. a plurality of cells, each cell comprising a capacitor and a first switch; a phase device cell having a plurality of second switches, the plurality of cells being vertically stacked on the phase device cell; and An apparatus comprising: the capacitor and the first switch in each cell are interconnected with the plurality of second switches to form a switched-capacitor circuit; The apparatus, wherein the switched-capacitor circuit is configured to transition between at least two states in response to switching of the first switch and the plurality of second switches in each cell.

16. 16. The apparatus of claim 15, wherein the plurality of cells comprises two sets of cells stacked vertically alternatingly, wherein in one cell of the set, the capacitor is connected to a first subset of the plurality of second switches at a first phase node of the switched capacitor circuit, and in another cell of the set, the capacitor is connected to a second subset of the plurality of second switches at a second phase node of the switched capacitor circuit.

17. during a first state of the switched-capacitor circuit, each first switch in one set of cells is on and each first switch in another set of cells is off; 17. The apparatus of claim 16, wherein during a second state of the switched-capacitor circuit, each of the first switches in one set of cells is off and each of the first switches in another set of cells is on.

18. Each cell is a top contact located on a top surface of the cell, the top contact being coupled to a contact of another cell stacked above the cell; a bottom contact located on a bottom surface of the cell, the bottom contact being coupled to a contact of another cell stacked below the cell; The apparatus according to any one of claims 15 to 17, comprising:

19. 20. The apparatus of claim 18, wherein a first phase node of the switched capacitor circuit is electrically connected to one of the top contacts and one of the bottom contacts, and a second phase node of the switched capacitor circuit is electrically connected to another one of the top contacts and another one of the bottom contacts.

20. 20. The apparatus of claim 18 or 19, wherein each first switch of each cell comprises a field effect transistor having source and drain terminals respectively connected to one of the top and one of the bottom contacts of the cell.

21. 21. The apparatus of claim 20, wherein in each cell, the capacitor is connected between the source terminal of the field effect transistor and one of a first phase node or a second phase node of the switched capacitor circuit.

22. 22. The apparatus of claim 15, wherein at least one of the cells comprises a plurality of capacitors and a plurality of first switches interconnected with the plurality of second switches to form the switched capacitor circuit.

23. The apparatus of any of claims 15 to 22, wherein at least one of the cells further comprises an inductor.

24. 1. A method of making a switched capacitor circuit, comprising the steps of: providing a first device layer; disposing a third device layer on the first device layer; interconnecting a plurality of first capacitors in the third device layer with a plurality of first switches in the first device layer; disposing a second device layer on the third device layer; interconnecting a plurality of second switches in the second device layer with the plurality of first capacitors; The method comprising:

25. disposing a fifth device layer on the second device layer; interconnecting a plurality of second capacitors in the fifth device layer with the plurality of second switches; disposing a fourth device layer on the fifth device layer; interconnecting a plurality of third switches in the fourth device layer with the plurality of second capacitors; 25. The method of claim 24, further comprising:

26. 26. The method of claim 24 or 25, further comprising coupling a bottom contact of the third device layer with a corresponding top contact of the first device layer to connect a positive terminal of one of the plurality of first capacitors to one of the plurality of first switches.

27. 27. The method of claim 24, further comprising coupling a bottom contact of the second device layer with a corresponding top contact of the third device layer to connect a negative terminal of one of the plurality of first capacitors to one of the plurality of second switches.

28. further comprising vertically embedding a multilayer ceramic capacitor into the substrate to form the third device layer; one or more contacts connected to a positive terminal of the multilayer ceramic capacitor located on the first surface of the third device layer; 28. The method of any of claims 24-27, wherein one or more contacts are connected to a negative terminal of the multilayer ceramic capacitor located on a second surface of the third device layer opposite the first surface.

29. The method of any of claims 24 to 27, further comprising embedding a multi-layer ceramic capacitor within a molded composite material to form the third device layer.

30. 30. The method of any of claims 24-29, further comprising embedding one or more of the plurality of first switches, the plurality of second switches, and the plurality of first capacitors with a molded interconnect substrate.

31. The method of any of claims 24 to 30, further comprising vertically stacking an inductor layer adjacent to the third device layer, the inductor layer comprising an inductor connected to one or more of the plurality of first capacitors.

32. 1. A method of making a switched capacitor circuit, comprising the steps of: providing a phase device cell including a plurality of phase switches of a switched capacitor circuit; vertically stacking a plurality of cells on the phase device cell, each of the cells including a capacitor and a stack switch; Including, The method, wherein the capacitor and the stack switch of each of the plurality of cells are interconnected with the plurality of phase switches.

33. The step of stacking the plurality of cells further comprises:

33. The method of claim 32, comprising vertically stacking one or more cells in one set and one or more cells in another set, wherein in each cell in the one set, the capacitor is connected to a first subset of the multiple phase switches at a first phase node of the switched capacitor circuit, and in each cell in the other set, the capacitor is connected to a second subset of the multiple phase switches at a second phase node of the switched capacitor circuit.

34. The step of stacking the plurality of cells further comprises: connecting, for each cell, a bottom contact located on a bottom surface of the cell to a contact of another cell stacked below the cell; connecting, for each cell, a top contact located on a top surface of the cell to a contact of another cell stacked above the cell; 34. The method of claim 32 or 33, comprising:

35. 35. The method of claim 34, wherein in each cell, the capacitor is connected between corresponding bottom and top contacts.

36. 36. The method of claim 34 or 35, wherein in each cell, the stack switch is connected between corresponding bottom and top contacts.

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