Robust half-bridge

Abstract

A semiconductor transistor including a drain region, a plurality of source regions, and a plurality of gate regions interleaved with the source regions.

Description

Technical Field

[0001] Related Applications This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63 / 343,348, filed May 18, 2022, the disclosure of which is hereby incorporated by reference in its entirety.

[0002] Field Embodiments of the present invention relate to providing a half-bridge circuit with improved shoot-through tolerance.

Background Art

[0003] Many circuits, particularly common elements in high-power conversion circuits, are half H-bridges or half-bridges. A half-bridge includes a first switch and a second switch, which are generally MOSFET transistors connected in series at a junction that functions as the output node of the half-bridge.

[0004] During operation, a first MOSFET transistor, conventionally called the high-side (HS) transistor or switch, is connected to the high-voltage terminal of a power source, and a second MOSFET transistor, conventionally called the low-side (LS) transistor or switch, is connected to the low-voltage terminal of the power source. Dedicated HS and LS gate drivers are connected to the gates of the HS and LS transistors, respectively, to control the transistors to be ON (closed) and conductive, or OFF (open) and non-conductive. A load is connected between the output node of the half-bridge and the low-voltage terminal of the power source. When the HS gate driver controls the HS transistor to be ON and the LS driver controls the LS transistor to be OFF, the output node of the half-bridge is at the voltage of the high-voltage terminal "V HSrises up to "」, and it can be said that the half-bridge is turned ON. The load is connected to the HS terminal of the power supply, and the power supply supplies current and power to the load. When the gate driver controls the HS transistor to be OFF and the LS transistor to be ON, the node of the half-bridge is at the voltage of the low-voltage terminal of the power supply "V LS 」, and it can be said that the half-bridge is turned OFF, and the power supply stops supplying current and power to the load. To prevent shoot-through rush of the current flowing through the half-bridge that may damage the short-circuited power supply and / or the elements of the circuit with the power supply, the HS and LS gate drivers are controlled synchronously. As a result, when one of the transistors is ON, the other is OFF.

[0005] Since the switching time of the HS and LS transistors is always affected by jitter, to assist in protecting the power supply from short circuits, before switching between the ON state and the OFF state of the half-bridge, the gate drives are synchronized to control both transistors to be OFF for a short period called the dead time period or simply the dead time. However, even when protected by the dead time pause, when switching between the dead time and the ON state of the half-bridge, a voltage surge in the LS transistor of the half-bridge may generate a voltage at the LS transistor gate, which may cause the LS transistor to turn ON while the HS transistor is ON, resulting in a shoot-through of the half-bridge.

Summary of the Invention

[0006] One aspect of an embodiment of the present disclosure relates to providing a half bridge with improved immunity to shoot-through. To provide enhanced immunity, in accordance with an embodiment of the present disclosure, an LS transistor is formed to have a gate region operable to control current to the same drain region and a plurality of source regions interleaved therewith. When the source regions are electrically connected in parallel to form a composite source and the gate regions are electrically connected in parallel to form a composite gate, the interleaved source and gate regions provide the LS transistor with a relatively large built-in gate-source capacitance connected by a current channel of relatively low impedance between the composite gate and the composite source. The large built-in capacitance relaxes the voltage amplitude between the gate and the source and operates to reduce the probability of shoot-through when the half bridge switches from dead time to ON.

[0007] This summary is provided to introduce a selection of concepts in a simplified form that are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Brief Description of the Drawings

[0008] Non-limiting examples of embodiments of the present invention are described below with reference to the drawings appended to the present invention listed after this paragraph. The same structures, elements or parts that appear in more than one drawing are generally given the same numbers in all the drawings in which they appear. In the drawings of the embodiments of the present disclosure, labels that display icons representing a given feature may be used to refer to the given feature. The dimensions of the components and features shown in the drawings are selected for convenience and to clarify the presentation and are not necessarily shown to scale.

[0009]

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DETAILED DESCRIPTION OF THE INVENTION

[0010] In the description, unless otherwise specified, adjectives such as "substantially" and "about" that modify the conditions or relative characteristics of one or more features of the embodiments of the present disclosure are understood to mean that the condition or characteristic is defined within an acceptable range allowed for the operation of the embodiments in the intended use. Whenever general terms in the present disclosure are illustrated by reference to exemplary examples or a list of exemplary examples, one or more of the examples referred to are by way of non-limiting exemplary examples of the general terms, and the general terms are not intended to be limited to the particular exemplary example or examples referred to. The phrase "in one embodiment" is used to introduce consideration of a configuration that is an example of a possible embodiment of the present disclosure, but not necessarily essential, regardless of whether it is associated with allowances such as "may", "optionally", or "by way of example". Each of the verbs "comprise", "include", and "have", and their inflected forms, are used to indicate that one or more objects of the verb are not necessarily a complete list of components, elements, or parts of one or more subjects of the verb. Unless otherwise indicated, the word "or" in this specification and the claims is considered to be an inclusive "or" rather than an exclusive "or", and indicates at least one item, or any combination of two or more items to which it is joined.

[0011] FIG. 1 schematically shows a prior art half bridge 10 common to many conversion circuits. The half bridge 10 includes a high side switch QHS-12 and a low side switch QLS-13, which are generally MOSFET transistors, connected in series at a junction 15 that functions as the output node of the half bridge 10. Each transistor has a source S, a drain D, and a gate G. The high side gate driver HS_driver 16 is connected between the gate G and the source S of the transistor QHS-12, and controls the voltage difference between the source and the gate to control QHS-12 to be ON (closed) and conductive, or OFF (open) and non-conductive. Similarly, the low side gate driver LS_driver 17 is connected between the source S and the gate G of the low side transistor QLS-13, and controls the low side transistor to be ON or OFF. In this figure, the half bridge 10 is shown connected to the high voltage terminal 20 of the load L and the high voltage power supply VS, which supplies the voltage HV+ to the high voltage terminal 20 and the voltage HV- to the low voltage terminal 25. As an example, it is assumed that the transistors QHS-12 and QLS-13 are n-channel transistors, the drain D of the transistor QHS-12 is connected to the high voltage terminal 20 that supplies the voltage HV+, and the source S of the transistor QLS-13 is connected to the low voltage terminal 25 that supplies the voltage HV-. The load L is connected between the output node 15 of the half bridge 10 and the low voltage terminal 25 of the power supply VS.

[0012] FIG. 1 shows the ON state of the half bridge 10 in a state where the high side gate driver HS-16 controls the transistor QHS-12 to be ON (switch closed) and the low side driver LS-17 controls the transistor QLS-13 to be OFF (switch open). As a result of the half bridge 10 being ON, the output node 15 is set to the voltage HV+ supplied by the terminal 20, and the power supply VS drives the current represented by the dashed arrow 45 through the load L.

[0013] Figures 2A through 2D schematically show that HS-driver 16 and LS-driver 17 control transistors QHS-12 and QLS-13 to turn half-bridge 10 ON and OFF, alternately connecting and disconnecting load L to voltage HV+ through the ON and OFF state sequence of a conventional half-bridge with a dead time period incorporated, and supplying power to load L with pulses of current. The timeline 47 along the bottom of Fig. 2A shows that, as also shown in Fig. 1, current 45 is being driven through the ON half-bridge 10 and load L. Fig. 2B shows half-bridge 10 during a dead time period in which both QHS-12 and QLS-12 are OFF, following the ON state of half-bridge 10 shown in Fig. 2A. When switching to the dead time, a transient decay current represented by the dashed line 50 supported by parasitic inductance and capacitance flows through load L for a limited time. Fig. 2C schematically shows that the half-bridge turns OFF by gate drivers 16 and 17 that control transistor QHS-12 to OFF and transistor QLS-13 to ON, respectively, followed by the dead time shown in Fig. 2D. In the OFF state, half-bridge node 15 drops to the low voltage HV- of terminal 25 of power supply VS, there is no voltage drop across load L, and power supply VS stops supplying current and power to the load.

[0014] Fig. 3A schematically shows details of half-bridge 10 related to the operation of the half-bridge, and illustrates the behavior of the half-bridge that can generate harmful current shoot-through and ringing of the voltage applied to load L when the half-bridge switches from the dead time (Fig. 2D) to ON (Fig. 2A).

[0015] Transistor QHS-12 has parasitic capacitances CdgHS, C gsCharacterized by HS and CdsHS, included in QHS - package - 51 having internal impedances ZgIN / H and ZkIN / H, and electrical connections can be made from outside the die to the gate G and source S of the transistor respectively through this internal impedance. The HS - driver 16 is connected to the gate G and source S of the transistor QHS - 12 through respective impedances ZgEx / H and ZkEx / H outside the QHS - package - 51. ZgEx / H and ZkEx / H generally have the characteristics of conductive traces connecting the HS - driver and the transistor QHS - 12 on the printed circuit board (PCB) on which the HS - driver and the transistor QHS - 12 are implemented. Similarly, the transistor QLS - 13 is characterized by parasitic capacitances CdgLS, C gs LS and CdsLS, included in QLS - package - 52 having internal impedances ZgIN / L and ZkIN / L, and electrical connections can be made to the gate G and source S of the transistor QLS - 13 respectively through this internal impedance. The LS - driver 17 is connected to the transistor QLS - 13 through ZgEx / L and ZkEx / L outside the QLS - package - 51.

[0016] When the transistor QHS - 12 is turned on to switch between the dead - time (Figure 2D) and the ON state (Figure 2A) of the half - bridge 10, a transient current represented by the block arrow 70 flows from the power supply VS through the transistor QHS - 12 to QLS - 13. The transient current 70 branches into transient currents represented by the dashed lines 71 and 72, and charges the parasitic capacitances CdgLS, C gs LS and CdsLS of the transistor QLS - 13 and flows towards the low - voltage terminal 25 of the power supply VS. A part 73 of the current 71 flows to the power supply VS through the impedances ZgIN / L, ZgEx / L, ZkEx / L, and ZkIN / L. The transient current 70 and its transient branch currents 71, 72, and 73 charge the parasitic capacitor C gsA voltage that raises LS causes a voltage to be generated at the gate G of QLS-13, creating a voltage difference between the gate G and the source S of transistor QLS-12, operating to turn on the transistor and causing a potentially harmful shoot-through current.

[0017] Conventional attempts to prevent shoot-through and / or slight ringing at output node 15 generally involve providing a capacitor 75 in parallel with transistor QLS-13, as schematically shown in FIG. 3B. As a result of structural constraints, capacitor 75 is implemented outside of QLS-package-52 and operates as a low impedance that shorts external impedances ZgEX / L and ZkEx / L. When switching between dead time and ON, transient currents 70’, 71’, 72’ and 73’ are generated, but as schematically shown in FIG. 3B, substantially no current flows through ZgEX / L and ZkEx / L. Capacitor 75 reduces the overall impedance between the gate G and the source S of QLS-13 to an impedance on the order of that generated by the impedance inside QLS-package 52 in parallel with capacitor 75. When the impedance is reduced, the voltage generated between the gate G and the source S of transistor QLS-13 is advantageously limited when half-bridge 10 switches from dead time to the ON state. gs *

[0018] FIG. 4 schematically shows a half-bridge 80 configured to exhibit relatively robust immunity to shoot-through according to an embodiment of the present disclosure. Half-bridge 80 includes a transistor QLS-85 having a “built-in” capacitor 90 that shorts not only external impedances ZgEX / L and ZkEx / L but also internal impedances ZgIN / L and ZkIN / L of QLS package 52. When switching between dead time and ON, transient currents 70 * 71 * and 72 * and 73 *However, as schematically shown in FIG. 4, substantially no transient current flows through the impedance series ZgIN / L, ZgEx / L, ZkEx / L, and ZkIN / L. The internal capacitor 90 has a ratio C gs increases LS / CgdLS and reduces the impedance between the gate G and the source S of the transistor QLS-85 to substantially the impedance of the capacitor 90 in parallel with the parasitic impedance C gs LS. The increase in the ratio C gs LS / CgdLS and the impedance reduction advantageously limit the voltage generated between the gate G and the source S of the transistor QLS-85 to a voltage substantially lower than the voltage provided by the prior art configuration shown in FIG. 3B when the half bridge 10 switches from the dead time to the ON state. The integrated internal capacitor C gs LS also enables faster switching and thus improves the overall efficiency.

[0019] FIGS. 5A and 5B schematically show the difference between a prior art transistor such as QLS-13 included in the half bridge 10 and a transistor QLS-85 according to an embodiment of the present disclosure that may be included in the half bridge 80 of FIG. 4 to mitigate or prevent shoot-through current in the half bridge.

[0020] The conventional transistor QLS-13 shown in FIG. 5A has a source region and a drain region overlapped by source and gate electrodes labeled S and D, respectively, a resistance between the source region and the drain region, and a gate region overlapped by a gate electrode G for controlling the current I indicated by the block arrow. For the sake of presentation convenience, in FIGS. 5A and 5B, the source, drain, and gate regions are not explicitly shown or distinguished from their respective electrodes and are referred to by the same designations S, D, and G as the electrodes. The parasitic capacitances C gs and Cdg couple the source region S to the gate region G and the gate region G to the drain region D, respectively. The parasitic capacitance Cds couples the drain region D to the source region S.

[0021] On the other hand, as shown in FIG. 5B, the transistor QLS-85 is configured to have a plurality (optionally three) of source regions S interleaved with three gate regions G operable to control the resistance between the same drain region D as the source region S and thereby the current. Each source region S has an internal parasitic capacitance C gs * coupled to the adjacent gate region G by. The three source regions are electrically connected in parallel to form a composite source S C and the three gate regions are electrically connected in parallel to form a composite gate G C to form. In the configuration shown in FIG. 5B, between the composite source S C and the composite gate G C there are five internal parasitic capacitances C gs * in parallel. Assuming that all parasitic capacitances have substantially the same magnitude, all the internal built-in parasitic capacitances schematically represented by the dashed capacitor C GS bridge the composite source S C and the composite gate G C and provide a relatively large built-in parasitic capacitance equal to about 5×C gs * to the transistor QLS-85. The large internal parasitic capacitance shorts the internal impedance of the transistor and operates to provide enhanced protection against shoot-through for the half-bridge 80.

[0022] As schematically shown in FIG. 5B, in the case of N gate-source pairs in QLS-85, generally, the built-in parasitic capacitance C GS may be approximated to be equal to about (2N - 1)C gs * . Note that the magnitude of C GS can be adjusted as needed for a given circuit and for the ambient stray capacitance and / or inductance to which the circuit may be exposed by selecting an appropriate number N of gate-source pairs. C GSThe built-in capacitance can also be adjusted by forming gate-source pairs having different sizes and / or different distances between the gate regions and the source regions of different gate-source pairs, or different distances between different gate-source pairs. For example, if a first gate-source pair has a lateral extent Lgs that is substantially parallel to the y-axis of the coordinate system shown in FIG. 5B, and an additional N' gate-source pairs optionally have a lateral extent αLgs of the same y-axis, where 0 ≦ α ≦ 1, then C GS is given by equation C GS ~C gs * +2N’αC gs * It may be approximated by. In the last equation, it is also assumed that the distances along the x-axis between all gate regions and their respective adjacent source regions are the same for all gate regions.

[0023] FIGS. 6A and 6B schematically show top views of transistors 100 and 120, respectively, according to an embodiment of the present disclosure, which have a relatively large built-in parasitic capacitance and may advantageously function as a low-side switch transistor in a half-bridge. Transistors 100 and 120 are characterized by source-gate pairs having a substantially rounded rectangular shape that optionally completely surrounds the drain of the transistor. Transistor 100 shown in FIG. 6A includes a single drain 106 surrounded by a source-gate pair including a peripheral source 102 and a nested peripheral gate 104 inside the peripheral source 102. Ignoring the rounded ends of the periphery 102 and the peripheral gate 104, and assuming that one side of the peripheral source-gate pair has a "one-sided" floating capacitance equal to approximately C gs * the total built-in parasitic capacitance C GS of transistor 100 may be estimated to be approximately 2C gs * equal to.

[0024] Similarly, transistor 120 shown in FIG. 6B includes two peripheral source-gate pairs and has approximately (2 × 3)C gs* equal to the total parasitic capacitance C GS may be estimated to have. Generally, a transistor having N peripheral source-gate pairs surrounding a single drain according to an embodiment of the present disclosure has a built-in floating capacitance C GS = 2(2N - 1)C gs * may be estimated to have. The surrounding function of the peripheral source-gate pair generally operates at about twice the built-in floating capacitance of a source-gate pair having a similar structure and shape to one side of the peripheral source-gate pair.

[0025] Figures 7A - 7D show schematic views of a composite switching device, also called a switching die, comprising a plurality of transistors 100 (Figure 6A) or 120 (Figure 6B) according to an embodiment of the present disclosure.

[0026] Figure 7A shows a schematic view of a switching die 200 comprising an array 202 of a plurality of transistors 100. In addition to the array 202, the switching die 200 comprises an array 204 of built-in capacitors 206 along the lower side of the array 202, each capacitor 206 having a central electrode 208 surrounded by a peripheral electrode 207. A conductive trace 221 connects the peripheral electrodes 207 of all the capacitors 206 and the sources 102 of all the transistors 100 in parallel. A conductive trace 222 connects the central electrodes 208 of all the capacitors 206 and the gates 104 of all the transistors 100 in parallel. A conductive trace 223 connects the drains 106 of all the transistors 100 in parallel.

[0027] Figure 7B shows a schematic view of a switching die 250 comprising a plurality of transistors 100 interleaved with an array 252 of built-in capacitors 206. A conductive trace 271 connects the peripheral electrodes 207 of all the capacitors 206 and the sources 102 of all the transistors 100 in parallel. A conductive trace 272 connects the central electrodes 208 of all the capacitors 206 and the gates 104 of all the transistors 100 in parallel. A conductive trace 273 connects the drains 106 of all the transistors 100 in parallel.

[0028] FIG. 7C shows a schematic diagram of a switching die 300 including an array 302 having a plurality of transistors 100. In addition to the array 302, the switching die 200 includes an array 304 of built-in capacitors 306 along the lower side of the array 302. Each capacitor 306 is surrounded by a peripheral electrode 307 and has a central electrode 308 that extends along the entire length along the lower side. Conductive traces 321 connect the peripheral electrodes 307 of all the capacitors 306 and the sources 102 of all the transistors 100 in parallel. Conductive traces 322 connect the central electrodes 308 of all the capacitors 306 and the gates 104 of all the transistors 100 in parallel. Conductive traces 323 connect the drains 306 of all the transistors 100 in parallel.

[0029] FIG. 7D shows a schematic diagram of a switching die 350 including a plurality of transistors 120 (FIG. 6B) according to an embodiment of the present disclosure. Conductive traces 371 connect the sources 102 of all the transistors 120 in parallel. The conductive traces connect the gates 104 of all the transistors 120 in parallel. Conductive traces 373 connect the drains 106 of all the transistors 120 in parallel.

[0030] The description of the embodiments of the invention in this application is provided by way of example and is not intended to limit the scope of the invention. The described embodiments have different features, and not all of them are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of features. Variations of the described embodiments of the invention and embodiments of the invention including different combinations of the features shown in the described embodiments will occur to those skilled in the art. The scope of the invention is limited only by the claims.

Claims

1. A drain region, a plurality of source regions, and a plurality of gate regions interleaved with the source regions A semiconductor transistor comprising:

2. The semiconductor transistor according to claim 1, wherein all of the source regions are electrically connected together.

3. The semiconductor transistor according to claim 2, wherein all of the gate regions are electrically connected together.

4. The number of the plurality of gate regions is equal to the number of the plurality of source regions so as to form a plurality of gate-source pairs, and each gate-source pair includes a gate region and a source region adjacent to the gate region on the side far from the drain region. The semiconductor transistor according to any one of claims 1 to 3.

5. The built-in internal gate-source capacitance C of the transistor ＧＳ The semiconductor transistor according to claim 4, wherein the sum of is an increasing function of the number of the gate-source pairs.

6. The semiconductor transistor according to claim 5, wherein at least two gate-source pairs have different lateral ranges.

7. The semiconductor transistor according to claim 5 or claim 6, wherein, for at least two of the plurality of gate-source pairs, the distance between the source region and the gate region is different.

8. The semiconductor transistor according to claim 5 or claim 6, wherein the distance between the gate region and the source region is the same for all of the plurality of gate-source pairs.

9. The semiconductor transistor according to claim 8, wherein the gate-source pairs are equally spaced.

10. N is equal to the number of gate-source pairs, and the capacitance between the gate region and the source region is C ｇｓ ＊ when represented by C ＧＳ is approximately (2N - 1)C ｇｓ ＊ equal to that of the semiconductor transistor according to claim 9.

11. The semiconductor transistor according to any one of claims 1 to 9, wherein the source regions of the plurality of source regions are peripheral source regions that completely surround the drain region.

12. The semiconductor transistor according to claim 11, wherein the gate regions of the plurality of gate regions are peripheral gate regions that completely surround the drain region.

13. A drain region, a peripheral source region that completely surrounds the drain region, and a peripheral source gate region that completely surrounds the drain region and is nested inside the source region A semiconductor transistor comprising:

14. A semiconductor switching die comprising a plurality of transistors according to any one of claims 1 to 13.

15. The semiconductor switching die according to claim 14, wherein the sources of the plurality of transistors are electrically connected in parallel.

16. The semiconductor switching die according to claim 14 or claim 15, wherein the gates of the plurality of transistors are electrically connected in parallel. **Claim 17** The semiconductor switching die according to any one of claims 14 to 16, wherein the drains of the plurality of transistors are electrically connected in parallel. **Claim 18** A half bridge having a low-side switch comprising the semiconductor transistor according to any one of claims 1 to 13.

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