System and Method for Minimum Reliability Bit (LRB) Identification

Abstract

A minimum reliable bit (LRB) identification method based on a cumulative distribution function (CDF) is disclosed. In some embodiments, the receiver includes a detector and a decoder. The detector is configured to receive a codeword and determine a list of reliability values of bits included in the codeword. The decoder is configured to receive, from the detector, the codeword and the list of reliability values, calculate a list of CDFs of the reliability values of the codeword, identify, from the CDF list, a group including a specific number of LRB having reliability values within a threshold range, and determine the positions of each LRB of the group in the codeword.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 354,040, entitled "System and Methods for Least Reliable Bit (LRB)". This U.S. Provisional Patent Application was filed on June 21, 2022, and the entire content thereof is incorporated herein by reference.

[0002] [Technical Field] The present disclosure relates to a decoding system for identifying the least reliable bit (LRB) of a codeword based on the cumulative distribution function (CDF).

Background Art

[0003] A difficult task in a communication system is to accurately decode a codeword received via a noisy channel. Before a message is transmitted, a transmitter may encode the message using an error - correcting code that forms a codeword (e.g., adding redundant bits or parity bits to the message). A receiver receives the message transmitted via a computer network and performs decoding (e.g., error - correction processing) to extract the original message. Typically, a receiver may perform hard - decision decoding or soft - decision decoding. Hard - decision decoding or hard decoding decodes each bit by obtaining a stream of bits and treating each bit as clearly a 1 or 0, e.g., sampling the received pulse and comparing the voltage to a threshold. On the other hand, soft - decision decoding or soft decoding treats the received signal as a probability distribution and calculates the likelihood of each possible transmitted bit (e.g., soft value) based on the characteristics of the received signal. Then, the soft values are processed to obtain the hard value of the bit, i.e., 0 or 1. Soft decoding can achieve higher accuracy and reliability but at the cost of complexity. Therefore, a simplified and efficient soft - decoding technique is desired.

Summary of the Invention

Means for Solving the Problems

[0004] To address the foregoing drawbacks, minimum reliable bit (LRB) identification based on the cumulative distribution function (CDF) is disclosed. In some embodiments, a receiver in a communication system includes a detector and a decoder. The detector is configured to receive a codeword and determine a list of reliability values for the bits included in the codeword. The decoder is configured to receive, from the detector, the codeword and the list of reliability values, calculate a list of CDFs of the reliability values of the codeword, identify, from the CDF list, a group including a specific number of LRB having reliability values within a threshold range, and determine the positions of each LRB of the group in the codeword.

[0005] The foregoing and other preferred features, including various novel details of the embodiments and combinations of elements, will now be described in more detail with reference to the accompanying drawings and pointed out in the claims. It is to be understood that the specific methods and apparatus are shown by way of illustration only and not as limitations. As will be understood by those skilled in the art, the principles and features described herein may be used in a variety of numerous embodiments.

Brief Description of the Drawings

[0006] The disclosed embodiments have advantages and features that will become more readily apparent from the detailed description, the appended claims, and the accompanying drawings (or figures). A brief introduction to the drawings is as follows.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

[0007] The drawings and the following description relate to preferred embodiments for purposes of illustration only. It should be noted that from the following description, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the claims.

[0008] Here, some embodiments are referred to in detail, and examples thereof are shown in the accompanying drawings. It should be noted that whenever possible, similar or like reference numerals may be used in the figures and may indicate similar or like functions. The drawings show embodiments of the disclosed system (or method) for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods shown herein can be used without departing from the principles described herein.

[0009] FIG. 1 shows an exemplary communication system 100 having error correction. Communication systems (wireless or wired) often rely on error correction mechanisms (e.g., forward error correction (FEC)) to control errors when information is transmitted over a noisy communication channel. As shown in FIG. 1, a transmitter (e.g., encoder 102) encodes input data (e.g., information, message) using an error correction code. The encoded data (i.e., codeword) is transmitted to a receiver over a noisy channel or transmission link 104.

[0010] FEC is an encoding method that improves the bit error rate of a communication link by adding redundant information (e.g., parity bits) to the input data at the transmitter so that the receiver can use the redundant information introduced into the communication link to detect and correct errors. FEC error correction codes can be block codes, convolutional codes, or concatenated codes. Block codes operate on fixed-size packets, convolutional codes operate on streams of arbitrary length, and concatenated codes generally have the characteristics of block codes and / or convolutional codes. The present disclosure focuses mainly on decoding concatenated codes and / or block codes such as turbo product codes (TPC), open FEC (oFEC) defined in International Telecommunication Union (ITU) G.709.3.

[0011] The receiver can detect, receive the encoded data including any changes made by noise during transmission, and then decode the received data to extract the input information of the transmitter. Decoding of error correction codewords usually includes hard decoding or soft decoding. Soft decoding can usually achieve better error correction ability than hard decoding for a given signal-to-noise ratio (SNR) or input error rate, but often sacrifices complexity in terms of power, range, latency, etc., as will be described below with respect to the Chase algorithm. The choice of using soft decoding or hard decoding can depend on the target error rate, noise level, as well as many system considerations. Determining the soft values used for soft decoding is not always easy or possible. The disclosure herein presents an optimized and computationally efficient soft decoding method that is excellent in performance in error correction.

[0012] In FIG. 1, the receiver includes a detector 106 and a soft decoder 108. In some embodiments, the detector 106 can detect and receive the codeword transmitted via the channel 104 and calculate reliability information for each bit of the codeword. The reliability information can include, as will be described below with respect to FIGS. 2-4, a cumulative distribution function (CDF), a log-likelihood ratio (LLR), etc. The soft decoder 108 can receive the reliability information from the detector 106 and decode the codeword to extract the original input information / message from the transmitter / coder 102. In some embodiments, the soft decoder 108 can be configured to determine a set of test patterns based on the reliability information and determine how to perform hard decision coding for the patterns within the set of test patterns. Note that FIG. 1 is shown for illustrative purposes, and it should be noted that other components (e.g., a hard decoder) can be included in the communication system 100. For example, one or more hard decoders (not shown) can be part of the detector 106 to assist in decoding and / or can be included in the soft decoder 108 (e.g., a Chase decoder) to determine the reliability information.

[0013] When a received codeword or code is decoded using soft decoding (typically, iterative soft decoding), one of the most popular algorithms for soft decoding a single component code is the Chase algorithm. The main idea of the Chase algorithm is that if a word or message decoded by a hard decoder (i.e., conventional hard decision) contains an error, then one of its "closest" words is most likely to match the transmitted message (i.e., the input information of the transmitter). Conventionally, the Euclidean distance between the received codeword and the original codeword is calculated, and an exhaustive search is performed to find the codeword. This type of decoding method is quickly prohibited due to the intractable computational complexity associated with the increase in the codeword size. The Chase algorithm is a maximum likelihood (ML) bit estimation, which is based on the observation that at high SNR, the ML codeword is very likely to be located within a specific sphere centered at a specific point (e.g., determined based on SNR and the received code). To reduce the number of codewords to be reviewed, only the set of the most likely codewords (i.e., the "closest" codewords) within the sphere is selected. Further explanation of the Chase algorithm is described in R. M. Pyndiah, Near-Optimum Decoding of Prodcut Codes:Block Turbo Codes.IEEE Transactions on Communications, Vol. 46, No. 8(1998).

[0014] Generally, the Chase algorithm enumerates a set of selected bit patterns decoded by a hard decoder. The results of applying the hard decoder to all bit patterns are used to generate soft decision metrics or reliability information, such as log(A), including likelihood ratio (LLR). In some embodiments, the pattern can be generated by taking bits within a hard pattern (slicing of soft bits) and inverting some of the least reliable bits (LRB). Different combinations of the least reliable bits are processed, and the output of the soft decoder is the candidate word with the best soft decision metric.

[0015] The Chase algorithm can improve performance in some way but has obvious drawbacks. The Chase algorithm requires the identification of the least reliable bit (or the least reliable position). When using the Chase algorithm, the entire codeword has to be analyzed to find the specified n least reliable bits (LRBs).

[0016] The reliability of a bit is often measured by the absolute value of the bit's LLR. In the Chase algorithm, LRB identification is based on reading a list of bit-by-bit LLRs, comparing the LLRs of each bit, and maintaining a dynamic list of N LRBs. The dynamic list is updated until all bits of the codeword have been scanned. The final result is a list of the least reliable bits. The list may also include the bit positions and bit LLR / reliability associated with the least reliable bits. Here, a significant amount of hardware and other computational resources may be required to implement a high-speed decoder.

[0017] The present system and method for LRB identification disclosed herein address the aforementioned drawbacks and improve the performance of error correction decoding. Conventional systems (e.g., Chase) use a one-pass (e.g., at read time) algorithm to find the LRB with a large decision tree, thereby causing a significant amount of power consumption and / or a large latency. In the present system, the comparison operation for LRB identification is performed against a fixed value, and the logic decision tree is significantly simplified. In some embodiments, the present system uses a two-pass algorithm to simplify the identification process and reduce power usage. Compared with the one-pass at read time in a Chase decoder, the two-pass can typically be realized when the decoding process is split between writing and reading. Thus, the present system reduces complexity and latency and increases efficiency and accuracy when applied in identifying the LRB of a codeword in the decoding process.

[0018] Furthermore, the present method can be used in any system that needs to identify extreme values in the data, which is particularly advantageous in the context of error correction decoding where the reliability resolution is low and only a limited amount of values are available for CDF determination.

[0019] Note that the "Chase decoder" or "Chase algorithm" in this specification refers to a general soft decoder that enumerates patterns as used in error correction literature. These do not necessarily have to select and refer to the original Chase prototype.

[0020] FIG. 2 shows an exemplary input codeword 200 with associated reliability information. The codeword 200 is an input to either the detector 106 or the soft decoder 108 of the receiver. The input codeword 200 may contain errors, and the receiver aims to decode it to correctly extract the original message of the transmitter. In some embodiments, the codeword 200 is encoded data (e.g., having an error correction code) transmitted from the transmitting side (e.g., the encoder 102) to the receiving side via the communication channel 104.

[0021] When a bit index 202 in the range from 0 to 9 is given, the input codeword 200 contains 10 bits. The LLR 204 of each bit is calculated (e.g., by the detector 106), which is the soft decision metric or reliability information used in subsequent soft decoding. In some embodiments, the sign (e.g., positive or negative) of the LLR value 204 corresponds to a hard decision. For example, a negative sign indicates that the corresponding bit is considered to be '1', while a positive sign corresponds to a decision of '0'. The magnitude of the LLR value 204 corresponds to the certainty or likelihood in that decision. In the example shown in FIG. 2, the reliability value 206 is the absolute value of the LLR 204.

[0022] An approach for LRB identification based on the generation of a cumulative distribution function (CDF) of reliability is disclosed herein. In some embodiments, the technique enables a receiver (e.g., detector 106 and soft decoder 108 of FIG. 1) to determine a list of values of the least reliable bits (e.g., reliability values 206 of FIG. 2) and identify from the list a maximum value that can be used to determine n LRB. The maximum value refers to the maximum reliability value within the LRB. Thus, the maximum value is the maximum LRB value or LRB threshold. By generating the CDF of reliability in the system, the receiver can simply examine the CDF to identify groups / bins of bits having reliability values within a threshold range (i.e., the maximum LRB value). This is described below with respect to FIGS. 3 and 4. The receiver can then examine the LLRs or list of reliability (e.g., list 200 in FIG. 2) to obtain the positions of the least reliable bits in the identified groups.

[0023] FIG. 3 shows an exemplary LRB identification result 300 from applying the technique to the codeword 200 of FIG. 2. The result 300 is a list of LRB for identifying three LRB from the codeword 200 of FIG. 2. In this example, the result 300 includes LRB index 302 and LRB value 304. The LRB index 302 is the location / position of each of the three least reliable bits within the codeword 200. The LRB value 304 measures the reliability of the corresponding least reliable bit.

[0024] This approach thus enables the construction of the CDF of reliability for (1) the entire sequence of received codewords or (2) a partial sequence of the codeword received at that instant. Since data decoding can be performed simultaneously while subsequent data (e.g., a new portion of a codeword, a new codeword) is still being transmitted to the receiver, this technique provides particular benefits for time-dependent data recovery.

[0025] In some embodiments, upon receiving a coded word, a receiver (e.g., detector 106 and soft decoder 108) may first calculate the CDF of this coded word and then use the LRB threshold to identify the LRB locations within the coded word. This approach can be used to perform iterative decoding easily and efficiently. In this system, the LLR can be updated from one coded word and written to memory. When decoding subsequent coded words later, the system can read the LLR from memory. Thus, by maintaining the CDF for each coded word in the write process, this technique may enable the bit or LRB positions to be easily identified when the LLR is read for the next coded word. Using this technique, the reliability value of each bit (e.g., LRB value 304) is used only once in a second pass to compare with a specified threshold. This system calculates the LRB more efficiently compared to a conventional Chase decoder. (In the description of the conventional Chase algorithm, determining the LRB in the first or preprocessing stage of Chase is a matter of arbitrary definition).

[0026] FIG. 4 shows an exemplary CDF 400 of reliability values calculated for the exemplary coded word 200 of FIG. 2. The CDF in this disclosure refers to the cumulative histogram of reliability information. In FIG. 4, each CDF index 402 is the maximum LRB value (i.e., the maximum reliability value within the LRB). Each CDF value 404 counts the total number of bits in the coded word 200 that have reliability values below the corresponding CDF index.

[0027] Assume that the CDF index, which is the maximum reliability value that can be in the LRB, is set to 1 (for example, 406). Referring to FIG. 2, only three bits (i.e., bit indices "2", "3", and "7") have reliability values of 0 or 1 that are less than or equal to the CDF index "1" at 406. Thus, the corresponding CDF value is "3" at 408. When the CDF index or the maximum reliability value is set to 2 at 410, these three bits with reliability values less than or equal to 2 still exist, and thus the CDF value at 412 is still "3". In FIG. 2, the maximum reliability value of all bits is 18, and thus the CDF value 414 counts all the "10" bits of the codeword 200 when the CDF index is set to "18" at 416.

[0028] Based on the CDF 400 shown in FIG. 4, the receiver (e.g., the soft decoder 108) may identify a specific number of LRB in the codeword 200. In the illustrated example, three LRB are selected. This means that the threshold is the first bin having a CDF value of 3 or more. According to the CDF 400, this is bin / group 1 having the CDF index "1" at 406. In other words, this bin contains the least reliable data bits having a reliability of 1 or less. This LRB identification result is shown in FIG. 3, where the LRB index 302 identifies each of the three least reliable bits, and the LRB value 304 indicates the reliability value corresponding to each identified bit.

[0029] FIG. 5 shows an exemplary method 500 for LRB identification. In some embodiments, the detector 106 is configured to receive a codeword (e.g., an error-containing codeword encoded with an error correction code) and generate reliability information (e.g., LLR) about the bits included in the codeword. As shown, at 502, a new bit of the codeword is read and the LLR can be determined. The bit and the LLR can be written to the memory at 504. Reliability information such as the LLR can be used as input data to the soft decoder 108 to construct the CDF of the codeword. The CDF can be written to and updated in the memory at 506.

[0030] As described above in FIGS. 2 to 4, the soft decoder 108 can read the CDF at 508, read the LLR determined for the codeword bits at 510, and identify and select the LRB based on the CDF and the LLR at 512. Once the LRB is determined, the soft decoder 108 can use the LRB to execute the decoding process. When iterative decoding is used, the soft decoder 108 can output the LLR (514) and output the CDF to be used in the next iteration (516). When the decoding is complete, at 514, the soft decoder 108 can also output the retrieved message, which should be the original message from the transmitter side 102. The retrieved message is typically extracted from the LLR by threshold processing, i.e., processing less than zero.

[0031] After decoding the codeword, the soft decoder 108 updates the CDF. In practice, when the soft decoder 108 executes the decoding of the codeword, the codeword is often interleaved (i.e., the bits being decoded belong to multiple codewords). Usually, the soft decoder 108 executes the decoding alternately between the codewords. For example, the decoding of the TPC can be executed row by row and then moved to the columns. This decoding process is repeated until the decoder ends. To process the interleaved codewords, the system is configured to prepare the CDF for the subsequent codewords to be decoded. Continuing with the example of the TPC, assuming that the last decoding stage in the TPC is by rows, the soft decoder 108 is configured to construct the column CDF to enable column LRB detection. In particular, since the bits need to be rearranged from rows to columns for decoding, the system advantageously configures the detector 106 and / or the soft decoder 108 to calculate and update the CDF after this bit rearrangement operation.

[0032] Therefore, the CDF is updated when the LLR is written into the memory after each individual current codeword has been decoded. Usually, in iterative decoding of related codes, after a codeword has been decoded, the CDFs of other codewords that use the same data bits as the other codewords must be updated. However, as described above, the CDF of the current codeword may also be updated. In the case of the TPC where decoding is performed alternately by rows and columns, after a column codeword has been decoded, the CDF for the row codeword should also be updated in preparation for row decoding, and vice versa. The CDF is updated during different iterations.

[0033] The CDF of the codeword may be written into the memory (such as 506, for example) or held in a register. In this system, once the CDF is determined, it can be replaced by a single number (such as the CDF threshold 406 in FIG. 4). This CDF is held in its entirety until the threshold is determined. For example, if two or three LRB (i.e., n = 2 or n = 3) need to be identified from the CDF list in FIG. 4, the CDF threshold is "1" as shown in 406. If any of four, five, or six LRB need to be identified, the threshold is "2" as shown in 410.

[0034] In some embodiments, when the number of LRB is predefined, instead of retaining the entire CDF, only the threshold values are extracted and stored. In some embodiments, a threshold value n is specified. The number of reliabilities equal to the threshold value n can be used to simplify the reliability comparison and the selection of LRB positions by selecting all bits with a reliability smaller than the threshold value n and the first n bits with equal reliability. Specifically, if n is known (e.g., predefined), the CDF value 404 need not retain numbers larger than n. As a result, the CDF list 400 of FIG. 4 can be truncated. Further, during the calculation of the CDF, it can be dynamically determined that certain values are no longer relevant and can thus be discarded. In other words, assuming FIG. 4 includes the intermediate CDF list 400 with n = 2, the threshold is currently "1", and when more data is added, it can only remain at 1 or become 0, so all rows with CDF index 402 values larger than 1 can be discarded. Based on these considerations used to reduce the size of the CDF list, system performance is improved by storing and using more meaningful information for decoding.

[0035] FIG. 6 shows an exemplary method 600 of using an oFEC decoder to apply LRB identification based on the CDF described herein. This LRB-CDF approach is particularly suitable for use in oFEC as defined in ITU G.709.3. oFEC is typically performed with a small number of bits per LLR. For example, in the ITU G.709.3 specification, 4 bits per LLR are recommended. These 4 bits include 3 bits after the absolute value. This indicates that the CDF only includes 2 3 = 8 levels. This also means an easy implementation and high efficiency of applying this LRB-CDF approach to an oFEC decoder. The operation flow of using an oFEC decoder to execute the LRB-CDF approach shown in FIG. 6 is the same as that shown in FIG. 5, so for the sake of brevity and clarity, the description will not be repeated here.

[0036] Figure 7 shows an exemplary high-degree oFEC decoder 700 having three soft iterations and two hard iterations according to some embodiments. This is the configuration proposed in the ITU G.709.3 standard and is also used in this system to show improved decoding performance.

[0037] Figure 8 shows an exemplary decoding process 800 that uses Chase decoding in an oFEC decoder. In the illustrated example, the soft iteration is implemented using a Chase decoder and the CDF is calculated for the oFEC decoder. As shown at 802, the codeword is arranged such that two 16×16 blocks are involved in two 16-block equations. The two equations are processed in one order once and then in another order, in an alternating order. Each bit is involved in exactly two equations. The soft decoder operates on groups of 16 equations and the Chase decoder also operates in multiples of 16. At 804, the LLRs for 16 equations are read and the previously determined CDF threshold is also read. In some embodiments, at 806, to find the LRB, the soft decoder reads the LLRs and during the read, the soft decoder compares the LLRs to the threshold and separately holds the value and index of the LRB. Then, the Chase decoder, at 808, executes all patterns based on the determined LRB and, at 810, updates the LLRs for the next iteration. Next, at 812, the LLRs are changed to the changed order of the bits in the equation. Based on the changed LLRs, the CDF is calculated at 814 and the LLRs are written to memory at 816. After all the LLRs of the codeword are written, the threshold is determined at 818 and written to memory at 820 for use in the next iteration.

[0038] In the case of oFEC, there is a delay between the reading and writing of the LLRs and thus the LLR values are typically written to memory. In the example of the 16×16 block shown for oFEC in Figure 8, there is a delay between the first equation in which the bit is involved and the second time in which the equation in which the bit is involved exists, so the LLR is written to memory. As a result, there is an opportunity to construct the CDF when the LLR is written to memory.

[0039] FIG. 9 shows an exemplary process 900 for CDF-based LRB identification. In some embodiments, a communication system includes an encoder / transmitter for transmitting information / messages to a receiver over a noisy communication channel. The encoder is configured to encode a codeword using an error correction code and transmit the codeword to the receiver over the communication channel. The receiver is configured to execute a CDF-based LRB identification process 900. In some embodiments, the receiver includes a detector and a soft decoder for implementing the steps of process 900.

[0040] At step 905, the codeword is received at the receiver. The codeword may contain errors, and the receiver aims to decode it to correctly extract the original message of the transmitter.

[0041] At step 910, a list of reliability values of the bits included in the codeword is determined. In some embodiments, each of the reliability values is the absolute value of a log-likelihood ratio (LLR). An example of the list of reliability values is shown in FIG. 2.

[0042] At step 915, a list of CDFs of the reliability values of the codeword is calculated. An example of the CDF list is shown in FIG. 4.

[0043] At step 920, a group of threshold values is identified from the CDF list. The group includes a specific number of LRB having reliability values within a threshold range. In some embodiments, the receiver (e.g., detector 106 and soft decoder 108 of FIG. 1) determines a list of values of the least reliable bits (e.g., reliability value 206 of FIG. 2) and identifies the maximum LRB value from the list that can be used to determine n LRB. The maximum LRB value refers to the maximum reliability value within the LRB. By generating the CDF of reliability in this system, the receiver can simply inspect the CDF to identify groups / bins of bits having reliability values within the threshold range (i.e., the maximum LRB value).

[0044] In step 925, the position of each LRB within the coded word is determined. The LRB is included in the identified group / bin. The receiver may examine the LLR or reliability list (e.g., list 200 in FIG. 2) to obtain the positions of these least reliable bits in the coded word. An example of the result is shown in FIG. 3.

[0045] In some embodiments, when a threshold is determined, there may be more bits with reliability values below the threshold than n bits. There is some degree of freedom as to which positions can be selected for bits from the identified bin / group. In some embodiments, when creating the CDF, the receiver may be configured to store, along with the threshold, the number of LRB's in the identified bin / group to be taken. This reduces ambiguity and unnecessary comparisons, thereby further improving the decoding performance.

[0046] [Additional Considerations] In some implementations, at least a portion of the techniques described above may be implemented, at runtime, by instructions that cause one or more processing devices to perform the processes and functions described above. Such instructions may include, for example, interpreted instructions such as script instructions, or executable code, or other instructions stored on a non-transitory computer-readable medium. The storage device 830 may be implemented in a distributed manner over a network, for example as a server farm or a set of servers widely distributed, or may be implemented on a single computing device.

[0047] Although an exemplary processing system has been described, embodiments of the subject matter, functional operations, and processes described in this specification can be implemented in other types of digital electronic circuitry, tangible computer software or firmware, computer hardware, or combinations of one or more of them, including the structures disclosed herein and their structural equivalents. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., as one or more modules of computer program instructions encoded on a tangible non-transitory program carrier for execution by, or to control the operation of, a data processing apparatus. Alternatively or additionally, the program instructions can be encoded on a machine-generated electrical, optical, or electromagnetic signal, e.g., a propagated signal generated artificially for transmission to an appropriate receiver device for execution by a data processing apparatus. A computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0048] The term "system" can include, by way of example, all kinds of apparatus, devices, and machines for processing data, including programmable processors, computers, or multiple processors or computers. A processing system can include dedicated logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). A processing system can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., processor firmware, protocol stack, database management system, operating system, or code that constitutes one or more combinations of them.

[0049] A computer program (which may also be called or described as a program, software, software application, module, software module, script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and can be deployed in any form, either as a stand-alone program or included as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may or may not correspond to a file in a file system. The program can be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), a single file dedicated to the program, or multiple cooperating files (e.g., files that store one or more modules, subprograms, or portions of code). A computer program can be deployed to be executed on one computer or located at one site, or distributed across multiple computers interconnected by a communication network and executed on multiple computers.

[0050] The processes and logical flows described herein can be performed by one or more programmable computers that execute one or more computer programs to function by operating on input data and generating output. The processes and logical flows can also be performed by dedicated logic circuitry, such as an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit), and the apparatus can also be implemented as dedicated logic circuitry, such as an FPGA or ASIC.

[0051] Computers suitable for the execution of a computer program can include, by way of example, general or special purpose microprocessors, or both, or any other kind of central processing unit. Generally, the central processing unit receives instructions and data from read-only memory or random access memory, or both. A computer generally includes a central processing unit for executing instructions and one or more memory devices for storing the instructions and data. Generally, a computer includes or is operatively coupled to one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or receives data from, transfers data to, or both of these. However, a computer need not have such devices. Further, a computer may be embedded in another device, such as, by way of example, a cellular phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive).

[0052] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices, magnetic disks, such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in, dedicated logic circuitry.

[0053] To provide interaction with a user, embodiments of the subject matter described herein can be implemented on a computer having a display device for displaying information to the user, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, and a keyboard and a pointing device, such as a mouse or trackball, by which the user can provide input to the computer. Other types of devices can be used to provide interaction with the user, and for example, the feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and the input received from the user can be in any form including acoustic, voice, or tactile input. Further, the computer can interact with the user by sending a document to a device used by the user and receiving the document from that device, such as by sending a web page to a web browser on the user's user device in response to a request received from the web browser.

[0054] Embodiments of the subject matter described herein can be implemented in a computing system that includes back-end components, such as a data server, or includes middleware components, such as an application server, or includes front-end components, such as a client computer having a graphical user interface or a web browser by which a user can interact with an implementation of the subject matter described herein, or includes any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, such as by a communication network. Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), such as the Internet.

[0055] A computing system may include clients and servers. The clients and servers are generally remote from each other and typically interact via a communication network. The relationship between a client and a server is created by computer programs that run on respective computers and have a client-server relationship with each other.

[0056] This specification includes many details of specific implementations, but these should not be construed as limitations on the scope of what can be claimed, but rather as descriptions of features that may be specific to particular embodiments. The specific features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately in multiple embodiments or in any suitable partial combination. Furthermore, features may be described above as acting in a certain combination and may initially be claimed as such, but in some cases, one or more features from the claimed combination can be deleted, and the claimed combination can be directed to a partial combination or a variation of a partial combination.

[0057] Similarly, operations are shown in the drawings in a particular order, but this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order to achieve the desired result, or that all of the shown operations be performed. In some situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0058] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes shown in the accompanying figures do not necessarily require the particular order or sequential order shown to achieve desirable results. In some embodiments, multitasking and parallel processing are advantageous. Other steps or acts may be provided or steps or acts may be eliminated from the described processes. Accordingly, other embodiments are within the scope of the following claims.

[0059] The phrases and terms used herein are for the purpose of description and should not be regarded as limiting.

[0060] As used herein, the term “substantially,” the phrase “substantially equal,” and other like phrases (e.g., “X has a value substantially equal to Y” or “X is substantially equal to Y”) should be understood to mean that one value (X) is within a predetermined range of another value (Y). The predetermined range may be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1% unless otherwise indicated.

[0061] As used in this specification and the claims, the term "one" should be understood to mean "at least one" unless the contrary intention is expressly stated. The phrase "and / or" as used in this specification and the claims should be understood to mean "either or both" of the elements so joined, i.e., elements that may be present conjunctively in some cases and disjunctively in other cases. A plurality of elements listed with "and / or" should likewise be construed as "one or more" of the elements so joined. Other elements may optionally be present whether or not they are related to the specifically identified elements by virtue of being specifically identified in the "and / or" clause. Thus, by way of non-limiting example, reference to "A and / or B", when used in conjunction with open-ended language such as "comprising", may refer in one embodiment to only A (optionally including elements other than B), in another embodiment to only B (optionally including elements other than A), and in yet another embodiment to both A and B (optionally including other elements), and so on.

[0062] As used in this specification and the claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" is inclusive, i.e., it includes at least one of several elements or a list of elements, but also includes more than one, and optionally, additional unenumerated items. Only terms such as "only one of", "exactly one of", or "consisting of" when used in the claims, where the contrary is clearly indicated, refer to exactly one element of several elements or a list of elements. Generally, the term "or" used is to be construed as indicating an exclusive alternative (i.e., "one or the other but not both") only when preceded by an exclusive term such as "either", "only one of", "only one of them", or "exactly one of". When "consisting essentially of" is used in the claims, it should have the ordinary meaning used in the field of patent law.

[0063] As used in this specification and the claims, in relation to a list of one or more elements, the phrase "at least one" means at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically listed in the list of elements, nor is it necessarily limited to excluding any combination of elements in the list of elements. This definition also allows for the possibility that elements other than those specifically identified in the list of elements referred to by the phrase "at least one" may optionally be present, whether or not they are related to the specifically identified elements. Thus, by way of non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") can, in one embodiment, refer to at least one, optionally two or more, of A, with no B present (and optionally including elements other than B), in another embodiment, refer to at least one, optionally two or more, of B, with no A present (and optionally including elements other than A), and in yet another embodiment, refer to at least one, optionally two or more, of A, and at least one, optionally two or more, of B (and optionally including other elements), and so on.

[0064] The use of "including", "comprising", "having", "containing", "involving", and variations thereof means including the items listed thereafter and additional items.

[0065] The use of ordinal terms such as "first," "second," "third," etc. in the claims to limit elements in the claims does not, by itself, imply any priority, precedence, or order of one claim element over another, or the temporal order in which acts of a method are performed. Terms indicating order are used only as labels to distinguish one claim element having a certain name from another element having the same name for the purpose of distinguishing claim elements (except for the use of terms indicating order).

[0066] Although some aspects of at least one embodiment of the present invention have been described in this way, it should be understood by those skilled in the art that various changes, modifications, and improvements will readily occur to them. Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the present invention. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. In a communication system, a receiver for identifying minimum reliability bits (LRBs), comprising: a detector configured to receive a codeword and determine a list of reliability values of the bits included in the codeword; a decoder coupled to the detector, the decoder being configured to receive, from the detector, the codeword and the list of reliability values, calculate a list of cumulative distribution functions (CDFs) of the reliability values of the codeword, identify, from the list of CDFs, a group including a specific number of LRBs having reliability values within a threshold range, and determine positions of each of the LRBs in the group within the codeword; a receiver comprising the decoder.

2. The receiver according to claim 1, wherein the reliability value among the plurality of reliability values is an absolute value of a log-likelihood ratio (LLR).

3. The receiver according to claim 1, wherein the decoder is further configured to decode the codeword based on the identified LRBs and positions associated with the LRBs.

4. The receiver according to claim 3, wherein the decoder is further configured to update the CDF after decoding the codeword, and the decoder is further configured to prepare the CDF for a subsequent codeword to be decoded in order to update the CDF.

5. The decoder is further configured to update the LLR of the codeword, and write the LLR to a memory; the receiver according to claim 3.

6. The receiver according to claim 5, wherein the decoder is further configured to read the LLR from the memory when decoding a next codeword at a later time.

7. The decoder is an open forward error correction (oFEC) decoder, and the oFEC decoder is configured to construct the CDF when writing the LLR to the memory; the receiver according to claim 1.

8. The receiver according to claim 1, wherein the decoder is further configured to construct the CDF for an entire sequence of the codewords or a partial sequence of the codewords.

9. The receiver uses a two-pass algorithm to simplify the LRB identification process, and the two-pass algorithm is realized when the decoding process is divided between a write operation and a read operation; the receiver according to claim 1.

10. The receiver according to claim 1, wherein the symbol word is encoded with an error correction code, and the detector is configured to receive the symbol word from the encoder via a communication channel.

11. A method for identifying minimum reliability bits (LRBs) by a receiver, comprising: receiving a symbol word encoded with an error correction code; determining a list of reliability values of the bits included in the symbol word; calculating a cumulative distribution function (CDF) of the reliability values of the symbol word; identifying from the CDF a group including a specific number of LRBs having the reliability values within a threshold range; determining positions of each LRB of the group within the symbol word.

12. The method according to claim 11, wherein the reliability value among the plurality of reliability values is an absolute value of a log-likelihood ratio (LLR).

13. The method according to claim 11, further comprising decoding the symbol word based on the identified LRBs and positions associated with the LRBs.

14. The method according to claim 13, further comprising updating the CDF after decoding the symbol word, wherein the updating comprises preparing the CDF for a subsequent symbol word to be decoded.

15. The method according to claim 13, further comprising updating the LLR of the symbol word and writing the LLR into a memory.

16. The method according to claim 15, further comprising reading the LLR from the memory when decoding a next symbol word at a later time.

17. The method according to claim 11, further comprising constructing the CDF when writing the LLR into a memory by an open forward error correction (oFEC) decoder.

18. The method according to claim 11, further comprising constructing the CDF for an entire sequence of the symbol words or a partial sequence of the symbol words.

19. The method according to claim 11, wherein the identifying the LRBs is simplified using a two-pass algorithm, and the two-pass algorithm is realized when a decoding process is divided between a writing operation and a reading operation.

20. The method according to claim 11, wherein the receiver comprises a detector and a soft decoder, and the receiver receives the encoded symbol word from an encoder via a communication channel.

Images