A package comprising a substrate having a bridge configured for an inner power distribution network

Abstract

A package comprising a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority and benefit to non - provisional application Ser. No. 17 / 835,861, filed with the United States Patent and Trademark Office on Jun. 8, 2022, the entire content of which is hereby incorporated by reference into this specification as if fully set forth herein in its entirety and for all applicable purposes.

[0002] Various features relate to a package having a substrate and an integrated device.

Background Art

[0003] A package may include a substrate and an integrated device. These components are integrally coupled to provide a package that can perform various electrical functions. There is a continuing need to provide packages that function better and that reduce the overall size of the package.

Summary of the Invention

[0004] Various features relate to a package having a substrate and an integrated device.

[0005] One example provides a package comprising a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0006] Another example provides a device that includes a package. The package includes a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0007] Another example provides a method for fabricating a package. The method includes providing a substrate. The method includes installing a bridge within the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate. The method includes coupling a first integrated device to the substrate. The method includes coupling a second integrated device to the substrate.

[0008] The various features, properties, and advantages may become apparent by reading the "Detailed Description of the Invention" described below in conjunction with the drawings that identify corresponding elements throughout.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] In the following description, specific details are set forth in order to provide a thorough understanding of the various aspects of the present disclosure. However, one of ordinary skill in the art will understand that the aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the present disclosure.

[0011] The present disclosure describes a package comprising a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate. A passive device may be located within the substrate. The bridge may be configured to provide at least one electrical path between the first integrated device and the second integrated device. The passive device is coupled to the bridge. The passive device may be regarded as part of the bridge. A encapsulation layer may be coupled to the bridge. The encapsulation layer is located within the substrate. The passive device may be coupled to the power distribution network of the bridge. As further described below, the package provides passive devices located closer to the first integrated device and / or the second integrated device, which helps to provide improved package performance while keeping the package small and thin.

[0012] Exemplary package comprising a substrate having a bridge FIG. 1 shows a side cross-sectional view of a package 100 including a substrate having a bridge. The bridge is configured to provide an electrical path for signals between integrated devices. The bridge is configured to provide an electrical path for a power distribution network (PDN). The package 100 is coupled to a board 106 via a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0013] Package 100 includes a substrate 102, an integrated device 103, an integrated device 105, and a bridge 107. The integrated device 103 can be a first integrated device. The integrated device 105 can be a second integrated device. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 is coupled to a board 106 via a plurality of solder interconnects 110. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and a plurality of board interconnects 162.

[0014] The integrated device 103 is coupled to a first surface (e.g., the top surface) of the substrate 102 via a plurality of solder interconnects 130. The plurality of solder interconnects 130 are coupled to the integrated device 103 and the plurality of interconnects 122 of the substrate 102. The integrated device 105 is coupled to the first surface (e.g., the top surface) of the substrate 102 via a plurality of solder interconnects 150. The plurality of solder interconnects 150 are coupled to the integrated device 105 and the plurality of interconnects 122 of the substrate 102.

[0015] The bridge 107 is located within the substrate 102. The substrate 102 may include a cavity 109. An example of a cavity within a substrate is shown and described at least in FIG. 11A below. The bridge 107 may be located within the cavity 109 of the substrate 102. The bridge 107 is configured to provide a plurality of electrical paths for signals between the integrated device 103 and the integrated device 105. The bridge 107 is configured to provide at least one electrical path for a power distribution network (PDN). The bridge 107 is configured to provide at least one electrical path for power. The bridge 107 is configured to provide at least one electrical path for ground. The bridge 107 may include a front side and a back side. As further described below, the bridge 107 is configured to provide at least one electrical path for power and / or ground through the back side of the bridge 107.

[0016] As will be further described below, at least in FIG. 2, at least one passive device may be coupled to bridge 107. For example, at least one passive device may be coupled to the back side of bridge 107. The passive device coupled to bridge 107 may be configured to be coupled to power and / or ground. The passive device coupled to bridge 107 can be regarded as part of bridge 107.

[0017] Bridge 107 includes a bridge substrate 170, at least one bridge dielectric layer 172 (e.g., at least one first bridge dielectric layer), at least one bridge dielectric layer 174 (e.g., at least one second bridge dielectric layer), a plurality of bridge interconnects 171, a plurality of bridge interconnects 173 (e.g., at least one first bridge interconnect), and a plurality of bridge interconnects 175 (e.g., at least one second bridge interconnect). The bridge substrate 170 may include a silicon substrate (e.g., a silicon bridge substrate). However, the bridge substrate 170 may include different materials. The at least one bridge dielectric layer 172 is coupled to a first side (e.g., the front side, the upper side) of the bridge substrate 170. The plurality of bridge interconnects 173 are disposed within and on (e.g., within and above) the at least one bridge dielectric layer 172. The plurality of bridge interconnects 173 may be a plurality of front-side bridge interconnects. The at least one bridge dielectric layer 172 and the plurality of bridge interconnects 173 can be regarded as a part of the front side of the bridge 107. The at least one bridge dielectric layer 174 is coupled to a second surface (e.g., the back side, the lower side) of the bridge substrate 170. The plurality of bridge interconnects 175 are disposed within and on (e.g., within and below) the at least one bridge dielectric layer 174. The at least one bridge dielectric layer 174 and the plurality of bridge interconnects 175 can be regarded as a part of the back side of the bridge 107. The plurality of bridge interconnects 175 may be a plurality of back-side bridge interconnects. The plurality of bridge interconnects 171 may extend through the front side of the bridge 107, the bridge substrate 170, and / or the back side. For example, the plurality of bridge interconnects 171 may extend through (e.g., partially or completely) the at least one bridge dielectric layer 172, the bridge substrate 170, and / or the at least one bridge dielectric layer 174. The plurality of bridge interconnects 171 may be coupled to the plurality of bridge interconnects 173 and the plurality of bridge interconnects 175. The plurality of bridge interconnects 171 may include a plurality of bridge vias (e.g., bridge via interconnects).

[0018] Bridge 107 is configured to provide a plurality of electrical paths for input / output signals, power supply, and / or ground. FIG. 1 shows three exemplary electrical paths that Bridge 107 can be configured to provide. Note that Bridge 107 can be configured to provide more than three electrical paths. Thus, Bridge 107 can be configured to provide other electrical paths.

[0019] FIG. 1 shows electrical path 101, electrical path 104, and electrical path 108. Electrical path 101 is an example of an electrical path between integrated device 103 and integrated device 105. Electrical path 101 is configured to provide an electrical path for input / output (I / O) signals between integrated device 103 and integrated device 105. Electrical path 101 can include (i) at least one solder interconnect from a plurality of solder interconnects 130, (ii) at least one interconnect from a plurality of interconnects 122, (iii) at least one bridge interconnect (e.g., 171, 173) from Bridge 107, (iv) at least one other interconnect from a plurality of interconnects 122, and (v) at least one other solder interconnect from a plurality of solder interconnects 150. Electrical path 101 extends through the front side of Bridge 107. Note that there can be a plurality of electrical paths similar to electrical path 101 between integrated device 103 and integrated device 105. In one example, each of the electrical paths between integrated device 103 and integrated device 105 that extend through the bridge can be configured as an electrical path for I / O signals.

[0020] Electrical path 104 is an example of an electrical path that extends through at least board 106, substrate 102, and bridge 107. Note that electrical path 104 can also extend to integrated device 103 and / or integrated device 105. In one example, electrical path 104 is configured to provide an electrical path for power (as part of a power distribution network). Power can be supplied to integrated device 103. In another example, electrical path 104 is configured to provide an electrical path for ground. Electrical path 104 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, and (iv) at least one bridge interconnect (e.g., 171, 173, 175) from bridge 107. Electrical path 104 can also include a solder interconnect from a plurality of solder interconnects 130. Electrical path 104 can also include a solder interconnect from a plurality of solder interconnects 150. Electrical path 104 can extend through the front side and / or the back side of bridge 107. In some implementations, there can be a plurality of electrical paths that extend through board 106, substrate 102, and bridge 107. Electrical path 104 can pass through the front side of bridge 107 and / or the back side of bridge 107. Electrical path 104 can extend in any direction (e.g., left to right, right to left, up and / or down). One or more currents passing through electrical path 104 can pass in any direction (e.g., left to right, right to left, up and / or down). One of these electrical paths may be configured to provide an electrical path for ground, and another of these electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0021] Electrical path 108 is an example of an electrical path that extends through at least board 106, substrate 102, and bridge 107. It should be noted that electrical path 108 can also extend to integrated device 103 and / or integrated device 105. In one example, electrical path 108 is configured to provide an electrical path for power (as part of a power distribution network). Power can be supplied to integrated device 103 and / or integrated device 105. In another example, electrical path 108 is configured to provide an electrical path for ground. Electrical path 108 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, and (iv) at least one bridge interconnect (e.g., 171, 173, 175) from bridge 107. For example, electrical path 108 can also include a solder interconnect from a plurality of solder interconnects 130 and / or a solder interconnect from a plurality of solder interconnects 150. Electrical path 108 can extend through the front side and / or the back side of bridge 107. In some implementations, there can be a plurality of electrical paths that extend through board 106, substrate 102, and bridge 107. Electrical path 108 can pass through the front side and / or the back side of bridge 107. Electrical path 108 can extend in any direction (e.g., from left to right, from right to left, up and / or down). One or more currents passing through electrical path 108 can pass in any direction (e.g., from left to right, from right to left, up and / or down). One of these electrical paths can be configured to provide an electrical path for ground, and another one of these electrical paths can be configured to provide an electrical path for power (as part of a power distribution network).

[0022] The above design and / or configuration has several advantages. First, the interconnects on / underneath the bridge 107 help provide more interconnects to improve power delivery to the integrated device 103 and / or the integrated device 105. Second, providing a bridge that includes interconnects configured as electrical paths for grounding helps improve the signal integrity of signals passing through the bridge 107, which helps improve the performance of the integrated device 103 and / or the integrated device 105.

[0023] In some implementations, the interconnects on the backside of the bridge 107 may have a different thickness than the interconnects on the front side of the bridge 107. For example, a plurality of bridge interconnects 173 (located in / on the front side of the bridge 107) may have a thickness within a first range of about 1 to 2 micrometers (e.g., a first thickness), and a plurality of bridge interconnects 175 (located in / on the backside of the bridge 107) may have a thickness greater than 2 micrometers (e.g., within a second range of about 3 to 6 micrometers) (e.g., a second thickness). The increased thickness of the plurality of bridge interconnects 175 (e.g., the backside metal layer) helps improve power delivery and helps reduce the IR drop across the bridge 107. The thicknesses described above may refer to the thickness of any metal layer (e.g., M1, M2, M3, M4, M5, M6, M7) and / or metal plane of the bridges described in the present disclosure. As described above, in some implementations, the substrate 102 may include passive devices. FIG. 2 shows a package 200 that includes a substrate having a bridge and at least one passive device. The passive device may be coupled to the power distribution network. The passive device may be configured to assist in providing effective decoupling to circuits within the package, the integrated device, the substrate, and / or the bridge. The package 200 is similar to the package 100 and thus may include components similar to those of the package 100.

[0024] Package 200 includes a substrate 102, an integrated device 103, an integrated device 105, and a bridge 207. The bridge 207 can be similar to the bridge 107. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 is coupled to a board 106 via a plurality of solder interconnects 110. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 and a plurality of board interconnects 162.

[0025] The integrated device 103 is coupled to a first surface (e.g., the top surface) of the substrate 102 via a plurality of solder interconnects 130. The plurality of solder interconnects 130 are coupled to the integrated device 103 and the plurality of interconnects 122 of the substrate 102. The integrated device 105 is coupled to the first surface (e.g., the top surface) of the substrate 102 via a plurality of solder interconnects 150. The plurality of solder interconnects 150 are coupled to the integrated device 105 and the plurality of interconnects 122 of the substrate 102.

[0026] The bridge 207 is located within the substrate 102. The substrate 102 may include a cavity 209. The bridge 207 may be located within the cavity 209 of the substrate 102. Note that a part of the cavity 209 may be filled with a gas (e.g., air). The bridge 207 is configured to provide a plurality of electrical paths for signals between the integrated device 103 and the integrated device 105. The bridge 207 is configured to provide at least one electrical path for a power distribution network (PDN). The bridge 207 is configured to provide at least one electrical path for power. The bridge 207 is configured to provide at least one electrical path for ground. The bridge 207 may include a front side and a back side. As will be further described below, the bridge 207 is configured to provide at least one electrical path for power and / or ground through the back side of the bridge 207.

[0027] Package 200 also includes passive device 203 and passive device 205. Passive device 203 can be the first passive device. Passive device 205 can be the second passive device. The passive device can include a capacitor. Passive device 203 and / or passive device 205 can be passive dies. Passive device 203 can be located within substrate 102. Passive device 205 can be located within substrate 102. Passive device 203 is coupled to the back side of bridge 207 via a plurality of solder interconnects 230. For example, passive device 203 can be coupled to a bridge interconnect (e.g., 175) of bridge 207 via a plurality of solder interconnects 230. Passive device 205 is coupled to the back side of bridge 207 via a plurality of solder interconnects 250. For example, passive device 205 can be coupled to a bridge interconnect (e.g., 175) of bridge 207 via a plurality of solder interconnects 250.

[0028] FIG. 2 shows electrical path 101, electrical path 204, and electrical path 208. Electrical path 101 in FIG. 2 can be the same as electrical path 101 in FIG. 1. Electrical path 204 can be the same as electrical path 104 in FIG. 1. Electrical path 208 can be the same as electrical path 108 in FIG. 1. However, as further described below, electrical path 204 includes passive device 203 and electrical path 208 includes passive device 205.

[0029] Electrical path 204 is an example of an electrical path that extends through at least board 106, substrate 102, bridge 207, and passive device 203. Note that electrical path 204 may also extend to integrated device 103 and / or integrated device 105. In one example, electrical path 204 is configured to provide an electrical path for power (as part of a power distribution network). Power may be supplied to integrated device 103 and / or integrated device 105. In another example, electrical path 204 is configured to provide an electrical path for ground. Electrical path 204 may include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, (iv) at least one bridge interconnect from bridge 207 (e.g., 171, 173, 175), and (v) terminals of passive device 203 (e.g., solder interconnect 230, interconnect). For example, electrical path 204 may also include a solder interconnect from a plurality of solder interconnects 130 and / or a solder interconnect from a plurality of solder interconnects 150. Electrical path 204 may extend through the front side and / or the back side of bridge 207. In some implementations, there may be a plurality of electrical paths that extend through board 106, substrate 102, bridge 207, and passive device 203. One of these electrical paths may be configured to provide an electrical path for ground, and another one of these electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0030] Electrical path 208 is an example of an electrical path that extends through at least board 106, substrate 102, bridge 207, and passive device 205. Note that electrical path 208 can also extend to integrated device 103 and / or integrated device 105. In one example, electrical path 208 is configured to provide an electrical path for power (as part of a power distribution network). The power can be supplied to integrated device 103 and / or integrated device 105. In another example, electrical path 208 is configured to provide an electrical path for ground. Electrical path 208 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, (iv) at least one bridge interconnect from bridge 207 (e.g., 171, 173, 175), and (v) terminals of passive device 205 (e.g., solder interconnect 250, interconnect). For example, electrical path 208 can also include a solder interconnect from a plurality of solder interconnects 130 and / or a solder interconnect from a plurality of solder interconnects 150. Electrical path 208 can extend through the front side and / or the back side of bridge 207. In some implementations, there can be a plurality of electrical paths that extend through board 106, substrate 102, and bridge 207. One of these electrical paths can be configured to provide an electrical path for ground, and another one of these electrical paths can be configured to provide an electrical path for power (as part of a power distribution network).

[0031] The above design and / or configuration has several advantages. First, the interconnects on and / or behind the bridge 207 help provide more interconnects to improve power delivery to the integrated device 103 and / or the integrated device 105. Second, providing a bridge that includes interconnects configured as electrical paths for grounding helps improve the signal integrity of signals passing through the bridge 207, which helps improve the performance of the integrated device 103 and / or the integrated device 105. Third, the passive device 203 and / or the passive device 205 provide improved decoupling capabilities compared to capacitors coupled to the underside of the substrate 102. Fourth, the passive device 203 and / or the passive device 205 closer to the integrated device(s) can help improve voltage droop.

[0032] In some implementations, additional materials and / or components may be provided in the package to provide a mechanically robust and stable package. FIG. 3 shows a package 300 that includes an encapsulation layer 310 within the substrate. The package 300 is similar to the package 200 and thus includes components similar to those of the package 200. The description of the package 200 and its components is also applicable to the package 300. The package 300 includes an encapsulation layer 310 located within the substrate 102. The encapsulation layer 310 may be located within the cavity 209 of the substrate 102. The cavity 209 may be filled with a gas (e.g., air).

[0033] FIG. 3 shows an encapsulation layer 310 that encapsulates passive device 203 and passive device 205. The encapsulation layer 310 may be coupled to the back side of the bridge 207 and / or may be a part of the back side of the bridge 207. The encapsulation layer 310 may also encapsulate the bridge 207. The encapsulation layer 310 may include a mold, resin, and / or epoxy. The encapsulation layer 310 can serve as a means for encapsulation. The encapsulation layer 310 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Note that other materials such as underfill can be used instead of or in combination with the encapsulation layer 310. In some implementations, the passive device 203, the passive device 205, and / or the encapsulation layer 310 can be regarded as part of the bridge 207. The encapsulation layer 310 helps to provide structural stability to the bridge 207, the substrate 102, and / or the package 300.

[0034] Note that possible electrical paths for package 300 can be similar to those described for package 100 of FIG. 1, package 200 of FIG. 2, or any electrical paths described in the present disclosure.

[0035] FIG. 4 shows a package 400 that includes a bridge having a direct backside connection. Package 400 is similar to package 300 and thus includes similar components as package 300. The description of package 300 and its components is applicable to package 400. Package 400 includes a bridge 207 located within substrate 102 and an encapsulation layer 310. The encapsulation layer 310 includes a plurality of interconnects 412 configured to enable at least one electrical path through the backside of the bridge 207. The encapsulation layer 310 may be located within cavity 209 of the substrate 102. Cavity 209 may be filled with a gas (e.g., air). In some implementations, the encapsulation layer 310 and / or the plurality of interconnects 412 may be considered part of the bridge 207. In some implementations, the encapsulation layer 310 and / or the plurality of interconnects 412 may be considered part of the substrate 102. The plurality of interconnects 412 may include a plurality of through-mold interconnects. The plurality of interconnects 412 may be coupled to the plurality of interconnects 122. The plurality of interconnects 412 may be coupled to the plurality of bridge interconnects 171, the plurality of bridge interconnects 173, and / or the plurality of bridge interconnects 175. The interconnects 412 may include through mold vias (TMVs). In some implementations, a power supply may pass through an electrical path that includes the plurality of interconnects 412. That is, the power supply can enter through the backside of the bridge 207. Using the plurality of interconnects 412 as an electrical path for the power supply may help improve the voltage droop.

[0036] FIG. 4 shows electrical path 101, electrical path 404, electrical path 408, electrical path 414, and electrical path 418. Electrical path 101 of FIG. 4 can be similar to electrical path 101 of FIG. 1.

[0037] Electrical path 404 is an example of an electrical path that extends through at least board 106 and substrate 102. Note that electrical path 404 can also extend up to integrated device 103. In one example, electrical path 404 is configured to provide an electrical path for power (as part of a power distribution network). Power can be supplied to integrated device 103. In another example, electrical path 404 is configured to provide an electrical path for ground. Electrical path 404 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, and (iii) at least one interconnect from a plurality of interconnects 122. Electrical path 404 can also include a solder interconnect from a plurality of solder interconnects 130. In some implementations, there can be a plurality of electrical paths that extend through board 106 and substrate 102. One of these electrical paths may be configured to provide an electrical path for ground, another one of these electrical paths may be configured to provide an electrical path for power (as part of a power distribution network), and another one of these electrical paths may be configured to provide an electrical path for input / output (I / O) signals.

[0038] Electrical path 408 is an example of an electrical path that extends through at least board 106 and substrate 102. Note that electrical path 408 can also extend to integrated device 103. In one example, electrical path 408 is configured to provide an electrical path for power (as part of a power distribution network). The power can be supplied to integrated device 105. In another example, electrical path 408 is configured to provide an electrical path for ground. Electrical path 408 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, and (iii) at least one interconnect from a plurality of interconnects 122. Electrical path 408 can also include a solder interconnect from a plurality of solder interconnects 150. In some implementations, there can be a plurality of electrical paths extending through board 106 and substrate 102. One of these electrical paths may be configured to provide an electrical path for ground, another of these electrical paths may be configured to provide an electrical path for power (as part of a power distribution network), and another of these electrical paths may be configured to provide an electrical path for input / output (I / O) signals.

[0039] Electrical path 414 is an example of an electrical path that extends through at least board 106, substrate 102, bridge 207, and passive device 203. Note that electrical path 414 can also extend to integrated device 103. In one example, electrical path 414 is configured to provide an electrical path for power (as part of a power distribution network). Power can be supplied to integrated device 103. In another example, electrical path 414 is configured to provide an electrical path for ground. Electrical path 414 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, (iv) at least one interconnect from a plurality of interconnects 412, (v) at least one bridge interconnect from bridge 207 (e.g., 171, 173, 175), and (v) terminals of passive device 203 (e.g., solder interconnect 230, interconnect). Electrical path 414 can also include a solder interconnect from a plurality of solder interconnects 130. Electrical path 414 can extend through encapsulation layer 310 and through the back side of bridge 207. In some implementations, there can be a plurality of electrical paths that extend through board 106, substrate 102, bridge 207, and passive device 203. One of these electrical paths may be configured to provide an electrical path for ground, and another one of these electrical paths may be configured to provide an electrical path for power (as part of a power distribution network).

[0040] Electrical path 418 is an example of an electrical path that extends through at least board 106, substrate 102, bridge 207, and passive device 203. Note that electrical path 418 can also extend to integrated device 105. In one example, electrical path 418 is configured to provide an electrical path for power (as part of a power distribution network). Power can be supplied to integrated device 105. In another example, electrical path 418 is configured to provide an electrical path for ground. Electrical path 418 can include (i) at least one board interconnect from a plurality of board interconnects 162, (ii) at least one solder interconnect from a plurality of solder interconnects 110, (iii) at least one interconnect from a plurality of interconnects 122, (iv) at least one interconnect from a plurality of interconnects 412, (v) at least one bridge interconnect from bridge 207 (e.g., 171, 173, 175), and (v) terminals of passive device 203 (e.g., solder interconnect 230, interconnect). Electrical path 418 can also include a solder interconnect from a plurality of solder interconnects 150. Electrical path 418 can extend through encapsulation layer 310 and through the back side of bridge 207. In some implementations, there can be a plurality of electrical paths that extend through board 106, substrate 102, bridge 207, and passive device 203. One of these electrical paths can be configured to provide an electrical path for ground, and another one of these electrical paths can be configured to provide an electrical path for power (as part of a power distribution network).

[0041] The above design and / or configuration has several advantages. First, the interconnects on and / or beneath the bridge 207 help provide more interconnects to improve power delivery to the integrated device 103 and / or the integrated device 105. Second, providing a bridge that includes interconnects configured as electrical paths to ground helps improve the signal integrity of signals passing through the bridge 207, which helps improve the performance of the integrated device 103 and / or the integrated device 105. Third, the passive device 203 and / or the passive device 205 provide improved decoupling capabilities compared to capacitors coupled to the bottom surface of the substrate 102. Fourth, the passive device 203 and / or the passive device 205 closer to the integrated device can help improve voltage droop. Fifth, the electrical paths through the encapsulation layer 310 and / or the backside of the bridge 207 can provide a more direct path to the passive device 203 and the integrated device, helping to provide improved decoupling of the circuit and / or a shorter path to the integrated device (e.g., 103, 105).

[0042] FIG. 5 shows an exemplary side cross-sectional view of bridge 207. As shown in FIG. 5, bridge 207 includes a bridge substrate 170, at least one bridge dielectric layer 172, at least one bridge dielectric layer 174, a plurality of bridge interconnects 171, a plurality of bridge interconnects 173, and a plurality of bridge interconnects 175. Bridge substrate 170 may include a silicon substrate (e.g., a silicon bridge substrate). However, bridge substrate 170 may include different materials. At least one bridge dielectric layer 172 is coupled to a first side (e.g., front side, upper side) of bridge substrate 170. A plurality of bridge interconnects 173 are disposed within and on (e.g., within and above) at least one bridge dielectric layer 172. The plurality of bridge interconnects 173 may be a plurality of front-side bridge interconnects. At least one bridge dielectric layer 172 and the plurality of bridge interconnects 173 can be regarded as a part of the front side of bridge 207. At least one bridge dielectric layer 174 is coupled to a second side (e.g., back side, lower side) of bridge substrate 170. A plurality of bridge interconnects 175 are disposed within and on (e.g., within and below) at least one bridge dielectric layer 174. At least one bridge dielectric layer 174 and the plurality of bridge interconnects 175 can be regarded as a part of the back side of bridge 207. The plurality of bridge interconnects 175 may be a plurality of back-side bridge interconnects. The plurality of bridge interconnects 171 may extend through the front side of bridge 207, bridge substrate 170, and / or the back side. For example, the plurality of bridge interconnects 171 may extend through (e.g., partially or completely) at least one bridge dielectric layer 172, bridge substrate 170, and / or at least one bridge dielectric layer 174. The plurality of bridge interconnects 171 may be coupled to the plurality of bridge interconnects 173 and the plurality of bridge interconnects 175. The plurality of bridge interconnects 171 may include a plurality of bridge vias (e.g., bridge via interconnects).

[0043] The plurality of bridge interconnecting portions 171 includes at least one bridge interconnecting portion 171a, at least one bridge interconnecting portion 171b, at least one bridge interconnecting portion 171c, at least one bridge interconnecting portion 171d, at least one bridge interconnecting portion 171e, and at least one bridge interconnecting portion 171f. The plurality of bridge interconnecting portions 173 may include at least one bridge interconnecting portion 173a, at least one bridge interconnecting portion 173b, at least one bridge interconnecting portion 173c, at least one bridge interconnecting portion 173d, and at least one bridge interconnecting portion 173e. The plurality of bridge interconnecting portions 175 includes at least one bridge interconnecting portion 175a, at least one bridge interconnecting portion 175b, at least one bridge interconnecting portion 175c, and at least one bridge interconnecting portion 175d.

[0044] In some implementations, at least one bridge interconnecting portion 173a may be configured to provide at least one electrical path for input / output (I / O) signals. In some implementations, at least one bridge interconnecting portion 173b may be configured to provide at least one electrical path for grounding. In some implementations, at least one bridge interconnecting portion 173c may be configured to provide at least one electrical path for input / output (I / O) signals. In some implementations, at least one bridge interconnecting portion 173d may be configured to provide at least one electrical path for grounding. In some implementations, at least one bridge interconnecting portion 173e may be configured to provide at least one electrical path for grounding, at least one electrical path for power supply, and / or at least one electrical path for input / output (I / O) signals.

[0045] In some implementations, at least one bridge interconnecting portion 171e may be configured to provide at least one electrical path for grounding, at least one electrical path for power supply, and / or at least one electrical path for input / output (I / O) signals.

[0046] At least one bridge interconnect 173a can be coupled to at least one bridge interconnect 173e. The at least one bridge interconnect 173e can include pads and / or vias. At least one bridge interconnect 173c can be coupled to at least one bridge interconnect 173e. At least one bridge interconnect 173b can be coupled to at least one bridge interconnect 171b and / or at least one bridge interconnect 171e. At least one bridge interconnect 175b can be coupled to at least one bridge interconnect 171b and / or at least one bridge interconnect 171e. At least one bridge interconnect 173d can be coupled to at least one bridge interconnect 171a and / or at least one bridge interconnect 171f. At least one bridge interconnect 175c can be coupled to at least one bridge interconnect 171a and / or at least one bridge interconnect 171f. As further described in FIG. 7, some implementations can have different paths and / or use different metal planes and / or metal layers for power, ground, and / or I / O signals. FIG. 5 shows that one metal layer or one metal plane can be configured to provide at least one electrical path for I / O signals, another metal layer or another metal plane can be configured to provide at least one electrical path for other I / O signals, and a metal layer or metal plane located between the metal layers or metal planes is configured to provide at least one electrical path for ground. This metal layer or ground metal layer is configured to assist in separating signals on different metal layers or metal planes, as well as different signals on the same metal layer or metal plane.

[0047] FIG. 6 shows an exemplary side cross-sectional view of bridge 207. The bridge 207 of FIG. 6 is similar to the bridge 207 of FIG. 5. However, the bridge 207 of FIG. 6 also includes a passive device 203, a passive device 205, and a encapsulation layer 310. The passive device 203 is coupled to the back side of the bridge 207 via a plurality of solder interconnects 230. For example, the passive device 203 can be coupled to at least one bridge interconnect 175d via a plurality of solder interconnects 230. The passive device 205 is coupled to the back side of the bridge 207 via a plurality of solder interconnects 250. For example, the passive device 205 can be coupled to at least one bridge interconnect 175d via a plurality of solder interconnects 250. The encapsulation layer 310 can encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 can be coupled to the back side of the bridge 207. For example, the encapsulation layer 310 can be coupled to the back side surface of at least one bridge dielectric layer 174. The passive device 203, the passive device 205, and / or the encapsulation layer 310 may or may not be considered part of the bridge 207.

[0048] FIG. 7 shows an exemplary side cross-sectional view of bridge 707. Bridge 707 includes components that are the same as or similar to those of bridge 207 in FIG. 6. Thus, bridge 707 in FIG. 7 can be considered similar to bridge 207 in FIGS. 5 and / or 6. However, bridge 707 in FIG. 7 has different arrangements and / or configurations of electrical paths for power, ground, and I / O signals. As shown in FIG. 7, the front side of bridge 707 includes interconnects configured to provide electrical paths for I / O signals, power, and ground, and the back side of bridge 707 is configured to provide electrical paths for power and / or ground. For example, at least a portion of a metal layer (from a plurality of bridge interconnects 173) on the front side of bridge 707 may be configured to provide an electrical path for an I / O signal, at least a portion of another metal layer (from a plurality of bridge interconnects 173) on the front side of bridge 707 may be configured to provide an electrical path for ground, and at least a portion of yet another metal layer (from a plurality of bridge interconnects 173) on the front side of bridge 707 may be configured to provide an electrical path for power. Similarly, at least a portion of a metal layer (from a plurality of bridge interconnects 175) on the back side of bridge 707 may be configured to provide an electrical path for ground, and at least a portion of another metal layer (from a plurality of bridge interconnects 175) on the back side of bridge 707 may be configured to provide an electrical path for power.

[0049] An integrated device (e.g., 103, 105) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a chiplet. A chiplet can be fabricated using a process that provides a better yield compared to other processes used to fabricate other types of integrated devices, which can reduce the overall cost of fabricating the chiplet. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects having different widths and / or spacings). In some implementations, several chiplets can be used to perform the functionality of one or more chips (e.g., one or more integrated devices).Using several chiplets to perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package.

[0050] Packages (e.g., 100, 200, 300, 400) can be implemented in a radio frequency (RF) package. The RF package can be a radio frequency front end (RFFE) package. Packages (e.g., 100, 200, 300, 400) can be configured to provide Wireless Fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). Packages (e.g., 100, 300) can be configured to support Global System for Mobile (GSM) communication, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). Packages (e.g., 100, 300) can be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0051] Although various packages having a substrate with a bridge have been described, next, a sequence for fabricating the bridge will be described below.

[0052] Exemplary Sequence for Fabricating a Bridge In some implementations, fabricating a bridge includes several processes. FIGS. 8A-8F show an exemplary sequence for preparing or fabricating a bridge. In some implementations, the sequence of FIGS. 8A-8F can be used to prepare or fabricate bridge 207. However, the process of FIGS. 8A-8F can be used to fabricate any of the bridges described in the present disclosure (e.g., 107, 707).

[0053] It should be noted that the sequences of FIGS. 8A to 8F may combine one or more steps in order to simplify and / or clarify the sequence for preparing or fabricating a bridge. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0054] Step 1 shows the state after a bridge substrate 170 is prepared, as shown in FIG. 8A. The bridge substrate 170 may include a silicon substrate.

[0055] Step 2 shows the state after a plurality of bridge interconnects 873a are formed on the first surface of the bridge substrate 170. The plurality of bridge interconnects 873a can be formed above the bridge substrate 170. A plating process can be used to form the plurality of bridge interconnects 873a.

[0056] Step 3 shows the state after a bridge dielectric layer 172a is formed on the first surface of the bridge substrate 170 and the plurality of bridge interconnects 873a. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 172a.

[0057] Step 4 shows the state after a plurality of bridge interconnects 873b are formed on the bridge dielectric layer 172a. The plurality of bridge interconnects 873b can be formed above the bridge dielectric layer 172a. A plating process can be used to form the plurality of bridge interconnects 873b.

[0058] Step 5 shows the state after a bridge dielectric layer 172b is formed on the plurality of bridge interconnects 873b and the bridge dielectric layer 172a, as shown in FIG. 8B. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 172b.

[0059] Stage 6 shows the state after a plurality of bridge interconnects are formed on the bridge dielectric layer 172b. The plurality of bridge interconnects 873c can be formed above the bridge dielectric layer 172b. A plating process can be used to form the plurality of bridge interconnects 873c.

[0060] Stage 7 shows the state after the bridge dielectric layer 172c is formed on the plurality of bridge interconnects 873c and the bridge dielectric layer 172b. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 172c.

[0061] Stage 8 shows the state after a plurality of bridge interconnects are formed on the bridge dielectric layer 172c. The plurality of bridge interconnects 873d can be formed above the bridge dielectric layer 172c. A plating process can be used to form the plurality of bridge interconnects 873d.

[0062] Stage 9 shows the state after the bridge dielectric layer 172d is formed on the plurality of bridge interconnects 873d and the bridge dielectric layer 172c, as shown in FIG. 8C. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 172d.

[0063] Stage 10 shows the state after a plurality of cavities 710 are formed in the bridge substrate 170 and at least one bridge dielectric layer 172. The bridge dielectric layer 172 may represent and / or include the bridge dielectric layers 172a, 172b, 172c, and / or 172d. The plurality of cavities 710 can be formed using a laser ablation process.

[0064] Stage 11 shows the state after a plurality of bridge interconnects 171 extending through the bridge substrate 170 and at least one bridge dielectric layer 172. A plating process can be used to form the plurality of bridge interconnects 171.

[0065] Stage 12 shows the state after a plurality of bridge interconnects are formed on the second surface of the bridge substrate 170, as shown in FIG. 8D. Stage 12 shows the state after the bridge is inverted and the interconnects are formed on the other surface. The plurality of bridge interconnects 875a can be formed above (or below depending on the orientation of the bridge substrate) the bridge substrate 170. A plating process can be used to form the plurality of bridge interconnects 875a.

[0066] Stage 13 shows the state after a bridge dielectric layer 174a is formed on the second surface of the bridge substrate 170 and the plurality of bridge interconnects 875a. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 174a.

[0067] Stage 14 shows the state after a plurality of cavities 810 are formed in the bridge dielectric layer 174a. An etching process (e.g., a photoetching process) can be used to form the cavities.

[0068] Stage 15 shows the state after a plurality of bridge interconnects 875b are formed on the bridge dielectric layer 174a. The plurality of bridge interconnects 875b can be formed above the bridge dielectric layer 174a and the plurality of bridge interconnects 875a. A plating process can be used to form the plurality of bridge interconnects 875b.

[0069] Stage 16 shows the state after the bridge dielectric layer 174b is formed over the plurality of bridge interconnects 875b and the bridge dielectric layer 174a, as shown in FIG. 8E. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 174b.

[0070] Stage 17 shows the state after the plurality of bridge interconnects 875c are formed over the bridge dielectric layer 174b. The plurality of bridge interconnects 875c can be formed above the bridge dielectric layer 174b. Before forming the plurality of bridge interconnects 875c, a plurality of cavities can be formed in the bridge dielectric layer 174b in the same manner as described in step 14 above. A plating process can be used to form the plurality of bridge interconnects 875c.

[0071] Stage 18 shows the state after the bridge dielectric layer 174c is formed over the plurality of bridge interconnects 875c and the bridge dielectric layer 174b. A deposition process and / or a lamination process can be used to form the bridge dielectric layer 174c.

[0072] Stage 19 shows the state after the plurality of bridge interconnects 875d are formed over the bridge dielectric layer 174. The bridge dielectric layer 174 may represent and / or include the bridge dielectric layers 174a, 174b, and / or 174c. The plurality of bridge interconnects 875d can be formed above the bridge dielectric layer 174. Before forming the plurality of bridge interconnects 875d, a plurality of cavities can be formed in the bridge dielectric layer 174c in the same manner as described in step 14 above. A plating process can be used to form the plurality of bridge interconnects 875d.

[0073] Stage 20 shows the state after the passive device 203 and the passive device 205 are coupled to the plurality of bridge interconnects 175, as shown in FIG. 8F. The passive device 203 can be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 230. The passive device 205 can be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 250. A solder reflow process can be used to couple the passive device 203 and / or the passive device 205.

[0074] Stage 21 shows the state after the encapsulation layer 310 is formed. The encapsulation layer 310 is coupled to the surface of the bridge 207. For example, the encapsulation layer 310 is coupled to at least one bridge dielectric layer 174. The encapsulation layer 310 can encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 can include a mold, a resin, and / or an epoxy. The encapsulation layer 310 can serve as a means for encapsulation. The encapsulation layer 310 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 21 shows an example of the bridge 207 including the bridge substrate 170, the plurality of bridge interconnects 171, at least one bridge dielectric layer 172, the plurality of bridge interconnects 173, at least one bridge dielectric layer 174, the plurality of bridge interconnects 175, the passive device 203, the passive device 205, and the encapsulation layer 310.

[0075] FIGS. 8A-8F show a process for fabricating a bridge, where the front side of the bridge is fabricated, followed by fabricating the bridge interconnects within the bridge substrate, and then the back side of the bridge is fabricated. Some implementations can fabricate the bridge using different processes and / or different sequences. For example, in some implementations, the front side and the back side of the bridge can be fabricated simultaneously, and bridge interconnects (e.g., substrate vias) extending from the front side of the bridge, the bridge substrate, and the back side of the bridge can be fabricated.

[0076] Exemplary sequence for fabricating a bridge In some implementations, fabricating a bridge involves several processes. FIGS. 9A-9D show an exemplary sequence for preparing or fabricating a bridge. In some implementations, the sequence of FIGS. 9A-9D can be used to prepare or fabricate bridge 207. However, the processes of FIGS. 9A-9D can be used to fabricate any of the bridges described in the present disclosure (e.g., 107, 707).

[0077] It should be noted that the sequence of FIGS. 9A-9D may combine one or more steps to simplify and / or clarify the sequence for preparing or fabricating a bridge. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure. FIGS. 9A-9D may show a sequence in which the front and back sides of the bridge are fabricated simultaneously.

[0078] Step 1 shows the state after bridge substrate 170 is prepared, as shown in FIG. 9A. Bridge substrate 170 may include a silicon substrate.

[0079] Step 2 shows the state after a plurality of bridge interconnects are formed on the first surface of bridge substrate 170 and on the second surface of bridge substrate 170. A plurality of bridge interconnects 873a can be formed above bridge substrate 170 (e.g., above the first surface of the bridge substrate), and a plurality of bridge interconnects 875a can be formed below bridge substrate 170 (e.g., below the second surface of the bridge substrate). A plating process can be used to form the plurality of bridge interconnects (e.g., 873a, 875a).

[0080] Stage 3 shows the state after the bridge dielectric layer 172a is formed over the first surface of the bridge substrate 170 and over the plurality of bridge interconnects 873a. Stage 3 also shows the state after the bridge dielectric layer 174a is formed over the second surface of the bridge substrate 170 and over the plurality of bridge interconnects 875a. A deposition process and / or a lamination process can be used to form the bridge dielectric layer (e.g., 172a, 174a).

[0081] Stage 4 shows the state after the plurality of bridge interconnects are formed over the bridge dielectric layer 172a and over the bridge dielectric layer 174a. For example, the plurality of bridge interconnects 873b can be formed above the bridge dielectric layer 172a, and the plurality of bridge interconnects 875b can be formed below the bridge dielectric layer 174a. A plating process can be used to form the plurality of bridge interconnects (e.g., 873b, 875b).

[0082] Stage 5 shows the state after the bridge dielectric layer 172b is formed over the plurality of bridge interconnects 873b and over the bridge dielectric layer 172a, as shown in FIG. 9B. Stage 5 also shows the state after the bridge dielectric layer 174b is formed over the plurality of bridge interconnects 875b and over the bridge dielectric layer 174a. A deposition process and / or a lamination process can be used to form the bridge dielectric layer (e.g., 172b, 174b).

[0083] Stage 6 shows the state after the plurality of bridge interconnects are formed over the bridge dielectric layer 172b and over the bridge dielectric layer 174b. The plurality of bridge interconnects 873c can be formed above the bridge dielectric layer 172b, and the plurality of bridge interconnects 875c can be formed below the bridge dielectric layer 174b. A plating process can be used to form the plurality of bridge interconnects (e.g., 873c, 875c).

[0084] Step 7 shows the state after the bridge dielectric layer 172c is formed over the plurality of bridge interconnects 873c. Step 7 also shows the state after the bridge dielectric layer 174c is formed over the plurality of bridge interconnects 875c. A deposition process and / or a lamination process can be used to form the bridge dielectric layer (e.g., 172c, 174c).

[0085] Step 8 shows the state after the plurality of bridge interconnects are formed over the bridge dielectric layer 172c and over the bridge dielectric layer 174c. The plurality of bridge interconnects 873d can be formed above the bridge dielectric layer 172c, and the plurality of bridge interconnects 875d can be formed under the bridge dielectric layer 174c. A plating process can be used to form the plurality of bridge interconnects (e.g., 873d, 875d).

[0086] Step 9 shows the state after the bridge dielectric layer 172d is formed over the plurality of bridge interconnects 873d and the bridge dielectric layer 172c, as shown in FIG. 9C. A deposition process and / or a lamination process can be used to form the bridge dielectric layer (e.g., 172d).

[0087] Step 10 shows the state after the plurality of cavities 710 are formed in the bridge substrate 170, at least one bridge dielectric layer 172, and / or at least one bridge dielectric layer 174. The plurality of cavities 710 can be formed using a laser ablation process. The bridge dielectric layer 172 may represent and / or include the bridge dielectric layers 172a, 172b, 172c, and / or 172d. The bridge dielectric layer 174 may represent and / or include the bridge dielectric layers 174a, 174b, and / or 174c.

[0088] Stage 11 shows the state after a plurality of bridge interconnects 171 extending through the bridge substrate 170, at least one bridge dielectric layer 172, and / or at least one bridge dielectric layer 174 are formed. A plating process can be used to form the plurality of bridge interconnects 171.

[0089] Stage 12 shows the state after the passive devices 203 and 205 are coupled to the plurality of bridge interconnects 175, as shown in FIG. 9D. The passive device 203 can be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 230. The passive device 205 can be coupled to the plurality of bridge interconnects 175 via a plurality of solder interconnects 250. A solder reflow process can be used to couple the passive device 203 and / or the passive device 205.

[0090] Stage 13 shows the state after the encapsulation layer 310 is formed. The encapsulation layer 310 is coupled to the surface of the bridge 207. For example, the encapsulation layer 310 can be coupled to the surface of at least one bridge dielectric layer 174. The encapsulation layer 310 can encapsulate the passive device 203 and / or the passive device 205. The encapsulation layer 310 can include a mold, resin, and / or epoxy. The encapsulation layer 310 can serve as a means for encapsulation. The encapsulation layer 310 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Stage 13 shows an example of a bridge 207 including the bridge substrate 170, the plurality of bridge interconnects 171, at least one bridge dielectric layer 172, the plurality of bridge interconnects 173, at least one bridge dielectric layer 174, the plurality of bridge interconnects 175, the passive device 203, the passive device 205, and the encapsulation layer 310.

[0091] Exemplary flow diagram of a method for fabricating a bridge In some implementations, fabricating a bridge involves several processes. FIG. 10 shows an exemplary flowchart of a method 1000 for preparing or fabricating a bridge. In some implementations, the method 1000 of FIG. 10 can be used to prepare or fabricate the bridge 207 described in this disclosure. However, the method 1000 can be used to prepare or fabricate any of the bridges described in this disclosure (e.g., 107, 707).

[0092] It should be noted that the method 1000 of FIG. 10 may combine one or more processes to simplify and / or clarify the method for preparing or fabricating a bridge. In some implementations, the order of the processes may be changed or modified.

[0093] The method prepares a bridge substrate (e.g., 170) (at 1005). The bridge substrate 170 may include a silicon substrate. Step 1 of FIG. 9A illustrates and describes an example of providing a bridge substrate.

[0094] The method forms bridge interconnects (e.g., 173, 175) and bridge dielectric layers (e.g., 172, 174) on the surface of a bridge substrate (at 1010). For example, a plurality of bridge interconnects can be formed on the first surface of bridge substrate 170 and on the second surface of bridge substrate 170. A plurality of bridge interconnects 873a can be formed above bridge substrate 170, and a plurality of bridge interconnects 875a can be formed below bridge substrate 170. A plating process can be used to form the plurality of bridge interconnects (e.g., 873a, 875a). In another example, a bridge dielectric layer 172a can be formed on the first surface of bridge substrate 170 and on the plurality of bridge interconnects 873a. In another example, a bridge dielectric layer 174a can be formed on the second surface of bridge substrate 170 and on the plurality of bridge interconnects 875a. A deposition process and / or a lamination process can be used to form the bridge dielectric layers (e.g., 172a, 174a). The above processes can be repeatedly executed to form some bridge interconnects and / or bridge dielectric layers. Stages 2 to 9 of FIGS. 9A - 9C illustrate and describe an example of forming bridge interconnects and bridge dielectric layers.

[0095] The method forms a plurality of cavities (e.g., 710) in the bridge substrate 170, at least one bridge dielectric layer 172, and / or at least one bridge dielectric layer 174 (at 1015). The plurality of cavities 710 can be formed using a laser ablation process. The plurality of cavities 710 can extend through at least one bridge dielectric layer 172, the bridge substrate 170, and / or at least one bridge dielectric layer 174. Stage 10 of FIG. 9C illustrates and describes an example of forming a cavity.

[0096] The method forms a plurality of bridge interconnects (e.g., 171) within a plurality of cavity portions 710 (at 1020). The plurality of bridge interconnects 171 can extend through at least one bridge dielectric layer 172, bridge substrate 170, and / or at least one bridge dielectric layer 174. A plating process can be used to form the plurality of bridge interconnects 171. The plurality of bridge interconnects 171 can be coupled to a plurality of bridge interconnects 173 and / or a plurality of bridge interconnects 175. Step 11 of FIG. 9C illustrates and describes an example of forming a bridge interconnect.

[0097] The method couples one or more passive devices (e.g., 203, 205) to the bridge interconnects (at 1025). For example, passive device 203 can be coupled to a plurality of bridge interconnects 175 via a plurality of solder interconnects 230, and passive device 205 can be coupled to a plurality of bridge interconnects 175 via a plurality of solder interconnects 250. A solder reflow process can be used to couple passive device 203 and / or passive device 205. Step 12 of FIG. 9D illustrates and describes an example of coupling a passive device to a bridge interconnect.

[0098] The method forms a encapsulation layer (e.g., 310) (at 1030). For example, encapsulation layer 310 can be coupled to the surface of bridge 207. Encapsulation layer 310 can encapsulate passive device 203 and / or passive device 205. Encapsulation layer 310 can include a mold, resin, and / or epoxy. Encapsulation layer 310 can serve as means for encapsulation. Encapsulation layer 310 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. Step 13 of FIG. 9D illustrates and describes an example of forming an encapsulation layer.

[0099] It should be noted that the method 1000 of FIG. 10 may be modified to fabricate the bridge in the manner described in FIGS. 8A-8F. In such an implementation, the method may form a bridge dielectric layer(s) and bridge interconnects on the front side of the bridge, then form interconnects in the bridge substrate, and then form a bridge dielectric layer(s) and bridge interconnects on the back side of the bridge. Once the front and back side bridge interconnects are fabricated, passive devices may be coupled to the bridge and a encapsulation layer may be formed.

[0100] Exemplary sequence for fabricating a package with a bridge In some implementations, fabricating a package may include several processes. FIGS. 11A-11D illustrate an exemplary sequence for preparing or fabricating a package with a bridge. In some implementations, the sequence of FIGS. 11A-11D may be used to prepare or fabricate the package 400. However, the processes of FIGS. 11A-11D may be used to fabricate any of the packages including the bridges described in this disclosure.

[0101] It should be noted that the sequence of FIGS. 11A-11D may combine one or more steps to simplify and / or clarify the sequence for preparing or fabricating a package with a bridge. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be exchanged or replaced without departing from the scope of this disclosure.

[0102] Step 1 of FIG. 11A shows the state after the substrate 102 and the carrier 1100 are prepared. The substrate 102 may be coupled to and located on the carrier 1100. The substrate 102 may include at least one dielectric layer 120 and a plurality of interconnects 122. FIGS. 13A-13B illustrate an example of fabricating a substrate including at least one dielectric layer and a plurality of interconnects.

[0103] Stage 2 shows the state after the cavity 209 is formed in the substrate 102. To form the cavity 209, a laser ablation process and / or an etching process can be used. The cavity 209 can extend through (e.g., partially or completely) the substrate 102 (e.g., through at least one dielectric layer 120 of the substrate 102). The surface of the carrier 1100 can be exposed through the cavity 209.

[0104] Stage 3 shows the state after the bridge 207 is placed in the cavity 209 and on the carrier 1100. A pick-and-place process can be used to place the bridge 207 in the cavity 209. Different implementation forms can place different bridges (e.g., 107, 707) in the cavity 209. The bridge 207 may or may not include a encapsulation layer. The bridge 207 may or may not include one or more passive devices. The bridge 207 may be located on and / or coupled to the carrier 1100.

[0105] Stage 4 in FIG. 11B shows the state after the dielectric layer 1120 is formed on the bridge 207. The dielectric layer 1120 can be similar to at least one dielectric layer 120. The dielectric layer 1120 can be formed along the side portion of the bridge 207 located in the cavity 209. The dielectric layer 1120 can fill the cavity portion of the substrate 102 where the cavity 209 is located. In some implementation forms, some portions of the cavity 209 are filled with the dielectric layer 1120. In some implementation forms, most, if not all, of the space in the cavity 209 not occupied by the bridge 207 can be filled with the dielectric layer 1120. To form the dielectric layer 1120, a deposition process and / or a lamination process can be used. In some implementation forms, instead of the dielectric layer 1120, a encapsulation layer similar to the encapsulation layer 310 can be used. The encapsulation layer provided on the bridge 207 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0106] Stage 5 shows the state after a plurality of cavity portions 1121 are formed in the dielectric layer 1120. To form the plurality of cavity portions 1121, a laser ablation process and / or an etching process (e.g., a lithography process) can be used. The dielectric layer 1120 can be regarded as a part of the dielectric layer 120. Thus, the dielectric layer 120 can include the dielectric layer 1120. The plurality of cavity portions 1121 can be regarded as being formed in the dielectric layer 120. The plurality of cavity portions 1121 can expose a part of the bridge 207. For example, the plurality of cavity portions 1121 can expose the bridge interconnecting portion of the bridge 207.

[0107] Stage 6 shows the state after a plurality of bridge interconnecting portions 1123 are formed on at least one dielectric layer 120 and / or the dielectric layer 1120. The dielectric layer 1120 can be regarded as a part of at least one dielectric layer 120. The plurality of bridge interconnecting portions 1123 can be coupled to the plurality of interconnecting portions 122 and to the bridge interconnecting portion (e.g., 173) of the bridge 207. To form the plurality of bridge interconnecting portions 1123, a plating process can be used.

[0108] Stage 7 in FIG. 11C shows the state after the carrier 1100 is decoupled from the substrate 102 and the bridge 207. The carrier 1100 can be removed and / or detached from the substrate 102 and / or the bridge 207.

[0109] Stage 8 shows the state after a plurality of cavity portions 1143 are formed in the encapsulation layer 310. To form the plurality of cavity portions 1143, a laser ablation and / or an etching process can be used.

[0110] Stage 9 shows the state after a plurality of interconnects 1145 are formed. The interconnects 1145 can be formed in and on the encapsulation layer 310. The plurality of interconnects 1145 can be formed on at least one dielectric layer 120. The plurality of interconnects 1135 can include interconnects regarded as part of the substrate 102 and / or bridge interconnects regarded as part of the bridge 207. Some or all of the plurality of interconnects 1145 can be regarded as part of the plurality of interconnects 122.

[0111] Stage 10 shows the state after a dielectric layer 1160 is formed on at least one dielectric layer 120 and / or the encapsulation layer 310. A deposition process and / or a lamination process can be used to form the dielectric layer 1160. The dielectric layer 1160 can be similar to at least one dielectric layer 120. The dielectric layer 1160 can be regarded as part of at least one dielectric layer 120.

[0112] Stage 11 shows the state after the integrated devices are coupled to the substrate 102. For example, the integrated device 103 is coupled to the substrate 102 via a plurality of solder interconnects 130, and the integrated device 105 is coupled to the substrate 102 via a plurality of solder interconnects 150. A solder reflow process can be used to couple the integrated devices (e.g., 103, 105) to the substrate 102.

[0113] Stage 12 shows the state after a plurality of solder interconnects 110 are coupled to the substrate 102. The plurality of solder interconnects 110 are coupled to the plurality of interconnects 122 of the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the substrate 102. Stage 12 can show an example of a package 400 including the substrate 102, the bridge 207, the integrated device 103, and the integrated device 105.

[0114] Exemplary flowchart of a method for fabricating a package with a bridge FIG. 12 shows an exemplary flow diagram of a method 1200 for preparing or fabricating a package that includes a bridge. In some implementations, method 1200 of FIG. 12 can be used to prepare or fabricate package 400 described in the present disclosure. However, method 1200 can be used to prepare or fabricate any of the packages described in the present disclosure.

[0115] It should be noted that method 1200 of FIG. 12 may combine one or more processes to simplify and / or clarify the method for preparing or fabricating a package. In some implementations, the order of the processes may be changed or modified.

[0116] The method prepares (at 1205) a substrate (e.g., 102) that includes at least one dielectric layer (e.g., 120) and a plurality of interconnects (e.g., 122). Substrate 102 can be coupled to carrier 1100. The substrate can be a laminated substrate. FIGS. 13A - 13B show an example of fabricating a substrate that includes at least one dielectric layer and a plurality of interconnects. Step 1 of FIG. 11A illustrates and describes an example of preparing a substrate and a carrier.

[0117] The method forms (at 1210) a cavity (e.g., 209) in substrate 102. To form cavity 209, a laser ablation process and / or an etching process can be used. Cavity 209 can extend through (e.g., partially or completely) substrate 102 (e.g., through at least one dielectric layer 120 of substrate 102). The surface of carrier 1100 can be exposed through cavity 209. Step 2 of FIG. 11A illustrates and describes an example of forming a cavity in a substrate.

[0118] The method installs a bridge (e.g., 207) in the cavity 209 of the substrate 102 and on the carrier 1100 (at 1215). A pick-and-place process can be used to install the bridge 207 in the cavity 209 of the substrate 102. Different implementations can install different bridges (e.g., 107, 207) in the cavity 209. The bridge 207 may or may not include at least one passive device. The bridge 207 may or may not include a encapsulation layer. The bridge 207 may be located on and / or coupled to the carrier 1100. Step 3 of FIG. 11A illustrates and describes an example of installing a bridge in the cavity of a substrate.

[0119] The method forms a dielectric layer and interconnects (e.g., bridge interconnects) on the bridge and / or the substrate (at 1220). For example, a dielectric layer 1120 can be formed on the bridge 207. The dielectric layer 1120 can be similar to at least one dielectric layer 120. The dielectric layer 1120 can be formed along the side portion of the bridge 207 located in the cavity 209. The dielectric layer 1120 can fill a portion of the cavity 209 of the substrate 102. A deposition process and / or a lamination process can be used to form the dielectric layer 1120. In some implementations, the dielectric layer 1120 can be an encapsulation layer similar to the encapsulation layer 310. The encapsulation layer provided on the bridge 207 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0120] Forming the interconnecting portion may include forming a cavity in the dielectric layer and performing an electroplating process. For example, a plurality of cavities 1121 can be formed in the dielectric layer 1120. To form the plurality of cavities 1121, a laser ablation process and / or an etching process (e.g., a lithography process) can be used. A plurality of bridge interconnecting portions 1123 can be formed on at least one dielectric layer 120 and / or on the dielectric layer 1120. The dielectric layer 1120 can be regarded as part of at least one dielectric layer 120. The plurality of bridge interconnecting portions 1123 can be coupled to the plurality of interconnecting portions 122 and to the bridge interconnecting portion (e.g., 173) of the bridge 207. To form the plurality of bridge interconnecting portions 1123, an electroplating process can be used.

[0121] Decouple carrier 1100 from substrate 102 and bridge 207. Carrier 1100 can be removed and / or detached from substrate 102 and / or bridge 207. Form a plurality of cavity portions 1143 in encapsulation layer 310. To form the plurality of cavity portions 1143, a laser ablation and / or etching process can be used. A plurality of interconnect portions 1145 can be formed. The interconnect portions 1145 can be formed in and on encapsulation layer 310. The plurality of interconnect portions 1145 can be formed on at least one dielectric layer 120. The plurality of interconnect portions 1135 can include an interconnect portion regarded as a part of substrate 102 and / or a bridge interconnect portion regarded as a part of bridge 207. A part or all of the plurality of interconnect portions 1145 can be regarded as a part of the plurality of interconnect portions 122. A dielectric layer 1160 can be formed on at least one dielectric layer 120 and / or encapsulation layer 310. To form dielectric layer 1160, a deposition process and / or a lamination process can be used. Dielectric layer 1160 can be the same as at least one dielectric layer 120. Dielectric layer 1160 can be regarded as a part of at least one dielectric layer 120. Stages 4 to 10 in FIGS. 11B and 11C show examples of forming a dielectric layer(s), forming cavity portions, and forming interconnect portions.

[0122] The method couples at least one integrated device to a substrate (at 1025). For example, integrated device 103 can be coupled to substrate 102 via a plurality of solder interconnects 130, and integrated device 105 can be coupled to substrate 102 via a plurality of solder interconnects 150. A solder reflow process can be used to couple the integrated devices (e.g., 103, 105) to substrate 102. Stage 11 in FIG. 11D illustrates and describes an example of coupling an integrated device to a substrate.

[0123] The method couples a plurality of solder interconnects to a substrate (at 1230). For example, the plurality of solder interconnects 110 can be coupled to the substrate 102. The plurality of solder interconnects 110 can be coupled to a plurality of interconnects 122 of the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the substrate 102. Step 12 of FIG. 11D illustrates and describes an example of coupling solder interconnects to a substrate.

[0124] Exemplary sequence for fabricating a substrate In some implementations, fabricating a substrate includes several processes. FIGS. 13A - 13B show an exemplary sequence for preparing or fabricating a substrate. In some implementations, the sequence of FIGS. 13A - 13B can be used to prepare or fabricate the substrate 102. However, the processes of FIGS. 13A - 13B can be used to fabricate any of the substrates described in the present disclosure.

[0125] It should be noted that the sequence of FIGS. 13A - 13B may combine one or more steps to simplify and / or clarify the sequence for preparing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure.

[0126] Step 1 shows the state after the carrier 1300 is prepared, as shown in FIG. 13A. A seed layer 1301 and interconnects 1302 can be located on the carrier 1300. The interconnects 1302 can be located on the seed layer 1301. A plating process and an etching process can be used to form the interconnects 1302. In some implementations, the carrier 1300 can be provided with a seed layer 1301 and a metal layer patterned to form the interconnects 1302. The interconnects 1302 can represent at least some of the interconnects from a plurality of interconnects 142.

[0127] Stage 2 shows the state after the dielectric layer 1320 is formed over the carrier 1300, the seed layer 1301, and the interconnect 1302. To form the dielectric layer 1320, a deposition process and / or a lamination process can be used. The dielectric layer 1320 can include a prepreg and / or a polyimide. The dielectric layer 1320 can include a photoimageable dielectric. However, different implementation forms can also use different materials for the dielectric layer.

[0128]

[0129] Stage 4 shows the state after the interconnect 1312 is formed in and over the dielectric layer 1320, including within and over the plurality of cavities 1310. For example, vias, pads, and / or traces can be formed. To form the interconnect, an electroplating process can be used.

[0130] Stage 5 shows the state after the dielectric layer 1322 is formed over the dielectric layer 1320 and the interconnect 1312. To form the dielectric layer 1322, a deposition process and / or a lamination process can be used. The dielectric layer 1322 can include a prepreg and / or a polyimide. The dielectric layer 1322 can include a photoimageable dielectric. However, different implementation forms can also use different materials for the dielectric layer.

[0131] Stage 6 shows the state after the plurality of cavities 1330 are formed in the dielectric layer 1322, as shown in FIG. 13B. The plurality of cavities 1330 can be formed using an etching process (e.g., a photolithography etching process) or a laser process.

[0132] Step 7 shows the state after the interconnect 1314 is formed in and on the dielectric layer 1322, including within and on top of the plurality of cavity portions 1330. For example, vias, pads, and / or traces can be formed. A plating process can be used to form the interconnects.

[0133] Step 8 shows the state after the carrier 1300 is decoupled (e.g., removed, detached, ground) from at least one dielectric layer 140 and the seed layer 1301, a portion of the seed layer 1301 is removed (e.g., etched away), leaving the substrate 102 including at least one dielectric layer 120 and the plurality of interconnects 122.

[0134] Exemplary flowchart of a method for fabricating a substrate In some implementations, fabricating a substrate includes several processes. FIG. 14 shows an exemplary flowchart of a method 1400 for preparing or fabricating a substrate. In some implementations, the method 1400 of FIG. 14 can be used to prepare or fabricate the substrate(s) of the present disclosure. For example, the method 1400 of FIG. 14 can be used to fabricate the substrate 102.

[0135] It should be noted that the method 1400 of FIG. 14 may combine one or more processes to simplify and / or clarify the method for preparing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0136] The method prepares a carrier (e.g., 1300) at (1405). Different implementations can use different materials for the carrier 1300. The carrier 1300 may include a seed layer (e.g., 1301). The seed layer 1301 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 13A illustrates and describes an example of a carrier having a prepared seed layer.

[0137] The method forms and patterns interconnects on the carrier 1300 and the seed layer 1301 (at 1410). To form the interconnects, a metal layer can be patterned. To form the metal layer and the interconnects, an electroplating process can be used. In some implementations, the carrier and the seed layer can include a metal layer. The metal layer is located on the seed layer and can be patterned to form interconnects (e.g., 1302). Step 1 of FIG. 13A illustrates and describes an example of forming and patterning interconnects on the seed layer and the carrier.

[0138] The method forms a dielectric layer 1320 on the seed layer 1301, the carrier 1300, and the interconnects 1302 (at 1415). To form the dielectric layer 1320, a deposition process and / or a lamination process can be used. The dielectric layer 1320 can include a prepreg and / or a polyimide. The dielectric layer 1320 can include a photoimageable dielectric. Forming the dielectric layer 1320 can also include forming a plurality of cavities (e.g., 1310) in the dielectric layer 1320. The plurality of cavities can be formed using an etching process (e.g., photolithography) or a laser process. Steps 2 and 3 of FIG. 13A illustrate and describe an example of forming the dielectric layer and the cavities within the dielectric layer.

[0139] The method forms interconnects in and on the dielectric layer (at 1420). For example, the interconnect 1312 can be formed in and on the dielectric layer 1320. To form the interconnects, an electroplating process can be used. Forming the interconnects can include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects can also include forming the interconnects within the cavities of the dielectric layer. Step 4 of FIG. 13A illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0140] The method forms a dielectric layer 1322 (at 1425) over the dielectric layer 1320 and the interconnect 1312. To form the dielectric layer 1322, a deposition process and / or a lamination process can be used. The dielectric layer 1322 can include a prepreg and / or a polyimide. The dielectric layer 1322 can include a photoimageable dielectric. Forming the dielectric layer 1322 can also include forming a plurality of cavities (e.g., 1330) in the dielectric layer 1322. The plurality of cavities can be formed using an etching process (e.g., photolithography) or a laser process. Stages 5 and 6 of FIGS. 13A - 13B illustrate and describe an example of forming a dielectric layer and cavities within the dielectric layer.

[0141] The method forms an interconnect within and over the dielectric layer (at 1430). For example, the interconnect 1314 can be formed within and over the dielectric layer 1322. To form the interconnect, an electroplating process can be used. Forming the interconnect can include providing a patterned metal layer over and / or within the dielectric layer. Forming the interconnect can also include forming the interconnect within the cavities of the dielectric layer. Forming the interconnect can include forming a post - interconnect. Stage 7 of FIG. 13B illustrates and describes an example of forming an interconnect within and over the dielectric layer, including forming a post - interconnect.

[0142] The method decouples a carrier (e.g., 1300) from a seed layer (e.g., 1301) (at 1435). The carrier 1300 can be removed and / or ground. The method can also (at 1435) remove a portion of the seed layer (e.g., 1301). An etching process can be used to remove the portion of the seed layer 1301. Stage 8 of FIG. 13B illustrates and describes an example of decoupling the carrier and seed layer removal.

[0143] Exemplary Electronic Device FIG. 15 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1502, a laptop computer device 1504, a stationary terminal device 1506, a wearable device 1508, or an autonomous vehicle 1510 may include a device 1500 as described herein. The device 1500 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1502, 1504, 1506, and 1508, and the vehicle 1510 shown in FIG. 15 are merely examples. Other electronic devices including, but not limited to, a group of devices (e.g., electronic devices) such as mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS)-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in autonomous vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof, can also incorporate the device 1500.

[0144] One or more of the components, processes, features, and / or functions shown in FIGS. 1-7, 8A-8F, 9A-9D, 10, 11A-11D, 12, 13A-13B, and 14-15 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. Note also that FIGS. 1-7, 8A-8F, 9A-9D, 10, 11A-11D, 12, 13A-13B, and 14-15, and their corresponding descriptions in the present disclosure, are not limited to dies and / or ICs. In some implementations, FIGS. 1-7, 8A-8F, 9A-9D, 10, 11A-11D, 12, 13A-13B, and 14-15, and their corresponding descriptions may be used to manufacture, fabricate, prepare, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink device, and / or an interposer.

[0145] Note that the figures in the present disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, not all components and / or parts may be shown for clarity purposes. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0146] The term "exemplary" is used herein to mean "an example, instance, or serving as an illustration." None of the implementation forms or aspects described herein as "exemplary" should be construed as necessarily being more preferred or advantageous than other aspects of the present disclosure. Similarly, the term "aspect" does not necessarily require that all aspects of the present disclosure include the features, advantages, or modes of operation being described. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., a mechanical coupling) between two objects. For example, if object A is physically in contact with object B and object B is in contact with object C, then objects A and C can still be considered to be coupled to each other even if they are not physically in direct contact with each other. Object A coupled to object B can be coupled to at least a part of object B. The term "electrically coupled" can mean that two objects are directly or indirectly integrally coupled such that an electric current (e.g., a signal, a power source, a ground) can pass between the two objects. Two electrically coupled objects may or may not have an electric current passing between them. The use of the terms "first," "second," "third," and "fourth" (and / or those greater than fourth) is discretionary. Any of the components being described can be the first component, the second component, the third component, or the fourth component. For example, a component referred to as the second component can also be the first component, the second component, the third component, or the fourth component. The terms "encapsulate," "encapsulating," and / or their derivatives mean that an object can partially encapsulate or fully encapsulate another object. The terms "top" and "bottom" are discretionary. A component located at the top may be located above a component located at the bottom. A component at the top may be regarded as a component at the bottom, and vice versa.As described in the present disclosure, a first component positioned "over" a second component can mean that the first component is positioned above or below the second component, depending on how the lower or upper part is defined at the discretion. In another example, the first component can be positioned on (e.g., above) the first surface of the second component, and the third component can be positioned on (e.g., below) the second surface of the second component, where the second surface is on the opposite side of the first surface. In the context where one component is disposed over another component, it should be further noted that the term "over" used in this application can be used to mean a component that is on and / or within another component (e.g., on the surface of the component or embedded within the component). Thus, for example, a first component over a second component can mean (1) the first component is above the second component but not in direct contact with the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is within the second component (e.g., embedded within the second component). A first component positioned "in" a second component can be partially positioned within the second component or fully positioned within the second component. A value that is about X to XX can mean a value between X and XX including X and XX. The value(s) between X and XX can be discrete or continuous. The term "about 'value X'" or "approximately value X" used in the present disclosure means within a range of 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0147] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect can be part of a circuit. Different implementations can use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and / or an electroplating process can be used to form an interconnect.

[0148] Also note that various disclosures included herein may be described as a process shown as a flowchart, a flow diagram, a structural diagram, or a block diagram. A flowchart may describe operations as a sequential process, but many of the operations can be performed in parallel or simultaneously. Additionally, the order of the operations may be rearranged. A process ends when its operations are complete.

[0149] Examples are described below to facilitate understanding of the present disclosure.

[0150] Aspect 1: A package comprising a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge comprises a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0151] Aspect 2: The package according to Aspect 1, wherein at least one first bridge interconnect is configured to provide a first electrical path for input / output (I / O) signals, and at least one second bridge interconnect is configured to provide a second electrical path for power supply.

[0152] Aspect 3: The package according to Aspect 1, wherein at least one first bridge interconnect is configured to provide a first electrical path for input / output (I / O) signals, and at least one second bridge interconnect is configured to provide a second electrical path for ground.

[0153] Aspect 4: The package according to Aspect 3, wherein at least one second bridge interconnect is configured to provide another electrical path for power supply.

[0154] Aspect 5: The package according to any one of Aspects 1 to 4, further comprising a passive device coupled to at least one second bridge interconnect.

[0155] Aspect 6: The package according to Aspect 5, further comprising a encapsulation layer encapsulating the passive device.

[0156] Aspect 7: The package according to aspect 5 or 6, wherein the bridge includes a front side and a back side, and the passive device is coupled to the back side of the bridge.

[0157] Aspect 8: The package according to aspect 7, wherein the bridge is configured to provide at least one electrical path for power, and the power passing through the bridge passes through the back side of the bridge.

[0158] Aspect 9: The package according to aspects 1 to 8, wherein a first integrated device is configured to be electrically coupled to the bridge.

[0159] Aspect 10: The package according to aspects 1 to 9, wherein a first integrated device is configured to be electrically coupled to a second integrated device via a substrate and a bridge.

[0160] Aspect 11: The package according to aspect 10, wherein input and / or output (I / O) signals are configured to pass between a first integrated device and a second integrated device through an electrical path including an interconnect from the substrate and a bridge interconnect from the bridge.

[0161] Aspect 12: The package according to aspects 1 to 11, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0162] Aspect 13: The package according to aspects 1 to 12, wherein at least one first bridge interconnect has a first thickness and at least one second bridge interconnect has a second thickness, and the second thickness is greater than the first thickness.

[0163] Aspect 14: The package according to aspect 13, wherein the first thickness is within a first range of about 1 to 2 micrometers and the second thickness is within a second range of about 3 to 6 micrometers.

[0164] Aspect 15: A device comprising a package including a substrate, a bridge located within the substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The bridge comprises a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate.

[0165] Aspect 16: The device according to aspect 15, wherein the first integrated device is configured to be electrically coupled to the second integrated device via the substrate and the bridge.

[0166] Aspect 17: The device according to aspect 16, wherein input and / or output (I / O) signals are configured to pass between the first integrated device and the second integrated device through an electrical path including an interconnect from the substrate and a bridge interconnect from the bridge.

[0167] Aspect 18: The device according to aspects 15 to 17, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

[0168] Aspect 19: The device according to aspects 15 to 18, further comprising a passive device coupled to at least one second bridge interconnect.

[0169] Aspect 20: The device according to aspect 19, further comprising a encapsulation layer encapsulating the passive device.

[0170] Aspect 21: The device according to aspect 19 or 20, wherein the bridge includes a front side and a back side, and the passive device is coupled to the back side of the bridge.

[0171] Aspect 22: A device according to aspect 21, wherein the bridge is configured to provide at least one electrical path for power supply, and the power supply passing through the bridge passes through the back side of the bridge.

[0172] Aspect 23: A device according to aspects 15 to 22, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

[0173] Aspect 24: A method for fabricating a package. The method includes providing a substrate. The method includes installing a bridge in the substrate. The bridge includes a bridge substrate, at least one first bridge dielectric layer coupled to a first surface of the bridge substrate, at least one first bridge interconnect located within the at least one first bridge dielectric layer, at least one second bridge dielectric layer coupled to a second surface of the bridge substrate, at least one second bridge interconnect located within the at least one second bridge dielectric layer, and at least one bridge interconnect extending through the at least one first bridge dielectric layer and the bridge substrate. The method includes coupling a first integrated device to the substrate. The method includes coupling a second integrated device to the substrate.

[0174] Aspect 25: A method according to aspect 24, wherein the package includes a passive device coupled to at least one second bridge interconnect.

[0175] Aspect 26: A method according to aspect 25, wherein the package includes a encapsulation layer encapsulating the passive device.

[0176] Aspect 27: The method according to aspect 25 or 26, wherein the bridge includes a front side and a back side, and the passive device is coupled to the back side of the bridge.

[0177] Aspect 28: The method according to aspect 27, wherein the bridge is configured to provide at least one electrical path for power, and the power passing through the bridge passes through the back side of the bridge.

[0178] The various features of the present disclosure described herein can be implemented in various systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is not intended to limit the claims, but is intended to be illustrative. Therefore, the present teachings can be easily applied to other types of devices, and many alternative forms, modifications, and variations will be apparent to those skilled in the art.

Description of Reference Numerals

[0179] 100 Package 102 Substrate 103 Integrated Device 105 Integrated Device 107 Bridge 170 Bridge Substrate 172 Bridge Dielectric Layer 173 Bridge Interconnection 174 Bridge Dielectric Layer 175 Bridge Interconnection

Claims

1. A substrate, A bridge located within the substrate, A bridge substrate, At least one first bridge dielectric layer coupled to a first surface of the bridge substrate, At least one first bridge interconnect located within the at least one first bridge dielectric layer, At least one second bridge dielectric layer coupled to a second surface of the bridge substrate, At least one second bridge interconnect located within the at least one second bridge dielectric layer, A bridge comprising the at least one first bridge dielectric layer and at least one bridge interconnect extending through the bridge substrate, A first integrated device coupled to the substrate, A second integrated device coupled to the substrate, a package.

2. The at least one first bridge interconnect is configured to provide a first electrical path for input / output (I / O) signals, The at least one second bridge interconnect is configured to provide a second electrical path for power supply, The package according to claim 1.

3. The at least one first bridge interconnect is configured to provide a first electrical path for input / output (I / O) signals, The at least one second bridge interconnect is configured to provide a second electrical path for ground, The package according to claim 1.

4. The package according to claim 3, wherein the at least one second bridge interconnect is configured to provide another electrical path for power supply.

5. The package according to claim 1, further comprising a passive device coupled to the at least one second bridge interconnect.

6. The package according to claim 5, further comprising a encapsulation layer encapsulating the passive device.

7. The bridge includes a front side and a back side, The passive device is coupled to the back side of the bridge, The package according to claim 5.

8. The bridge is configured to provide at least one electrical path for power supply, The power supply passing through the bridge passes through the back side of the bridge, The package according to claim 7.

9. The package according to claim 1, wherein the first integrated device is configured to be electrically coupled to the bridge.

10. The package according to claim 1, wherein the first integrated device is configured to be electrically coupled to the second integrated device via the substrate and the bridge.

11. The package according to claim 10, wherein input and / or output (I / O) signals pass between the first integrated device and the second integrated device through an electrical path including an interconnect from the substrate and a bridge interconnect from the bridge.

12. The package according to claim 1, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

13. The at least one first bridge interconnect includes a first thickness, the at least one second bridge interconnect has a second thickness, and the second thickness is greater than the first thickness, the package according to claim 1.

14. The first thickness is within a first range of about 1 to 2 micrometers, the second thickness is within a second range of about 3 to 6 micrometers, the package according to claim 13.

15. A package comprising: a substrate; a bridge located within the substrate, the bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located within the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located within the at least one second bridge dielectric layer; a bridge comprising the at least one first bridge dielectric layer and at least one bridge interconnect extending through the bridge substrate; a first integrated device coupled to the substrate; and a second integrated device coupled to the substrate. A device.

16. The device according to claim 15, wherein the first integrated device is configured to be electrically coupled to the second integrated device via the substrate and the bridge.

17. The device according to claim 16, wherein an input and / or output (I / O) signal passes between the first integrated device and the second integrated device through an electrical path including an interconnect from the substrate and a bridge interconnect from the bridge.

18. The device according to claim 15, wherein the first integrated device includes a first chiplet and the second integrated device includes a second chiplet.

19. The device according to claim 15, further comprising a passive device coupled to the at least one second bridge interconnect.

20. The device according to claim 19, further comprising a encapsulation layer encapsulating the passive device.

21. The bridge includes a front side and a back side, The passive device is coupled to the back side of the bridge, The device according to claim 19.

22. The bridge is configured to provide at least one electrical path for power, The power passing through the bridge passes through the back side of the bridge, The device according to claim 21.

23. The device according to claim 15, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in an autonomous vehicle.

24. A method for fabricating a package, comprising: providing a substrate; forming in the substrate a bridge comprising: a bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located within the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located within the at least one second bridge dielectric layer; installing a bridge comprising the at least one first bridge dielectric layer and at least one bridge interconnect extending through the bridge substrate. coupling a first integrated device to the substrate; A method comprising coupling a second integrated device to the substrate. **Claim 25** The method of claim 24, wherein the package comprises a passive device coupled to the at least one second bridge interconnect. **Claim 26** The method of claim 25, wherein the package comprises an encapsulation layer encapsulating the passive device. **Claim 27** The bridge includes a front side and a back side; The passive device is coupled to the back side of the bridge; The method of claim 25. **Claim 28** The bridge is configured to provide at least one electrical path for power; The power passing through the bridge passes through the back side of the bridge; The method of claim 27.

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