CPP-Independent Source-Drain Contact Formation for a Gate-All-Around Device with Dielectric Isolation

Abstract

A semiconductor structure is presented, the semiconductor structure comprising a source / drain (S / D) epitaxial growth formed over a lower dielectric isolation region, at least one first semiconductor layer disposed within the S / D epitaxial growth of the S / D region, and at least one second semiconductor layer partially disposed within the gate region. The at least one second semiconductor layer extends from the gate region into the spacer region, enabling connection to the S / D epitaxial growth. The semiconductor structure further comprises a first region comprising adjacent devices exhibiting a first contact gate - poly - pitch (CPP) defining a first gate - to - gate space, and a second region comprising adjacent devices exhibiting a second CPP defining a second gate - to - gate space, the second gate - to - gate space being larger than the first gate - to - gate space, such that the adjacent devices exhibiting the first CPP have a gate - to - gate pitch smaller than that of the adjacent devices exhibiting the second CPP.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and more particularly to contact gate poly-pitch agnostic source / drain (S / D) contact formation for gate-all-around (GAA) devices with bottom dielectric isolation.

Background Art

[0002] When FinFETs were first commercialized at the 22 nm node, it brought about a revolutionary change in the way transistors are constructed. Compared with previous planar transistors, the fin with the gate contacting on three sides enabled significantly better control of the channel formed inside the fin. However, as the 5 nm and 3 nm nodes are reached and such FinFETs are adopted at the 5 nm and 3 nm nodes, the problems increase even more, so it seems that FinFETs have reached the limit of their usefulness.

[0003] Device manufacturers adjust transistors for each node to provide both performance improvement and power reduction at a smaller device area and lower cost. However, further shrinking the dimensions of FinFETs causes limitations or challenges, for example, in drive current and electrostatic control. In planar transistors, by widening the channel width, more current can flow and the transistor can be switched on and off faster. However, the evolution of complementary metal oxide semiconductor (CMOS) designs to standard cells with a lower track height means less freedom in fin dimensions. In single-fin devices at nodes below 5 nm, sufficient drive current will not be able to be supplied. Also, although three sides of the fin are controlled by the gate, one side remains uncontrolled. As the gate length gets shorter, the short-channel effect becomes even greater and leakage through the non-contacted bottom of the device increases. As a result, smaller devices will not be able to meet the power and performance targets.

[0004] As semiconductor integrated circuits (ICs) or chips are miniaturized, stacked nanosheets, which are two-dimensional nanostructures with a thickness in the range of about 1 to 100 nanometers, are increasingly used. Nanosheets and nanowires are regarded as device options suitable for scaling semiconductor devices below 5 nm. A general process flow for nanosheet formation includes the removal of a sacrificial layer of silicon germanium (SiGe) between silicon (Si) sheets. The gate-all-around, i.e., GAA, transistor design aims to continue progress in semiconductor space at the transistor level as much as possible in accordance with Moore's law.

[0005] A GAA transistor is a modified transistor structure in which the gate contacts the channel from all sides, enabling continuous scaling. Initial GAA devices use vertically stacked nanosheets. Initial GAA devices are constructed of individual horizontal sheets with all sides surrounded by gate material. This results in improved channel control compared to FinFETs. The on-capacitance of a GAA transistor increases by vertically stacking multiple nanosheets with the gate material wrapping around the channel, unlike FinFETs which require arranging multiple fins for larger currents. The dimensions of the nanosheets can be adjusted to suit the specific performance required of the transistor. However, similar to fins, as technology improves and the ability to print finer features continues to increase, the width and spacing of the nanosheets will decrease.

[0006] GAA thus enables an improvement over conventional transistor designs by surrounding the silicon semiconductor channel with gate material on four sides, rather than covering it from three sides with a gate (e.g., a FinFET device). The main advantage of the GAA transistor design is to reduce the design size and increase the potential for channel length scaling, thereby enabling an increase in transistor density. The GAA transistor is thus thought to be a successor to the FinFET. Summary of the Invention

[0007] According to one embodiment, a semiconductor structure is provided. The semiconductor structure includes a source / drain (S / D) epitaxial growth formed over a bottom dielectric isolation (BDI) region, and at least one first semiconductor layer disposed within the S / D epitaxial growth of the S / D region, where the at least one first semiconductor layer is a non-active channel; at least one second semiconductor layer partially disposed within a gate region, where the at least one second semiconductor layer is an active channel and the at least one second semiconductor layer extends from the gate region into a spacer region to enable connection to the S / D epitaxial growth; a first region including adjacent devices defining a first contact gate-poly-pitch (CPP) that defines a first gate-to-gate space; and a second region including adjacent devices defining a second CPP that defines a second gate-to-gate space, where the adjacent devices defining the first CPP have a gate-to-gate canyon that is advantageously smaller than the adjacent devices defining the second CPP such that the second gate-to-gate space is larger than the first gate-to-gate space. Advantages of such a structural configuration include, among other things, enabling reliable landing of trench-type metal contacts on epi integrated in the space of the large canyon, as well as a significant improvement in the Si surface available for S / D epi nucleation.

[0008] According to another embodiment, a semiconductor structure is provided. The semiconductor structure includes a bottom dielectric isolation (BDI) region disposed in direct contact with a substrate, source / drain (S / D) epitaxial growth having a vertical portion disposed over the BDI region, at least one first semiconductor layer disposed within the S / D epitaxial growth of the S / D region, and at least one second semiconductor layer disposed partially within a gate region, the at least one second semiconductor layer extending from the gate region into a spacer region and enabling connection to the S / D epitaxial growth, a first region comprising adjacent devices exhibiting a first contact gate - poly - pitch (CPP) defining a first gate - to - gate space, and a second region comprising adjacent devices exhibiting a second CPP defining a second gate - to - gate space, the second gate - to - gate space being larger than the first gate - to - gate space, and the adjacent devices exhibiting the first CPP advantageously having a smaller gate - to - gate pitch than the adjacent devices exhibiting the second CPP. Advantages of such a structural configuration include, at least, not only enabling reliable landing of trench - type metal contacts on epi - integrated in a large - cation space, but also including a significant improvement in the Si surface available for S / D epi - nucleation.

[0009] According to yet another embodiment, a method is provided. The method includes forming fins on a substrate, where the fins comprise layers in which a first semiconductor material and a second semiconductor material are alternately arranged; forming a sacrificial gate; forming a sacrificial dielectric on the fins in a gate region; directly constructing a bottom dielectric isolation (BDI) region between the fins and the substrate; forming a first spacer; depositing an interlayer dielectric (ILD) in a source / drain (S / D) region; selectively etching the first spacer; recessing the fins to form an internal spacer; forming a source / drain (S / D) epitaxial growth; forming a second spacer that is in direct contact with the S / D epitaxial growth on the S / D epitaxial growth; etching the first semiconductor material of the fins in the S / D region to selectively remove the internal spacer formed in the S / D region; selectively etching the second spacer to expose the upper surface of the S / D epitaxial growth; and forming a cladded S / D epitaxy in the S / D region such that the cladded S / D epitaxy surrounds the second semiconductor material of the fins. Advantages of such a method include, at least, providing an inexpensive and optimal solution for preventing punch-through of the bottom dielectric isolation between S / D recesses using a simple spacer, thereby enabling the simulated reproduction of a constant anion space design for any CPP and any gate length.

[0010] In a preferred aspect, the central axis of at least one first semiconductor layer in the S / D region is horizontally aligned with the central axis of at least one second semiconductor layer extending from the gate region to the spacer region.

[0011] In another preferred aspect, at least one first semiconductor layer is made of the same material as at least one second semiconductor layer.

[0012] In yet another preferred embodiment, the S / D epitaxial growth defines a vertical portion that extends above the upper surfaces of at least one first semiconductor layer and at least one second semiconductor layer from the BDI region.

[0013] In a preferred embodiment, the vertical portion of the S / D epitaxial growth connects at least one first semiconductor layer of the S / D region to at least one second semiconductor layer that extends from the gate region to the spacer region.

[0014] In another preferred embodiment, the S / D epitaxial growth completely surrounds at least one first semiconductor layer.

[0015] In yet another preferred embodiment, adjacent devices of a first region indicating a first CPP include an S / D region in which at least one first semiconductor layer is not disposed within the S / D, and adjacent devices of a second region indicating a second CPP include an S / D region in which at least one second semiconductor layer is disposed within the S / D.

[0016] In yet another preferred embodiment, the metal contact extends below the upper surface of the vertical portion defined by the S / D epitaxial growth.

[0017] Advantages of the present invention include producing transistors that consume less power, have excellent performance, occupy less area on a wafer, and reduce semiconductor manufacturing costs. The main architectural challenge of GAA devices arises because the structures being built are complex. GAA transistors are fabricated by first growing a superlattice with alternating epitaxial layers of SiGe and Si that form the basis of the nanosheets. The main steps include, but are not limited to, depositing internal dielectric spacers to protect the S / D regions and define the gate width, as well as channel release etching to remove the sacrificial layer. The space left after removing the sacrificial layer then needs to be filled with gate dielectric and metal, including between the nanosheets. New materials have been introduced for the gate metal and new architectural steps are constantly evolving. There are also additional challenges, including punch-through of the lower dielectric in the variable space of the gate-to-gate cations and contact landing on unintegrated epi in the wide PC-to-PC cations. For example, if there are devices with a large pitch where BDI is useful or required under the S / D, a (100) template that can fill the large S / D voids will be needed somewhere in the S / D region.

[0018] Exemplary embodiments of the present invention advantageously address such challenges by using simple spacers to enable the simulated reproducibility of a constant cation space design for any CPP and any gate length. This is useful as it provides an inexpensive and optimal solution to prevent punch-through of the lower dielectric separation between the S / D recesses.

[0019] Note that the exemplary embodiments are described in relation to various subject matters. Specifically, while some embodiments are described in relation to method-type claims, other embodiments are described in relation to apparatus-type claims. However, one of ordinary skill in the art will appreciate, unless otherwise specified, that any combination of features belonging to one type of subject matter, in addition to any combination of features relating to different subject matters, specifically, any combination of features of method-type claims and features of apparatus-type claims, is also disclosed within this document, as will be inferred from the above description and the following description.

[0020] These features and advantages, as well as other features and advantages, will become apparent from the following detailed description of the exemplary embodiments of the present disclosure, which is to be read in conjunction with the accompanying drawings.

[0021] In the following description of the preferred embodiments of the present invention, details will be presented with reference to the following figures.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0023] Throughout the drawings, the same or similar reference numerals represent the same or similar elements.

[0024] Embodiments according to the present invention provide a method and device that advantageously enable contact gate - poly - pitch (CPP) - independent source / drain (S / D) contact formation for a gate - all - around (GAA) device with bottom dielectric isolation, comprising a stacked mandrel of the S / D region horizontally aligned with a stacked channel of the gate region. The stacked mandrel of the S / D region and the stacked channel of the gate region may be beneficial because they are made of the same material. Complete bottom dielectric isolation in the gate region and the S / D region is advantageously achieved, and a vertical S / D epitaxy that extends from the bottom dielectric isolation up to above the topmost mandrel and connects the stacked mandrel of the S / D region and the stacked channel of the gate region is provided as a beneficial improvement. It is further advantageous because a clad S / D epitaxy is realized around the stacked mandrel of the S / D region to connect the vertical S / D epitaxy between the stacked mandrel of the S / D region and the stacked channel of the gate region.

[0025] Exemplary embodiments of the present invention further provide an improved silicon (Si) surface available for S / D epitaxial nucleation. In other words, the non-cut sheet of (Si) in the S / D region is advantageous because it enables the nucleation of a large amount of crystalline epi. Exemplary embodiments of the present invention are further advantageous in that trench-type metal contacts can be reliably landed on epi integrated in a large gate-cation space. In a wide cation where the substrate is covered with bottom dielectric isolation (BDI) or BOX (in the case of SOI), since the substrate is not exposed, S / D epitaxy cannot nucleate at the center of the cation. As a result, epitaxy is formed only on the sidewalls of adjacent devices, which may prevent trench-type contacts from landing on the S / D epi. Adding such a Si mandrel above the BDI or BOX (in the case of SOI) in the S / D region is advantageous because it enables the formation of a reliable nucleation point for S / D epitaxy integrated in the space between wide gates. By the exemplary method of the present invention, it is further advantageous that by using a simple spacer, a constant cation space design for any CPP and any gate length can be simulated and reproduced. This enables the prevention of punch-through of improved bottom dielectric isolation between S / D recesses, which is beneficial in GAA semiconductor processing.

[0026] Examples of semiconductor materials that can be used for forming such nanosheet structures include silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), group III-V compound semiconductors, or group II-VI compound semiconductors, or combinations thereof. Group III-V compound semiconductors are materials that include at least one element from group III of the periodic table and at least one element from group V of the periodic table. Group II-VI compound semiconductors are materials that include at least one element from group II of the periodic table and at least one element from group VI of the periodic table.

[0027] While the present invention will be described with respect to a given exemplary architecture, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention. Note that for clarity, some features may not be shown in all figures. This is not intended to be construed as limiting any particular embodiment or illustrative figure, or the claims.

[0028] FIG. 1 is a cross-sectional view of a semiconductor structure comprising a nanosheet stack formed on a substrate according to an embodiment of the present invention.

[0029] The nanosheet stack 20 is formed on the substrate 10 in various exemplary embodiments.

[0030] Specifically, in structure 5A, a sacrificial layer 22 is formed on the substrate 10 in the source / drain (S / D) region. The sacrificial layer 22 contains silicon germanium (SiGe) having a Ge concentration in the range of about 40% to about 75%. The nanosheet stack 20 is formed on the sacrificial layer 22, and the nanosheet stack 20 includes layers in which a first semiconductor material (or layer) 24 and a second semiconductor material (or layer) 26 are alternately arranged. The first semiconductor material 24 can be, for example, silicon germanium (SiGe) having a Ge concentration in the range of about 15% to about 50%, and the second semiconductor material 26 can be, for example, silicon (Si). The first semiconductor layer 24 and the second semiconductor layer 26 can be referred to as mandrels or channels. Note that a "stack" can include one or more layers or channels, or at least one layer or channel.

[0031] Structure 5A is a cross-sectional view along axis Y1 shown in top view 7.

[0032] Structure 5B shows the same structure as structure 5A in the second spacer region and is a cross-sectional view along axis Y2 shown in top view 7.

[0033] The structure 5C shows the same structure as the structure 5A in the first spacer region, and is a cross-sectional view along the axis Y3 shown in the top view 7.

[0034] The structure 5D shows the same structure as the structure 5A in the gate region, and is a cross-sectional view along the axis Y4 shown in the top view 7.

[0035] The structure 5E shows the same structure as the structure 5A, and is a cross-sectional view along the axis X that horizontally extends across the first spacer 40, the second spacer 44, and the sacrificial material 36 shown in the top view 7.

[0036] The top view 7 shows the spatial relationship between the first spacer 40, the second spacer 44, the sacrificial material 36, and the fin 20'.

[0037] The substrate 10 can be a semiconductor or insulator with an active surface semiconductor layer in one or more embodiments. The substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 can be essentially (e.g., excluding contaminants) a single element (e.g., silicon), predominantly (e.g., doped) a single element, such as silicon (Si) or germanium (Ge), or the substrate 10 can include a compound, such as Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate 10 can comprise a plurality of material layers, such as a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GeOI), or a silicon-germanium-on-insulator substrate (SGOI). The substrate 10 can also comprise other layers forming the substrate 10 that include a high-k oxide or a high-k nitride, or both. The substrate 10 can be a silicon wafer in one or more embodiments. In one embodiment, the substrate 10 is a single crystal silicon wafer.

[0038] Referring to, for example, the nanosheet stack 20, the first semiconductor material 24 can be the first layer in a stack of sheets of alternately arranged materials. The nanosheet stack 20 thus comprises a first semiconductor material (or layer) 24 and a second semiconductor material (or layer) 26. Specifically, it is contemplated that the first semiconductor material 24 can be formed of silicon germanium and the second semiconductor material 26 can be formed of silicon, but it should be understood that any suitable materials can be used instead, as long as the two semiconductor materials have an etching selectivity with respect to each other. As used herein, the term "selective" in relation to a material removal process indicates that the material removal rate of the first material is faster than the removal rate of at least one other material of the structure to which the material removal process is applied. The alternately arranged semiconductor materials 24 / 26 can be deposited by any suitable mechanism. Specifically, it is contemplated that the semiconductor materials 24 / 26 can epitaxially grow on each other, but alternate deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition are also contemplated.

[0039] FIG. 2 is a cross-sectional view of the semiconductor structure of FIG. 1 with a hard mask deposited and fins formed, according to one embodiment of the present invention.

[0040] In various exemplary embodiments, the fin 20' is formed by depositing a hard mask 30 and selectively etching the nanosheet stack 20. A space 28 is defined between the fins 20'. The etching also acts on the sacrificial layer 22 and the substrate 10. By the etching, specifically, a recessed sacrificial layer 22' is formed between the substrate 10 and the fin 20'. The etching also recesses the substrate 10 within the space 28 defined between the fins 20'. The recessed region is also referred to as a trench. The fins 20' can be seen in the S / D region, the second spacer region, the first spacer region, and the gate region. The fins 20' include alternately arranged semiconductor layers 24' / 26'.

[0041] The hard mask 30 can be, for example, a hard mask containing nitride. The hard mask 30 can include any one or more of, among other materials, SiO, SiN, SiCN, SiBN, or SiBCN, or a combination thereof. The hard mask 30 can be an oxide, for example, a hard mask of silicon oxide. The hard mask 30 can be patterned by any suitable patterning technique including, but not limited to, lithography followed by etching, sidewall image transfer (SIT), direct patterning, self-aligned double patterning (SADP), self-aligned multiple patterning (SAMP), self-aligned quadruple patterning (SAQP), or any suitable combination of these techniques.

[0042] Any etching technique known in the art can be used to form the recesses.

[0043] FIG. 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a shallow trench isolation (STI) region is formed and the hard mask is removed, according to one embodiment of the present invention.

[0044] The STI region 32 is formed on the substrate 10 in various exemplary embodiments. The STI region 32 extends into the recess or trench of the substrate 10. Then, the hard mask 30 is selectively removed. The formation of the STI region 32 may include FCVD oxide deposition, chemical mechanical polishing (CMP) that stops at the hard mask of the fin, selectively recessing the STI oxide to a desired height, and stripping of the hard mask of the fin.

[0045] FIG. 4 is a cross-sectional view of the semiconductor structure of FIG. 3 in which a dummy oxide is deposited, a dummy gate including a sacrificial material and a hard mask is formed, and patterning and etching of the dummy gate are performed, according to one embodiment of the present invention.

[0046] In various exemplary embodiments, a dielectric liner 34, a sacrificial material 36, and a hard mask 38 are formed in the gate region. The dielectric liner 34 surrounds or encapsulates the fin 20'. The sacrificial material 36 is formed on the fin 20' of the gate region.

[0047] The dielectric liner 34 can be, for example, an oxide layer.

[0048] The sacrificial material 36 can be, for example, amorphous silicon (a-Si).

[0049] The hard mask 38 can be, for example, a hard mask containing nitrides. The hard mask 38 includes, among other materials, one or more of SiO, SiN, SiCN, SiBN, or SiBCN, or a combination thereof. The hard mask 38 can be an oxide hard mask, for example, a silicon oxide hard mask. The hard mask 38 can be patterned by any suitable patterning technique including, but not limited to, lithography followed by etching, direct patterning, self-aligned double patterning (SADP), self-aligned multi-patterning (SAMP), self-aligned quad-patterning (SAQP), or any suitable combination of these techniques.

[0050] The liner 34, the sacrificial material 36, and the hard mask 38 can also be seen in a cross-sectional view along the X direction.

[0051] FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 according to an embodiment of the present invention, in which the sacrificial layer of the nanosheet stack is removed, the first spacer is selectively deposited to form a lower dielectric isolation (BDI) layer adjacent to the substrate, and the gate spacer is formed together with the BDI layer.

[0052] In various exemplary embodiments, a lower dielectric isolation (BDI) region 42 is formed by depositing the first spacer 40 and replacing the recessed sacrificial layer 22' located between the substrate 10 and the fin 20'. The first spacer 40 surrounds or encircles the fin 20' and the dummy gate in the first spacer region. The first spacer 40 is also formed at the opposing ends of the sacrificial material 36 in a cross-sectional view along the X direction. The BDI region 42 is formed directly between the substrate 10 and the fin 20'. The BDI region 42 can be made of the same material as the first spacer 40.

[0053] The first spacer 40 and the BDI region 42 may include one or more of films of SiN, SiBN, SiCN, SiBCN, SiO, SiOC, SiON, or SiOCN, or a combination thereof.

[0054] FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 in accordance with an embodiment of the present invention, in which a second spacer is selectively deposited and an interlayer dielectric (ILD) is deposited over a source / drain (S / D) region.

[0055] In various exemplary embodiments, a second spacer 44 is selectively deposited in a second spacer region and an interlayer dielectric (ILD) 46 is deposited over fins 20' of a source / drain (S / D) region. In the X direction, the second spacer 44 is formed adjacent to the first spacer 40 such that the second spacer 44 directly contacts the first spacer 40. Further in the X direction, the ILD 46 directly contacts the second spacer 44. Planarization, such as chemical mechanical polishing (CMP), is performed to planarize the upper surfaces of the first spacer 40, the second spacer 44, and the ILD 46.

[0056] The second spacer 44 can be, for example, titanium oxide (TiOx).

[0057] The ILD 46 can be any suitable material, such as, for example, porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. Any known manner of forming the ILD 46 can be utilized. The ILD 46 can be formed, for example, using CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD.

[0058] FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 in accordance with an embodiment of the present invention, in which the second spacer is selectively removed, the fins are recessed, and an internal spacer is formed.

[0059] In various exemplary embodiments, the second spacer 44 is selectively removed, the exposed fin 20' is recessed, and an internal spacer 50 is formed. By selectively removing the second spacer 44, an opening 48 is created. In the second spacer region, the upper surface 43 of the BDI region 42 is exposed. The internal spacer 50 can be seen in the first spacer region. The views of the S / D region and the gate region remain the same. In the X direction, within the opening 48, the upper surface 43 of the BDI region 42 is exposed.

[0060] The internal spacer 50 can include one or more of a film of SiN, SiBN, SiCN, SiBCN, SiO, SiOC, SiON, or SiOCN, or a combination thereof.

[0061] Etching can include a dry etching process such as reactive ion etching, plasma etching, ion beam etching, or laser ablation. Etching can further include a wet chemical etching process that uses one or more chemical etchants to remove a portion of a blanket layer that is not protected by a patterned photoresist.

[0062] In some examples, a portion of the first semiconductor material 24 (e.g., a SiGe layer) can be selectively removed by selective wet etching or selective dry etching, leaving all or a portion of the second semiconductor material 26. By removing, a gap, opening, or depression is created between the second semiconductor materials 26.

[0063] The dry and wet etching processes can have adjustable etching parameters, such as the etching agent used, etching temperature, etching solution concentration, etching pressure, power output, RF bias voltage, RF bias output, etching agent flow rate, and other suitable parameters. The dry etching process can include a bias-applied plasma etching process that uses a chlorine-based chemical reaction. Other dry etching gases can include tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), helium (He), and chlorine trifluoride (ClF3). In dry etching, anisotropic etching can also be performed using mechanisms such as DRIE (deep reactive-ion etching). Chemical vapor etching can be used as a selective etching method, and the etching gases can include hydrogen chloride (HCl), tetrafluoromethane (CF4), and a gas mixture with hydrogen (H2). Chemical vapor etching can be performed by CVD at suitable pressures and temperatures.

[0064] FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 in accordance with an embodiment of the present invention, in which S / D epitaxial growth is performed, the ILD is removed, and a third spacer is deposited on the S / D epitaxial growth.

[0065] In various exemplary embodiments, first, S / D epitaxial growth 52 is performed. S / D epitaxial growth 52 can be seen in the X direction in the second spacer region. Then, the ILD 46 is removed and a third spacer 54 is deposited. The third spacer 54 is formed directly on the S / D epitaxial growth 52. The third spacer 54 can be seen in the X direction only in the second spacer region.

[0066] The S / D epitaxial growth 52 is in direct contact with the BDI region 42 in the second spacer region. In the X direction, the S / D epitaxial growth 52 is in direct contact with the sidewalls of the inner spacer 50. The S / D epitaxial growth 52 actually extends in the vertical direction and is in direct contact with a part of the sidewall of the first spacer 40. Thus, the S / D epitaxial growth 52 defines a vertical portion or region.

[0067] In the S / D region, the fins 20' are exposed such that an opening 56 is defined between the fins 20'. Further in the X direction, an opening 58 is defined that separates the third spacer 54 formed around the sacrificial material 36.

[0068] The third spacer 54 can be, for example, titanium oxide (TiOx).

[0069] The terms "epitaxial growth" and "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, and the semiconductor material to be grown has substantially the same crystal characteristics as the semiconductor material of the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the atoms to be deposited move around on the surface and reach the deposition surface with sufficient energy to orient themselves to the crystal arrangement of the atoms on the deposition surface. Thus, in some examples, an epitaxial film deposited on a {100}-oriented crystal surface will be {100}-oriented.

[0070] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 according to an embodiment of the present invention, in which the remaining sacrificial layer of the fin is removed to create a gap between the semiconductor layers of the fin, and the inner spacer is also removed after selectively removing the sacrificial material.

[0071] In various exemplary embodiments, the remaining sacrificial layer of fin 20' is removed, creating a gap 60 between semiconductor materials 26' of fin 20'. This is clearly shown in the X direction in the S / D region. In the X direction, the internal spacer 50 is also etched back.

[0072] FIG. 10 is a cross-sectional view of the semiconductor structure of FIG. 9, according to an embodiment of the present invention, in which the semiconductor layer of the nanosheet stack is optionally thinned and a third spacer is selectively removed.

[0073] The semiconductor material 26' of the nanosheet stack is optionally thinned in various exemplary embodiments, creating a thinned semiconductor material 26'', and the third spacer 54 is selectively removed to expose the S / D epitaxial growth 52. Not only the top surface 53 of the S / D epitaxial growth 52 but also the sidewalls of the S / D epitaxial growth 52 are exposed. The S / D epitaxial growth 52 can be seen in the X direction in the second spacer region. The thinned semiconductor material 26'' may also be referred to as the first stacked semiconductor layer 26''.

[0074] FIG. 11 is a cross-sectional view of the semiconductor structure of FIG. 10, according to an embodiment of the present invention, in which additional S / D epitaxial growth is performed around the thinned semiconductor layer, an ILD is deposited on the additional S / D epitaxial growth, and chemical mechanical polishing (CMP) is performed to remove the remaining hard mask.

[0075] In various exemplary embodiments, it is advantageous that additional S / D epitaxial growth 62 is performed around the thinned semiconductor material (or layer) 26'' and on the existing S / D epitaxial growth 52. The additional S / D epitaxial growth 62 may be referred to as clad S / D epitaxy surrounding a non-cut Si sheet (i.e., the thinned semiconductor layer 26''). Then, an ILD 64 is deposited on the clad S / D epitaxial growth 62 and CMP is performed to remove the remaining hard mask 38.

[0076] FIG. 12 is a cross-sectional view of the semiconductor structure of FIG. 11, according to an embodiment of the present invention, in which the sacrificial gate and the gate dielectric layer are removed from the gate region, exposing the semiconductor layer region of the fin in the gate region.

[0077] In various exemplary embodiments, not only is the sacrificial material 36 and the sacrificial semiconductor layer 24' of the fin 20' removed from the gate region, but also the semiconductor layer region of the fin 20' in the gate region is exposed in the X direction. During this process, the dielectric liner 34 is also selectively removed. A gap or opening 66 is created between the remaining semiconductor layers 26' of the gate region. The semiconductor layer 26' may also be referred to as the second stacked semiconductor layer 26'.

[0078] FIG. 13 is a cross-sectional view of the semiconductor structure of FIG. 12, according to an embodiment of the present invention, in which a high-k metal gate (HKMG), a self-aligned contact (SAC) cap, and a trench-type metal contact are formed.

[0079] In various exemplary embodiments, a high-k metal gate (HKMG) 70, a self-aligned contact (SAC) cap 72, and a trench-type metal contact 74 are formed. The SAC cap 72 is formed directly on top of the HKMG 70. The HKMG 70 can be seen in the gate region. The HKMG 70 surrounds, encapsulates, or encloses the semiconductor layer 26' of the gate region. The trench-type metal contact 74 is in direct contact with the clad S / D epitaxial growth 62. The trench-type metal contact 74 advantageously extends below the upper surface of the vertical portion defined by the clad S / D epitaxial growth 62.

[0080] The first stacked semiconductor layer 26'' is advantageously disposed within the clad S / D epitaxial growth 62 of the S / D region, where the first stacked semiconductor layer 26'' has a first thickness. The second stacked semiconductor layer 26' is advantageously disposed within the HKMG 70 of the gate region, where the second stacked semiconductor layer 26' has a second thickness.

[0081] The central axis of the first stacked semiconductor layer 26'' in the S / D region is horizontally aligned with the central axis of the second stacked semiconductor layer 26' in the gate region. Further, the first stacked semiconductor layer 26'' can be made of the same material as the second stacked semiconductor layer 26'.

[0082] The clad S / D epitaxial growth 62 is advantageous in that it defines a vertical portion that extends above the upper surfaces of the first stacked semiconductor layer 26'' and the second stacked semiconductor layer 26' from the BDI region 42. The vertical portion of the clad S / D epitaxial growth 62 is advantageous in that it connects the first stacked semiconductor layer 26'' in the S / D region to the second stacked semiconductor layer 26' that extends from the gate region to the inner spacer region.

[0083] Note that the clad S / D epitaxial growth 62 completely surrounds the first stacked semiconductor layer 26'' in the S / D region. Further note that the HKMG 70 completely surrounds the second stacked semiconductor layer 26' in the gate region.

[0084] In structure 76A, the trench-type metal contact 74 is in direct contact with the clad S / D epitaxial growth 62 that surrounds the thinned semiconductor layer 26''.

[0085] In structure 76B, the trench-type metal contact 74 is in direct contact with the clad S / D epitaxial growth 62 where there is no semiconductor layer.

[0086] In structure 76C, the first spacer 40 surrounds the inner spacer 50 and the alternately arranged semiconductor layers 26'.

[0087] In structure 76D, the HKMG 70 surrounds the semiconductor layer 26' in the gate region.

[0088] In the structure 76E, the trench-type contact 74 is in direct contact with the clad S / D epitaxial growth 62 that surrounds the thinned semiconductor layer 26''. The HKMG 70 surrounds the semiconductor layer 26'.

[0089] In various embodiments, the high-k materials of the HKMG 70 include work function metals such as titanium nitride, titanium carbide, titanium aluminum carbide, tantalum nitride, and tantalum carbide, conductive metals such as tungsten, aluminum, and copper, and silicon dioxide (SiO2), hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), hafnium silicon oxynitride (Hf w Si x O y N z ), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (Zr w Si x O y N z ), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium strontium titanate (e.g., BaTiO3 - SrTiO3), barium titanate (e.g., BaTiO3), strontium titanate (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead scandium tantalate (Pb(Sc x Ta 1-x ), and oxides such as lead zinc niobate (e.g., PbZn 1 / 3 Nb 2 / 3 O3), but are not limited thereto.

[0090] The conductive material or the trench-type contact 74 can be, for example, cobalt (Co).

[0091] Non-limiting examples of suitable conductive materials include doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include dopants incorporated during or after deposition. Conductive metals can be deposited by suitable deposition processes such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0092] FIG. 14 is a cross-sectional view of the semiconductor structure of FIG. 5 when the contact poly-pitch (CPP) in the X direction is different, according to another embodiment of the present invention.

[0093] Fin 20' is likewise formed on the BDI region 42 formed on the substrate 10 in various exemplary embodiments. Fin 20' comprises alternately arranged semiconductor materials (or layers) 24' / 26'. The first semiconductor material 24' can be, for example, silicon germanium (SiGe) with a SiGe concentration of 25%, and the second semiconductor material 26' can be, for example, silicon (Si). A dielectric liner 34, a sacrificial material 36, and a hard mask 38 are formed on the fin 20'. The first spacer 40 is formed at opposite ends of the sacrificial material 36. The hard mask 38 is formed on the sacrificial material 36. The first spacer 40 is in direct contact with the sidewalls of the hard mask 38.

[0094] In structure 80A, the CPP is 42 nm, and as a result, the spacing between the first spacers 40 is D1.

[0095] In structure 80B, the CPP is 100 nm, and as a result, the spacing between the first spacers 40 becomes D2.

[0096] In structure 80C, the CPP is 200 nm, and as a result, the spacing between the first spacers 40 becomes D3.

[0097] Thus, the first region on the wafer with adjacent devices shows a first CPP where the space between the gates is "a". The second region on the wafer with adjacent devices shows a second CPP where the space between the gates is "b". The adjacent devices with the first CPP show that the inter-gate cations are smaller than those of the adjacent devices with the second CPP such that "a < b". The adjacent devices with the first CPP show that the S / D epitaxial region has no semiconductor layer disposed within the S / D. The adjacent devices with the second CPP show that the S / D epitaxial region has a semiconductor layer disposed within the S / D. In the adjacent devices with the second CPP, the horizontal space separating the edge of the semiconductor layer of the S / D epitaxial region and the edge of the semiconductor layer of the device region is equal to the gate-to-gate space "a" of the first CPP region.

[0098] FIG. 15 is a cross-sectional view of the semiconductor structure of FIG. 14 in accordance with an embodiment of the present invention, in which an organic planarization layer (OPL) is deposited on the structure 80A and a second spacer is deposited on the structures 80B and 80C.

[0099] In various exemplary embodiments, in structure 80A, the OPL 81 is deposited.

[0100] In structures 80B and 80C, the second spacer 44 is deposited.

[0101] In structure 80B, the opening O1 is formed, and in structure 80C, the opening O2 is formed.

[0102] FIG. 16 is a cross-sectional view of the semiconductor structure of FIG. 15, in accordance with one embodiment of the present invention, in which an ILD is deposited on the structures 80B, 80C and the OPL is removed.

[0103] The ILD is deposited such that in various exemplary embodiments, an ILD 46 is formed in the opening O1 of the structure 80B and an ILD 46' is formed in the opening O2 of the structure 80C. Next, the OPL 81 is selectively removed from the structure 80A. The OPL 81 can be removed, for example, by ashing.

[0104] FIG. 17 is a cross-sectional view of the semiconductor structure of FIG. 16, in accordance with one embodiment of the present invention, in which a second spacer is selectively removed, the fin is recessed, and an internal spacer is formed.

[0105] In various exemplary embodiments, the second spacer 44 is selectively removed, the fin is recessed to create an opening 82, and an internal spacer 84 is formed. The ILD 46 and ILD 46' each remain on the structures 80B, 80C.

[0106] Any etching technique known in the art can be used to form the recess. In one example, reactive ion etching (RIE) is performed.

[0107] FIG. 18 is a cross-sectional view of the semiconductor structure of FIG. 17, in accordance with one embodiment of the present invention, in which S / D epitaxial growth is performed between the fins, the ILD is removed, and a third spacer is formed on the S / D epitaxial growth.

[0108] In various exemplary embodiments, S / D epitaxial growth 86 is performed between the fins, the ILDs 46, 46' are selectively removed, and a third spacer 88 is formed on the S / D epitaxial growth 86. The third spacer 88 is in direct contact with the upper portion of the S / D epitaxial growth 86. The S / D epitaxial growth 86 has a designed equal width "a".

[0109] In the structure 80B, an opening 89 is defined, while in the structure 80C, an opening 89' is defined. The opening 89' is larger than the opening 89.

[0110] FIG. 19 is a cross-sectional view of the semiconductor structure of FIG. 18 according to an embodiment of the present invention, in which the sacrificial layer of the nanosheet laminate is selectively removed in the structures 80B and 80C to create a gap between the semiconductor layers of the nanosheet laminate, and the internal spacer is removed after the sacrificial layer is selectively removed.

[0111] In various exemplary embodiments, in the structures 80B and 80C, the sacrificial layer of the nanosheet laminate is selectively removed to create a gap 90 between the semiconductor materials (or layers) 26' of the fins. Further, the internal spacer 84 formed on the fins within the openings 89 and 89' is selectively removed. As a result, only the semiconductor layer 26' of the fins remains within the openings 89 and 89'.

[0112] FIG. 20 is a cross-sectional view of the semiconductor structure of FIG. 19 according to an embodiment of the present invention, in which the semiconductor layer of the fin is optionally thinned and the third spacer is selectively removed.

[0113] In various exemplary embodiments, in the structures 80B and 80C, the semiconductor layer 26' of the fin is optionally thinned to create a thinned semiconductor layer 26'', and the third spacer 88 is selectively removed to expose the S / D epitaxial growth 86.

[0114] FIG. 21 is a cross-sectional view of the semiconductor structure of FIG. 20 according to an embodiment of the present invention, in which additional S / D epitaxial growth is performed around the thinned semiconductor layer, an ILD is deposited on the additional S / D epitaxial growth, and chemical mechanical polishing (CMP) is performed to remove the remaining hard mask.

[0115] In various exemplary embodiments, it is advantageous that additional S / D epitaxial growth 92 is performed around the thinned semiconductor layer 26'' and on the existing S / D epitaxial growth 86. The additional S / D epitaxial growth 92 can be referred to as clad S / D epitaxy surrounding the non-cut Si sheet (i.e., the thinned semiconductor layer 26''). Then, ILDs 94, 94', 94'' are deposited on the clad S / D epitaxial growth 92, and CMP is performed to remove the remaining hard mask 38. The ILD 94 is present in the structure 80A, the ILD 94' is present between the fins 20' in the structure 80B, and the ILD 94'' is present between the fins 20' in the structure 80C. The clad S / D epitaxial growth 92 comprises vertical portions having an equal designed width “a”.

[0116] FIG. 22 is a cross-sectional view of the semiconductor structure of FIG. 21 with the remaining sacrificial gate, gate dielectric layer, and sacrificial semiconductor layer removed, according to an embodiment of the present invention.

[0117] In various exemplary embodiments, the sacrificial material 36 and the sacrificial semiconductor layer 24' of the fins 20' are removed to expose the regions of the semiconductor layer 26' of the fins. The dielectric liner 34 is also selectively removed during this process. A gap or opening 96 is created between the remaining semiconductor layers 26'.

[0118] FIG. 23 is a cross-sectional view of the semiconductor structure of FIG. 22 with a high-k metal gate (HKMG), self-aligned contact (SAC) cap, and trench-type contact formed, according to an embodiment of the present invention.

[0119] In various exemplary embodiments, a high-k metal gate (HKMG) 100, a self-aligned contact (SAC) cap 102, and trench metal contacts 104, 106, 108 are formed. The SAC cap 102 is formed directly on top of the HKMG 100. The HKMG 100 surrounds the semiconductor layer 26'. The trench metal contacts 104, 106, 108 are in direct contact with the recessed S / D epitaxial growth 92. The recessed S / D epitaxial growth 92 comprises vertical portions having a designed equal width "a".

[0120] In structure 110A, the trench metal contact 104 is in direct contact with the sidewalls of the recessed S / D epitaxial growth 92 and the first spacer 40.

[0121] In structure 110B, the trench metal contact 106 is in direct contact with the sidewalls of the recessed S / D epitaxial growth 92 and the ILD 94'. The trench metal contact 106 is not in contact with the first spacer 40.

[0122] In structure 110C, the trench metal contact 108 is in direct contact with the sidewalls of the recessed S / D epitaxial growth 92 and the ILD 94''. The trench metal contact 108 is not in contact with the first spacer 40.

[0123] Thus, structures 110A, 110B, 110C are advantageous in that they can show the integration of various CPPs on the same chip where the anion space between the stacked mandrel in the S / D region and the stacked channel in the gate region is equal to the minimum gate pitch design for any CPP on the chip, which is beneficial for GAA semiconductor processing.

[0124] Exemplary embodiments of the present invention, in conclusion, present a method and structure that advantageously enable CPP-independent S / D contact formation for a GAA device with bottom dielectric isolation, comprising a stacked channel in the gate region and a stacked mandrel in the S / D region horizontally aligned therewith. The stacked mandrel in the S / D region and the stacked channel in the gate region can be beneficial as they are made of the same material. Complete bottom dielectric isolation in the gate region and the S / D region is advantageously achieved, and a vertical S / D epitaxy is presented that extends above the topmost mandrel from the bottom dielectric isolation and connects the stacked mandrel in the S / D region and the stacked channel in the gate region. It is further advantageous as a clad S / D epitaxy is realized around the stacked mandrel in the S / D region to connect the vertical S / D epitaxy between the stacked mandrel in the S / D region and the stacked channel in the gate region.

[0125] Exemplary embodiments of the present invention further provide an improved Si surface that can be utilized for S / D epitaxial nucleation. In other words, the (Si) non-cut sheet in the S / D region enables the nucleation of a large amount of crystalline epi. Exemplary embodiments of the present invention are further advantageous in that they enable a trench-type metal contact to be reliably landed on epi integrated in a large gate-cation space. By the exemplary method of the present invention, it is further advantageous that a constant cation space design for any CPP and any gate length can be simulatedly reproduced using a simple spacer. This enables prevention of punch-through of improved lower dielectric isolation between S / D recesses. Also, in a wide cation where the substrate is covered with BDI or BOX (in the case of SOI), since the substrate is not exposed, S / D epitaxy cannot nucleate at the center of the cation. As a result, epitaxy is formed only on the sidewalls of adjacent devices, which may prevent a trench-type contact from landing on the S / D epi. Adding such a Si mandrel above the BDI or BOX (in the case of SOI) in the S / D region is advantageous in that it enables a nucleation point to be surely formed for S / D epitaxy integrated in the space between wide gates.

[0126] With respect to FIGS. 1 to 23, deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). As used herein, "depositing" includes, for example, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion-beam deposition, electron-beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation, and may include any currently known or later developed technique suitable for the material to be deposited, but is not limited thereto.

[0127] As used herein, the term "processing" includes, as necessary to form the described structures, deposition, patterning, exposure, development, etching, cleaning, stripping, implantation, doping, stressing, laminating, or removal of materials or photoresists, or combinations thereof.

[0128] Although the present invention will be described with respect to a particular exemplary architecture, it is to be understood that other architectures, structures, substrate materials, and process features and steps / blocks can be varied within the scope of the present invention.

[0129] It will also be understood that when an element such as a layer, region, or substrate is said to be "on" or "on top of" another element, that element can be directly on top of the other element or intervening elements may also be present. In contrast, when an element is said to be "directly on" or "directly on top of" another element, no intervening elements are present. It will also be understood that when an element is said to be "connected" or "coupled" to another element, that element can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0130] This embodiment may include the design of an integrated circuit chip created in a graphical computer programming language and storable on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not fabricate the photolithographic mask used to fabricate the chip or chips, the designer can transmit the resulting design to such an entity either physically (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet), either directly or indirectly. The stored design is then converted into a format suitable for fabricating a photolithographic mask (e.g., GDSII), which typically includes multiple copies of the chip design to be formed on a wafer. The photolithographic mask is used to define the areas of the wafer (or layers on the wafer, or both) on which etching or other processing is to be performed.

[0131] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be provided by the fabricator in an as-wafer form (i.e., a single wafer comprising a plurality of unpackaged chips), as bare dies, or in a packaged form. In a packaged form, the chips can be mounted in a single chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either or both surface interconnects or buried interconnects). The chips are then integrated, in any case, as part of either (a) an intermediate product such as a motherboard or (b) a final product, with other chips, individual circuit elements, or other signal processing devices, or combinations thereof. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-cost applications to advanced computer products with displays, keyboards, or other input devices, and central processing units.

[0132] It should also be understood that the material compounds are described with respect to the listed elements, such as SiGe. Such compounds, for example in SiGe, contain Si x Ge 1-x and, where x is 1 or less, for example, various proportions of the elements are included within the compound. In addition, other elements may be included in the compound and still function in accordance with this embodiment. Compounds containing additional elements will be referred to herein as alloys.

[0133] References in the specification to "one embodiment" or "an embodiment" of the present invention, as well as to these other variations, mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment of the present invention. Thus, the appearances throughout the specification of phrases such as "in one embodiment" or "in an embodiment", as well as the appearances of other variations, do not necessarily all refer to the same embodiment.

[0134] Any use of the following “ / ”, “or ~, or both”, and “at least one of ~” is intended to include, for example, in the case of “A / B”, “A or B, or both”, and “at least one of A and B”, the selection of only the first-listed option (A), the selection of only the second-listed option (B), or the selection of both options (A and B). It should be understood that as a further example, in the case of “A, B, or C, or a combination thereof” and “at least one of A, B, and C”, such expressions include the selection of only the first-listed option (A), the selection of only the second-listed option (B), the selection of only the third-listed option (C), the selection of only the first and second-listed options (A and B), the selection of only the first and third-listed options (A and C), the selection of only the second and third-listed options (B and C), or the selection of all three options (A, B, and C). As will be readily apparent to those skilled in this art and related arts, this can be extended by the number of items listed.

[0135] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. It should be further understood that the singular forms “a”, “an”, and “the” used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. When used in this specification, the terms “comprising”, “comprises”, “including”, or “includes”, or combinations thereof, identify the presence of the stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0136] Spatially relative terms such as "under", "below", "beneath", "above", "over", etc. may be used herein to facilitate description and to describe the illustrated relationship of one element or feature to another element or feature. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, an element described as "under" or "beneath" another element or feature would, when the device in the figure is turned upside down, be oriented "above" the other element or feature. Thus, the term "under" can encompass both an upward and a downward orientation. The device may be oriented in other directions (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, when a layer is said to be between two other layers, it will be understood that the layer may be the only layer between the two other layers or that one or more intervening layers may also be present.

[0137] As used herein, terms such as first, second, etc. may be used to describe various elements, but it will be understood that such elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could, without departing from the scope of the present concept, be termed a second element.

[0138] Preferred (intended to be illustrative and not limiting) embodiments of methods and structures for CPP-independent S / D contact formation for GAA devices with lower dielectric isolation have been described, but those skilled in the art should note that modifications and changes can be made in view of the above teachings. Accordingly, it should be understood that modifications may be made to the specific embodiments described within the scope of the invention as outlined in the appended claims. Thus, while aspects of the invention have been described including the details and particularity required by patent law, what is claimed and desired to be protected by patent is set forth in the appended claims.

Claims

1. Source / drain (S / D) epitaxial growth formed over a lower dielectric isolation (BDI) region, and At least one first semiconductor layer disposed within the S / D epitaxial growth of the S / D region, the at least one first semiconductor layer being a non-active channel, at least one first semiconductor layer; At least one second semiconductor layer partially disposed within the gate region, the at least one second semiconductor layer being an active channel, the at least one second semiconductor layer extending from the gate region into a spacer region and enabling connection to the S / D epitaxial growth, at least one second semiconductor layer; A first region comprising adjacent devices showing a first contact gate poly pitch (CPP) defining a first gate-to-gate space; A second region comprising adjacent devices showing a second CPP defining a second gate-to-gate space, the adjacent devices showing the first CPP having a smaller gate-to-gate cation than the adjacent devices showing the second CPP such that the second gate-to-gate space is larger than the first gate-to-gate space, a second region; A semiconductor structure comprising.

2. The semiconductor structure according to claim 1, wherein a central axis of the at least one first semiconductor layer of the S / D region is horizontally aligned with a central axis of the at least one second semiconductor layer extending from the gate region to the spacer region.

3. The semiconductor structure according to claim 1, wherein the at least one first semiconductor layer is made of the same material as the at least one second semiconductor layer.

4. The semiconductor structure according to claim 1, wherein the S / D epitaxial growth defines a vertical portion extending above an upper surface of the at least one first semiconductor layer and the at least one second semiconductor layer from the BDI region.

5. The semiconductor structure according to claim 4, wherein the vertical portion of the S / D epitaxial growth connects the at least one first semiconductor layer of the S / D region to the at least one second semiconductor layer extending from the gate region to the spacer region.

6. The semiconductor structure according to claim 1, wherein the S / D epitaxial growth completely surrounds the at least one first semiconductor layer.

7. The adjacent device of the first region indicating the first CPP includes the S / D region where the at least one first semiconductor layer is not disposed in the S / D, and the adjacent device of the second region indicating the second CPP includes the S / D region where the at least one second semiconductor layer is disposed in the S / D. The semiconductor structure according to claim 1.

8. The semiconductor structure according to claim 1, wherein the metal contact extends below the upper surface of the vertical portion defined by the S / D epitaxial growth.

9. A lower dielectric isolation (BDI) region disposed to be in direct contact with the substrate, and a source / drain (S / D) epitaxial growth having a vertical portion disposed on the BDI region, and at least one first semiconductor layer disposed within the S / D epitaxial growth of the S / D region, and at least one second semiconductor layer partially disposed within the gate region, the at least one second semiconductor layer extending from the gate region into the spacer region and enabling connection to the S / D epitaxial growth. A first region including adjacent devices indicating a first contact gate poly pitch (CPP) defining a first gate-to-gate space, and A second region including adjacent devices indicating a second CPP defining a second gate-to-gate space, wherein the adjacent devices indicating the first CPP have a smaller gate-to-gate cation than the adjacent devices indicating the second CPP such that the second gate-to-gate space is larger than the first gate-to-gate space. A semiconductor structure comprising.

10. The semiconductor structure according to claim 9, wherein the central axis of the at least one first semiconductor layer in the S / D region is horizontally aligned with the central axis of the at least one second semiconductor layer extending from the gate region to the spacer region.

11. The semiconductor structure according to claim 9, wherein the at least one first semiconductor layer is made of the same material as the at least one second semiconductor layer.

12. The semiconductor structure according to claim 9, wherein the S / D epitaxial growth defines a vertical portion extending above the upper surfaces of the at least one first semiconductor layer and the at least one second semiconductor layer from the BDI region.

13. The vertical portion of the S / D epitaxial growth connects the at least one first semiconductor layer of the S / D region to the at least one second semiconductor layer extending from the gate region to the spacer region, the semiconductor structure according to claim 9.

14. The S / D epitaxial growth completely surrounds the at least one first semiconductor layer, the semiconductor structure according to claim 9.

15. The adjacent devices in the first region indicating the first CPP include the S / D region where the at least one first semiconductor layer is not disposed in the S / D, and The adjacent devices in the second region indicating the second CPP include the S / D region where the at least one second semiconductor layer is disposed in the S / D, The semiconductor structure according to claim 9.

16. A metal contact extends below the upper surface of the vertical portion of the S / D epitaxial growth, the semiconductor structure according to claim 9.

17. Forming fins on a substrate, the fins comprising layers in which a first semiconductor material and a second semiconductor material are alternately arranged, forming fins, Forming a sacrificial dielectric on the fins in the gate region, Forming a sacrificial gate, Constructing a bottom dielectric isolation (BDI) region directly between the fins and the substrate, Forming a first spacer, Depositing an interlayer dielectric (ILD) on the source / drain (S / D) region, Selectively etching the first spacer, Recessing the fins to form internal spacers, Forming a source / drain (S / D) epitaxial growth, Forming a second spacer directly contacting the S / D epitaxial growth on the S / D epitaxial growth, Etching the first semiconductor material of the fins in the S / D region to selectively remove the internal spacers formed in the S / D region, Selectively etching the second spacer to expose the upper surface of the S / D epitaxial growth, and Forming the clad S / D epitaxy in the S / D region so that the clad S / D epitaxy surrounds the second semiconductor material of the fins including, method.

18. Before forming the clad S / D epitaxy, further comprising thinning the second semiconductor material of the fin in the S / D region. The method according to claim 17.

19. Removing the sacrificial dielectric of the gate region, and Forming a high-k metal gate (HKMG) around the second semiconductor material of the fin in the gate region The method according to claim 17, further comprising.

20. The method according to claim 17, wherein the S / D epitaxial growth defines a vertical portion extending above the upper surface of the second semiconductor material of the fin from the BDI region.

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