Image Sensor and Its Readout Circuit

Abstract

The present application provides an image sensor and its readout circuit (1). Among them, the readout circuit (1) of the image sensor consists of a lamp voltage circuit (10), a comparison circuit (20), a counter circuit (30), and an inversion control circuit (40). When switching the count, the inversion control circuit (40) is provided to control the counter circuit (30) to invert from the first digital code value to the second digital code value. Thus, in the second quantization period, the counter circuit (30) counts from the second digital code value to the third digital code value based on the second digital code value, realizing correlated double sampling, removing fixed pattern noise, improving the imaging quality, and in the readout circuit (1), there is no need to provide a buffer and an additional holding circuit, simplifying the circuit structure, reducing power consumption, and ensuring that the counter circuit operates in a high-frequency counting mode.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This application claims the priority of Chinese Patent Application No. 202310729218.X, filed with the China National Intellectual Property Administration on June 19, 2023, with the invention title "Image Sensor and Its Readout Circuit", the priority of Chinese Patent Application No. 202310732730.X, filed with the China National Intellectual Property Administration on June 19, 2023, with the invention title "Image Sensor and Its Readout Circuit", the priority of Chinese Patent Application No. 202321569685.2, filed with the China National Intellectual Property Administration on June 19, 2023, with the utility model title "Image Sensor and Its Readout Circuit", and the priority of Chinese Patent Application No. 202321569770.9, filed with the China National Intellectual Property Administration on June 19, 2023, with the utility model title "Image Sensor and Its Readout Circuit", and all of their contents are incorporated herein by reference.

[0002] This application belongs to the technical field of image sensors, and particularly relates to image sensors and their readout circuits.

Background Art

[0003] CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application values in fields such as machine vision, consumer electronics, high - definition monitoring, and medical imaging. An Analog - to - Digital Converter (ADC) is an important component of a CMOS image sensor readout circuit and is responsible for converting the analog signal output from a pixel into a digital signal. In CMOS image sensors, generally, column ADCs well - known as single - slope ADC (SS ADC), successive - approximation ADC (SAR ADC), and cyclic ADC (Cyclic ADC) are used.

[0004] The counter in a conventional SS ADC is usually an up-down counter capable of realizing the switching between up-counting / down-counting. As shown in FIG. 1, the N-bit counter circuit consists of counter units connected in cascade. When count_up is 1, the output signal QB at the inverted output terminal of the current stage serves as the clock signal for the next stage in the up-counting mode. When count_up is 0, the output signal Q at the non-inverted output terminal of the current stage serves as the clock signal for the next stage in the down-counting mode. After two counts are stopped, the final count result D <n-1:0>Store it in memory.

[0005] Since the operating frequency of count_clk is particularly high (usually several hundred MHz or even exceeding 1 GHz), in a conventional up-down counter, it is necessary to insert a 2:1 multiplexer and a driving buffer between the counter units of each stage, resulting in an increase in power consumption. At the same time, this structure faces the problem of maintaining the stability of the first quantization result during the switching of up / down counting, requiring an additional holding circuit, making the circuit layout more complex, increasing the parasitic capacitance and resistance of the wiring, further increasing the power consumption, and limiting the maximum operating frequency of the counter.

Summary of the Invention

Problems to be Solved by the Invention

[0006] An object of the present application is to provide a readout circuit for an image sensor for solving the problems of high power consumption and complex structure existing in a conventional up-down counter.

Means for Solving the Problems

[0007] In order to solve the above technical problems, the technical solutions used in the embodiments of the present application are as follows.

[0008] The first aspect of the embodiment of the present application is a ramp voltage circuit arranged to output a ramp voltage signal respectively in a first quantization period and a second quantization period of a pixel unit; a comparison circuit, the first input terminal of which is connected to the pixel unit, the second input terminal of which is connected to the ramp voltage circuit, and which is arranged to compare a reset signal or a pixel signal output from the pixel unit with the ramp voltage signal and output a reset pulse signal or a pixel pulse signal; A counter circuit connected to the comparison circuit, configured to count a first pulse signal during the first quantization period and store a first digital code value. During the second quantization period, the counter circuit counts a second pulse signal based on a second digital code value and stores it as a third digital code value. The first pulse signal and the second pulse signal are respectively a reset pulse signal and a pixel pulse signal with respect to each other. And the counter circuit, A readout circuit of an image sensor including: a counter circuit connected to the counter circuit, which is triggered by a mode selection signal between the first quantization period and the second quantization period to output an inversion control signal, and the counter circuit is triggered by the inversion control signal to invert and store the first digital code value to the second digital code value.

[0009] The second aspect of the embodiment of the present application is An image sensor including a pixel array including a plurality of pixel units arranged in an array, a control circuit, and a plurality of readout circuits of the image sensors as described above, Each readout circuit of the image sensors is connected to a plurality of pixel units arranged in a column respectively, and each readout circuit of the image sensors is further connected to the control circuit respectively.

Advantages of the Invention

[0010] Compared with the prior art, in the embodiment of the present application, the readout circuit of the image sensor is connected by a lamp voltage circuit, a comparison circuit, a counter circuit and an inversion control circuit. When switching the count, by installing the inversion control circuit, the counter circuit is controlled to invert the first digital code value to the second digital code value. In the second quantization period, the counter circuit counts to the third digital code value based on the second digital code value, realizing correlated double sampling, removing fixed pattern noise, improving the imaging quality. Also, in the readout circuit, there is no need to install a buffer and an additional holding circuit, simplifying the circuit structure, reducing power consumption, and ensuring that the counter circuit operates in a high-frequency counting mode, which has the beneficial effect.

[0011] Regarding the beneficial effects of the above second aspect, reference may be made to the relevant descriptions of the above first aspect, and it should be understood that the description will not be repeated here.

[0012] To more clearly explain the technical solutions in the embodiments of the present application, the drawings necessary for use in the following descriptions of the embodiments or the prior art will be briefly described. Obviously, the drawings in the following descriptions are only some embodiments of the present application, and those skilled in the art can also obtain other drawings based on these drawings without creative labor.

Brief Description of the Drawings

[0013]

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Mode for Carrying Out the Invention

[0014] To make the technical problems, technical solutions, and beneficial effects to be solved by the present application clearer, the present application will be described in more detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present application and do not limit the present application.

[0015] Also, the terms "first" and "second" are only for the purpose of explanation and should not be understood as indicating relative importance, implying, or implicitly indicating the number of the indicated technical features. Thus, the features limited by "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, "a plurality" means two or more unless otherwise specifically limited.

[0016] Embodiment 1 The first aspect of the embodiment of the present application provides a readout circuit of an image sensor. As shown in FIG. 2, the image sensor usually includes a control circuit 3, a pixel array 100, and a readout circuit 1, and may further include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array. The plurality of pixel units arranged in columns are commonly connected. The control circuit 3 selects the pixel units of each row by a row selection signal and sequentially outputs the pixel signals of each row to the readout circuit 1. The plurality of pixel units arranged in columns are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information based on the digital code value.

[0017] Here, the pixel unit usually includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. The photoelectric conversion element includes a photodiode PD, but is not limited thereto. For example, it may be a Pin-type photodiode PD. At the same time, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more. That is, the structure of the pixel unit can be selected correspondingly, and the specific structure is not limited. As shown in FIG. 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. The cathode of the photodiode PD is connected to the first end of the transfer transistor TX. The second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all connected to a floating diffusion node. The anode of the photodiode PD is grounded. The second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD. The second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL. The second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output a corresponding pixel signal.

[0018] A CMOS image sensor employing a column array readout circuit 1 faces the problem of fixed pattern noise (FPN) because, due to factors such as process and temperature, there is a certain degree of inconsistency in the threshold voltages of the transistors of the pixels in each column. In the case of the same light irradiation, the inconsistency deteriorates the column consistency of the pixel output signals. A correlated double sampling (CDS) operation can be performed using the 4T active pixel structure shown in FIG. 3, where the reset signal and the exposure signal of the pixel are read out respectively, and then the two are differentiated. Since the two signals contain the same fixed pattern noise (FPN), the FPN can be removed by the difference, and the imaging quality can be improved.

[0019] In a general CDS operation, in an SS ADC, two ramp signals are used to perform quantization twice on the reset signal and the exposure signal of the pixel respectively, and the counter circuit is controlled to perform downcount and upcount respectively during the two quantizations, so as to differentiate the analog voltage value output by the pixel in the digital domain. Therefore, the counter circuit in this structure is an up-down counter capable of switching between upcount and downcount. As shown in FIG. 1, the N-bit counter circuit consists of cascaded counter units. When count_up is 1, the output signal QB at the inverted output terminal of the current stage serves as the clock signal count_clk of the next stage in the upcount mode. When count_up is 0, the output signal Q at the non-inverted output terminal of the current stage serves as the clock signal count_clk of the next stage in the downcount mode. After the two counts stop, the final count result D <n-1:0>Store it in the memory.

[0020] Since the operating frequency of count_clk is particularly high (usually several hundred MHz or even exceeding 1 GHz), in a conventional up-down counter, it is necessary to insert a 2:1 multiplexer MUX1 and a driving buffer between the counter units of each stage, which increases power consumption. At the same time, this structure faces the problem of maintaining the stability of the first quantization result during the switching of up / down counting, requiring an additional holding circuit, making the circuit layout more complex, increasing the parasitic capacitance and resistance of the wiring, further increasing power consumption, and limiting the maximum operating frequency of the counter.

[0021] To solve the above technical problems, as shown in FIG. 4, in this embodiment, the readout circuit 1 of the image sensor includes a ramp voltage circuit 10 arranged to output a ramp voltage signal during the first quantization period and the second quantization period of the pixel unit respectively, a comparison circuit 20 having a first input terminal connected to the pixel unit, a second input terminal connected to the ramp voltage circuit 10, comparing the reset signal or the pixel signal output from the pixel unit with the ramp voltage signal, and arranged to output a reset pulse signal or a pixel pulse signal, a counter circuit 30 connected to the comparison circuit 20, configured to count the first pulse signal during the first quantization period, store the first digital code value, during the second quantization period, count the second pulse signal based on the second digital code value, and store it as the third digital code value, where one of the first pulse signal and the second pulse signal is a reset pulse signal and the other is a pixel pulse signal, an inversion control circuit 40 connected to the counter circuit 30, triggered by a mode selection signal mode_sel to output an inversion control signal trig_pulse between the first quantization period and the second quantization period, and the counter circuit 30 is triggered by the inversion control signal trig_pulse to invert and store the first digital code value into the second digital code value.

[0022] In this embodiment, the lamp voltage circuit 10 generates two lamp voltage signals during a first quantization period and a second quantization period, and the slopes and gains of the two lamp voltage signals may be the same or different.

[0023] The lamp voltage signals corresponding to the corresponding periods are output to the comparison circuit 20. The comparison circuit 20 receives the reset signal or the pixel signal of the pixel unit during the corresponding period. The reset signal and the pixel signal are respectively compared with the lamp voltage signal. The reset signal and the lamp voltage signal are compared within the first quantization period or the second quantization period to generate a reset pulse signal, and the pixel signal and the lamp voltage signal are compared within another quantization period to generate a pixel pulse signal.

[0024] The counter circuit 30 up - counts or down - counts the reset pulse signal or the pixel pulse signal within the first quantization period. When the first quantization is completed, it generates and stores the first digital code value after quantization. Here, the counter circuit 30 has a function of inverting the digital code value stored in itself based on the inversion control signal trig_pulse. For example, it inverts the first digital code value 0100 to generate 1011.

[0025] During the two quantization periods, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs the inversion control signal trig_pulse in response to a trigger. The counter circuit 30 inverts the first digital code value stored in itself based on the received inversion control signal trig_pulse to generate the second digital code value, which is used as the initial state of the second quantization, that is, the base value for the second count of the counter circuit 30.

[0026] At the initial time of the second quantization period, the mode selection signal mode_sel switches its state, the counter circuit 30 returns to the counting mode, quantizes the second pulse signal within the second quantization period, and the counter circuit 30 performs up - counting or down - counting based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, and the second quantization is completed.

[0027] Since the second quantization counts based on the inverse digital code value of the result of the first quantization, it is equivalent to calculating the difference value for two digital code values. For example, the result of the first quantization is a reset signal, which is inverted to -Vrst, and the quantization result of the second pixel signal is -Vrst + Vsig. Since the same FPN is included in the two signals, the FPN can be removed by taking the difference, and the imaging quality can be improved.

[0028] At the same time, by adopting reverse counting, the counter circuit 30 does not need to switch between up counting and down counting, nor does it need to install a separate holding circuit. Instead, only the corresponding reverse control circuit 40 needs to be added. Compared with the conventional counter circuit 30, the number of transistors can be reduced, the layout area can be further reduced, the wiring can be optimized, and the purpose of reducing power consumption can be achieved.

[0029] Here, the lamp voltage circuit 10 can use corresponding signal sources, voltage generation circuits, etc. For example, the lamp generator shown in FIG. 2, and the comparison circuit 20 can use structures such as comparators. Preferably, as shown in FIG. 2, the comparison circuit 20 includes a first capacitor, a second capacitor, and a comparator. The first end of the first capacitor is connected to the signal end of the lamp generation circuit. The first end of the second capacitor is used to input the reset signal or the pixel signal output from the pixel unit. The second end of the first capacitor is connected to the non-inverting input end of the comparator. The second end of the second capacitor is connected to the inverting input end of the comparator. When the lamp voltage signal is smaller than the corresponding reset signal or pixel signal, the comparator outputs a low level, and the counter circuit 30 starts counting. When the lamp voltage signal is larger than the corresponding reset signal or pixel signal, the comparator outputs a high level, and the counter circuit 30 stops counting. The counting result at this time is the digital code value after signal quantization.

[0030] The quantization order of the reset pulse signal and the pixel pulse signal can be set as needed. First, the reset pulse signal is quantized, and then the pixel pulse signal is quantized, or first the pixel pulse signal is quantized, and then the reset pulse signal is quantized. That is, preferably, the counter circuit 30 counts the reset pulse signal during the first quantization period, stores the first digital code value, and during the second quantization period, counts the pixel pulse signal based on the second digital code value and stores it as the third digital code value.

[0031] Alternatively, the counter circuit 30 is configured to count the pixel pulse signal during the first quantization period, store the first digital code value, and during the second quantization period, count the reset pulse signal based on the second digital code value and store it as the third digital code value.

[0032] When the reset pulse signal is quantized first and the pixel pulse signal is quantized later, during the first quantization period, the counter circuit 30 first quantizes the reset pulse signal, and the counter circuit 30 quantizes to generate a first digital code value, for example, Vrst. During the interval between the two quantization periods, the counter circuit 30 receives an inversion control signal trig_pulse, inverts the first digital code value corresponding to the reset pulse signal to the second digital code value, that is, generates -Vrst. During the second quantization period, the pixel pulse signal is quantized, and the counter circuit 30 counts based on the second digital code value to generate a third digital code value, that is, -Vrst + Vsig. Since the same FPN is included in the two signals, the FPN can be removed by taking the difference, and the imaging quality can be improved.

[0033] Alternatively, when the pixel pulse signal is quantized first and then the reset pulse signal is quantized, in the first quantization period, the counter circuit 30 quantizes the pixel pulse signal first, and the counter circuit 30 generates a first digital code value, for example, Vsig, after quantization. During the two quantization periods, the counter circuit 30 receives the inversion control signal trig_pulse, inverts the first digital code value corresponding to the pixel pulse signal to a second digital code value, that is, generates -Vsig. In the second quantization period, the counter circuit 30 quantizes the pixel pulse signal, and the counter circuit 30 counts based on the second digital code value to generate a third digital code value, that is, -Vsig + Vrst. Since similar FPN is included in the two signals, the FPN can be removed by taking the difference, and the imaging quality can be improved.

[0034] The counter circuit 30 can adopt structures such as corresponding D flip-flops DFFs and latches, and the inversion control circuit 40 can adopt signal sources, selection circuits, etc.

[0035] Compared with the prior art, in the embodiment of the present application, the readout circuit 1 of the image sensor is connected by the lamp voltage circuit 10, the comparison circuit 20, the counter circuit 30, and the inversion control circuit 40. When switching the count, the inversion control circuit 40 is provided to control the counter circuit 30 to invert the first digital code value to the second digital code value. In the second quantization period, the counter circuit 30 counts to the third digital code value based on the second digital code value, realizes correlated double sampling, removes fixed pattern noise, improves the imaging quality, and in the readout circuit 1, there is no need to provide a buffer and an additional holding circuit, simplifies the wiring structure, reduces power consumption, and can ensure that the counter circuit 30 operates in a high-frequency counting mode, which has beneficial effects.

[0036] Embodiment 2 Based on Embodiment 1, optimization and implementation are carried out. As shown in FIG. 5, preferably, the counter circuit 30 includes a first counter unit 31 to an nth counter unit. The inversion control circuit 40 includes n selection circuits. The first input terminal of the i-th selection circuit is used to input the inversion control signal trig_pulse. The second input terminal of the first selection circuit 41 is used to input the clock signal count_clk. The third input terminal of the first selection circuit 41 is used to input the output signal cmp_out of the comparator. The second input terminals of the second selection circuit 42 to the n-th selection circuit are connected to the output terminals of the counter units of the (i - 1)-th stage. The output terminal of the i-th selection circuit is connected to the input terminal of the counter unit of the i-th stage, where i = 1, 2, …, n. The i-th selection circuit outputs the inversion control signal trig_pulse or the clock signal count_clk according to the mode selection signal mode_sel. The first counter units 31 to the n-th counter units are configured to count the first pulse signal during the first quantization period, store their respective first count values of their own stages, and combine the count values of the counter units of each stage to generate a first digital code value. Between the first quantization period and the second quantization period, the first counter units 31 to the n-th counter units invert the first count value by the inversion control signal trig_pulse and store it as a second count value, and combine the count values of the counter units of each stage to generate a second digital code value. During the second quantization period, the first counter units 31 to the n-th counter units count the second pulse signal based on the second count value and store it as a third count value, and combine the count values of the counter units of each stage to generate a third digital code value.

[0037] In this embodiment, taking the example of quantizing the reset pulse signal for the first time and the pixel pulse signal for the second time, each selection circuit is connected to the front end of the counter unit, and based on the received mode selection signal mode_sel, outputs the corresponding signal at the signal input end to its own output end. Before quantization, each counter unit is reset. During the first quantization period, the pixel unit outputs a reset signal to the comparison circuit 20. The comparison circuit 20 compares the reset signal with the ramp voltage signal to generate a reset pulse signal, and the reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the mode selection signal mode_sel at the first level, triggers the communication between its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuits select the count value of the previous-stage counter unit and output it to the subsequent-stage counter unit. Each stage of the counter unit stores its own first count value, and combines the first count values of each stage of the counter unit to generate a first digital code value.

[0038] Between the first quantization period and the second quantization period, the mode selection signal mode_sel is switched to the second level. Each selection circuit outputs the inversion control signal trig_pulse at the first input end to the counter unit at the rear end. Each counter unit is switched to the inversion mode, inverts its internally stored first count value to the second count value, combines the second count values stored in each counter unit to generate a second digital code value. Then, the mode selection signal mode_sel is switched back to the first level again, the inversion control signal trig_pulse is similarly switched to the level state, and each counter unit is switched to the count mode.

[0039] During the second quantization period, each selection circuit is triggered to output the clock signal count_clk to the counter unit at the backend based on the received mode selection signal mode_sel of the first level. Each counter unit counts the second pulse signal based on the second count value and stores it as the third count value, combines the count values of the counter units at each stage to generate the third digital code value, reads it out correspondingly, thereby completing one complete quantization period. Finally, the third digital code value after the difference between the reset signal and the pixel signal of the pixel is obtained, fixed pattern noise is removed, and the imaging quality is improved.

[0040] Here, the selection circuit can select the corresponding switch structure, selector, etc., and the counter unit can select the structure of the corresponding flip-flop, latch, etc.

[0041] Embodiment 3 Based on Embodiment 2, optimization and implementation are carried out. In one selectable embodiment, as shown in FIG. 6, the first selection circuit 41 includes an AND gate AND1, a 2:1 multiplexer MUX1, and a first inverter U1. The first input terminal of the AND gate AND1 is used to input the clock signal count_clk, the second input terminal of the AND gate AND1 is used to input the output signal cmp_out of the comparator, the first input terminal of the 2:1 multiplexer MUX1 is used to input the inversion control signal trig_pulse, the output terminal of the AND gate AND1 is connected to the second input terminal of the 2:1 multiplexer MUX1, the output terminal of the 2:1 multiplexer MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 constitutes the output terminal of the first selection circuit 41. The second selection circuit 42 to the nth selection circuit each include a 2:1 multiplexer MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input terminal of the 2:1 multiplexer MUX1 is used to input the inversion control signal trig_pulse, the second input terminal of the 2:1 multiplexer MUX1 is used to input the numerical value output from the previous counter unit, the output terminal of the 2:1 multiplexer MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 is used to constitute the output terminal of the selection circuit.

[0042] The counter unit has a D flip-flop DFF and a second inverter U2. The clock signal count_clk terminal of the D flip-flop DFF of the counter unit at the i-th stage is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF of the counter unit at the i-th stage is connected to the input terminal of the second inverter U2 and the data input terminal of the D flip-flop DFF. The output terminal of the second inverter U2 is connected to the second input terminal of the i + 1-th selection circuit.

[0043] In this embodiment, the inverted output terminal of the D flip-flop DFF is connected to the first inverter U1, and the output terminal of the first inverter U1 is used as the count output terminal of the counter unit to realize up counting.

[0044] Referring to FIGS. 6 and 7, prior to quantization, at times t1 to t2, count_rst is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0045] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator is switched to the high level. After performing an AND operation between the high-level clock signal count_clk and the AND gate AND1, the clock signal count_clk is output to the second input terminal of the 2:1 multiplexer MUX1. At this time, the mode selection signal mode_sel is at the high level, the clock signal count_clk is strobed and output to the first inverter U1, and then output to the D flip-flop DFF. The D flip-flop DFF performs an up count according to the clock signal count_clk.

[0046] At time t4, the output of the comparison circuit 20 is inverted, the count stops, the first quantization ends, the count value of the first quantization result is stored in each D flip-flop DFF, and the first digital code value is generated by combining the first count values output from each second inverter U2.

[0047] At time t5, the mode selection signal mode_sel is switched to the low level, and each counter unit is switched to the inversion mode.

[0048] At time t6, the inversion control signal trig_pulse is switched to the low level, selected by the 2:1 multiplexer MUX1 and output to the first inverter U1, generating a rising edge at the clock input terminal of the D flip-flop DFF, inverting the count value of the first quantization result stored in the D flip-flop DFF, and using it as the initial state before the second quantization. The second digital code value is generated by combining the second count values output from each second inverter U2.

[0049] At time t7, the mode selection signal mode_sel is switched to the high level, the counter unit returns to the count mode, and at time t8, the inversion control signal trig_pulse is switched to the high level.

[0050] At time t9, the second quantization of the pixel pulse signal is performed from the initial state. At time t10, the output of the comparison circuit 20 is inverted and the count stops, and the second quantization ends. At times t11 to t12, the final quantization result is stored in the corresponding memory module and then read out. So far, one complete quantization cycle is completed, and finally the digital code value after the difference between the pixel reset signal and the exposure signal is obtained.

[0051] Embodiment 4 Based on Embodiment 2 for optimization and implementation, in another selectable embodiment, as shown in FIG. 8, the first selection circuit 41 includes an AND gate AND1, a 2:1 multiplexer MUX1, and a first inverter U1. The first input terminal of the AND gate AND1 is used to input the clock signal count_clk, the second input terminal of the AND gate AND1 is used to input the output signal cmp_out of the comparator, the first input terminal of the 2:1 multiplexer MUX1 is used to input the inversion control signal trig_pulse, the output terminal of the AND gate AND1 is connected to the second input terminal of the 2:1 multiplexer MUX1, the output terminal of the 2:1 multiplexer MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 constitutes the output terminal of the first selection circuit 41. The second selection circuit 42 to the nth selection circuit each include a 2:1 multiplexer MUX1 and a first inverter U1. In the second selection circuit 42 to the nth selection circuit, the first input terminal of the 2:1 multiplexer MUX1 is used to input the inversion control signal trig_pulse, the second input terminal of the 2:1 multiplexer MUX1 is used to input the value output from the previous counter unit, the output terminal of the 2:1 multiplexer MUX1 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 is used to constitute the output terminal of the selection circuit.

[0052] Preferably, the counter unit includes a D flip-flop DFF. The clock signal count_clk terminal of the D flip-flop DFF in the counter unit of the i-th stage is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop DFF in the counter unit of the i-th stage is connected to the data input terminal of the D flip-flop DFF. The non-inverted output terminal of the D flip-flop DFF is connected to the second input terminal of the (i + 1)-th selection circuit.

[0053] In this embodiment, the non-inverted output terminal of the D flip-flop DFF serves as the count output terminal of the counter unit to realize downcounting.

[0054] Referring to FIGS. 7 and 8, prior to quantization, at times t1 to t2, count_rst is switched to the low level, and the values in all D flip-flops DFF are reset (the outputs all become 0).

[0055] At time t3, the first quantization is performed. At this time, the output signal cmp_out of the comparator is switched to the high level. After the clock signal count_clk performs an AND operation with the AND gate AND1 at the high level, the clock signal count_clk is output to the second input terminal of the 2:1 multiplexer MUX1. At this time, the mode selection signal mode_sel is at the high level, the clock signal count_clk is strobed and output to the first inverter U1, and then output to the D flip-flop DFF. The D flip-flop DFF performs downcounting according to the clock signal count_clk.

[0056] At time t4, the output of the comparison circuit 20 is inverted, the counting stops, the first quantization ends, the count value of the first quantization result is stored in each D flip-flop DFF, and the first digital code value is generated by combining the first count values output from each D flip-flop DFF.

[0057] At time t5, the mode selection signal mode_sel is switched to the low level, and each counter unit is switched to the inversion mode.

[0058] At time t6, the inversion control signal trig_pulse is switched to the low level, selected by the 2:1 multiplexer MUX1 and output to the first inverter U1, generating a rising edge at the clock input terminal of the D flip-flop DFF, inverting the count value of the first quantization result stored in the D flip-flop DFF, setting it as the initial state before the second quantization, and combining the second count values output from each D flip-flop DFF to generate a second digital code value.

[0059] At time t7, the mode selection signal mode_sel is switched to the high level, the counter unit returns to the counting mode, and at time t8, the inversion control signal trig_pulse is switched to the high level.

[0060] At time t9, the second quantization of the pixel pulse signal is performed from the initial state. At time t10, the output of the comparison circuit 20 is inverted and the counting stops, and the second quantization ends. At times t11 to t12, the final quantization result is stored in the corresponding memory module and then read out. Up to this point, one complete quantization cycle is completed, and finally, the digital code value after the difference between the pixel reset signal and the exposure signal is obtained.

[0061] Embodiment 5 Based on Embodiment 1, optimization and implementation are carried out. As shown in FIG. 9, preferably, the readout circuit 1 of the image sensor includes a memory circuit 50. The memory circuit 50 is connected to the counter circuit 30, stores the third digital code value, and is triggered and read out by a read control signal.

[0062] In this embodiment, after the second quantization is completed, the counter circuit 30 obtains a third digital code value, which is the difference value between the digital code values corresponding to the reset pulse signal and the pixel pulse signal. As shown in FIG. 7, at times t11 to t12, the write signal output to the memory circuit 50 is enabled to be at a high level, and the final quantization result is written and stored in the memory circuit 50, and then read out. So far, one complete quantization cycle is completed, and finally, the digital code value after the difference between the reset signal and the exposure signal of the pixel is obtained.

[0063] Here, the memory circuit 50 can select a single memory Mem or a plurality of memories Mem. When a single memory Mem is adopted, a plurality of memory partitions are provided in the memory Mem, and each memory partition stores one third count value respectively. The plurality of third count values are combined to generate a third digital code value. When a plurality of memories Mem are adopted, each memory Mem stores one third count value respectively.

[0064] In one selectable embodiment, as shown in FIG. 10, the memory circuit 50 includes n memories Mem. The n memories Mem are respectively connected to one counter unit and store the count values of the corresponding bit numbers of the third digital code value.

[0065] In this embodiment, the memory circuit 50 is constituted by a plurality of memories Mem, and each stores a third count value of 1 bit. Here, in order to simplify the structure, preferably, the memory of the memory Mem is 1 bit.

[0066] Embodiment 6 All Direction Auto Focus (ADAF) plays an important role in the image sensor. As shown in FIG. 11, in the pixel array, four pixels are arranged in a 2×2 pattern, sharing one floating diffusion node and source follower transistor. During readout, first txa and txc are turned on to read out the two pixel signals on the right and obtain the right phase information, and then txb and txd are turned on to read out the two pixel signals on the left and obtain the left phase information. Based on these two phase information, the phase difference can be calculated to perform auto focus.

[0067] Next, the dynamic range is an important factor in the imaging quality of the image sensor. Dual Conversion Gain (DCG) is applied to the pixel circuit of the image sensor. Under low illuminance conditions, a small integration capacitance is used to improve the conversion gain and sensitivity. Under high illuminance conditions, a large integration capacitance is used to improve the stored charge and reduce the conversion gain to improve the dynamic range.

[0068] Correlated Double Sampling (CDS) technology can remove the thermal noise and some fixed pattern noise caused by pixel reset, and can significantly improve the noise performance of the image sensor. In CDS technology, it is necessary to separately read out the reset signal and exposure signal of the pixel and take the difference between the two. Therefore, when using CDS technology in a four-phase pixel structure or dual conversion gain technology, one column of pixels needs to correspond to two sets of readout circuits. One set quantizes the reset signal and the right pixel signal or high gain pulse signal, and the other set quantizes the reset signal and the left pixel signal or low gain pulse signal. In this way, the complexity of the image sensor structure and power consumption increase.

[0069] Here, a pixel unit usually includes at least one sub-pixel. For example, the pixel unit shown in FIG. 11 includes four sub-pixels arranged in at least a 2×2 array. At least two sub-pixels form a pixel group and are controlled to output a reset signal or pixel signals simultaneously. The sub-pixels in the pixel unit may be grouped into one pixel group by two, or may be grouped in other combination methods, and the specific grouping method is not limited.

[0070] When the pixel unit includes four sub-pixels in at least a 2×2 array, the four sub-pixels share one floating diffusion node FD and a source follower transistor. During reading, first, txa and txc are turned on to read the two pixel signals on the right and obtain the right phase information, and then txb and txd are turned on to read the two pixel signals on the left and obtain the left phase information. (Alternatively, first, txa and txb are turned on to read the two pixel signals on the upper side and obtain the upper phase information, and then txc and txd are turned on to read the two pixel signals on the lower side and obtain the lower phase information.) Based on these two phase information, the phase difference can be calculated to perform autofocus.

[0071] In order to simplify the structure of the image sensor and its reading circuit 1 and reduce power consumption, in this embodiment, the first quantization period is a reset sampling period, the second quantization period is the first exposure sampling period, the reset sampling period includes at least one, and the pixel signals include two. The lamp voltage circuit 10 is arranged to output a lamp voltage signal for each sampling period. The comparison circuit 20 is further arranged to compare at least one reset signal or two pixel signals output from the pixel unit with the lamp voltage signal and output at least one reset pulse signal and two pixel pulse signals at intervals. The counter circuit 30 is further configured to count at least one reset pulse signal during at least one reset sampling period, store it as at least one first digital code value, count a first pixel pulse signal based on a second digital code value during a first exposure sampling period, store it as a third digital code value, count a second pixel pulse signal based on a fourth digital code value during a second exposure sampling period, and store it as a fifth digital code value. The inversion control circuit 40 is connected to the counter circuit 30 and the memory circuit 50, and is triggered by a mode selection signal mode_sel to output an inversion control signal trig_pulse to the counter circuit 30 before each exposure sampling period, and is triggered so that the counter circuit 30 inverts the first digital code value in the memory to generate a second digital code value or a fourth digital code value. As shown in FIG. 12, the readout circuit of the image sensor further includes a memory circuit 50. The memory circuit 50 is connected to the counter circuit 30, stores at least one first digital code value, and is triggered by a write-back control signal rewrite_en to write back one of the at least one first digital code values to the counter circuit 30 before the second exposure sampling period.

[0072] In this embodiment, the lamp voltage signals output by the lamp voltage circuit 10 during the reset sampling period and the exposure sampling period may be the same or different, and the specific magnitude is set based on the voltage amplitudes of the reset signal and the pixel signal.

[0073] Here, the reset signal may include one or more. Correspondingly, the reset sampling period may be one or more. In the case of one reset signal, during the reset sampling period, the comparison circuit 20 compares the reset signal with the reset ramp voltage signal to generate a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts up or down the reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, indicating that the quantization of the reset signal is complete. The counter circuit 30 counts to generate a first digital code value, stores it in itself, and writes it to the memory circuit 50.

[0074] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs an inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored first digital code value to a second digital code value, and sets it as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal to generate a first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction as the first pixel pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops operating, indicating that the quantization of the first pixel pulse signal is complete. The counter circuit 30 counts to generate a third digital code value. The third digital code value is the difference value between the digital code value corresponding to the first pixel signal and the reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0075] Thereafter, the counter circuit 30 is reset. Before the second exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored first digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back first digital code value, and generates a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value, and the fourth digital code value is set to the initial state of the second exposure sampling. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the second pixel signal during the second exposure sampling period, the comparison circuit 20 compares the second pixel signal with the pixel lamp voltage signal, generates a second pixel pulse signal, the second pixel pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction on the second pixel pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the second pixel pulse signal is completed, the counter circuit 30 counts to generate a fifth digital code value, and the fifth digital code value is the difference value between the second pixel signal and the digital code value corresponding to the reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0076] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the memory circuit 50 and read out to the corresponding control circuit 3 under the control of the read control signal. The control circuit 3 determines the image information based on the third digital code value and the fifth digital code value.

[0077] When the reset signal includes two reset signals corresponding to two pixel signals, during the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal to generate a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts up or down the first reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, indicating that the quantization of the first reset signal is completed. The counter circuit 30 then counts to generate a first digital code value for the first one and writes it into the memory circuit 50.

[0078] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal to generate a second reset pulse signal. The second reset pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction as the second reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, indicating that the quantization of the second reset signal is completed. The counter circuit 30 then counts to generate a first digital code value for the second one and stores it internally.

[0079] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored second first digital code value to the second digital code value, and sets it as the initial state of the first exposure sampling period. After that, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel lamp voltage signal to generate the first pixel pulse signal. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the first pixel pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops operating, and the quantization of the first pixel pulse signal is completed. The counter circuit 30 counts to generate the third digital code value. The third digital code value is the difference value between the first pixel signal and the digital code value corresponding to the second reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0080] Thereafter, the counter circuit 30 is reset. Before the second exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored first first digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back first first digital code value to generate a fourth digital code value, and sets the fourth digital code value as the initial state of the second exposure sampling. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the second pixel signal during the second exposure sampling period, the comparison circuit 20 compares the second pixel signal with the pixel lamp voltage signal to generate a second pixel pulse signal, the second pixel pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction on the second pixel pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the second pixel pulse signal is completed, the counter circuit 30 counts to generate a fifth digital code value, and the fifth digital code value is the difference value between the digital code values corresponding to the second pixel signal and the second reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0081] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the memory circuit 50 and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information based on the third digital code value and the fifth digital code value.

[0082] During the entire quantization process, it is necessary to quantize the reset signal only once. For the pixel signals read twice, in order to time-division multiplex one set of counter circuits 30, the quantization of two pixel pulse signals can be completed with only one set of read circuits 1, simplifying the structure of the image sensor, reducing power consumption, determining image information based on the quantization results of the two pixel pulse signals, realizing autofocus or high dynamic range, and improving the imaging quality.

[0083] The counter circuit 30, the inversion control circuit 40, and the memory circuit 50 can be specifically determined based on the corresponding reset signal, the type of pixel signal, and the input / output logic.

[0084] Also, the path through which the memory circuit 50 writes back may directly output to the counter circuit 30 or indirectly output to the counter circuit 30 via the inversion control circuit 40, and the specific write-back method is not limited.

[0085] Compared with the prior art, in the embodiment of the present application, the above image sensor circuit quantizes and stores the reset signal into the first digital code value during the reset sampling period, and during the first exposure sampling period, quantizes the first pixel pulse signal based on the second digital code value, thereby realizing correlated double sampling. During the second exposure sampling period, quantizes the second pixel pulse signal based on the fourth digital code value, thereby realizing correlated double sampling. The second digital code value and the fourth digital code value are inversion values corresponding to the first digital code value. In the whole quantization process, it is necessary to quantize the reset signal only once. The pixel signals read twice are time-division multiplexed by one set of counter circuits 30, so that the quantization of two pixel pulse signals can be completed by only one set of readout circuits 1, simplifying the structure of the image sensor, reducing power consumption, determining image information based on the quantization results of the two pixel pulse signals, realizing autofocus or high dynamic range, and having the beneficial effect of improving the imaging quality.

[0086] Embodiment 7 Based on Embodiment 6 for optimization and implementation, in one selectable embodiment, the image sensor includes a pixel array 100. Each pixel array 100 includes pixel units arranged in an array. The readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in at least 2×2, among which at least two sub-pixels form a pixel group and are controlled to output the reset signal or the pixel signal simultaneously. At least one reset signal is a reset signal generated when pixel units are reset simultaneously, The first pixel pulse signal and the second pixel pulse signal are each one of a corresponding pixel group pulse signal in the simultaneous exposure of a pixel group and an image pulse signal corresponding to the simultaneous exposure of sub-pixels in a pixel unit.

[0087] In this embodiment, the readout circuit 1 is applied to the ADAF technology. Four sub-pixels share one floating diffusion node and a source follower transistor. During readout, first, the pixel group is turned on, and the pixel group signal Vsigl of at least two sub-pixels in the pixel group is read out. For example, the two pixel signals on the right side are read out to obtain right phase information.

[0088] Then, all the sub-pixels of the pixel unit are turned on, and the image signal Vsig corresponding to the pixel unit is read out. Accordingly, the comparison circuit 20 obtains all phase information.

[0089] Specifically, as shown in FIG. 13, during the reset sampling period, the comparison circuit 20 compares the reset signal with the reset ramp voltage signal to generate a reset pulse signal. The reset pulse signal is input to the counter circuit 30. The counter circuit 30 up-counts or down-counts the reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the reset signal is completed, the counter circuit 30 counts to generate a first digital code value, stores it in itself, and writes it to the storage circuit 50.

[0090] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored first digital code value to the second digital code value, and sets it as the initial state of the first exposure sampling period. Thereafter, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl with the pixel ramp voltage signal to generate a pixel group pulse signal. The pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the pixel group pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops operating, and the quantization of the pixel group pulse signal is completed. The counter circuit 30 counts to generate a third digital code value. The third digital code value is the difference value between the digital code value corresponding to the pixel group signal Vsigl and the reset signal, that is, Vsigr - Vrst, which realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0091] Thereafter, the counter circuit 30 is reset. Before the second exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored first digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back first digital code value, and generates a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value, and the fourth digital code value is set to the initial state of the second exposure sampling. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the image signal Vsig during the second exposure sampling period, the comparison circuit 20 compares the image signal Vsig with the pixel lamp voltage signal, generates an image pulse signal, the image pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction with respect to the image pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the image pulse signal is completed, the counter circuit 30 counts to generate a fifth digital code value, and the fifth digital code value is the difference value between the digital code value corresponding to the second pixel signal and the reset signal, that is, Vsigr + Vsigl - Vrst, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0092] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the memory circuit 50, read out by the corresponding control circuit 3 from the read control signal, and the control circuit 3 determines the left and right pixel information or the up and down pixel information based on the fifth digital code value and the third digital code value, obtains the phase difference from the pixel information, performs autofocus, and can improve the user experience.

[0093] Also, in the quantization process, it is necessary to quantize only one reset signal. The pixel signals read twice time-division multiplex one set of counter circuits 30, simplify the structure of the image sensor, reduce power consumption, determine image information based on the quantization results of two pixel pulse signals, achieve autofocus, and improve imaging quality.

[0094] Embodiment 8 Based on Embodiment 6, optimization and implementation are performed. In other alternative embodiments, the reset sampling period includes a continuous first reset sampling period and a second reset sampling period. At least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal and the second pixel pulse signal are each one of a high-gain image pulse signal and a low-gain image pulse signal. In the first reset sampling period, the counter circuit 30 counts one of the reset pulse signals and generates one first digital code value. In the second reset sampling period, the counter circuit 30 counts another reset pulse signal and generates another first digital code value. In the first exposure sampling period, the counter circuit 30 counts the first pixel pulse signal based on the second digital code value and stores it as a third digital code value. In the second exposure sampling period, the counter circuit 30 counts the second pixel pulse signal based on the fourth digital code value and stores it as a fifth digital code value.

[0095] In this embodiment, the readout circuit 1 is applied to the HDR technology. The pixel unit or sub-pixel includes different integration capacitances, and switches between different integration capacitances at different illuminances. Here, under low illuminance conditions, a small integration capacitance is used to improve the conversion gain and sensitivity. Under high illuminance conditions, a large integration capacitance is used to improve the stored charge and reduce the conversion gain to improve the dynamic range.

[0096] Correspondingly, the reset signal includes a low-gain reset signal lcg_rst and a high-gain reset signal hcg_rst. As shown in FIG. 14, during the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal to generate a first reset pulse signal. The first reset pulse signal is input to the counter circuit 30. The counter circuit 30 counts up or down the first reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, indicating that the quantization of the first reset signal is completed. The counter circuit 30 then counts to generate a first digital code value and writes it to the memory circuit 50.

[0097] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal to generate a second reset pulse signal and outputs it to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction as the second reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, indicating that the quantization of the second reset signal is completed. The counter circuit 30 then counts to generate a second first digital code value and stores it internally.

[0098] Here, one of the second reset signal and the first reset signal is the high-gain reset signal hcg_rst, and the other is the low-gain reset signal lcg_rst. Correspondingly, one of the second reset pulse signal and the first reset pulse signal is the high-gain reset pulse signal, and the other is the low-gain reset pulse signal.

[0099] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30, the counter circuit 30 switches to the inversion mode, and inverts the stored second first digital code value to the second digital code value, taking it as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel lamp voltage signal. The first pixel signal and the second reset signal are the image signal and the reset signal with the same gain. For example, they are the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst respectively. By comparing, the first pixel pulse signal is generated. The first pixel pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the first pixel pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops operating, the quantization of the first pixel pulse signal is completed, the counter circuit 30 counts to generate the third digital code value, and the third digital code value is the difference value of the digital code values corresponding to the first pixel signal and the second reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0100] After that, the counter circuit 30 is reset. Before the second exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the first rewritten first digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the first rewritten first digital code value, generates a fourth digital code value, and sets the fourth digital code value as the initial state of the second exposure sampling. Then, the counter circuit 30 returns to the count mode, quantizes the second pixel signal during the second exposure sampling period, and the second pixel signal and the first reset signal are image signals and reset signals with the same gain. For example, they are a low-gain image signal lcg_sig and a low-gain reset signal lcg_rst respectively. The comparison circuit 20 compares the second pixel signal with the pixel lamp voltage signal, generates a second pixel pulse signal, the second pixel pulse signal is output to the counter circuit 30, the counter circuit 30 performs a count operation in the same direction on the second pixel pulse signal based on the fourth digital code value, and when the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the count operation, the quantization of the second pixel pulse signal is completed, the counter circuit 30 counts to generate a fifth digital code value, and the fifth digital code value is the difference value of the digital code values corresponding to the second pixel signal and the first reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0101] At the same time, the third digital code value and the fifth digital code value obtained by the two quantizations are finally stored in the memory circuit 50 and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information based on the third digital code value and the fifth digital code value.

[0102] In the whole quantization process, it is necessary to quantize the reset signal only once. Since the pixel signals read twice are time-division multiplexed by one set of counter circuits 30, the quantization of two pixel pulse signals can be completed by only one set of readout circuits 1, simplifying the structure of the image sensor, reducing power consumption, determining image information based on the quantization results of the two pixel pulse signals, realizing a high dynamic range, and improving the imaging quality.

[0103] Corresponding to the signal input / output logic of Embodiment 7 and Embodiment 8 above, preferably, as shown in FIG. 15, the counter circuit 30 includes a first counter unit 31 to an nth counter unit. The memory circuit 50 includes n memory units, for example, a first memory unit 51, a second memory unit 52, etc. The memory units are respectively connected to the counter unit and the inversion control circuit 40. Each memory unit includes a first memory Mem1, a second memory Mem2, and a NAND gate NOR1. The input ends of the first memory Mem1 and the second memory Mem2 are respectively connected to the counter unit. The output end of the first memory Mem1 is connected to the first input end of the NAND gate NOR1. The second input end of the NAND gate NOR1 is used to input a write-back control signal rewrite_en. The NAND gate NOR1 constitutes the output end of the memory unit. The first memory Mem1 is configured to store the corresponding 1-bit count value of at least one of the first digital code values. The first memory Mem1 and the second memory Mem2 respectively store the corresponding 1-bit count value of one of the third digital code value and the fifth digital code value.

[0104] When applied to the readout circuit 1 of Embodiment 7, as shown in FIGS. 12, 13, and 15, during the reset sampling period, the comparison circuit 20 compares the reset signal and the reset ramp voltage signal to generate a reset pulse signal. The reset pulse signal is input to the counter circuit 30, and the reset pulse signal is output to the first counter unit 31 to the nth counter unit via the inversion control circuit 40. The n counter units count up or down the reset pulse signal. When the output of the comparison circuit 20 is inverted, the n counter units stop counting, the quantization of the reset signal is completed, the n counter units count to generate and store the bit count values of the first digital code value, and the bit count values of the first digital code value are respectively stored in the first memory Mem1.

[0105] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel, the inversion control circuit 40 outputs the inversion control signal trig_pulse to the counter circuit 30, the n counter units are switched to the inversion mode, and the stored first digital code value is inverted to the second digital code value as the initial state of the first exposure sampling period. Thereafter, the n counter units return to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the pixel group signal Vsigl and the pixel ramp voltage signal to generate a pixel group pulse signal. The pixel group pulse signal is output to the n counter units via the inversion control circuit 40. The n counter units perform a counting operation in the same direction with respect to the pixel group pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the n counter units stop the counting operation, the quantization of the pixel group pulse signal is completed, the n counter units count to generate the third digital code value, and the third digital code value is the difference value between the digital code value corresponding to the pixel group signal Vsigl and the reset signal, that is, Vsigr - Vrst, realizing correlated double sampling, reducing the influence of noise, improving the imaging quality, and storing the n-bit count values in the third digital code value in the n second memories Mem respectively.

[0106] Thereafter, the n counter units are reset. Before the second exposure sampling period, the first memory Mem1 receives a write-back control signal rewrite_en, and writes back the stored first digital code value to the counter circuit 30 via the NAND gate NOR1 and the inversion control circuit 40. At the same time, the n counter units receive an inversion control signal trig_pulse, invert the written-back first digital code value, and generate a fourth digital code value. At this time, the fourth digital code value is equal to the second digital code value, and the fourth digital code value is set to the initial state of the second exposure sampling. Thereafter, the n counter units return to the counting mode, quantize the image signal Vsig during the second exposure sampling period. The comparison circuit 20 compares the image signal Vsig with the pixel lamp voltage signal to generate an image pulse signal. The image pulse signal is output to the n counter units. The n counter units perform a counting operation in the same direction with respect to the image pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, and the quantization of the image pulse signal is completed. The counter circuit 30 counts to generate a fifth digital code value. The count value of the n-bit coin of the fifth digital code value is stored in the first memory Mem1. Here, the fifth digital code value is the difference value between the digital code value corresponding to the second pixel signal and the reset signal, that is, Vsigr + Vsigl - Vrst, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0107] When applied to the readout circuit 1 of Embodiment 8, as shown in FIGS. 11, 13, and 14, during the first reset sampling period, the comparison circuit 20 compares the first reset signal with the reset ramp voltage signal to generate a first reset pulse signal. The first reset pulse signal corresponds to the pulse signal of the high-gain reset signal hcg_rst or the low-gain reset signal lcg_rst. The first reset pulse signal is input to n counter units via the inversion control circuit 40. The n counter units perform an up-count or down-count on the first reset pulse signal. When the output of the comparison circuit 20 is inverted, the n counter units stop counting, the quantization of the first reset signal is completed, the n counter units count to generate a count value, and the combination of the n count values generates a first digital code value of the first one and writes it to the n first memories Mem1.

[0108] Before the second reset sampling period, the n counter units are reset. During the second reset sampling period, the comparison circuit 20 compares the second reset signal with the reset ramp voltage signal. One of the second reset signal and the first reset signal is the high-gain reset signal hcg_rst, and the other is the low-gain reset signal lcg_rst. A second reset pulse signal is generated. One of the second reset pulse signal and the first reset pulse signal is the high-gain reset pulse signal, and the other is the low-gain reset pulse signal. The second reset pulse signal is output to the n counter units via the inversion control circuit 40. The n counter units perform a count operation in the same direction with respect to the second reset pulse signal. When the output of the comparison circuit 20 is inverted, the n counter units stop counting, the quantization of the second reset signal is completed, the n counter units count to generate n count values, and the combination of the n count values generates a second first digital code value and stores it inside the n counter units themselves.

[0109] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs the inversion control signal trig_pulse to n counter units. The n counter units switch to the inversion mode, invert the stored count values respectively, and the combination of the inverted count values is generated as the second digital code value, which serves as the initial state of the first exposure sampling period. Then, the n counter units return to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the first pixel signal with the pixel ramp voltage signal, and generates the first pixel pulse signal after comparison. The first pixel pulse signal is output to the n counter units via the inversion control circuit 40. The n counter units perform a counting operation in the same direction as the first pixel pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the n counter units stop operating, the quantization of the first pixel pulse signal is completed, the n counter units count to generate the third digital code value, and each bit count value of the third digital code value is stored in each second memory Mem2 respectively. Here, the third digital code value is the difference value between the digital code value corresponding to the first pixel signal and the second reset signal, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0110] After that, the n counter units are reset. Before the second exposure sampling period, each first memory Mem1 receives a write-back control signal rewrite_en, writes back the stored first first digital code value to the n counter units, and the n counter units receive an inversion control signal trig_pulse, invert the written-back first first digital code value to generate a fourth digital code value. The fourth digital code value serves as the initial state for the second exposure sampling. Then, the n counter units return to the counting mode, quantize the second pixel signal during the second exposure sampling period. The comparison circuit 20 compares the second pixel signal with the pixel lamp voltage signal to generate a second pixel pulse signal. The second pixel pulse signal is output to the n counter units. The n counter units perform a counting operation in the same direction with respect to the second pixel pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the n counter units stop the counting operation, and the quantization of the second pixel pulse signal is completed. The n counter units count to generate a fifth digital code value. The fifth digital code value is the difference value between the second pixel signal and the digital code value corresponding to the first reset signal. The n-bit count values of the fifth digital code value are respectively stored in the n first memories Mem1, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0111] Embodiment 9 Based on Embodiment 6, optimization and implementation are carried out. In another alternative embodiment, the image sensor includes a pixel array 100. Each pixel array 100 includes pixel units arranged in an array. The readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column. The pixel unit includes at least four sub-pixels arranged in at least 2×2. Among them, at least two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes consecutive first and second reset sampling periods, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of a pixel group in the low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in a pixel unit. The second exposure sampling period includes consecutive third and fourth exposure sampling periods. The first digital code value includes a first sub-digital code value and a second sub-digital code value. The counter circuit 30 counts the low-gain reset pulse signal during the first reset sampling period and generates a first sub-digital code value. During the second reset sampling period, it counts the high-gain reset pulse signal and generates a second sub-digital code value. During the first exposure sampling period, it counts the high-gain image pulse signal based on the second digital code value and stores it as a third digital code value. The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value. During the third exposure sampling period, it counts the low-gain pixel group pulse signal based on the fourth digital code value and stores it as a fifth sub-digital code value. During the fourth exposure sampling period, it is configured to count the low-gain image pulse signal based on the fourth digital code value and store it as a sixth sub-digital code value. The memory circuit 50 is connected to the counter circuit 30, stores the first sub-digital code value, and is configured to be triggered by a write-back control signal rewrite_en before the third and fourth exposure sampling periods to write back the first sub-digital code value to the counter circuit 30. The inversion control circuit 40 is connected to the counter circuit 30 and the memory circuit 50, and is triggered by an inversion control signal trig_pulse before each exposure sampling period. The counter circuit 30 is controlled to invert the first sub-digital code value of the memory to generate a fourth digital code value and invert the second sub-digital code value to generate a second digital code value.

[0112] In this embodiment, the readout circuit 1 is applied to realize autofocus with a low conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain image pulse signal. The second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0113] Referring to FIG. 16, in the first reset sampling period, the comparison circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal to generate a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts up or down the low-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the low-gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate a first sub-digital code value and writes it into the memory circuit 50.

[0114] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst and the reset ramp voltage signal to generate a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it internally.

[0115] Before the first exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs an inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored second sub-digital code value to a second digital code value, and sets it as the initial state of the first exposure sampling period. Then, the counter circuit 30 returns to the counting mode. During the first exposure sampling period, the comparison circuit 20 compares the high-gain image signal hcg_sig and the pixel ramp voltage signal, and generates a high-gain image pulse signal by comparison. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain image pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops operating, the quantization of the high-gain image pulse signal is completed, and the counter circuit 30 counts to generate a third digital code value, which is the difference value between the digital code values corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0116] Thereafter, the counter circuit 30 is reset. Before the third exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored first sub-digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back first sub-digital code value to generate a fourth digital code value, and sets the fourth digital code value as the initial state of the third exposure sampling period. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the low-gain pixel group signal lcg_sign during the third exposure sampling period, the comparison circuit 20 compares the low-gain pixel group signal lcg_sign with the pixel ramp voltage signal to generate a low-gain pixel group pulse signal, the low-gain pixel group pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction on the low-gain pixel group pulse signal based on the fourth digital code value, and when the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the low-gain pixel group pulse signal is completed, the counter circuit 30 counts to generate a fifth sub-digital code value which is the difference value between the digital code values corresponding to the low-gain pixel group signal lcg_rst and the low-gain reset signal lcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0117] After that, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, rewrites the stored first sub-digital code value back to the counter circuit 30 again, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the rewritten first sub-digital code value, generates a fourth digital code value, sets the fourth digital code value as the initial state of the fourth exposure sampling period. Then, the counter circuit 30 returns to the counting mode, quantizes the low-gain image signal lcg_sig during the fourth exposure sampling period. The comparison circuit 20 compares the low-gain image signal lcg_sig with the pixel lamp voltage signal to generate a low-gain image pulse signal. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the low-gain image pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a sixth sub-digital code value, which is the difference value between the digital code values corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0118] At the same time, the third digital code value, the fifth sub-digital code value, and the sixth sub-digital code value obtained by three quantizations are finally stored in the memory circuit 50 and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information based on the third digital code value, the fifth sub-digital code value, and the sixth sub-digital code value, realizes autofocus in the low conversion gain mode, and improves the imaging quality and user experience.

[0119] Embodiment 10 Based on Embodiment 6 for optimization and implementation, in another selectable embodiment, the image sensor includes a pixel array 100, each pixel array 100 includes pixel units arranged in an array, the readout circuit 1 of each image sensor is connected to a plurality of pixel units arranged in a column respectively, the pixel unit includes four sub-pixels arranged in 2×2, among which, two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes consecutive first and second reset sampling periods, and at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The second pixel pulse signal includes a low-gain image pulse signal. The first exposure sampling period includes consecutive third and fourth exposure sampling periods. The first digital code value includes a first sub-digital code value and a second sub-digital code value. The counter circuit 30 counts the low-gain reset pulse signal in the first reset sampling period and generates the first sub-digital code value. In the second reset sampling period, the high-gain reset pulse signal is counted to generate the second sub-digital code value. The third digital code value includes a third sub-digital code value and a fourth sub-digital code value. In the third exposure sampling period, the high-gain pixel group pulse signal is counted based on the second digital code value and stored as the third sub-digital code value. In the fourth exposure sampling period, the high-gain image pulse signal is counted based on the second digital code value and stored as the fourth sub-digital code value. During the second exposure sampling period, it is configured to count a low-gain image pulse signal based on the fourth digital code value and store it as the fifth digital code value. The memory circuit 50 is connected to the counter circuit 30, stores the first sub-digital code value and the second sub-digital code value, and is triggered by a write-back control signal rewrite_en before the fourth exposure sampling period and the second exposure sampling period to write the second sub-digital code value and the first sub-digital code value back to the counter circuit 30. The inversion control circuit 40 is connected to the counter circuit 30 and the memory circuit 50, and is triggered by an inversion control signal trig_pulse before each exposure sampling period to control the counter circuit 30 to invert the second sub-digital code value of the memory to generate a second digital code value and invert the first sub-digital code value to generate a fourth digital code value.

[0120] In this embodiment, the readout circuit 1 is applied to realize autofocus with a high conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset signal lcg_rst. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of a pixel group in the high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of sub-pixels in a pixel unit. The second pixel pulse signal includes a low-gain image pulse signal.

[0121] Referring to FIG. 17, during the first reset sampling period, the comparison circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal to generate a low-gain reset pulse signal and input it to the counter circuit 30. The counter circuit 30 up-counts or down-counts the low-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the low-gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate a first sub-digital code value and writes it to the memory circuit 50.

[0122] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst and the reset ramp voltage signal to generate a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it internally.

[0123] Before the third exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs an inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored second sub-digital code value to a second digital code value, and sets it as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the signal hcg_sigl of the high-gain pixel group during the third exposure sampling period. The comparison circuit 20 compares the signal hcg_sigl of the high-gain pixel group and the pixel ramp voltage signal to generate a high-gain pixel group pulse signal. The high-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain pixel group pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the high-gain pixel group pulse signal is completed, the counter circuit 30 counts to generate a third sub-digital code value, and the third sub-digital code value is the difference value between the digital code value corresponding to the high-gain pixel group signal hcg_sigl and the high-gain reset signal hcg_rst, realizing correlated double sampling, reducing the influence of noise, and improving the imaging quality.

[0124] Thereafter, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, rewrites the stored second sub-digital code value back to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the rewritten second sub-digital code value to generate a second digital code value, sets the second digital code value as the initial state of the fourth exposure sampling period. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the high-gain image signal hcg_sig during the fourth exposure sampling period. The comparison circuit 20 compares the high-gain image signal hcg_sig with the pixel lamp voltage signal to generate a high-gain image pulse signal. The high-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain image pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, and the quantization of the high-gain image pulse signal is completed. The counter circuit 30 counts to generate a fourth sub-digital code value, which is the difference value between the digital code values corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0125] Then, the counter circuit 30 is reset again. Before the second exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored first sub-digital code value to the counter circuit 30, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back first sub-digital code value to generate a fourth digital code value, and sets the fourth digital code value as the initial state of the second exposure sampling period. Then, the counter circuit 30 returns to the counting mode, quantizes the low-gain image signal lcg_sig during the second exposure sampling period, the comparison circuit 20 compares the low-gain image signal lcg_sig with the pixel lamp voltage signal to generate a low-gain image pulse signal, the low-gain image pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction on the low-gain image pulse signal based on the fourth digital code value, and when the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the low-gain image pulse signal is completed, the counter circuit 30 counts to generate a fifth sub-digital code value which is the difference value between the digital code values corresponding to the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0126] At the same time, the third sub-digital code value, the fourth sub-digital code value, and the fifth digital code value obtained by three quantizations are finally stored in the memory circuit 50 and read out to the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information based on the third sub-digital code value, the fourth sub-digital code value, and the fifth digital code value, realizes autofocus in the high conversion gain mode, and improves the imaging quality and user experience.

[0127] Corresponding to the signal input / output logic of Embodiment 9 and Embodiment 10 above, as shown in FIG. 18, preferably, the counter circuit 30 includes a first counter unit 31 to an nth counter unit. The memory circuit 50 includes n memory units, and each memory unit is connected to the counter unit and the inversion control circuit 40 respectively. Each memory unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a NAND gate NOR1, and a first 2:1 multiplexer MUX1. The input terminals of the first memory Mem1, the second memory Mem2, and the third memory Mem3 are simultaneously connected to the counter unit. The output terminal of the first memory Mem1 is connected to the first input terminal of the first 2:1 multiplexer MUX1. The output terminal of the second memory Mem2 is connected to the second input terminal of the first 2:1 multiplexer MUX1. The control terminal of the first 2:1 multiplexer MUX1 is used to input the write-back selection signal mem_sel. The output terminal of the first 2:1 multiplexer MUX1 is connected to the first input terminal of the NAND gate NOR1. The second input terminal of the NAND gate NOR1 is used to input the write-back control signal rewrite_en. The NAND gate NOR1 constitutes the output terminal of the memory circuit 50. The first memory Mem1 is used to store the corresponding 1-bit count value among the first sub-digital code values. The second memory Mem2 is used to store the corresponding 1-bit count value among the second sub-digital code values. The first memory Mem1, the second memory Mem2, and the third memory Mem3 respectively store the corresponding 1-bit count values among the three digital code values after three exposure samplings.

[0128] In this embodiment, the difference between the circuit structures adopted in Embodiment 7 and Embodiment 8 is that the memory circuit 50 includes three memories and further includes one first 2:1 multiplexer MUX1, and n first memories Mem1 are used to store the n-bit count values of the first sub-digital code values corresponding to the low-gain reset signal lcg_rst during the reset sampling period, and n second memories Mem2 are used to store the n-bit count values of the second sub-digital code values corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0129] At the same time, when realizing autofocus in the low-gain mode or autofocus in the high-gain mode, before the corresponding exposure sampling period, based on the first sub-digital code value or the second sub-digital code value that needs to be written back, the corresponding write-back selection signal mem_sel is output to the first 2:1 multiplexer MUX1, and the first sub-digital code value or the second sub-digital code value is selected and written back to the n counter units by the inversion control circuit 40.

[0130] The n-bit counter unit counts the pulse signals input during the reset sampling period and the exposure sampling period and generates the corresponding digital code value.

[0131] After each exposure sampling period, finally, the three digital code values obtained by quantization are respectively stored in the first memory Mem1, the second memory Mem2, and the third memory Mem3. For example, when the readout circuit 1 realizes autofocus with a low conversion gain, it is applied to the third digital code value, the fifth sub-digital code value, and the sixth sub-digital code value obtained by three exposure samplings. Here, the n-bit count values of the third digital code value are respectively stored in the n first memories Mem1, the n-bit count values of the fifth sub-digital code value are respectively stored in the n second memories Mem2, and the n-bit count values of the sixth sub-digital code value are respectively stored in the n third memories Mem3.

[0132] Alternatively, the readout circuit 1 is applied to the third sub-digital code value, the fourth sub-digital code value, and the fifth digital code value obtained by three exposure samplings when realizing autofocus with a high conversion gain. The n-bit count values of the third sub-digital code value are respectively stored in n first memories Mem1, the n-bit count values of the fourth sub-digital code value are respectively stored in n second memories Mem2, and the n-bit count values of the fifth digital code value are respectively stored in n third memories Mem3. The three memories are read out to the corresponding control circuit 3 based on the read control signal, and the control circuit 3 determines the image information based on the count values of each memory circuit 50.

[0133] Embodiment 11 Based on Embodiment 6, optimization and implementation are performed. In another selectable embodiment, the image sensor includes a pixel array 100. Each pixel array 100 includes pixel units arranged in an array. The readout circuit 1 of each image sensor is respectively connected to a plurality of pixel units arranged in a column. The pixel unit includes four sub-pixels arranged in a 2×2 manner. Among them, two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a continuous first reset sampling period and a second reset sampling period. At least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a first pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a first image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The second pixel pulse signal includes a second pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a second image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The first exposure sampling period includes a continuous third exposure sampling period and a fourth exposure sampling period. The second exposure sampling period includes the consecutive fifth exposure sampling period and sixth exposure sampling period, The first digital code value includes the first sub-digital code value and the second sub-digital code value, In the first reset sampling period, the counter circuit 30 counts the low-gain reset pulse signal and generates the first sub-digital code value, In the second reset sampling period, the counter circuit 30 counts the high-gain reset pulse signal and generates the second sub-digital code value, The third digital code value includes the third sub-digital code value and the fourth sub-digital code value, In the third exposure sampling period, the counter circuit 30 counts the first pixel group pulse signal based on the second digital code value and stores it as the third sub-digital code value, In the fourth exposure sampling period, the counter circuit 30 counts the first image pulse signal based on the second digital code value and stores it as the fourth sub-digital code value, The fifth digital code value includes the fifth sub-digital code value and the sixth sub-digital code value, In the fifth exposure sampling period, the counter circuit 30 counts the second pixel group pulse signal based on the fourth digital code value and stores it as the fifth sub-digital code value, In the sixth exposure sampling period, the counter circuit 30 is configured to count the second image pulse signal based on the fourth digital code value and store it as the sixth sub-digital code value. The memory circuit 50 is connected to the counter circuit 30 and is configured to store the first sub-digital code value and the second sub-digital code value. Before the fourth exposure sampling period, it is triggered by the write-back control signal rewrite_en to write back the second sub-digital code value to the counter circuit 30. Before the fifth exposure sampling period and the sixth exposure sampling period, it is triggered by the write-back control signal rewrite_en to write back the first sub-digital code value to the counter circuit 30. The inversion control circuit 40 is connected to the counter circuit 30 and the memory circuit 50, and is triggered by an inversion control signal trig_pulse before each exposure sampling period, so that the counter circuit 30 inverts the second sub-digital code value of the memory to generate a second digital code value, and inverts the first sub-digital code value to generate a fourth digital code value.

[0134] In this embodiment, the readout circuit 1 is applied to realize autofocus simultaneously with high conversion gain and low conversion gain. The reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The second pixel pulse signal includes a low-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit.

[0135] As shown in FIGS. 16 and 17, in the first reset sampling period, the comparison circuit 20 compares the low-gain reset signal lcg_rst with the reset ramp voltage signal, generates a low-gain reset pulse signal and inputs it to the counter circuit 30. The counter circuit 30 counts up or down the low-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the low-gain reset signal lcg_rst is completed, and the counter circuit 30 counts to generate a first sub-digital code value and writes it into the memory circuit 50.

[0136] Before the second reset sampling period, the counter circuit 30 is reset. During the second reset sampling period, the comparison circuit 20 compares the high-gain reset signal hcg_rst with the reset ramp voltage signal to generate a high-gain reset pulse signal. The high-gain reset pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain reset pulse signal. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops counting, the quantization of the high-gain reset signal hcg_rst is completed, and the counter circuit 30 counts to generate a second sub-digital code value and stores it internally.

[0137] Before the third exposure sampling period, the inversion control circuit 40 receives the mode selection signal mode_sel. The inversion control circuit 40 outputs an inversion control signal trig_pulse to the counter circuit 30. The counter circuit 30 switches to the inversion mode, inverts the stored second sub-digital code value to a second digital code value, and sets it as the initial state of the third exposure sampling period. Then, the counter circuit 30 returns to the counting mode and quantizes the signal hcg_sigl of the high-gain pixel group during the third exposure sampling period. The comparison circuit 20 compares the signal hcg_sigl of the high-gain pixel group with the pixel ramp voltage signal to generate a high-gain pixel group pulse signal. The high-gain pixel group pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the high-gain pixel group pulse signal based on the second digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the high-gain pixel group pulse signal is completed, and the counter circuit 30 counts to generate a third sub-digital code value, which is the difference value between the signal hcg_sigl of the high-gain pixel group and the digital code value corresponding to the high-gain reset signal hcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0138] Thereafter, the counter circuit 30 is reset again. Before the fourth exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, writes back the stored second sub-digital code value to the counter circuit 30 again, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the written-back second sub-digital code value to generate a second digital code value, and sets the second digital code value as the initial state of the fourth exposure sampling period. Thereafter, the counter circuit 30 returns to the count mode, quantizes the high-gain image signal hcg_sig during the fourth exposure sampling period, the comparison circuit 20 compares the high-gain image signal hcg_sig with the pixel lamp voltage signal to generate a high-gain image pulse signal, the high-gain image pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction with respect to the high-gain image pulse signal based on the second digital code value, and when the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the high-gain image pulse signal is completed, the counter circuit 30 counts to generate a fourth sub-digital code value which is the difference value between the digital code values corresponding to the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0139] Before the fifth exposure sampling period, the memory circuit 50 receives a write-back control signal rewrite_en, writes back the stored first sub-digital code value to the counter circuit 30, and the counter circuit 30 receives an inversion control signal trig_pulse, inverts the written-back first sub-digital code value to generate a fourth digital code value, and sets the fourth digital code value as the initial state of the fifth exposure sampling period. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the low-gain pixel group signal lcg_sign during the fifth exposure sampling period, the comparison circuit 20 compares the low-gain pixel group signal lcg_sign with the pixel ramp voltage signal to generate a low-gain pixel group pulse signal, the low-gain pixel group pulse signal is output to the counter circuit 30, the counter circuit 30 performs a counting operation in the same direction with respect to the low-gain pixel group pulse signal based on the fourth digital code value, and when the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, the quantization of the low-gain pixel group pulse signal is completed, the counter circuit 30 counts to generate a fifth sub-digital code value which is the difference value of the digital code values corresponding to the low-gain pixel group signal lcg_sign1 and the low-gain reset signal lcg_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0140] Thereafter, the counter circuit 30 is reset again. Before the sixth exposure sampling period, the memory circuit 50 receives the write-back control signal rewrite_en, rewrites the stored first sub-digital code value back to the counter circuit 30 again, and the counter circuit 30 receives the inversion control signal trig_pulse, inverts the rewritten first sub-digital code value to generate a fourth digital code value, sets the fourth digital code value as the initial state of the sixth exposure sampling period. Thereafter, the counter circuit 30 returns to the counting mode, quantizes the low-gain image signal lcg_sig during the sixth exposure sampling period. The comparison circuit 20 compares the low-gain image signal lcg_sig with the pixel lamp voltage signal to generate a low-gain image pulse signal. The low-gain image pulse signal is output to the counter circuit 30. The counter circuit 30 performs a counting operation in the same direction with respect to the low-gain image pulse signal based on the fourth digital code value. When the output of the comparison circuit 20 is inverted, the counter circuit 30 stops the counting operation, and the quantization of the low-gain image pulse signal is completed. The counter circuit 30 counts to generate a sixth sub-digital code value, which is the difference value between the digital code values corresponding to the low-gain image signal lcg_sig_sig and the low-gain reset signal lcg_rst_rst, realizes correlated double sampling, reduces the influence of noise, and improves the imaging quality.

[0141] At the same time, the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value, and the sixth sub-digital code value obtained by the four quantizations are finally stored in the memory circuit 50 and read out by the corresponding control circuit 3 in the read control signal. The control circuit 3 determines the image information based on the third sub-digital code value, the fourth sub-digital code value, and the fifth digital code value, realizes autofocus in the high conversion gain mode, and improves the imaging quality and user experience.

[0142] Corresponding to the signal input / output logic of Embodiment 11 above, as shown in FIG. 19, preferably, the counter circuit 30 includes a first counter unit 31 to an nth counter unit. The memory circuit 50 includes n memory units, and each memory unit is connected to one counter unit and the inversion control circuit 40 respectively. Each memory unit includes a first memory Mem1, a second memory Mem2, a third memory Mem3, a fourth memory Mem4, a NAND gate NOR1, and a first 2:1 multiplexer MUX1. The input terminals of the first memory Mem1, the second memory Mem2, and the third memory Mem3 are simultaneously connected to the counter unit. The output terminal of the first memory Mem1 is connected to the first input terminal of the first 2:1 multiplexer MUX1. The output terminal of the second memory Mem2 is connected to the second input terminal of the first 2:1 multiplexer MUX1. The control terminal of the first 2:1 multiplexer MUX1 is used to input the write-back selection signal mem_sel. The output terminal of the first 2:1 multiplexer MUX1 is connected to the first input terminal of the NAND gate NOR1. The second input terminal of the NAND gate NOR1 is used to input the write-back control signal rewrite_en. The NAND gate NOR1 constitutes the output terminal of the memory circuit 50. The first memory Mem1 is configured to store the corresponding 1-bit count value among the first sub-digital code values. The second memory Mem2 is configured to store the corresponding 1-bit count value among the second sub-digital code values. The first memory Mem1, the second memory Mem2, the third memory Mem3, and the fourth memory Mem4 respectively store the corresponding 1-bit count values among the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value, and the sixth sub-digital code value.

[0143] In this embodiment, the difference between the circuit structures adopted in Embodiment 9 and Embodiment 10 is that the memory circuit 50 includes four memories, and n first memories Mem1 are used to store the n-bit count values of the first sub-digital code values corresponding to the low-gain reset signal lcg_rst during the reset sampling period, and n second memories Mem2 are used to store the n-bit count values of the second sub-digital code values corresponding to the high-gain reset signal hcg_rst during the reset sampling period.

[0144] At the same time, when realizing autofocus in the low-gain mode or autofocus in the high-gain mode, before the corresponding exposure sampling period, based on the first sub-digital code value or the second sub-digital code value that needs to be rewritten, the corresponding rewrite selection signal mem_sel is output to the first 2:1 multiplexer MUX1, and the first sub-digital code value or the second sub-digital code value is selected and rewritten to the n counter units by the inversion control circuit 40.

[0145] The n-bit counter unit counts the pulse signals input during the reset sampling period and the exposure sampling period, and generates the corresponding digital code value.

[0146] After each exposure sampling period, the finally quantized four digital code values are respectively stored in the first memory Mem1, the second memory Mem2, the third memory Mem3, and the fourth memory Mem4. The four memories are read out to the corresponding control circuit 3 based on the read control signal, and the control circuit 3 determines the image information based on the digital code values of each memory circuit 50.

[0147] Preferably, in some embodiments, after the corresponding digital code value is pre-read by the memory and then reset, the pre-read memory can be multiplexed into the memory of the subsequent digital code value, thereby further reducing the number of memories and reducing the occupied area.

[0148] Embodiment 12 Based on Embodiments 6 to 11, optimization and implementation are performed. Preferably, as shown in FIGS. 15, 18, and 19, the counter circuit 30 includes a first counter unit 31 to an nth counter unit. The inversion control circuit 40 includes n selection circuits. The first input terminal of the i-th selection circuit is used to input an inversion control signal trig_pulse. The second input terminal of the first selection circuit 41 is used to input a clock signal count_clk. The second input terminals of the second selection circuit 42 to the nth selection circuit are connected to the output terminal of the (i - 1)-th stage counter unit. The third input terminal of the i-th selection circuit is used to input a low-level signal. The fourth input terminal of the first selection circuit 41 is used to input an output signal count_out of the comparison circuit 20. The output terminal of the i-th selection circuit is connected to the input terminal of the i-th stage counter unit, where i = 1, 2,..., n. The i-th selection circuit is triggered by a mode selection signal mode_sel and a write-back control signal rewrite_en to output a signal input from its first input terminal, second input terminal, or third input terminal.

[0149] In this embodiment, the inversion control circuit 40 realizes the transmission of an inversion control signal trig_pulse, a rewritten digital code value, and a clock signal count_clk.

[0150] Each selection circuit is connected to the front end of the counter unit, outputs the corresponding signal at the input end to its own output end based on the received mode selection signal mode_sel. Before quantization, each counter unit is reset. During the reset sampling period, the pixel unit outputs a reset signal to the comparison circuit 20. The comparison circuit 20 compares the reset signal with the ramp voltage signal to generate a reset pulse signal. The reset pulse signal is output to the first selection circuit 41. Each selection circuit receives the mode selection signal mode_sel at the first level, triggers the communication between its own second input end and output end. The first selection circuit 41 outputs the clock signal count_clk to the first counter unit 31. The subsequent selection circuits selectively output the count value of the previous-stage counter unit to the next-stage counter unit. Each stage of the counter unit stores its own first count value respectively, and combines the first count values of each stage of the counter unit to generate a first digital code value.

[0151] In the inversion mode during the exposure sampling period, the mode selection signal mode_sel is switched to the second level. Each selection circuit outputs the inversion control signal trig_pulse at the first input end to the counter unit at the rear end. Each counter unit is switched to the inversion mode, and inverts the first count value stored inside it into the second count value or the fourth digital code value. Then, the mode selection signal mode_sel is switched to the first level again, and the level state of the inversion control signal trig_pulse is switched similarly. Each counter unit is switched to the count mode.

[0152] Also, in the write-back mode during the exposure sampling period, after receiving the write-back control signal rewrite_en, the memory circuit 50 writes back the stored corresponding first digital code value to n selection circuits. The n selection circuits write back the written-back first digital code value to n counter units.

[0153] Continuing to refer to FIGS. 15, 18, and 19, preferably, the first selection circuit 41 includes an AND gate AND1, a second 2:1 multiplexer MUX2, a third 2:1 multiplexer MUX3, and a first inverter U1. The first input terminal of the AND gate AND1 is used to input the clock signal count_clk, the second input terminal of the AND gate AND1 is used to input the output signal count_out of the comparison circuit 20, the first input terminal of the second 2:1 multiplexer MUX2 is used to input the inversion control signal trig_pulse, the output terminal of the AND gate AND1 is connected to the second input terminal of the 2:1 multiplexer, the second input terminal of the second 2:1 multiplexer MUX2 is used to input the low-level signal tie_lo, the control terminal of the second 2:1 multiplexer MUX2 is connected to the output terminal of the storage circuit 50, the output terminal of the second 2:1 multiplexer MUX2 is connected to the first input terminal of the third 2:1 multiplexer MUX3, the second input terminal of the third 2:1 multiplexer MUX3 is used to input the clock signal count_clk or a numerical value output from the previous counter unit, the control terminal of the third 2:1 multiplexer MUX3 is used to input the mode selection signal mode_sel, the output terminal of the third 2:1 multiplexer MUX3 is connected to the input terminal of the first inverter U1, and the output terminal of the first inverter U1 is used to input a corresponding one of the signals of the inversion control signal trig_pulse, the clock signal trig_pulse, and the low-level signal tie_lo. The second selection circuit 42 to the nth selection circuit each include a second 2:1 multiplexer MUX2, a third 2:1 multiplexer MUX3, and a first inverter U1. The first input terminal of the second 2:1 multiplexer MUX2 is used to input the inversion control signal trig_pulse. The second input terminal of the second 2:1 multiplexer MUX2 is used to input the low-level signal tie_lo. The control terminal of the second 2:1 multiplexer MUX2 is connected to the output terminal of its storage circuit 50. The output terminal of the second 2:1 multiplexer MUX2 is connected to the first input terminal of its third 2:1 multiplexer MUX3. The second input terminal of the third 2:1 multiplexer MUX3 is used to input the clock signal count_clk or the numerical value output from the previous counter unit. The control terminal of the third 2:1 multiplexer MUX3 is used to input its mode selection signal mode_sel. The output terminal of the third 2:1 multiplexer MUX3 is connected to the input terminal of its first inverter U1. The output terminal of the first inverter U1 is used to output the corresponding one of the signals among the inversion control signal trig_pulse, its clock signal count_clk, the low-level signal tie_lo, and the numerical value output from the previous counter unit.

[0154] Continuing to refer to FIGS. 6, 8, 15, 18, and 19, the counter unit includes a D flip-flop DFF and a second inverter U2, or the counter unit includes a D flip-flop DFF.

[0155] In this embodiment, when the inverted output terminal of the D flip-flop DFF is connected to the second inverter U2 and the second inverter U2 is the output terminal of the counter unit, the counter unit constitutes an up-counter. When the non-inverted output terminal of the D flip-flop DFF constitutes the output terminal of the counter unit, the counter unit constitutes a down-counter. Through operations such as inversion and write-back of the reset signal, when the counter unit continuously quantizes the reset signal and the pixel signal, there is no need to perform switching operations between up-counting and down-counting, nor is it necessary to provide an additional holding circuit. Compared with the conventional counter circuit 30, the number of transistors can be reduced, the layout area and optimized wiring can be reduced, and the purpose of reducing power consumption can be achieved.

[0156] As shown in FIGS. 13 and 14, taking up-counting as an example, when the selection circuit and the counter unit are applied to the ADAF mode, the timing of the next complete quantization cycle of the ADAF mode is as follows.

[0157] At times t0 to t1, count_rstb is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0158] At time t2, quantization of the reset signal is performed. At this time, the output signal count_out of the comparison circuit 20 is switched to the high level. After the clock signal count_clk performs an AND operation with the AND gate AND1 at the high level, the clock signal count_clk is output to the second input terminal of the third 2:1 multiplexer MUX3. At this time, the mode selection signal mode_sel is at the high level, the clock signal count_clk is strobed and output to the first inverter U1, and then output to the first D flip-flop DFF. Each D flip-flop DFF performs up-counting according to the clock signal count_clk.

[0159] At time t3, the output of the comparison circuit 20 is inverted, the counting stops, the quantization of the reset signal is completed, each bit count value of the first digital code value of the quantization result of the reset signal is stored in each D flip-flop DFF, and the first count values output from each second inverter U2 are combined to generate the first digital code value.

[0160] At times t4 to t5, the read control signal is switched to the high level, and the first quantization result is stored in the first memory Mem1.

[0161] At time t5, the mode selection signal mode_sel is switched to the low level, and each counter unit is switched to the inversion mode.

[0162] At time t6, the inversion control signal trig_pulse is switched to the low level, and the second 2:1 multiplexer MUX2 and the third 2:1 multiplexer MUX3 generate a rising edge at the clock input terminal of each D flip-flop DFF, and invert the digital code of the first quantization result stored in each D flip-flop DFF to obtain the initial state before the second quantization.

[0163] At time t7, the mode selection signal mode_sel is switched to the high level, the counter unit returns to the counting mode, and at time t8, the inversion control circuit 40 is switched to the high level.

[0164] At time t9, the quantization of the pixel group signal Vsigl starts from the initial state. At time t10, the output of the comparison circuit 20 is inverted, the counting stops, the quantization of the pixel group signal Vsigl is completed, and the third digital code value of the difference between the pixel group signal Vsigl and the reset signal is stored in the D flip-flop DFF.

[0165] At times t11 to t12, sram_wrt is enabled, the final quantization result is stored in the second memory Mem2, and then read out.

[0166] At times t12 to t13, count_rstb is switched to the low level, and the values in all D flip - flops DFF are reset (outputs all become 0).

[0167] At time t13, the mode selection signal mode_sel is switched to the low level, the write - back control signal rewrite_en is switched to the high level, and the counter unit is switched to the write - back mode.

[0168] At time t14, the inversion control signal trig_pulse is switched to the low level, and the second 2:1 multiplexer MUX2 and the third 2:1 multiplexer MUX3 generate a rising edge at the clock input terminal of the D flip - flop DFF, write and invert the first digital code value stored in the first memory Mem1 into the n - bit counter unit, and set it as the initial state before quantization of the image signal Vsig.

[0169] At time t15, the mode selection signal mode_sel is switched to the high level, the counter unit returns to the count mode, and at time t16, the inversion control signal trig_pulse is switched to the high level.

[0170] At time t17, quantization of the image signal Vsig starts from the initial state. At time t18, the output of the comparison circuit 20 is inverted, the count stops, quantization of the image signal Vsig ends, and the difference between the image signal Vsig and the reset signal, that is, the image quantization value of correlated double sampling, is stored in the D flip - flop DFF.

[0171] At times t19 to t20, the read control signal is enabled, the final quantization result is stored in the first memory Mem1 and then read out.

[0172] Referring to FIGS. 13 and 15, when the selection circuit is applied to the PGHDR mode, the timing of one complete quantization cycle in the PGHDR mode is as follows.

[0173] At times t0 to t1, count_rstb is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0174] At time t2, quantization of the low-gain reset signal lcg_rst is performed. At this time, the output signal count_out of the comparison circuit 20 is switched to the high level. After the clock signal count_clk performs an AND operation with the high level through the AND gate AND1, the clock signal count_clk is output to the second input terminal of the third 2:1 multiplexer MUX3. At this time, the mode selection signal mode_sel is at the high level, the clock signal count_clk is strobed and output to the first inverter U1, and then output to the first D flip-flop DFF. Each D flip-flop DFF performs an up-count by the clock signal count_clk.

[0175] At time t3, the output of the comparison circuit 20 is inverted, the count stops, the quantization of the low-gain reset signal lcg_rst ends, and the first sub-digital code of the quantization result of the low-gain reset signal lcg_rst is stored in the D flip-flop DFF.

[0176] At times t4 to t5, the read control signal is switched to the high level, and the first sub-digital code is stored in each first memory Mem1.

[0177] At times t5 to t6, count_rstb is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0178] At time t7, quantization of the high-gain reset signal hcg_rst starts from the initial state. At time t8, the output of the comparison circuit 20 is inverted and the count stops, and the quantization of the high-gain reset signal hcg_rst ends. The second sub-digital code of the high-gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0179] At time t9, the mode selection signal mode_sel is switched to the low level, and the counter is switched to the inversion mode. At time t10, the inversion control signal trig_pulse is switched to the low level, and is output to the clock input terminal of the D flip-flop DFF by the second 2:1 multiplexer MUX2 and the third 2:1 multiplexer MUX3 to generate a rising edge, and the digital code of the quantization result for the second time stored in each D flip-flop DFF is inverted to the second digital code value to return to the initial state before the second quantization.

[0180] At time t11, the mode selection signal mode_sel is switched to the high level, and the counter unit returns to the count mode. At time t12, the mode selection signal mode_sel is switched to the high level.

[0181] At time t13, quantization of the high-gain image signal hcg_sig starts from the initial state. At time t14, the output of the comparison circuit 20 is inverted, the count stops, and the quantization of the high-gain image signal hcg_sig ends. The difference between the high-gain image signal hcg_sig and the reset signal, that is, the image quantization value of correlated double sampling with a high conversion gain, is stored in the D flip-flop DFF. At times t15 to t16, sram_wrt is enabled, and the final quantization result is stored in the second memory Mem2 and then read out.

[0182] At times t16 to t17, count_rstb is switched to the low level, and the values in all D flip - flops DFF are reset (outputs all become 0). At time t17, the mode selection signal mode_sel is switched to the low level, the write - back control signal rewrite_en is switched to the high level, and the counter unit is switched to the write - back mode.

[0183] At time t18, the inversion control signal trig_pulse is switched to the low level, a rising edge is generated at the clock input terminal of the D flip - flop DFF, and the first sub - digital code value corresponding to the low - gain reset signal lcg_rst stored in the first memory Mem1 is written back to the counter unit and inverted to be the initial state before quantization of the low - gain image signal lcg_sig.

[0184] At time t19, the mode selection signal mode_sel is switched to the high level, the counter unit returns to the count mode, and at time t20, the inversion control signal trig_pulse is switched to the high level.

[0185] At time t21, the quantization of the low - gain image signal lcg_sig starts from the initial state. At time t22, the output of the comparison circuit 20 is inverted, the count stops, the quantization of the low - gain image signal lcg_sig ends, and the difference between the low - gain image signal lcg_sig and the reset signal, that is, the image quantization value of correlated double sampling with a low conversion gain, is stored in the D flip - flop DFF. At times t23 to t24, the read control signal is enabled, the final quantization result is stored in the first memory Mem1 and then read out.

[0186] Up to this point, one complete quantization cycle is completed, and finally, the image quantization value of correlated double sampling with a high conversion gain and the image quantization value of correlated double sampling with a low conversion gain are obtained.

[0187] When the selection circuit is applied with a low conversion gain to realize the ADAF mode, the timing within one complete quantization cycle is as shown in Fig. 16.

[0188] At times t0 to t1, count_rstb is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0189] At time t2, quantization of the low gain reset signal lcg_rst is performed, the counter performs up counting by the high-speed clock count_clk, at time t3, the output of the comparison circuit 20 is inverted, the counting stops, the quantization of the low gain reset signal lcg_rst ends, and the first sub-digital code value of the quantization result of the low gain reset signal lcg_rst is stored in the D flip-flop DFF.

[0190] At times t4 to t5, the read control signal is switched to the high level, and the first quantization result is stored in the first memory Mem1.

[0191] At times t5 to t6, count_rstb is switched to the low level, and the values in all D flip-flops DFF are reset (all outputs become 0).

[0192] At time t7, quantization of the high gain reset signal hcg_rst is started from the initial state, at time t8, the output of the comparison circuit 20 is inverted and the counting stops, the quantization of the high gain reset signal hcg_rst ends, and the second sub-digital code value of the high gain reset signal hcg_rst is stored in the D flip-flop DFF.

[0193] At time t9, the mode selection signal mode_sel is switched to the low level, the connection between each stage of the counter is disconnected, and at time t10, the inversion control signal trig_pulse is switched to the low level, generating a rising edge at the clock input terminal of the D flip-flop DFF, inverting the digital code of the second quantization result stored in the D flip-flop DFF, and setting it to the initial state before the third quantization.

[0194] At time t11, the mode selection signal mode_sel is switched to the high level, the counter returns to the count mode, and at time t12, the inversion control signal trig_pulse is switched to the high level.

[0195] At time t13, the quantization of the high-gain image signal hcg_sig starts from the initial state, and at time t14, the output of the comparison circuit 20 is inverted and the counting stops, and the quantization of the high-gain image signal hcg_sig is completed. The difference between the high-gain image signal hcg_sig and the high-gain reset signal hcg_rst, that is, the image quantization value of correlated double sampling with a high conversion gain, is stored in the D flip-flop DFF.

[0196] At time t15, the write-back control signal rewrite_en and the mode selection signal mode_sel are switched to the high level, the counter is switched to the write-back mode, the first sub-digital code value stored in the first memory Mem1 is selected and written back to the counter. At time t15 - t16, sram_wrt is enabled, the final quantization result is stored in the second memory Mem2 and then read out.

[0197] At times t16 to t17, count_rstb is switched to the low level to reset the values in all D flip - flops DFF (outputs all become 0). At time t17, the mode selection signal mode_sel is switched to the low level to disconnect the connection between each stage of the counter. At time t18, the inversion control signal trig_pulse is switched to the low level to generate a rising edge at the clock input terminal of the D flip - flop DFF, and write back and invert the first sub - digital code value corresponding to the low - gain reset signal lcg_rst stored in the first memory Mem1 to the counter unit to set it to the initial state before the fourth quantization. At time t19, the mode selection signal mode_sel is switched to the high level, and the counter returns to the counting mode. At time t20, the inversion control signal trig_pulse is switched to the high level.

[0198] At time t21, the quantization of the low - gain pixel group signal lcg_sigl starts from the initial state. At time t22, the output of the comparison circuit 20 is inverted, the counting stops, and the quantization of the low - gain pixel group signal lcg_sigl ends. The D flip - flop DFF stores the difference between the low - gain pixel group signal lcg_sigl and the low - gain reset signal lcg_rst, that is, the quantization value of the pixel group signal Vsigl of correlated double sampling with a low conversion gain. At times t23 to t24, hcg_wrt is enabled to store the final quantization result in the third memory Mem3 and then read it out.

[0199] At time t24 to t25, count_rstb is switched to the low level, resetting the values in all D flip-flops DFF (outputs all become 0). At time t25, the mode selection signal mode_sel is switched to the low level, disconnecting the connection between each stage of the counter unit. At time t26, the inversion control signal trig_pulse is switched to the low level, generating a rising edge at the clock input terminal of the D flip-flop DFF, writing back and inverting the first digital code value stored in the first memory Mem1 to the counter, setting it to the initial state before the fifth quantization. At time t27, the mode selection signal mode_sel is switched to the high level, and the counter returns to the counting mode. At time t28, the inversion control signal trig_pulse is switched to the high level.

[0200] At time t29, the quantization of the low-gain image signal lcg_sig starts from the initial state. At time t30, the output of the comparison circuit 20 is inverted, the counting stops, and the quantization of the low-gain image signal lcg_sig ends. The D flip-flop DFF stores the difference between the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst, that is, the image quantization value of correlated double sampling at the low conversion gain. At times t31 to t32, lcg_wrt is enabled, storing the final quantization result in the first memory Mem1 and then reading it out.

[0201] Up to this point, one complete quantization cycle is completed, sequentially obtaining the image quantization value of correlated double sampling at the high conversion gain, the pixel group quantization value of correlated double sampling at the low conversion gain, and the image quantization value of correlated double sampling at the low conversion gain.

[0202] By analogy, when the selection circuit is applied with a high conversion gain to realize the ADAF mode, or when it is applied with both high and low conversion gains to realize the ADAF mode simultaneously, the selection circuit selects the corresponding inversion control signal trig_pulse or digital code value based on the received corresponding mode selection signal mode_sel or the written-back digital code value, and outputs it to the counter unit, causing the counter unit to perform operations such as counting and inversion.

[0203] Every time quantization is completed, the corresponding digital code value is stored in the corresponding memory. Each memory reads out based on the received read control signal to the control circuit 3, and the control circuit 3 determines the image information based on each digital code value.

[0204] Here, in order to realize the inversion function of the D flip-flop DFF in the above embodiment, as shown in FIG. 20, preferably, the D flip-flop DFF includes a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a seventh inverter U7, an eighth inverter U8, a first transfer gate tran1, a second transfer gate tran2, a third transfer gate tran3, and a fourth transfer gate tran4. In this embodiment, the first transfer gate tran1, the fourth inverter U4, the fifth inverter U5, and the second transfer gate tran2 constitute a master stage latch. The third transfer gate tran3, the sixth inverter U6, the seventh inverter U7, and the fourth transfer gate tran4 constitute a slave stage latch. The master stage latch stably latches and outputs the input value of the D-type flip-flop DFF. The slave stage latch stably latches and outputs the output value of the master stage latch. The third inverter U3 inverts the input data signal and outputs it to the master stage latch. The eighth inverter U8 inverts and outputs the output value of the slave stage latch. When the clock signal count_clk terminal of the D-type flip-flop DFF receives a rising edge, the third inverter U3, the master stage latch, the slave stage latch, and the eighth inverter U8 invert and output the latched numerical value.

[0205] Embodiment 13 The present application further provides an image sensor. As shown in FIG. 2, the image sensor includes a pixel array 100, a control circuit 3, and a readout circuit 1 for a plurality of image sensors. For the specific structure of the readout circuit 1 of the image sensor, refer to the above embodiments. Since the present image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects of the technical solutions of the above embodiments, and will not be described one by one here. Among them, the pixel array 100 includes a plurality of pixel units arranged in an array, The readout circuit 1 for each image sensor is respectively connected to a plurality of pixel units arranged in a column, and the readout circuit 1 for each image sensor is further respectively connected to the control circuit 3.

[0206] In this embodiment, the image sensor usually includes a control circuit 3, a pixel array 100, and a readout circuit 1, and may further include a clock generator and a digital I / O port. The pixel array 100 includes a plurality of pixel units arranged in an array. The plurality of pixel units arranged in a column are commonly connected. The control circuit 3 selects the pixel units of each row by a row selection signal, sequentially outputs the pixel signals of each row to the readout circuit 1, and the plurality of pixel units arranged in a column are connected to the corresponding readout circuit 1. The readout circuit 1 performs analog-to-digital conversion and outputs the corresponding digital code value to the control circuit 3, so that the control circuit 3 determines the image information based on the digital code value.

[0207] Here, the pixel unit usually includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. Among them, the photoelectric conversion element includes a photodiode PD, but is not limited thereto. For example, it may be a Pin-type photodiode PD. At the same time, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more. That is, the structure of the pixel unit can be selected correspondingly, and the specific structure is not limited. As shown in FIG. 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. Among them, the cathode of the photodiode PD is connected to the first end of the transfer transistor TX, and the second end of the transfer transistor TX, the first end of the reset transistor RST, and the controlled end of the source follower transistor SF are all connected to a floating diffusion node. The anode of the photodiode PD is grounded, the second end of the reset transistor RST and the first end of the source follower transistor SF are both connected to the positive power supply terminal VDD, the second end of the source follower transistor SF is connected to the first end of the row selection transistor SEL, and the second end of the row selection transistor SEL constitutes the output end of the pixel unit 2 and is used to output the corresponding pixel signal.

[0208] The above embodiments are only for explaining the technical solutions of the present application and do not limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions described in each of the above embodiments or perform equivalent substitutions for some of the technical features therein. It should be understood that these modifications or substitutions do not deviate from the spirit and scope of the technical solutions of each embodiment of the present application for the corresponding technical solutions and should all be included in the protection scope of the present application.

Claims

1. A readout circuit of an image sensor, comprising: a ramp voltage circuit arranged to output a ramp voltage signal during a first quantization period and a second quantization period of a pixel unit respectively; a comparison circuit having a first input terminal connected to the pixel unit and a second input terminal connected to the ramp voltage circuit, for comparing a reset signal or a pixel signal output from the pixel unit with the ramp voltage signal and outputting a reset pulse signal or a pixel pulse signal; a counter circuit connected to the comparison circuit, arranged to count a first pulse signal during the first quantization period and store a first digital code value, and during the second quantization period, the counter circuit counts a second pulse signal based on a second digital code value and stores it as a third digital code value, wherein the first pulse signal and the second pulse signal are respectively the reset pulse signal and the pixel pulse signal; a reverse control circuit connected to the counter circuit, which outputs a reverse control signal triggered by a mode selection signal between the first quantization period and the second quantization period, so that the counter circuit is triggered by the reverse control signal to reverse and store the first digital code value to the second digital code value. A readout circuit of an image sensor, characterized by the above.

2. The counter circuit is arranged to count the reset pulse signal during the first quantization period and store the first digital code value, and count the pixel pulse signal based on the second digital code value during the second quantization period and store it as the third digital code value, or alternatively, the counter circuit is arranged to count the pixel pulse signal during the first quantization period, store the first digital code value, count the reset pulse signal based on the second digital code value during the second quantization period, and store it as the third digital code value. The readout circuit of an image sensor according to Claim 1, characterized by the above.

3. The counter circuit includes a first counter unit to an nth counter unit. The inversion control circuit includes n selection circuits. The first input terminal of the i-th selection circuit is used to input the inversion control signal. The second input terminal of the first selection circuit is used to input a clock signal. The third input terminal of the first selection circuit is used to input the output signal of the comparator. The second input terminals of the second to n-th selection circuits are connected to the output terminal of the counter unit at the (i - 1)-th stage. The output terminal of the i-th selection circuit is connected to the input terminal of the counter unit at the i-th stage, where i = 1, 2,..., n. The i-th selection circuit outputs the inversion control signal or the clock signal according to the mode selection signal. The first to n-th counter units count the first pulse signal during the first quantization period, respectively store the first count value of their own stage, and are arranged to generate the first digital code value by combining the count values of the counter units of each stage. Between the first quantization period and the second quantization period, the first to n-th counter units invert the first count value according to the inversion control signal and store it as the second count value, and generate the second digital code value by combining the count values of the counter units of each stage. During the second quantization period, the first to n-th counter units count the second pulse signal based on the second count value and store it as the third count value, and generate the third digital code value by combining the count values of the counter units of each stage. The readout circuit of the image sensor according to claim 1, characterized in that.

4. The first selection circuit includes an AND gate, a 2:1 multiplexer, and a first inverter. The first input terminal of the AND gate is used to input the clock signal. The second input terminal of the AND gate is used to input the output signal of the comparator. The first input terminal of the 2:1 multiplexer is used to input the inversion control signal. The output terminal of the AND gate is connected to the second input terminal of the 2:1 multiplexer. The output terminal of the 2:1 multiplexer is connected to the input terminal of the first inverter. The output terminal of the first inverter constitutes the output terminal of the first selection circuit. The second selection circuit to the nth selection circuit each include a 2:1 multiplexer and a first inverter. In the second selection circuit to the nth selection circuit, the first input terminal of the 2:1 multiplexer is used to input the inversion control signal, the second input terminal of the 2:1 multiplexer is used to input the numerical value output from the previous counter unit, the output terminal of the 2:1 multiplexer is connected to the input terminal of the first inverter, and the output terminal of the first inverter is used to constitute the output terminal of the selection circuit. The readout circuit of the image sensor according to claim 3, characterized in that.

5. The readout circuit of the image sensor further includes a storage circuit. The storage circuit is connected to the counter circuit, stores the third digital code value, and is triggered by a read control signal to read out. The storage circuit includes n memories. The n memories are respectively connected to one of the counter units, and respectively store the count values corresponding to the number of bits of the third digital code value. The readout circuit of the image sensor according to claim 3, characterized in that.

6. The first quantization period is a reset sampling period, the second quantization period is a first exposure sampling period, the reset sampling period includes at least one, and the pixel signal includes two. The lamp voltage circuit is further arranged such that each sampling period outputs a lamp voltage signal. The comparison circuit is further arranged to compare at least one reset signal or two pixel signals output from the pixel unit with the lamp voltage signal, and output at least one reset pulse signal and two pixel pulse signals at intervals. The counter circuit is further arranged to count the at least one reset pulse signal during at least one reset sampling period, store it as at least one first digital code value, count the first pixel pulse signal based on the second digital code value during the first exposure sampling period, store it as a third digital code value, count the second pixel pulse signal based on the fourth digital code value during the second exposure sampling period, and store it as a fifth digital code value. The inversion control circuit is connected to the counter circuit and the memory circuit, and before each exposure sampling period, it is triggered by a mode selection signal and outputs an inversion control signal to the counter circuit, thereby triggering the counter circuit to invert the first digital code value of the memory to generate the second digital code value or the fourth digital code value. The readout circuit of the image sensor further includes a memory circuit. The memory circuit is connected to the counter circuit, stores the at least one first digital code value, and is triggered by a write-back control signal before the second exposure sampling period, and is arranged to write back one of the at least one first digital code values to the counter circuit. The readout circuit of the image sensor according to claim 2, characterized in that.

7. The image sensor includes a pixel array, the pixel array includes pixel units arranged in an array, the readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, the pixel unit includes at least four sub-pixels arranged in at least 2×2, and at least two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The at least one reset signal is a reset signal generated when the pixel units are reset simultaneously. The first pixel pulse signal and the second pixel pulse signal are respectively one of the corresponding pixel group pulse signals for the simultaneous exposure of the pixel group and the image pulse signals for the simultaneous exposure of the sub-pixels in the pixel unit. The readout circuit of the image sensor according to claim 6, characterized in that.

8. The reset sampling period includes consecutive first reset sampling periods and second reset sampling periods, the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal and the second pixel pulse signal are respectively one of a high-gain image pulse signal and a low-gain image pulse signal. The counter circuit is In the first reset sampling period, counts one of the reset pulse signals and generates one first digital code value. During the second reset sampling period, another reset pulse signal is counted to generate another first digital code value. During the first exposure sampling period, the first pixel pulse signal is counted based on the second digital code value and stored as a third digital code value. During the second exposure sampling period, the second pixel pulse signal is counted based on the fourth digital code value and stored as a fifth digital code value. The readout circuit of the image sensor according to claim 6, characterized in that.

9. The counter circuit includes a first counter unit to an nth counter unit. The memory circuit includes n memory units, and each memory unit is connected to one counter unit and the inversion control circuit respectively. Each memory unit includes a first memory, a second memory, and a NAND gate. The input terminals of the first memory and the second memory are respectively connected to one counter unit. The output terminal of the first memory is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input the write-back control signal. The NAND gate constitutes the output terminal of the memory unit. The first memory is arranged to store the corresponding 1-bit count value of at least one of the first digital code values. The first memory and the second memory respectively store the corresponding 1-bit count value of one digital code value among the third digital code value and the fifth digital code value. The readout circuit of the image sensor according to claim 7 or 8, characterized in that.

10. The image sensor includes a pixel array, the pixel array includes pixel units arranged in an array, the readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a row, the pixel unit includes at least four sub-pixels arranged in at least 2×2, and at least two sub-pixels constitute a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a continuous first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain image pulse signal, and the second pixel pulse signal includes a low-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the low-gain mode and a low-gain image pulse signal corresponding to simultaneous exposure of sub-pixels in the pixel unit. The second exposure sampling period includes consecutive third exposure sampling periods and fourth exposure sampling periods. The first digital code value includes a first sub-digital code value and a second sub-digital code value. The counter circuit In the first reset sampling period, counts a low-gain reset pulse signal and generates a first sub-digital code value. In the second reset sampling period, counts a high-gain reset pulse signal and generates a second sub-digital code value. In the first exposure sampling period, counts the high-gain image pulse signal based on a second digital code value and stores it as a third digital code value. The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value. In the third exposure sampling period, counts the low-gain pixel group pulse signal based on the fourth digital code value and stores it as a fifth sub-digital code value. In the fourth exposure sampling period, is arranged to count the low-gain image pulse signal based on the fourth digital code value and store it as a sixth sub-digital code value. The memory circuit is connected to the counter circuit, stores the first sub-digital code value, and is arranged to be triggered by a write-back control signal to write back the first sub-digital code value to the counter circuit before the third exposure sampling period and the fourth exposure sampling period. The inversion control circuit is connected to the counter circuit and the memory circuit, is triggered by an inversion control signal before each exposure sampling period, and is controlled such that the counter circuit inverts the first sub-digital code value of the memory to generate the fourth digital code value and inverts the second sub-digital code value to generate the second digital code value. The readout circuit of the image sensor according to claim 6, characterized in that.

11. The image sensor includes a pixel array, the pixel array includes pixel units arranged in an array, the readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, the pixel unit includes four sub-pixels arranged in a 2×2 manner, and two sub-pixels form a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes consecutive first and second reset sampling periods, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a high-gain pixel group pulse signal corresponding to simultaneous exposure of the pixel group in the high-gain mode and a high-gain image pulse signal corresponding to simultaneous exposure of the sub-pixels in the pixel unit. The second pixel pulse signal includes a low-gain image pulse signal. The first exposure sampling period includes consecutive third and fourth exposure sampling periods. The first digital code value includes a first sub-digital code value and a second sub-digital code value. The counter circuit In the first reset sampling period, counts the low-gain reset pulse signal and generates a first sub-digital code value. In the second reset sampling period, counts the high-gain reset pulse signal and generates a second sub-digital code value. The third digital code value includes a third sub-digital code value and a fourth sub-digital code value. In the third exposure sampling period, counts the high-gain pixel group pulse signal based on the second digital code value and stores it as the third sub-digital code value. In the fourth exposure sampling period, counts the high-gain image pulse signal based on the second digital code value and stores it as the fourth sub-digital code value. In the second exposure sampling period, is arranged to count the low-gain image pulse signal based on the fourth digital code value and store it as the fifth digital code value. The memory circuit is connected to the counter circuit, stores the first sub-digital code value and the second sub-digital code value, and is arranged to be triggered by a write-back control signal before the fourth exposure sampling period and the second exposure sampling period to write back the second sub-digital code value and the first sub-digital code value to the counter circuit. The inversion control circuit is connected to the counter circuit and the memory circuit, and is triggered by an inversion control signal before each exposure sampling period, and is controlled such that the counter circuit inverts the second sub-digital code value of the memory to generate the second digital code value, and inverts the first sub-digital code value to generate the fourth digital code value. The readout circuit of the image sensor according to claim 6, characterized in that.

12. The counter circuit includes a first counter unit to an nth counter unit. The memory circuit includes n memory units, and each memory unit is connected to one counter unit and the inversion control circuit respectively. Each memory unit includes a first memory, a second memory, a third memory, a NAND gate, and a first 2:1 multiplexer. The input terminals of the first memory, the second memory, and the third memory are simultaneously connected to one of the counter units. The output terminal of the first memory is connected to the first input terminal of the first 2:1 multiplexer. The output terminal of the second memory is connected to the second input terminal of the first 2:1 multiplexer. The control terminal of the first 2:1 multiplexer is used to input a write-back selection signal. The output terminal of the first 2:1 multiplexer is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input the write-back control signal. The NAND gate constitutes the output terminal of the memory circuit. The first memory is used to store the corresponding 1-bit count value of the first sub-digital code value. The second memory is used to store the corresponding 1-bit count value of the second sub-digital code value. The first memory, the second memory, and the third memory further respectively store the corresponding 1-bit count values of the three digital code values after three exposure samplings. The readout circuit of the image sensor according to claim 10 or 11, characterized in that.

13. The image sensor includes a pixel array, the pixel array includes pixel units arranged in an array, the readout circuit of the image sensor is respectively connected to a plurality of pixel units arranged in a column, the pixel unit includes four sub-pixels arranged in 2×2, two sub-pixels constitute a pixel group and are controlled to output a reset signal or a pixel signal simultaneously. The reset sampling period includes a consecutive first reset sampling period and a second reset sampling period, and the at least one reset pulse signal includes a high-gain reset pulse signal and a low-gain reset pulse signal. The first pixel pulse signal includes a first pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the high-gain mode and a first image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The second pixel pulse signal includes a second pixel group pulse signal corresponding to the simultaneous exposure of the pixel group in the low-gain mode and a second image pulse signal corresponding to the simultaneous exposure of the sub-pixels in the pixel unit. The first exposure sampling period includes a consecutive third exposure sampling period and a fourth exposure sampling period. The second exposure sampling period includes a consecutive fifth exposure sampling period and a sixth exposure sampling period. The first digital code value includes a first sub-digital code value and a second sub-digital code value. The counter circuit is In the first reset sampling period, counting the low-gain reset pulse signal to generate a first sub-digital code value. In the second reset sampling period, counting the high-gain reset pulse signal to generate a second sub-digital code value. The third digital code value includes a third sub-digital code value and a fourth sub-digital code value. In the third exposure sampling period, counting the first pixel group pulse signal based on the second digital code value and storing it as the third sub-digital code value. In the fourth exposure sampling period, counting the first image pulse signal based on the second digital code value and storing it as the fourth sub-digital code value. The fifth digital code value includes a fifth sub-digital code value and a sixth sub-digital code value, During the fifth exposure sampling period, the second pixel group pulse signal is counted based on the fourth digital code value and stored as the fifth sub-digital code value, During the sixth exposure sampling period, the second image pulse signal is counted based on the fourth digital code value and stored as the sixth sub-digital code value. The memory circuit is connected to the counter circuit, stores the first sub-digital code value and the second sub-digital code value, and is triggered by a write-back control signal before the fourth exposure sampling period to write back the second sub-digital code value to the counter circuit, and is triggered by a write-back control signal before the fifth exposure sampling period and the sixth exposure sampling period to write back the first sub-digital code value to the counter circuit. The inversion control circuit is connected to the counter circuit and the memory circuit, and is triggered by an inversion control signal before each exposure sampling period, and is controlled such that the counter circuit inverts the second sub-digital code value of the memory to generate the second digital code value and inverts the first sub-digital code value to generate the fourth digital code value. The readout circuit of the image sensor according to claim 6, characterized in that.

14. The counter circuit includes a first counter unit to an nth counter unit, The memory circuit includes n memory units, and each memory unit is connected to one counter unit and the inversion control circuit respectively, Each memory unit includes a first memory, a second memory, a third memory, a fourth memory, a NAND gate, and a first 2:1 multiplexer. The input terminal of the first memory, the input terminal of the second memory, and the input terminal of the third memory are simultaneously connected to one counter unit. The output terminal of the first memory is connected to the first input terminal of the first 2:1 multiplexer. The output terminal of the second memory is connected to the second input terminal of the first 2:1 multiplexer. The control terminal of the first 2:1 multiplexer is used to input a write-back selection signal. The output terminal of the first 2:1 multiplexer is connected to the first input terminal of the NAND gate. The second input terminal of the NAND gate is used to input a write-back control signal. The NAND gate constitutes the output terminal of the memory circuit. The first memory is used to store the corresponding 1-bit count value among the first sub-digital code values. The second memory is used to store the corresponding 1-bit count value among the second sub-digital code values. The first memory, the second memory, the third memory, and the fourth memory further respectively store the corresponding 1-bit count values among the third sub-digital code value, the fourth sub-digital code value, the fifth sub-digital code value, and the sixth sub-digital code value. The readout circuit of the image sensor according to claim 13, characterized in that.

15. The counter circuit includes a first counter unit to an nth counter unit. The inversion control circuit includes n selection circuits. The first input terminal of the ith selection circuit is used to input the inversion control signal. The second input terminal of the first selection circuit is used to input a clock signal. The second input terminals of the second selection circuit to the nth selection circuit are connected to the output terminal of the (i - 1)th stage counter unit. The third input terminal of the ith selection circuit is used to input a low-level signal. The fourth input terminal of the first selection circuit is used to input the output signal of the comparison circuit. The output terminal of the ith selection circuit is connected to the input terminal of the ith stage counter unit, where i is 1, 2,..., n. The ith selection circuit is triggered by a mode selection signal and a write-back control signal to output a signal input from its first input terminal, second input terminal, or third input terminal. The readout circuit of the image sensor according to claim 6, characterized in that.

16. The first selection circuit includes an AND gate, a second 2:1 multiplexer, a third 2:1 multiplexer, and a first inverter. The first input terminal of the AND gate is used for inputting the clock signal. The second input terminal of the AND gate is used for inputting the output signal of the comparison circuit. The first input terminal of the second 2:1 multiplexer is used for inputting the inversion control signal. The output terminal of the AND gate is connected to the second input terminal of the 2:1 multiplexer. The second input terminal of the second 2:1 multiplexer is used for inputting the low-level signal. The control terminal of the second 2:1 multiplexer is connected to the output terminal of the storage circuit. The output terminal of the second 2:1 multiplexer is connected to the first input terminal of the third 2:1 multiplexer. The second input terminal of the third 2:1 multiplexer is used for inputting a numerical value output from the clock signal or the previous counter unit. The control terminal of the third 2:1 multiplexer is used for inputting the mode selection signal. The output terminal of the third 2:1 multiplexer is connected to the input terminal of the first inverter. The output terminal of the first inverter is used for outputting a signal that outputs a corresponding signal among the inversion control signal, the clock signal, and the low-level signal. The second selection circuit to the nth selection circuit each include a second 2:1 multiplexer, a third 2:1 multiplexer, and a first inverter. The first input terminal of the second 2:1 multiplexer is used for inputting the inversion control signal. The second input terminal of the second 2:1 multiplexer is used for inputting the low-level signal. The control terminal of the second 2:1 multiplexer is connected to the output terminal of the storage circuit. The output terminal of the second 2:1 multiplexer is connected to the first input terminal of the third 2:1 multiplexer. The second input terminal of the third 2:1 multiplexer is used for inputting a numerical value output from the clock signal or the previous counter unit. The control terminal of the third 2:1 multiplexer is used for inputting the mode selection signal. The output terminal of the third 2:1 multiplexer is connected to the input terminal of the first inverter. The output terminal of the first inverter is used for outputting a corresponding one of the signals among the inversion control signal, the clock signal, the low-level signal, and the numerical value output from the previous counter unit. The readout circuit of the image sensor according to claim 15, characterized in that...

17. Each counter unit includes a D flip-flop and a second inverter. The clock signal terminal of the D flip-flop of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop of the i-th stage counter unit is connected to the input terminal of the second inverter and the data input terminal of the D flip-flop. The output terminal of the second inverter is connected to the second input terminal of the (i + 1)-th selection circuit. The readout circuit of the image sensor according to claim 3 or 15, characterized in that...

18. Each counter unit includes a D flip-flop. The clock signal terminal of the D flip-flop of the i-th stage counter unit is connected to the signal output terminal of the i-th selection circuit. The inverted output terminal of the D flip-flop of the i-th stage counter unit is connected to the data input terminal of the D flip-flop. The non-inverted output terminal of the D flip-flop is connected to the second input terminal of the (i + 1)-th selection circuit. The readout circuit of the image sensor according to claim 3 or 15, characterized in that...

19. An image sensor, comprising: The image sensor includes a pixel array including a plurality of pixel units arranged in an array, a control circuit, and a readout circuit of the image sensor according to claim 1. Each readout circuit of the image sensor is connected to a plurality of pixel units arranged in a column, and each readout circuit of the image sensor is further connected to the control circuit. An image sensor, characterized in that...

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