Design of Photonic Integrated Circuits Based on Arrays of Inversely Designed Components

Abstract

In some embodiments, a method for designing a photonic device is provided. **Solution**: The design optimization system receives an initial design of a photonic device. The initial design includes one or more inputs, one or more outputs, several sub-component regions, and several waveguides for connecting the sub-component regions. The design optimization system simulates each sub-component region to determine the simulated s-parameters of each sub-component region. The design optimization system determines the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each sub-component region and the s-parameters of the waveguides. The design optimization system determines the overall gradient associated with the overall s-parameters. The design optimization system optimizes one or more sub-component regions based on the overall gradient to create an updated design of the photonic device.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the priority of U.S. Patent Application No. 17 / 828,864, filed on May 31, 2022, the content of which is incorporated herein by reference.

[0002] (Field of the Invention) This disclosure generally relates to photonic devices, and in particular, but not exclusively, to photonic integrated circuits, photonic multiplexers, and photonic demultiplexers.

Background Art

[0003] Optical fiber communication is typically used to transmit information from one location to another via light that is modulated to carry the information. For example, many telecommunications companies use optical fibers to transmit telephone signals, Internet communications, and cable television signals. However, the cost of deploying optical fibers for optical fiber communication can be exorbitant. Therefore, technologies have been developed to more efficiently use the bandwidth available within a single optical fiber. Wavelength - division multiplexing is one such technology that uses different wavelengths to bundle multiple optical carrier signals onto a single optical fiber.

[0004] Furthermore, digital logic has historically been implemented by constructing logic circuits from conductors and other electrical components. Other technologies have been sought to increase speed, increase efficiency, and reduce the size of digital logic. One such technology is the use of photonic devices to form photonic integrated circuits that operate on light instead of electricity to form logic circuits.

Summary of the Invention

[0005] In some embodiments, a non-transitory computer-readable medium is provided. Logic is stored on the computer-readable medium, and the logic causes the computing system to perform actions for designing a photonic device in response to execution by one or more processors of the computing system. These actions include receiving, by a design optimization system, an initial design of a photonic device, where the initial design includes one or more inputs, one or more outputs, several sub-component regions, and several waveguides for connecting the sub-component regions; simulating, by the design optimization system, each sub-component region to determine simulated s-parameters for each sub-component region; determining, by the design optimization system, an overall s-parameter of the simulated photonic device based on the simulated s-parameters of each sub-component region and the s-parameters of the waveguides; determining, by the design optimization system, an overall gradient associated with the overall s-parameter; and optimizing, by the design optimization system, one or more sub-component regions based on the overall gradient to create an updated design of the photonic device.

[0006] In some embodiments, a method for designing a photonic device is provided. A design optimization system receives an initial design of a photonic device. The initial design includes one or more inputs, one or more outputs, several sub-component regions, and several waveguides for connecting the sub-component regions. The design optimization system simulates each sub-component region to determine the simulated s-parameters of each sub-component region. The design optimization system determines the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each sub-component region and the s-parameters of the waveguides. The design optimization system determines the overall gradient associated with the overall s-parameters. The design optimization system optimizes one or more sub-component regions based on the overall gradient to create an updated design of the photonic device.

Brief Description of the Drawings

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, and like reference numerals refer to like parts throughout the various figures unless otherwise specified. Not all instances of elements are necessarily labeled so as not to clutter the drawings where appropriate. The drawings are not necessarily to scale and instead focus on illustrating the principles being described. To readily identify any particular element or action, the most significant digit(s) in the reference numeral refers to the figure number in which that element is first introduced.

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[0008] In the context of generating designs of photonic integrated circuits (including, but not limited to, multi-channel photonic demultiplexers, multi-channel photonic multiplexers, and photonic logic devices), embodiments of techniques for inverse design of physical devices are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown in detail or described in order to avoid obscuring certain aspects.

[0009] Throughout this specification, the phrase "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0010] Wavelength division multiplexing and its variations (e.g., dense wavelength division multiplexing, coarse wavelength division multiplexing, etc.) utilize the bandwidth of an optical fiber by bundling a plurality of optical carrier signals onto a single optical fiber. When the plurality of carrier signals are bundled together, they are transmitted from one location to another via the single optical fiber, where they can be demultiplexed so as to be read out by an optical communication device. However, devices for separating carrier signals from each other are still prohibitively expensive in terms of cost, size, etc.

[0011] Furthermore, the design of photonic devices such as those used in optical communications has traditionally been designed through conventional techniques where it may be determined through simple guesswork and checking methods or manually guided grid searches in which a few design parameters from a given design or building block are adjusted for suitability for a particular application. However, in reality, these devices can have design parameters ranging from hundreds to over billions depending on the device size and functionality. Thus, as the functionality of photonic devices increases and manufacturing tolerances improve to enable smaller device feature sizes, it becomes increasingly important to fully utilize these improvements through optimized device designs.

[0012] Techniques for the inverse design of photonic integrated circuits (e.g., multi-channel photonic demultiplexers and / or multiplexers and / or logic devices) are described herein. More specifically, the techniques described in the embodiments herein utilize gradient-based optimization in combination with first-principles simulations to generate a design from an understanding of the underlying physics expected to govern the operation of the photonic integrated circuit. The embodiments and techniques described herein are not limited to the conventional techniques used in the design of photonic devices, where a small number of design parameters of a given building block are adjusted based on suitability for a particular application. Rather, the first-principles-based design described herein does not necessarily rely on human intuition and can generally result in a design that outperforms current state-of-the-art designs in terms of performance, size, robustness, or combinations thereof. Further, the embodiments and techniques described herein provide a scalable optimization of a nearly unlimited number of design parameters, rather than being limited to a small number of design parameters due to conventional techniques. Although the design and manufacture of photonic integrated circuits are described throughout this specification, it will also be understood that similar inverse design techniques can be used to generate designs for other types of physical devices.

[0013] Providing a large design space with a large number of design parameters can increase the diversity of functions achievable through the inverse design of photonic devices, but it should be noted that as the number of design parameters increases, the amount of computing power consumed to simulate performance and update the design increases rapidly. In some embodiments of the present disclosure, techniques are provided for dividing a large design space into smaller sub-components that can be simulated in parallel, thereby significantly reducing the amount of computing power consumed and reducing the amount of time required to optimize the design.

[0014] FIG. 1 is a functional block diagram illustrating a system 100 for optical communication (e.g., via wavelength division multiplexing or other techniques) between an optical communication device 102 and an optical communication device 120 via an optical signal 110, according to various aspects of the present disclosure. More generally, the optical communication device 102 is configured to transmit information by modulating light from one or more light sources into a multi-channel optical signal 110 (e.g., a single optical signal including a plurality of distinct wavelength channels), and this multi-channel optical signal is then transmitted from the optical communication device 102 to the optical communication device 120 via an optical fiber, an optical waveguide, a waveguide, or other photonic device. The optical communication device 120 receives the multi-channel optical signal 110 and demultiplexes each of the plurality of distinct wavelength channels from the multi-channel optical signal 110 to extract the transmitted information. In some embodiments, it is understood that the optical communication device 102 and the optical communication device 120 can be separate individual devices (e.g., an optical transceiver or transmitter is communicatively coupled to a separate optical transceiver or receiver via one or more optical fibers). However, in other embodiments, it is understood that the optical communication device 102 and the optical communication device 120 can be part of a single component or device (e.g., a smartphone, a tablet, a computer, an optical device, etc.). For example, both the optical communication device 102 and the optical communication device 120 can be embedded within a monolithic integrated circuit and be components on the monolithic integrated circuit that are coupled to each other via a waveguide adapted to carry the optical signal 110 between the optical communication device 102 and the optical communication device 120 or otherwise transmit the optical signal between one location and another. Further, in other embodiments, at least one of the optical communication device 102 and the optical communication device 120 can implement logic other than or in addition to wavelength multiplexing or demultiplexing.

[0015] In the illustrated embodiment, the optical communication device 102 includes a controller 104, one or more interface devices 112 (e.g., optical fiber couplers, optical waveguides, waveguides, etc.) coupled to each other, a multiplexer (mux), a demultiplexer (demux), or a combination thereof (MUX / DEMUX 114), one or more light sources 116 (e.g., light emitting diodes, lasers, etc.), and one or more optical sensors 118 (e.g., photodiodes, phototransistors, photoreceptors, etc.). The controller includes one or more processors 106 (e.g., one or more central processing units, application specific circuits, field programmable gate arrays, or others) and a memory 108 (e.g., volatile memory such as DRAM and SAM, non-volatile memory such as ROM, flash memory, etc.). It is understood that the optical communication device 120 may include elements the same as or similar to those of the optical communication device 102, which are omitted for clarity.

[0016] The controller 104 adjusts the operation of the optical communication device 102 to transmit and / or receive an optical signal 110 (e.g., a multi-channel optical signal having a plurality of separate wavelength channels or others). The controller 104 includes software (e.g., instructions included in the memory 108 coupled to the processor 106) and / or hardware logic (e.g., application specific integrated circuits, field programmable gate arrays, etc.) that, when executed by the controller 104, cause operations to be performed on the controller 104 and / or the optical communication device 102.

[0017] In one embodiment, the controller 104 may allocate the operations of the optical communication device 102 to cause the light source 116 to generate a plurality of distinct wavelength channels, which are multiplexed into a multi-channel optical signal 110 via the MUX / DEMUX 114, and the multi-channel optical signal is then transmitted to the optical communication device 120 via the interface device 112. In other words, the light source 116 may output light having different wavelengths (e.g., 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1506 nm, 1514 nm, 1551 nm, 1571 nm or another one) that can be modulated or pulsed via the controller 104 to generate a plurality of distinct wavelength channels representing information. The plurality of distinct wavelength channels are then combined or otherwise multiplexed into the multi-channel optical signal 110 that is transmitted to the optical communication device 120 via the interface device 112 via the MUX / DEMUX 114. In the same or another embodiment, the controller 104 may allocate the operations of the optical communication device 102 such that a plurality of distinct wavelength channels are demultiplexed from the multi-channel optical signal 110 received from the optical communication device 120 via the interface device 112 via the MUX / DEMUX 114.

[0018] In some embodiments, it is understood that certain elements of the optical communication device 102 and / or the optical communication device 120 may be omitted to avoid obscuring some aspects of the present disclosure. For example, the optical communication device 102 and the optical communication device 120 may include amplification circuits, lenses, or components to facilitate the transmission and reception of the optical signal 110. Further, in some embodiments, it is understood that the optical communication device 102 and / or the optical communication device 120 may not necessarily include all of the elements illustrated in FIG. 1. For example, in one embodiment, the optical communication device 102 and / or the optical communication device 120 is a passive device that operates as an intermediate device that can passively multiplex a plurality of distinct wavelength channels into the multi-channel optical signal 110 and / or demultiplex a plurality of distinct wavelength channels from the multi-channel optical signal 110.

[0019] Figures 2A and 2A each illustrate an exemplary demultiplexer 206 and multiplexer 208 according to various aspects of the present disclosure. The demultiplexer 206 and multiplexer 208 are possible embodiments of the MUX / DEMUX 114 illustrated in FIG. 1 and may be part of an integrated photonic circuit, a silicon photonic device, or others.

[0020] As illustrated in FIG. 2A, the demultiplexer 206 includes an input region 202 and a plurality of output regions 204. The demultiplexer 206 receives a multi-channel optical signal 110 including a plurality of distinct wavelength channels (e.g., Ch.1, Ch.2, Ch.3,...Ch.N each having a center wavelength corresponding to λ1, λ2, λ3,...λN respectively) through the input region 202 (e.g., a waveguide that may correspond to the interface device 112 illustrated in FIG. 1), optically separates each of the plurality of distinct wavelength channels from the multi-channel optical signal 110, and is configured to guide each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 204 (e.g., a plurality of waveguides that may correspond to the interface device 112 illustrated in FIG. 1). More specifically, in the illustrated embodiment, each of the output regions 204 receives one of the plurality of distinct wavelength channels that can be output as a plurality of optical signals (e.g., λ1, λ2, λ3,...λ N ) or a portion of the multi-channel optical signal representing the same. Each of the plurality of output regions 204 may be coupled to a respective optical sensor (e.g., corresponding to the optical sensor 118 illustrated in FIG. 1), and the optical sensor may be utilized to convert the optical signal demultiplexed from the multi-channel optical signal 110 into an electrical signal for further processing.

[0021] In the illustrated embodiment of FIG. 2B, the multiplexer 208 includes a plurality of input regions 216 and an output region 210. The multiplexer 208 includes a plurality of distinct optical signals (e.g., λ1, λ2, λ3,...λ N) are each configured to be received by one of a plurality of input regions 216 (e.g., a plurality of waveguides that may correspond to the interface device 112 illustrated in FIG. 1). The multiplexer 208 is structured to optically couple (i.e., multiplex) each of a plurality of distinct wavelength channels to a multi-channel optical signal 110 guided to an output region 210 (e.g., a waveguide that may correspond to the interface device 112 illustrated in FIG. 1), or is otherwise configured. In some embodiments, it is understood that the demultiplexer 206 illustrated in FIG. 2A and the multiplexer 208 illustrated in FIG. 2B can be bidirectional such that each device can function as both a demultiplexer and a multiplexer.

[0022] FIG. 2C illustrates exemplary distinct wavelength channels of a multi-channel optical signal in accordance with various aspects of the present disclosure (e.g., Ch.N is the multi-channel optical signal 110 illustrated in FIGS. 1, 2A, and 2B). The exemplary channels can represent individual channels included in a plurality of distinct wavelength channels of a multi-channel optical signal that can be demultiplexed and / or multiplexed by the demultiplexer 206 of FIG. 2A and / or the multiplexer 208 of FIG. 2B. Each of the distinct wavelength channels includes at least one of 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1506 nm, 1514 nm, 1551 nm, or 1571 nm, or other different center wavelengths (λ N) may have. In the illustrated embodiment of FIG. 2C, a separate wavelength channel has a channel bandwidth 212 of approximately 13 nm width. However, in other embodiments, the channel bandwidth may differ from the 13 nm width. Rather, the channel bandwidth may be considered a configurable parameter depending on the structure of the MUX / DEMUX 114 of FIG. 1, the demultiplexer 206 of FIG. 2A, and / or the multiplexer 208 of FIG. 2B. For example, in some embodiments, each of a plurality of separate wavelength channels may share a common bandwidth that may correspond to 13 nm or other values. Referring again to FIG. 2C, the channel bandwidth 212 may be defined as the width of the passband region 218 (i.e., defined as being between PB1 and PB2). The passband region 218 may represent the approximate power transmission of the demultiplexer or multiplexer. It is understood that in some embodiments, the passband region 218 may include ripples as illustrated in FIG. 2C that correspond to variations within the passband region 218. In one or more embodiments, the ripple within the passband region around the center value 214 may be + / -2 dB or less, + / -1 dB or less, + / -0.5 dB or less, or other values. In some embodiments, the channel bandwidth 212 may be defined by the passband region 218. In other embodiments, the channel bandwidth 212 may be defined as the measured power above a threshold (e.g., dB th ). For example, the demultiplexer 206 illustrated in FIG. 2A optically separates channel N from the multi-channel optical signal 110 and corresponds to the channel bandwidth of channel N equal to the range of wavelengths above the threshold that are transmitted to the output region 204 mapped to channel N (i.e., λ N) may have. In the same or other embodiments, when optimizing the design, the isolation of the channel (i.e., defined by the channel bandwidth 212) may also be considered. The isolation may be defined as the ratio between the passband region 218 and the stopband region (e.g., the region smaller than SB1 and larger than SB2). The transition band regions (e.g., the first transition region between SB1 and PB1, and the second transition region between PB2 and SB2) are exemplary and it should be further understood that they may be exaggerated for illustrative purposes. In some embodiments, the optimization of the design of the photonic demultiplexer may also include target metrics such as the gradient and width of the transition band region.

[0023] Figures 3A - 3D illustrate different views of an exemplary photonic demultiplexer according to an embodiment of the present disclosure. The photonic demultiplexer 316 is one possible implementation of the MUX / DEMUX 114 illustrated in FIG. 1 and the demultiplexer 206 illustrated in FIG. 2A. The following discussion may be directed to photonic integrated circuits capable of demultiplexing a plurality of distinct wavelength channels from a multi - channel optical signal, but in other embodiments, according to embodiments of the present disclosure, the demultiplexer (e.g., demultiplexer 316) may also or alternatively be capable of multiplexing a plurality of distinct wavelength channels into a multi - channel optical signal. Similarly, other embodiments may implement functions other than multiplexing / demultiplexing, including but not limited to digital logic.

[0024] FIG. 3A illustrates a cross-sectional view of the demultiplexer 316 along a transverse plane within the active layer defined by the width 320 and length 322 of the demultiplexer 316. As illustrated, the demultiplexer 316 includes an input region 302 (e.g., corresponding to the input region 202 illustrated in FIG. 2A), a plurality of output regions 304 (e.g., corresponding to the plurality of output regions 204 illustrated in FIG. 2A), and a dispersion region optically disposed between the input region 302 and the plurality of output regions 304. The input region 302 and the plurality of output regions 304 (e.g., output region 308, output region 310, output region 312, and output region 314) can each be a waveguide (e.g., a slab waveguide, a strip waveguide, a slot waveguide, etc.) capable of propagating light along a path of the waveguide. The dispersion region 332 includes a first material and a second material that are unevenly scattered so as to form a plurality of interfaces that collectively structure the dispersion region 332 such that each corresponds to a change in the refractive index of the dispersion region 332 and optically separates each of a plurality of distinct wavelength channels (e.g., Ch.1, Ch.2, Ch.3,...Ch.N illustrated in FIG. 2A) from a multi-channel optical signal (e.g., the optical signal 110 illustrated in FIG. 2A) when the input region 302 receives the multi-channel optical signal and guides each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 304. In other words, the input region 302 is adapted to receive a multi-channel optical signal including a plurality of distinct wavelength channels, and each of the plurality of output regions 304 is adapted to receive a corresponding one of the plurality of distinct wavelength channels demultiplexed from the multi-channel optical signal via the dispersion region 332.

[0025] As illustrated in FIG. 3A and more clearly shown by FIGS. 3D and 4A - 4B, the shapes and arrangements of the non - uniformly dispersed first and second materials create a plurality of interfaces that collectively form a material interface pattern along the cross - sectional area of a dispersion region 332 that is at least partially surrounded by a peripheral region 318 that includes the second material. In some embodiments, the peripheral region 318 has a substantially homogeneous composition that includes the second material. In the illustrated embodiment, the dispersion region 332 includes a first side 328 and a second side 330, each having an inner boundary (i.e., an unlabeled dashed line of the peripheral region 318 disposed between the dispersion region 332 and the dashed line corresponding to the outer boundary of the peripheral region 318) and an interface. The first side 328 and the second side 330 are disposed corresponding to opposite side surfaces of the dispersion region 332. The input region 302 is disposed proximate to the first side 328 (e.g., one side of the input region 302 abuts the first side 328 of the dispersion region 332), while each of the plurality of output regions 304 is disposed proximate to the second side 330 (e.g., one side of each of the plurality of output regions 304 abuts the second side 330 of the dispersion region 332).

[0026] In the illustrated embodiment, each of the plurality of output regions 304 is parallel to one of the others of the plurality of output regions 304. However, in other embodiments, the plurality of output regions 304 may not be parallel to each other or may not be disposed on the same side (e.g., one or more of the plurality of output regions 304 and / or the input region 302 may be disposed proximate to a side of the dispersion region 332 adjacent to the first side 328 and / or the second side 330). In some embodiments, when the plurality of output regions includes at least three output regions, adjacent ones of the plurality of output regions are separated from each other by a common separation distance. For example, as illustrated, adjacent output regions 308 and output region 310 are separated from each other by a distance 306, which may be common to the separation distances between other pairs of adjacent output regions.

[0027] As illustrated in the embodiment of FIG. 3A, the demultiplexer 316 includes four output regions 304 (e.g., output region 308, output region 310, output region 312, output region 314), each of which is mapped (i.e., by the structure of the dispersion region 332) to one of four channels included in a plurality of distinct wavelength channels. More specifically, a plurality of interfaces of the dispersion region 332 defined by the non-uniform interspersion of the first and second materials form a material interface pattern along the cross-sectional area of the dispersion region 332 (e.g., as shown in FIGS. 3A, 4A, or 4B), such that when the input region 302 divides the multi-channel optical signal into regions, each of the four channels is optically separated from the multi-channel optical signal in the dispersion region 332 and each of the four channels is routed to one of the four output regions 304.

[0028] Note that the first and second materials of the dispersion region 332 are arranged and shaped within the dispersion region such that the material interface pattern is substantially proportional to the design obtained in the inverse design process. The inverse design process will be discussed in more detail later in this disclosure. More specifically, in some embodiments, the inverse design process includes an iterative gradient-based optimization of the design based at least in part on a loss function that incorporates performance loss (e.g., reduced or otherwise adjusted via iterative gradient-based optimization to implement a function) and manufacturing loss (e.g., for implementing manufacturability and binarization of the first and second materials). In the same or other embodiments, other optimization techniques may be used instead of or in addition to the gradient-based optimization. Advantageously, this enables the optimization of a nearly unlimited number of design parameters to achieve functionality and performance within a given area that may not have been possible with conventional design techniques.

[0029] For example, in one embodiment, the dispersion region 332 is structured to optically separate each of the four channels from the multi-channel optical signal within a predetermined area of 35 μm × 35 μm (e.g., as defined by the width 324 and length 326 of the dispersion region 332) when the input region 302 receives the multi-channel optical signal. In the same or another embodiment, the dispersion region is structured to accommodate a common bandwidth for each of the four channels, and each of the four channels has a different center wavelength. In one embodiment, the common bandwidth is about 13 nm wide, and the different center wavelengths are selected from the group consisting of 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1506 nm, 1514 nm, 1551 nm, and 1571 nm. In some embodiments, the overall structure of the demultiplexer 316 (e.g., including the input region 302, the peripheral region 318, the dispersion region 332, and the plurality of output regions 304) fits within a predetermined area (e.g., as defined by the width 320 and length 322). In one embodiment, the predetermined area is 35 μm × 35 μm. In other embodiments, the dispersion region 332 and / or the demultiplexer 316 can fit within other areas larger or smaller than 35 μm × 35 μm, which is understood to result in changes to the structure of the dispersion region 332 (e.g., the arrangement and shape of the first and second materials and / or other components of the demultiplexer 316).

[0030] In the same or other embodiments, the dispersion region is structured to have a power transmission of -2 dB or more from the input region 302 through the dispersion region 332 to the corresponding one of the plurality of output regions 304 for a given wavelength of one of the plurality of distinct wavelength channels. For example, when channel 1 of a multi-channel optical signal is mapped to output region 308, when the demultiplexer 316 receives the multi-channel optical signal in the input region 302, the dispersion region 332 optically separates channel 1 from the multi-channel optical signal and guides a portion of the multi-channel optical signal corresponding to channel 1 to the output region 308 with a power transmission of -2 dB or more. In the same or another embodiment, the dispersion region 332 is structured such that the adverse power transmission (i.e., isolation) for a given wavelength to any of the plurality of output regions other than the corresponding one of the plurality of output regions from the input region is -30 dB or less, -22 dB or less, or other. For example, when channel 1 of a multi-channel optical signal is mapped to output region 308, the adverse power transmission from the input region 302 to any other one of the plurality of output regions (e.g., output region 310, output region 312, output region 314) other than the corresponding one (e.g., output region 308) of the plurality of output regions is -30 dB or less, -22 dB or less, or other. In some embodiments, the maximum power reflection from the demultiplexer 316 of the input signal (e.g., the multi-channel optical signal) received in the input region (e.g., input region 302) is reflected back to the input region by the dispersion region 332 or, otherwise, is -40 dB or less, -20 dB or less, -8 dB or less, or other. In other embodiments, the power transmission, adverse power transmission, maximum power, or other performance characteristics may be different from the respective values discussed herein, and it is understood that the structure of the dispersion region 332 may vary due to the inherent relationship between the structure, function, and performance of the demultiplexer 316.

[0031] FIG. 3B illustrates a vertical schematic or stack of various layers included in an exemplary embodiment of the demultiplexer 316. However, it is understood that the exemplary embodiments are not exhaustive and that certain features or elements may be omitted to avoid obscuring particular aspects of the invention. In the exemplary embodiment, the demultiplexer 316 includes a substrate 334, a dielectric layer 336, an active layer 338 (such as shown in the cross-sectional view of FIG. 3A), and a cladding layer 340. In some embodiments, the demultiplexer 316 may be a photonic integrated circuit or a silicon photonic device that is compatible, in part or otherwise, with conventional manufacturing techniques (such as lithography techniques like photolithography, electron beam lithography, etc., sputtering, thermal evaporation, physical and chemical vapor deposition, etc.).

[0032] In one embodiment, a silicon on insulator (SOI) wafer may be first provided, which includes a support substrate corresponding to substrate 334 (e.g., a silicon substrate), a silicon dioxide dielectric layer corresponding to dielectric layer 336, a silicon layer (e.g., intrinsic, doped, or otherwise), and an oxide layer (e.g., intrinsic, grown, or otherwise). In one embodiment, the silicon in active layer 338 may be selectively etched by lithographically creating on the SOI wafer a pattern that is transferred through a dry etching process (e.g., via a photoresist mask or other hard mask) to remove portions of the silicon. The silicon may be etched all the way to dielectric layer 336 to form voids, which may then be backfilled with silicon dioxide, which is then encapsulated with silicon dioxide to form cladding layer 340. In one embodiment, there may be several etch depths, including the complete etch depth of the silicon, to obtain the target structure. In one embodiment, the silicon may be 206 nm thick, and thus the complete etch depth may be 206 nm. In some embodiments, this may be a two-step encapsulation process that is done with intermediate chemical mechanical planarization where two silicon dioxide depositions are used to provide a flat surface.

[0033] FIG. 3C illustrates a more detailed view of active layer 338 (with respect to FIG. 3B) along a portion of peripheral region 318 that includes input region 302 of FIG. 3A. In the illustrated embodiment, active layer 338 includes a first material 342 having a refractive index of ε1 and a second material 344 having a refractive index of ε2 that is different from ε1. Homogeneous regions of the first material 342 and the second material 344 may form waveguides or portions of waveguides corresponding to input region 302 and the plurality of output regions 304, as illustrated in FIGS. 3A and 3C.

[0034] FIG. 3D illustrates a more detailed view of the active layer 338 (with respect to FIG. 3B) along the dispersion region 332. As described above, the active layer 338 includes a first material 342 (e.g., silicon) and a second material 344 (e.g., silicon dioxide) that are non-uniformly scattered to form a plurality of interfaces 346 that collectively form a material interface pattern. Each of the plurality of interfaces 346 that form the interface pattern structures the dispersion region (i.e., the shape and arrangement of the first material 342 and the second material 344) corresponding to the change in the refractive index of the dispersion region 332 to at least partially provide the function of the demultiplexer 316 (i.e., when the input region 302 receives a multi-channel optical signal, the optical separation of a plurality of distinct wavelength channels from the multi-channel optical signal and the respective guiding of each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 304).

[0035] As shown in FIGS. 3A - 3D, in the illustrated embodiment of the demultiplexer 316, the change in refractive index is shown as being consistent in the vertical direction (i.e., it is understood that the first material 342 and the second material 344 form interfaces that are substantially perpendicular or at right angles to the horizontal plane or cross-section of the demultiplexer 316. However, in the same or other embodiments, the plurality of interfaces (e.g., the interfaces 346 illustrated in FIG. 3D) may not be substantially perpendicular to the horizontal plane or cross-section of the demultiplexer 316.

[0036] FIG. 4A illustrates a more detailed cross-sectional view of the dispersion region of an exemplary photonic demultiplexer 400 according to an embodiment of the present disclosure. FIG. 4B illustrates a more detailed view of the interface pattern formed by the shape and arrangement of the first material 410 and the second material 412 for the dispersion region of the photonic demultiplexer 400 of FIG. 4A. The photonic demultiplexer 400 is one possible implementation of the MUX / DEMUX 114 illustrated in FIG. 1, the demultiplexer 206 illustrated in FIG. 2A, and the demultiplexer 316 illustrated in FIGS. 3A - 3D.

[0037] As illustrated in FIGS. 4A and 4B, the photonic demultiplexer 400 includes an input region 402, a plurality of output regions 404a-404d, and a dispersion region 406 optically disposed between the input region 402 and the plurality of output regions 404a-404d. The dispersion region 406 is at least partially surrounded by a peripheral region 408 including an inner boundary 414 and an outer boundary 416. It is understood that like-named or labeled elements of the photonic demultiplexer 400 may similarly correspond to like-named or labeled elements of other demultiplexers described in embodiments of the present disclosure.

[0038] The first material 410 (i.e., the black region within the dispersion region 406) and the second material 412 (i.e., the white region within the dispersion region 406) of the photonic demultiplexer 400 are non-uniformly scattered to create a plurality of interfaces that collectively form a material interface pattern 420 as illustrated in FIG. 4B. More specifically, an inverse design process that utilizes iterative gradient-based optimization, Markov chain Monte Carlo optimization, or other optimization techniques is combined with first-principles simulations to generate a design that is substantially replicated by the dispersion region 406 in a proportional or scaled manner such that the photonic demultiplexer 400 provides the desired functionality. In the illustrated embodiment, the dispersion region 406 is structured to optically separate each of a plurality of distinct wavelength channels from a multi-channel optical signal and guide each of the plurality of distinct wavelength channels to a corresponding one of the plurality of output regions 404a-404d when the input region 402 receives the multi-channel optical signal. More specifically, the plurality of output regions 404a-404d are each mapped to wavelength channels having center wavelengths corresponding to 1271 nm, 1291 nm, 1311 nm, and 1331 nm. In another embodiment, the output regions 404a-404d are each mapped to wavelength channels having center wavelengths corresponding to 1506 nm, 1514 nm, 1551 nm, and 1571 nm.

[0039] As illustrated in FIG. 4B, a material interface pattern 420 defined by the black lines within the dispersion region 406 and corresponding to the change in refractive index within the dispersion region 406 includes a plurality of protrusions 422a and 422b. The first protrusion 422a is formed from the first material 410 and extends from the peripheral region 408 into the dispersion region 406. Similarly, the second protrusion 422b is formed from the second material 412 and extends from the peripheral region 408 into the dispersion region 406. As further illustrated in FIG. 4B, the dispersion region 406 includes a plurality of islands 424a and 424b formed from either the first material 410 or the second material 412. The plurality of islands 424a and 424b includes a first island 424a formed from the first material 410 and surrounded by the second material 412. The plurality of islands 424a and 424b also includes a second island 424b formed from the second material 412 and surrounded by the first material 410.

[0040] In some embodiments, the material interface pattern 420 includes one or more dendritic shapes, each of the one or more dendritic shapes being formed from the first material 410 or the second material 412 and defined as a branching structure having a width that alternately increases and decreases in size along a corresponding direction. Referring back to FIG. 4A, for clarity, the dendritic structure 418 has a black boundary and is labeled with white arrows. As can be seen, the width of the dendritic structure 418 alternatively increases and decreases in size along the corresponding direction (i.e., the white arrow overlapping the length of the dendritic structure 418) to create a branching structure. In other embodiments, it is understood that there may be no protrusions, no islands, no dendritic structures, or any number of protrusions, islands of any material included in the dispersion region 406, dendritic structures, or combinations thereof, including zero.

[0041] In some embodiments, the inverse design process includes manufacturing losses implementing a minimum feature size to ensure manufacturability of the design. In an exemplary embodiment of the photonic demultiplexer 400 illustrated in FIGS. 4A and 4B, the material interface pattern 420 is shaped to implement a minimum feature size within the dispersion region 406 such that a plurality of interfaces within the cross-sectional area formed by the first material 410 and the second material 412 do not have a radius of curvature less than a threshold size. For example, if the minimum feature size is 150 nm, the radius of curvature for any of the plurality of interfaces has a size less than the threshold size corresponding to the reciprocal of half of the minimum feature size (i.e., 1 / 75 nm -1 ). Implementing such a minimum feature size prevents the inverse design process from generating a design that is not manufacturable by taking into account manufacturing constraints, limitations, and / or yields. In the same or other embodiments, different or additional checks on metrics related to manufacturability may be utilized to implement a minimum width or spacing as the minimum feature size.

[0042] FIG. 5 is a functional block diagram illustrating a system 500 for generating a design of a photonic integrated circuit (i.e., a photonic device) according to an embodiment of the present disclosure. The system 500 can be utilized to perform an inverse design process that generates a design using iterative gradient-based optimization that takes into account the underlying physics governing the operation of the photonic integrated circuit. More specifically, the system 500 is a design tool that can be utilized to optimize the structural parameters of a photonic integrated circuit (e.g., the shape and arrangement of the first and second materials within the dispersion region of the embodiments in the present disclosure) based on first-principles simulations (e.g., electromagnetic simulations for determining the field response of a photonic device to an excitation source) and iterative gradient-based optimization. In other words, the system 500 can provide a design obtained by an inverse design process that is substantially replicated (i.e., scaled proportionally) by the dispersion regions 332 and 406 of the demultiplexer 316 and the photonic demultiplexer 400 illustrated in FIGS. 3A and 4A, respectively.

[0043] As illustrated, system 500 includes a controller 512, a display 502, an input device 504, a communication device 506, a network 508, a remote resource 510, a bus 534, and a bus 520. Controller 512 includes a processor 514, a memory 516, a local storage 518, and a photonic device simulator 522. Photonic device simulator 522 includes an operation simulation engine 526, a manufacturing loss calculation logic 528, a calculation logic 524, an adjoint simulation engine 530, and an optimization engine 532. It is understood that in some embodiments, controller 512 may be a distributed system.

[0044] Controller 512 is coupled to a display 502 (e.g., a light emitting diode display, a liquid crystal display, etc.) coupled to bus 534 through bus 520 to display information to a user who utilizes system 500 to optimize the structural parameters of a photonic device (i.e., a demultiplexer). Input device 504 is coupled to bus 534 through bus 520 to communicate information and command selections to processor 514. Input device 504 may include a mouse, a trackball, a keyboard, a stylus, or other computer peripherals to facilitate interaction between the user and controller 512. In response, controller 512 can provide verification of the interaction through display 502.

[0045] Another device that can optionally be coupled to controller 512 is communication device 506 for accessing remote resources 510 of the distributed system via network 508. Communication device 506 can include any of several networking peripheral devices, such as those used to couple to Ethernet, the Internet, or a wide area network. Communication device 506 can further include a mechanism for providing connectivity between controller 512 and the outside world. Note that any or all of the components of system 500 and related hardware illustrated in FIG. 5 can be used in various embodiments of the present disclosure. Remote resource 510 can be part of the distributed system and can include any number of processors, memories, and other resources for optimizing the structural parameters of photonic devices.

[0046] Controller 512 orchestrates the operation of system 500 for optimizing the structural parameters of photonic devices. Processor 514 (e.g., one or more central processing units, graphics processing units, and / or tensor processing units, etc.), memory 516 (e.g., volatile memory such as DRAM and SRAM, non-volatile memory such as ROM, flash memory, etc.), local storage 518 (e.g., magnetic memory such as a computer disk drive), and photonic device simulator 522 are coupled to each other through bus 520. Controller 512 includes software (e.g., instructions included in memory 516 coupled to processor 514) and / or hardware logic (e.g., application specific integrated circuit, field programmable gate array, etc.) that causes controller 512 or system 500 to perform an operation when executed by controller 512. The operation can be based on instructions stored in any one or a combination of memory 516, local storage 518, physical device simulator 522, and remote resource 510 accessed through network 508.

[0047] In the illustrated embodiment, the components of the photonic device simulator 522 are utilized to optimize the structural parameters of a photonic device (e.g., the MUX / DEMUX 114 of FIG. 1, the demultiplexer 206 of FIG. 2A, the multiplexer 208 of FIG. 2B, the demultiplexer 316 of FIGS. 3A-3D, and the photonic demultiplexer 400 of FIGS. 4A-4B). In some embodiments, the system 500 performs simulations (e.g., operation simulations and adjoint simulations) that model the field response (e.g., the electric and magnetic fields within the photonic device) using the finite-difference time-domain (FDTD) method, the finite-difference frequency-domain (FDFD) method, or any other suitable technique, and thereby optimizes the structural parameters of the photonic device. The operation simulation engine 526 provides instructions for performing an electromagnetic simulation of a photonic device that operates in response to an excitation source within the simulation environment. In particular, the operation simulation determines the field response of the simulation environment (and thus the photonic device described by the simulation environment) in response to an excitation source for determining the performance metric of the physical device (e.g., based on an initial description or input design of the photonic device that describes the structural parameters of the photonic device within the simulation environment having a plurality of voxels). The structural parameters can correspond to, for example, a particular design, material composition, dimensions, etc. of the physical device. The manufacturing loss calculation logic 528 provides instructions for determining the manufacturing loss utilized to implement a minimum feature size to ensure manufacturability. In some embodiments, the manufacturing loss is also used to implement binarization of the design (i.e., such that the photonic device includes a first material and a second material that are interspersed to form a plurality of interfaces). The calculation logic 524 computes a loss metric determined via a loss function that incorporates the performance loss based on the performance metric and the manufacturing loss.The adjoint simulation engine 530 is utilized in conjunction with the operational simulation engine 526 to perform adjoint simulation of a photonic device to backpropagate a loss metric through the simulation environment via a loss function to determine how changes in the structural parameters of the photonic device affect the loss metric. The optimization engine 532 is utilized to update the structural parameters of the photonic device to reduce the loss metric and generate a revised description of the photonic device (i.e., revise the design).

[0048] Figures 6A - 6C illustrate non - limiting exemplary embodiments of an initial setup of a simulation environment 606 that describes a photonic device according to various aspects of the present disclosure, performs an operational simulation of the photonic device in response to an excitation source within the simulation environment 608, and performs an adjoint simulation of the photonic device within the simulation environment 610. The initial setup of the simulation environment, the one - dimensional representation of the simulation environment, the operational simulation of the physical device, and the adjoint simulation of the physical device can be implemented using the system 500 illustrated in FIG. 5.

[0049] As illustrated in FIGS. 6A - 6C, the simulation environment is represented two - dimensionally. However, it is understood that other numbers of dimensions (e.g., three - dimensional space) can also be used to describe the simulation environment and the photonic device. In some embodiments, the optimization of the structural parameters of the photonic device illustrated in FIGS. 6A - 6C is achieved via an inverse design process that particularly includes simulations (e.g., operational simulations and adjoint simulations) that model the field responses (e.g., electric and magnetic fields) to the excitation source using the finite - difference time - domain (FDTD) method, the finite - difference frequency - domain (FDFD) method, or any other suitable technique.

[0050] FIG. 6A illustrates an exemplary simulation environment 606 for explaining a photonic integrated circuit (i.e., photonic devices such as waveguides, demultiplexers, etc.) according to a non-limiting embodiment of the present disclosure. More specifically, in response to receiving an initial description of a photonic device defined by one or more structural parameters (e.g., input design), a system (e.g., system 500 of FIG. 5) configures the simulation environment 606 to represent the photonic device. As illustrated, the simulation environment 606 (and thus the subsequent photonic device) is described by a plurality of voxels 612 that represent individual (i.e., discretized) elements of a two-dimensional (or other dimensional) space. Each of the voxels 612 is illustrated as a two-dimensional square. However, it is understood that the voxels can be represented as cubes or other shapes in three-dimensional space. It is understood that the specific shape and dimensions of the plurality of voxels 612 can be adjusted according to the simulation environment 606 and the photonic device being simulated. Further, note that only a portion of the plurality of voxels 612 is shown in order to avoid obscuring other aspects of the simulation environment 606.

[0051] Each of the plurality of voxels 612 may be associated with a structure value, a field value, and a source value. Collectively, the structure values of the simulation environment 606 describe the structural parameters of the photonic device. In one embodiment, the structure values may correspond to the permittivity, permeability, and / or refractive index that collectively describe the structure (i.e., material) boundaries or interfaces of the photonic device (e.g., the material interface pattern 420 of FIG. 4B). For example, the interface 616 may represent a location where the permittivity changes within the simulation environment 606 and may define the boundary of the photonic device where a first material contacts a second material or otherwise creates an interface. The field value describes the field (or loss) response calculated in response to an excitation source described by the source value (e.g., via Maxwell's equations). The field response may correspond, for example, to a vector that describes the electric field and / or magnetic field (e.g., in one or more orthogonal directions) at a particular time step for each of the plurality of voxels 612. Thus, the field response may be at least partially based on the structural parameters of the photonic device and the excitation source.

[0052] In the illustrated embodiment, the photonic device corresponds to an optical demultiplexer having a design region 614 (e.g., corresponding to the dispersion region 332 of FIG. 3A and / or the dispersion region 406 of FIG. 4A), and the structural parameters of the physical device can be updated or otherwise modified. More specifically, through an inverse design process, iterative gradient-based optimization of a loss metric determined from a loss function is performed to generate a design of a photonic device that functionally causes a multi-channel optical signal to be demultiplexed and guided to a corresponding one of the output ports 604 from the input port 602. Thus, the input port 602 of the photonic device (e.g., corresponding to the input region 302 of FIG. 3A, the input region 402 of FIG. 4A, etc.) corresponds to the location of an excitation source for providing an output (e.g., a Gaussian pulse, a wave, a waveguide mode response, etc.). The output of the excitation source interacts with the photonic device based on the structural parameters (e.g., the electromagnetic wave corresponding to the excitation source can be perturbed, retransmitted, attenuated, refracted, reflected, diffracted, scattered, absorbed, dispersed, amplified, or other things can be done as the wave propagates through the photonic device in the simulation environment 606). In other words, the excitation source can change the field response of the photonic device, which depends on the underlying physics governing the physical region and structural parameters of the photonic device. The excitation source begins at or is otherwise proximate to the input port 602 and is positioned to propagate (or otherwise affect the field values of a plurality of voxels) through the design region 614 toward the output port 604 of the photonic device. In the illustrated embodiment, the input port 602 and the output port 604 are positioned outside the design region 614. In other words, in the illustrated embodiment, only a portion of the structural parameters of the photonic device can be optimized.

[0053] However, in other embodiments, the entire photonic device may be placed within the design region 614 such that the structural parameters may represent any part or all of the design of the photonic device. The electric and magnetic fields within the simulation environment 606 (and subsequently the photonic device) can vary in response to the excitation source (e.g., represented by the field values of individual voxels that collectively correspond to the field response of the simulation environment). The output port 604 of the optical demultiplexer can be used to determine a performance metric of the photonic device in response to an excitation source (e.g., power transmission from the input port 602 to a particular one of the output ports 604). An initial description of the photonic device, including the initial structural parameters, excitation source, performance parameters or metrics, and other parameters that describe the photonic device, is received by the system (e.g., system 500 of FIG. 5) and used to configure a simulation environment 606 for performing a first principle-based simulation of the photonic device. These specific values and parameters can be defined directly by the user (e.g., the user of system 500 of FIG. 5), indirectly (e.g., by calling predetermined values stored in the memory 516, local storage 518, or remote resource 510 via the controller 512), or by a combination thereof.

[0054] FIG. 6B illustrates a non-limiting exemplary embodiment of a simulation of the operation of a photonic device in response to an excitation source within a simulation environment 608, according to various aspects of the present disclosure. In the illustrated embodiment, the photonic device is an optical demultiplexer structured to optically separate each of a plurality of distinct wavelength channels included in a multi-channel optical signal received at an input port 602 and to guide each of the plurality of distinct wavelength channels to a corresponding one of a plurality of output ports 604. The excitation source can be selected (randomly or otherwise) from the plurality of distinct wavelength channels and begins at the input port 602 with a specified spatial, phase, and / or temporal profile. The simulation of the operation is performed over a plurality of time steps, including the illustrated time step. When performing the simulation of the operation, changes to the field response (e.g., field values) of each of the plurality of voxels 612 are incrementally updated in response to the excitation source over the plurality of time steps. The change in the field response at a particular time step is at least partially based on the structural parameters, excitation source, and field response of the simulation environment 610 at the immediately preceding time step included in the plurality of time steps. Similarly, in some embodiments, the source values of the plurality of voxels 612 are updated (e.g., based on a spatial profile and / or temporal profile that describes the excitation source). It is understood that the simulation of the operation is incremental and that the field values (and source values) of the simulation environment 610 are incrementally updated at each time step as time progresses for each of the plurality of time steps during the simulation of the operation. Note further that in some embodiments, the update is an iterative process and that the update of each field and source value is at least partially based on the previous update of each field and source value.

[0055] Once the operation simulation reaches a steady state (e.g., the change in the field value in response to the excitation source substantially stabilizes or decreases to a negligible value), or ends in some other way, one or more performance metrics can be determined. In one embodiment, the performance metric corresponds to the power transmission at a corresponding one of the output ports 604 mapped to distinct wavelength channels being simulated by the excitation source. In other words, in some embodiments, the performance metric represents the power (at one or more frequencies of interest) in the target mode shape at a particular location of the output port 604. The loss value or metric of an input design (e.g., an initial design and / or any refined design in which the structural parameters have been updated) based at least in part on the performance metric can be determined via a loss function. The loss metric, in conjunction with the adjoint simulation, can be used to update the structural parameters (i.e., increase the performance metric) to reduce the loss metric, or otherwise determine the structural gradient (e.g., the effect of the structural parameters on the loss metric) for modification. Note that the loss metric can be further based on manufacturing loss values and / or other loss values utilized to implement the minimum feature size of the photonic device to facilitate manufacturability of the device.

[0056] FIG. 6C illustrates a non-limiting, exemplary embodiment of an adjoint simulation within simulation environment 610 by backpropagating a loss metric, according to various aspects of the present disclosure. More specifically, the adjoint simulation is a time-reversed simulation in which the loss metric is treated as an excitation source that interacts with the photonic device to cause a loss response. In other words, an adjoint (or virtual source) based on the loss metric is placed at another location corresponding to a location used when determining the output region (e.g., output port 604) or performance metric. The adjoint source is treated as a physical stimulus or excitation source during the adjoint simulation. The loss response of simulation environment 608 is calculated for each of a plurality of time steps (e.g., backwards in time) in response to the adjoint source. The loss response collectively refers to the loss values of a plurality of voxels 612 that are incrementally updated in response to the adjoint source over a plurality of time steps. A change in the loss response based on the loss metric may correspond to a loss gradient, which indicates how a change in the field response of the physical device affects the loss metric. The loss gradient and the field gradient may be combined in a suitable manner to determine the structural gradient of the photonic device / simulation environment (e.g., how a change in the structural parameters of the photonic device within the simulation environment affects the loss metric). Knowing the structural gradient for a particular cycle (e.g., the operation simulation and the adjoint simulation), the structural parameters can be updated to reduce the loss metric and generate a modified description or design of the photonic device.

[0057] In some embodiments, the iterative cycle of performing an operation simulation and an adjoint simulation, determining a structural gradient, and updating a structural parameter to reduce a loss metric is continuously performed as part of an inverse design process that utilizes iterative gradient-based optimization. An optimization scheme such as gradient descent can be used to determine a specific amount or degree of change to the structural parameters of a photonic device to incrementally reduce the loss metric. More specifically, after each cycle, the structural parameters are updated (e.g., optimized) to reduce the loss metric. The operation simulation, adjoint simulation, and update of the structural parameters are iteratively repeated until the loss metric substantially converges, falls below a threshold or range, or is within that range, such that the photonic device provides the desired performance while maintaining manufacturability.

[0058] While the inverse design process described above is effective, as the size of the design region 614 increases, the amount of computational time spent performing the operation simulation, adjoint simulation, gradient determination, and update of the structural parameters increases significantly. Further, the number of iterations before the loss metric converges can similarly increase as the size of the design region 614 increases. Unfortunately, for some desired functions (e.g., multiplexing / demultiplexing specific wavelengths and / or multiplexing / demultiplexing a specific number of wavelengths with each other and / or implementing digital logic), a smaller design region 614 may not provide sufficient physical area for the desired functionality to be implemented. For example, given the physical characteristics of wave propagation through the design region 614, a minimum distance may be required for the wave to be converted from a first position or orientation to a second position or orientation. However, increasing the area of the design region 614 excessively may result in more computational resources being taken up by the simulation and gradient calculations than would actually be beneficial.

[0059] Thus, in some embodiments of the present disclosure, the simulation and optimization of a large design region 614 can be achieved by dividing the design region into sub-component regions connected by waveguides. The simulation and optimization of each sub-component region can be calculated simultaneously, and the simulation of the waveguides can be calculated in advance to accelerate the simulation and optimization of the entire design. The total size of the design region is still available for implementing functions even when divided into sub-component regions, thus dramatically reducing the calculation time while maintaining the benefits of a large design region.

[0060] FIG. 7 is a schematic diagram illustrating a non-limiting exemplary embodiment of a design region of a photonic integrated circuit divided into sub-component regions according to various aspects of the present disclosure. In the photonic integrated circuit 700, an input waveguide 704, a first output waveguide 706, a second output waveguide 708, and a third output waveguide 710 are provided around the design region similar to the input region 402 and output regions 404a - 404d illustrated in FIGS. 4A and 4B, and the input ports 602 / output ports 604 illustrated in FIGS. 6A - 6C. However, instead of a single monolithic design region 614 as illustrated in the previous figures, the design region of the photonic integrated circuit 700 is divided into a plurality of sub-component regions 702.

[0061] In the illustrated embodiment, each of the sub-component regions 702 is of a matching size. By selecting the matching size of the sub-component regions 702, the simultaneous simulation of each of the sub-component regions 702 is completed substantially simultaneously, and since each of the sub-component regions 702 is much smaller than the entire design region, the computational resources for simulating each sub-component region 702 are dramatically reduced compared to the entire design region (especially considering that the computational complexity of the simulation is exponential with respect to the simulated area).

[0062] The photonic integrated circuit 700 includes a plurality of internal waveguides 712 that connect sub-component regions 702. The computational complexity of simulating the photonic integrated circuit 700 is further reduced by using standard shapes and sizes for the internal waveguides 712 and by excluding the internal waveguides 712 themselves from the optimization process. Thus, the s-parameters of a single internal waveguide 712 can be calculated once and then reused during future simulations of the entire photonic integrated circuit 700, dramatically reducing the total area to be simulated while maintaining the overall size of the photonic integrated circuit 700, thereby enabling the implementation of complex functions that utilize a larger overall size. Regions of the photonic integrated circuit 700 that are neither within the sub-component regions 702 nor within the internal waveguides 712 can be separated by an opaque barrier and can be ignored during optimization.

[0063] The internal waveguides 712 are defined by structural parameters that specify the materials within the regions of the internal waveguides 712. The illustrated internal waveguides 712 are shown as having straight walls and a single material, but in some embodiments, the internal waveguides 712 can have more complex structural parameters that include, but are not limited to, regular or irregular features along the walls and / or within the central portion of the internal waveguides 712. Further, as described above, at least a portion of the internal waveguides 712 can be curved to connect sub-component regions 702 that are not adjacent in the horizontal or vertical direction.

[0064] A photonic integrated circuit 700 is illustrated in which a plurality of sub-component regions 702 are fully connected by pairs of straight internal waveguides 712, but it will be understood that this is merely a non-limiting example. In some embodiments, more or fewer internal waveguides 712 may be used and may be arranged in an irregular pattern. Further, in some embodiments, internal waveguides 712 of various shapes, including but not limited to curved internal waveguides 712, may be used so that sub-component regions 702 other than those adjacent vertically or horizontally may be connected. The s-parameters of the curved internal waveguides 712 are also pre-simulated to be plugged into the overall simulation as described above for the illustrated straight internal waveguides 712.

[0065] FIG. 8 is a block diagram illustrating a non-limiting exemplary embodiment of a system in accordance with various aspects of the present disclosure. Overall, the illustrated embodiment of system 800 is configured to generate a proposed segmentation design, optimize the proposed segmentation design, and fabricate a physical device based on the proposed segmentation design.

[0066] As shown, system 800 includes a design generation system 814, a manufacturing system 816, and a design optimization system 802. Communication between the design generation system 814, the design optimization system 802, and the manufacturing system 816 may be via a network (not shown), via the exchange of removable computer-readable media (not shown), or via any other suitable technique. The design generation system 814, the manufacturing system 816, and the design optimization system 802 are illustrated as separate systems, but in some embodiments, some of these systems may be integrated. As one non-limiting example, the design generation system 814 and the design optimization system 802 may be integrated into a single system. Also, in some embodiments, the system illustrated in FIG. 8 as a single system may be divided into multiple systems.

[0067] In some embodiments, the design generation system 814 may include one or more computing devices configured to generate a proposed design to achieve a desired result. For example, the design generation system 814 may provide a user interface that accepts specifications such as the number of input ports, the number of output ports, the desired functionality of the proposed design (including, but not limited to, the expected output at each output port given a particular input at each input port), the size of the design area, the number and / or size of sub-component areas, and / or any other aspect of the proposed design. In some embodiments, the design generation system 814 may automatically generate some aspects of the proposed design, including, but not limited to, the size and / or number of sub-component areas 702, the number and / or position of internal waveguides 712 connecting the sub-component areas 702.

[0068] In some embodiments, the manufacturing system 816 can be any suitable system for manufacturing a segmented design. In some embodiments, the manufacturing system 816 can be a photolithography system or an additive manufacturing system. In some embodiments, the manufacturing system 816 may have characteristics including a minimum feature size, a minimum feature shape, and / or other constraints useful for defining the segmented design that the manufacturing system 816 can manufacture. To that end, the manufacturing system 816 can be provided with a design rule checker configured to process the proposed segmented design to determine whether the proposed segmented design complies with the constraints of the manufacturing system 816.

[0069] In some embodiments, design optimization system 802 can be any suitable computing device or collection of computing devices configured to provide the described functionality. In some embodiments, design optimization system 802 can be a server computing device, a desktop computing device, a laptop computing device, a mobile computing device, a tablet computing device, or one or more computing devices of a cloud computing system. In some embodiments, design optimization system 802 can include or be capable of providing the components described with respect to system 500 illustrated in FIG. 5 and described above, and / or system 500 of FIG. 5 can include or be capable of providing the components described with respect to design optimization system 802.

[0070] As shown, design optimization system 802 includes one or more processors 810, a network interface 812, and a computer-readable medium 804. In some embodiments, the one or more processors 810 can include multiple processors and / or multiple processing cores to provide substantial computing power. In some embodiments, network interface 812 can be configured to communicate with design generation system 814 and / or manufacturing system 816 via any suitable type of wired network (including, but not limited to, Ethernet, FireWire, and USB), wireless network (including, but not limited to, 2G, 3G, 4G, 5G, LTE, Wi-Fi, WiMAX, and Bluetooth), or a combination thereof. In some embodiments, instead of network interface 812, design optimization system 802 can be configured to communicate with design generation system 814 and / or manufacturing system 816 via the transfer of a removable computer-readable medium (not shown).

[0071] As shown, computer-readable medium 804 stores logic that causes optimization system 802 to provide sub-component optimization engine 806 and overall optimization engine 808 in response to execution by one or more processors 810.

[0072] In some embodiments, sub-component optimization engine 806 is configured to simultaneously simulate sub-component regions 702 of a proposed segmented design, determine gradients of sub-component regions 702, and optimize sub-component regions 702 based on the gradients. In some embodiments, overall optimization engine 808 is configured to determine overall s-parameters of a proposed segmented design and determine an overall gradient of the proposed segmented design using simulations of sub-component regions 702 and pre-computed simulations of internal waveguides 712. In some embodiments, overall optimization engine 808 is also configured to optimize the positions of one or more internal waveguides 712 as part of the optimization process. Further details regarding the actions performed by sub-component optimization engine 806 and overall optimization engine 808 are provided below.

[0073] As used herein, "engine" refers to logic embodied in hardware instructions or software instructions that can be written in programming languages such as C, C++, C#, COBOL, Java™, PHP, Perl, HTML, CSS, JavaScript, VBScript, ASPX, Go, Python. The engine may be compiled into an executable program or written in an interpreted programming language. The software engine can be called from other engines or from themselves. Generally, the engines described herein refer to logic modules that can be merged with other engines or split into sub-engines. The engine is stored in any type of computer-readable medium or computer storage device, stored on one or more general-purpose computers, and thereby executed, and thus, a dedicated computer configured to provide the engine or its functionality can be created. The engine can be implemented by logic programmed into an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another hardware device.

[0074] As used herein, the term "computer-readable medium" refers to a removable or non-removable device that implements any technology capable of storing information, volatile or non-volatile, that can be read by a processor of a computing device, including but not limited to hard drives, flash memory, solid-state drives, random-access memory (RAM), read-only memory (ROM), CD-ROMs, DVDs, or other disk storage devices, magnetic cassettes, magnetic tapes, and magnetic disk storage devices. The computer-readable medium may also include a plurality of devices configured to collectively store the described information.

[0075] Figures 9A - 9B are flowcharts illustrating non - limiting exemplary embodiments of a method for optimizing the design of a photonic device according to various aspects of the present disclosure. In method 900, design optimization system 802 uses simulations and optimizations of sub - component region 702, along with pre - calculated performance characteristics of internal waveguide 712, to accelerate simulations and optimizations of a proposed segmented design of a photonic device.

[0076] Method 900 proceeds from the start block to block 902, where design generation system 814 generates a proposed design that includes a number of input ports and a number of output ports, and provides the proposed design to design optimization system 802. Also, the proposed design may include one or more desired performance characteristics associated with each output port for various predicted inputs to each input port, so that the simulated performance can be compared with the desired performance characteristics for optimization purposes. In some embodiments, the proposed design may indicate one or more constraints on the overall design, including but not limited to the size and / or shape of the overall design, constraints on the position of one or more of the input ports and / or one or more of the output ports, and / or other constraints.

[0077] In block 904, the overall optimization engine 808 of the design optimization system 802 determines an initial design based on the proposed design, including a number of sub-component regions 702 and a number of internal waveguides 712. In some embodiments, the number of sub-component regions 702 can be automatically determined by the overall optimization engine 808. For example, the overall optimization engine 808 can search for the size and / or shape of the overall design from the proposed design and automatically divide the initial design into sub-component regions 702 of a predetermined size based on the size and / or shape. For example, the overall optimization engine 808 can search for the size and / or shape of the overall design from the proposed design and automatically divide the initial design into a predetermined number of sub-component regions 702 spaced apart by a predetermined amount based on the size and / or shape. In some embodiments, the specifications of the sub-component regions 702 and / or the internal waveguides 712 can be provided within the proposed design.

[0078] In some embodiments, the proposed design can provide several internal waveguides 712 that are used to connect each of the subcomponent regions 702. For example, in the proposed design for the photonic integrated circuit 700 illustrated in FIG. 7, two internal waveguides 712 are designated to connect each of the subcomponent regions 702. In some embodiments, the proposed design can show more or fewer internal waveguides 712 for connecting each of the subcomponent regions 702. In some embodiments, the proposed design can also define the shape (e.g., straight, curved, etc.) of the internal waveguides 712. In some embodiments, the proposed design can indicate that fewer subcomponent regions than all of the subcomponent regions 702 should be fully connected in the initial design so that some subcomponent regions 702 can be connected by more or fewer internal waveguides 712 than others. In some embodiments, the proposed design can provide specific positions for the internal waveguides 712. In some embodiments, the overall optimization engine 808 can determine specific positions of the internal waveguides 712 based on the guidance provided by the proposed design. In some embodiments, the overall optimization engine 808 can automatically determine both the number and positions of the internal waveguides 712.

[0079] In block 906, the subcomponent optimization engine 806 of the design optimization system 802 initializes each subcomponent region. In some embodiments, initialization includes determining an initial set of structural parameters (e.g., the pattern of materials within voxels 612 (e.g., pixels, segments)) for each subcomponent region 702. In some embodiments, initialization can set the material within the voxels 612 to a single value. In some embodiments, initialization can set the material within the voxels 612 to random values. In some embodiments, initialization can set the material within the voxels 612 to match the structural parameters of a previously designed physical device.

[0080] In block 908, the global optimization engine 808 determines the s-parameters of the internal waveguide 712. In some embodiments, the global optimization engine 808 may determine the s-parameters by simulating the performance of the sample internal waveguide using the FDTD method, the FDFD method, or any other suitable method for generating the s-parameters of the sample internal waveguide. Then, for each of the internal waveguides 712 used in the design, the s-parameters determined for the sample internal waveguide may be used. The s-parameters may be determined separately for each type of internal waveguide used in the design (e.g., a straight internal waveguide of a given length, a curved internal waveguide, etc.), but may be reused each time an internal waveguide of the same size and shape is used in the design. In some embodiments, the global optimization engine 808 can store the s-parameters of the internal waveguide in a reference data store. In some embodiments, the global optimization engine 808 can determine the s-parameters of the internal waveguide 712 by retrieving previously determined s-parameters from the reference data store.

[0081] Next, method 900 proceeds to block 910 through the continuity terminal ( "Terminal A"), and the sub-component optimization engine 806 simultaneously simulates the sub-component regions to obtain the simulated s-parameters for each sub-component region. The structural parameters for each sub-component region 702 can be used in simulations that use the FDTD method, the FDFD method, or any other suitable method for generating the simulated s-parameters. Any suitable technique can be used to simultaneously simulate the sub-component regions 702. For example, a multi-threaded method can be used to concurrently execute multiple simulations on one or more processing cores. As another example, a serverless function or other distributed computing technique can be used to distribute the simulation of each sub-component region 702 among multiple cloud-based computing devices. By using sub-component regions 702 of matching sizes, the simulations take substantially the same amount of time to complete, and no single simulation functions as a bottleneck.

[0082] In block 912, the overall optimization engine 808 combines the simulated s-parameters with the s-parameters of the internal waveguide 712 to determine the overall s-parameters of the initial design. One characteristic of s-parameters known to those skilled in the art is that the s-parameters of a composite circuit can be modeled by combining the s-parameters of the individual components with simple operations such as matrix multiplication, more complex techniques such as the Gunnar algorithm described in Filipsson, Gunnar, "A new general computer algorithm for S-matrix calculation of interconnected multiports", 11th European Microwave Conference, IEEE, 1981 (which is hereby incorporated by reference in its entirety), or any other suitable technique. Thus, the overall s-parameters can be easily determined by appropriately combining the simulated s-parameters of the subcomponent region 702 and the s-parameters of the internal waveguide 712. In some embodiments, the s-parameters of the input and output ports may also be considered.

[0083] The method 900 then proceeds to the continuity terminal ("Terminal B"). The method 900 proceeds from Terminal B (FIG. 9B) to block 914, where the overall optimization engine 808 determines the overall gradient of the overall loss function based on the desired performance characteristics. In some embodiments, a comparison of the desired performance with the overall s-parameters can be performed to determine a performance loss value. To calculate the overall gradient, the derivative of the performance loss value can be determined.

[0084] In block 916, the sub-component optimization engine 806 updates the structural parameters of one or more sub-component regions based on the global gradient. In some embodiments, the global gradient indicates the changes to be made to the structural parameters throughout the design region 614 in order to reduce the difference between the global performance loss value and the desired performance. The changes indicated by the global gradient are mapped to the appropriate sub-component regions 702 so that appropriate changes can be made to the sub-component regions 702. Since all of the sub-component regions 702 can be updated using a single global gradient, the effect is to optimize all of the sub-component regions 702 at once rather than using individual optimizations for each sub-component region 702. Thus, by eliminating individual optimizations of the sub-component regions 702, computational resources are dramatically saved.

[0085] In some embodiments, all of the sub-component regions 702 can be optimized each time block 916 is reached in method 900. In some embodiments, a subset of the sub-component regions 702 can be optimized during each iteration of block 916. For example, the first level of the sub-component regions 702 (i.e., the sub-component regions 702 closest to the output ports) may be optimized during the first iteration, and the second level of the sub-component regions 702 (i.e., the set of sub-component regions 702 immediately upstream of the first level of the sub-component regions 702) may be optimized during the second iteration, and so on. Similarly, each subset can be processed over two or more iterations before moving on to the next subset.

[0086] In an optional block 918, the overall optimization engine 808 optimizes the position of one or more waveguides. In some embodiments, the overall optimization engine 808 can determine whether the overall performance is improved by moving the position of one or more of the internal waveguide 712, the input port, and / or the output port. This can be achieved by monitoring performance values along the perimeter of the photonic integrated circuit 700 and / or the individual sub-component regions 702, and moving the waveguide when the overall optimization engine 808 determines that the performance is better at different positions of the waveguide. A detailed description of the techniques for moving the position of the waveguide is provided in the commonly owned and co-pending U.S. patent application Ser. No. 17 / 586,370, filed Jan. 27, 2022, the entire disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0087] In some embodiments, the overall optimization engine 808 can review the field values within adjacent sub-component regions 702, and if it determines that the signal strength passing through the waveguide is less than a threshold amount, the associated waveguide can be removed from the design to simplify future calculations. The optional block 918 is exemplified as optional because in some embodiments the position of the waveguide can be fixed and / or the optimization of the position of the waveguide may not be performed during all iterations of method 900.

[0088] Method 900 then proceeds to decision block 920, where a determination is made as to whether method 900 has been performed to optimize the design. In some embodiments, the optimization can continue until a desired level of performance is obtained. In some embodiments, the optimization can continue until the performance loss value converges to a minimum value (i.e., further iterations are not expected to further improve performance). In some embodiments, the optimization can be performed for a predetermined number of iterations, and the determination can check whether that number of iterations has already been performed.

[0089] In decision block 920, if it is determined that method 900 is not being performed, the result of decision block 920 is "no", and method 900 returns to block 910 via terminal A and performs subsequent optimization iterations. Otherwise, if method 900 is being performed, the result of decision block 920 is "yes", and method 900 proceeds to optional block 922.

[0090] In optional block 922, the global optimization engine 808 identifies unused sub-component regions. In some embodiments, the global optimization engine 808 reviews the simulated field values within the sub-component region 702 (determined during the simulation in block 910) to determine whether there are any sub-component regions 702 that do not receive any signals during the operation of the photonic integrated circuit 700. In some embodiments, the global optimization engine 808 can identify the unused sub-component regions 702 by finding sub-component regions 702 in which all waveguides have been removed by the processing in optional block 918.

[0091] In optional block 924, the global optimization engine 808 removes all waveguides connected to the unused sub-component regions 702 and the structural parameters of the unused sub-component regions 702. Since no signals reach the unused sub-component regions 702, the structural parameters and the associated waveguides (if any remain after the processing in optional block 918) can be removed without affecting the performance of the remaining part of the photonic integrated circuit 700.

[0092] In optional block 926, the global optimization engine 808 inserts other functions into unused sub-component regions. In some embodiments, to replace the removed sub-component region 702, a predetermined test structure with its own input and output ports can be inserted. This is advantageous because it provides a structure that can be used to test the manufacturing process of the remainder of the photonic integrated circuit 700 as close as physically possible to the photonic integrated circuit 700, without the need to reserve space within the photonic integrated circuit 700 that would otherwise be useful for providing the functionality of the photonic integrated circuit 700. In some embodiments, the "other functions" can be inserted by laying out multiple photonic integrated circuits 700 on a single wafer such that unused portions of the photonic integrated circuits 700 interlace with each other to allow more photonic integrated circuits 700 to be mounted on a single wafer. Optional blocks 922, 924, and 926 are illustrated as optional in some embodiments because method 900 may leave unused sub-component regions 702 within the photonic integrated circuit 700.

[0093] In block 928, the design optimization system 802 transmits the updated design to the manufacturing system 816 to fabricate a photonic device. The manufacturing system 816 can then fabricate the photonic device as defined by the updated design.

[0094] Method 900 then proceeds to an end block and ends.

[0095] In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments of the present disclosure. However, one of ordinary skill in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0096] Throughout this specification, the phrase "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0097] The order in which some or all of the blocks appear in each method flowchart should not be regarded as limiting. Rather, those skilled in the art having the benefit of this disclosure will understand that the actions associated with some of the blocks may be performed in various orders not illustrated, or even in parallel.

[0098] The processes described above have been described with respect to computer software and hardware. The techniques described may constitute machine-executable instructions embodied within a tangible or non-transitory machine-readable storage medium (e.g., a computer) that, when executed by a machine, cause the machine to perform the actions described. Additionally, the processes may be embodied within, for example, an application specific integrated circuit (ASIC) or other hardware.

[0099] The above description of the exemplary embodiments of the present invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Specific embodiments and examples of the invention are described herein for illustrative purposes, but as will be recognized by those skilled in the art, various modifications are possible within the scope of the invention.

[0100] These changes can be made to the present invention in light of the above detailed description. In general, the terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed herein. Rather, the scope of the present invention should be determined solely by the following claims, which should be construed in accordance with established principles of claim interpretation.

Claims

1. A non - transitory computer - readable medium storing logic that causes a computing system to perform actions for designing a photonic device in response to execution by one or more processors of the computing system, the actions including: Receiving, by a design optimization system, an initial design of the photonic device, the initial design including one or more inputs, one or more outputs, several sub - component regions, and several waveguides for connecting the sub - component regions; Simulating, by the design optimization system, each sub - component region to determine simulated s - parameters of each sub - component region; Determining, by the design optimization system, overall s - parameters of a simulated photonic device based on the simulated s - parameters of each sub - component region and the s - parameters of the waveguides; Determining, by the design optimization system, an overall gradient associated with the overall s - parameters; Optimizing, by the design optimization system, one or more sub - component regions based on the overall gradient to create an updated design of the photonic device; A non - transitory computer - readable medium comprising the above.

2. The actions further include: Repeating the simulating action, the determining action, and the optimizing action until the simulated performance of the simulated photonic device reaches a predetermined threshold or a predetermined number of iterations is executed. The non - transitory computer - readable medium according to claim 1.

3. The actions further include: Providing the updated design to a manufacturing system to manufacture the photonic device. The non - transitory computer - readable medium according to claim 1.

4. The actions further include: Searching for predetermined s - parameters of the waveguides. Determining the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each subcomponent region and the s-parameters of the waveguide includes using the searched-for predetermined s-parameters of the waveguide, the non-transitory computer-readable medium of claim 1.

5. Simulating each subcomponent region to determine the simulated s-parameters of each subcomponent region includes simultaneously simulating each subcomponent region, the non-transitory computer-readable medium of claim 1.

6. Optimizing a subcomponent region includes updating at least one of the size of the subcomponent region and the structural parameters of the subcomponent region, the non-transitory computer-readable medium of claim 1.

7. The action further includes optimizing at least one of the position and shape of at least one waveguide, the non-transitory computer-readable medium of claim 1.

8. Optimizing the position of at least one waveguide includes removing at least one waveguide, the non-transitory computer-readable medium of claim 7.

9. The action further includes removing the subcomponent region from the updated design in response to determining that the subcomponent region is not connected to any waveguide, the non-transitory computer-readable medium of claim 8.

10. The action further includes inserting a predetermined test structure to replace the removed subcomponent region, the non-transitory computer-readable medium of claim 9.

11. A method for designing a photonic device, the method comprising receiving, by a design optimization system, an initial design of the photonic device, the initial design including one or more inputs, one or more outputs, several subcomponent regions, and several waveguides for connecting the subcomponent regions, receiving the initial design of the photonic device To determine the simulated s-parameters of each sub-component region, the design optimization system simulates each sub-component region, and the design optimization system determines the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each sub-component region and the s-parameters of the waveguide. The design optimization system determines the overall gradient associated with the overall s-parameters. The design optimization system optimizes one or more sub-component regions based on the overall gradient to create an updated design of the photonic device. A method comprising: **Claim 12** The method according to claim 11, further comprising repeating the simulating action, the determining action, and the optimizing action until the simulated performance of the simulated photonic device reaches a predetermined threshold or a predetermined number of iterations is executed. **Claim 13** The method according to claim 11, further comprising providing the updated design to a manufacturing system to manufacture the photonic device. **Claim 14** The method further includes searching for predetermined s-parameters of the waveguide, and determining the overall s-parameters of the simulated photonic device based on the simulated s-parameters of each sub-component region and the s-parameters of the waveguide includes using the searched predetermined s-parameters of the waveguide. The method according to claim 11. **Claim 15** The method according to claim 11, wherein simulating each sub-component region to determine the simulated s-parameters of each sub-component region includes simulating each sub-component region simultaneously. **Claim 16** The method according to claim 11, wherein optimizing the sub-component region includes updating at least one of the size of the sub-component region and the structural parameters of the sub-component region. **Claim 17** The method according to claim 11, further comprising optimizing at least one of the position and shape of at least one waveguide. **Claim 18** The method of claim 17, wherein optimizing the position of at least one waveguide includes removing at least one waveguide. **Claim 19** The method of claim 18, further comprising removing the sub-component region from the updated design in response to determining that the sub-component region is no longer connected to any waveguide. **Claim 20** The method of claim 19, further comprising adding a predetermined test structure to replace the removed sub-component region.

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