Dynamic guard band with timing protection and performance protection

Abstract

The embodiment includes detecting a first number of throttle amounts in the processor in response to monitoring the processor during operation, determining that the first number of throttle amounts satisfies a first condition regarding a throttle amount threshold, and modifying the voltage level of the processor by a first amount. The embodiment includes detecting a second number of throttle amounts in the processor in response to modifying the voltage level of the processor by the first amount, determining that the second number of throttle amounts satisfies a second condition regarding the throttle amount threshold, and modifying the voltage level of the processor by a second amount. (Figure 3)

Description

Background Art

[0001] The present invention generally relates to computer systems, and more specifically, to computer-implemented methods, computer systems, and computer program products configured and arranged to provide dynamic guard bands with timing protection and / or performance protection.

[0002] In a distributed computing environment, there can be a number of jobs or queries arriving as workloads to be processed at processors within the computing environment. A processor core is a processing unit that reads instructions to perform a particular action. Instructions are chained together such that when executed in real time at the processor, the processor executes the desired workload formed by the instructions. A multi-core processor is a computer processor on a single integrated circuit having two or more distinct processing units, each of which reads and executes program instructions. Instructions are normal instructions (such as add, move data, branch, etc.), but a single processor can execute instructions simultaneously in separate cores to improve the overall speed of a program that supports multi-threading or other parallel computing techniques.

[0003] Problems can occur in the operation of the processor, and the cores of the processor are executed to avoid the problems. There is a need for technology to improve the timing and / or performance of the processor.

Summary of the Invention

[0004] Embodiments of the present invention are directed to a computer-implemented method for a dynamic guard band with timing protection and / or performance protection. A non-limiting computer-implemented method includes the computer detecting a first number of throttle amounts in the processor in response to monitoring the processor during operation, and the computer determining that the first number of throttle amounts meets a first condition regarding a throttle amount threshold. The method includes the computer modifying the voltage level of the processor by a first amount, and in response to modifying the voltage level of the processor by the first amount, the computer detecting a second number of throttle amounts in the processor. The method also includes the computer determining that the second number of throttle amounts meets a second condition regarding the throttle amount threshold, and the computer modifying the voltage level of the processor by a second amount.

[0005] This provides an improvement over known methods for using a static guard band by increasing the supply voltage to the processor core when the processing instructions of the workload become stronger or vary greatly (noisy), thereby reducing the performance degradation of the workload on the processor core, and thereby preventing the workload from having multiple (or subsequent) cycles in an interrupted state of execution. Once the number of cycles in an interrupted state of execution is reduced (or is zero), this indicates that the strong or noisy phase of the workload is complete and the supply voltage can be reduced.

[0006] In addition to, or as an alternative to, one or more of the features described above or below, a further embodiment of the present invention discloses that modifying the voltage level of the processor by the first amount comprises the step of increasing the voltage level of the processor by the first amount. This advantageously improves the flow of instructions of the workload by increasing the supply voltage, which allows the processor core to avoid cycles in which execution is interrupted; also, this can reduce circuit errors, and as a result, the rate of recovery events can be reduced, and the possibility that the processor core experiences an irrecoverable error or a checkstop, resulting in a service interruption, can be reduced.

[0007] In addition to, or as an alternative to, one or more of the features described above or below, a further embodiment of the present invention discloses that modifying the voltage level of the processor by the second amount comprises the step of decreasing the voltage level of the processor by the second amount. This advantageously reduces the power used by the processor core when the intensity or variation of the workload is reduced.

[0008] In addition to, or as an alternative to, one or more of the features described above or below, a further embodiment of the present invention discloses the step of checking that the power usage is less than a power usage threshold before modifying the voltage level of the processor by the first amount. This advantageously checks and ensures that the power usage of the processor chip or the processor is within tolerance before increasing the supply voltage.

[0009] In addition to, or as an alternative to, one or more of the features described above or below, a further embodiment of the present invention discloses a step of checking whether the power consumption is greater than a power consumption threshold, and in response to the power consumption being greater than the power consumption threshold, rejecting a request to modify the voltage level by the first amount and maintaining the current voltage level. This advantageously prevents the supply voltage from increasing when the supply voltage has been increased to its maximum value and / or the processor chip / processor has approached its maximum current or power consumption.

[0010] In addition to, or as an alternative to, one or more of the features described above or below, a further embodiment of the present invention discloses a step of providing a condition for returning the voltage level to a default voltage level in response to determining that the power consumption is greater than a maximum power consumption threshold. This advantageously prevents the failure of the processor core and / or the processor when its power consumption is greater than the maximum value, thereby preventing the failure of the power supply, regulator, or chip that could result in service interruption or permanent damage to one or more system components.

[0011] Other embodiments of the present invention implement the features of the above methods in a computer system and a computer program product.

[0012] Further technical features and benefits are realized by the technology of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered part of the claimed subject matter. For a better understanding, please refer to the detailed description and the drawings.

Brief Description of the Drawings

[0013] The details of the exclusive rights described herein are particularly pointed out and are clearly claimed in the claims at the conclusion of the specification. The above and other features and advantages of the embodiments of the present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

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DETAILED DESCRIPTION OF THE INVENTION

[0029] One or more embodiments of the present invention describe a computer-implemented method, a computer system, and a computer program product configured and arranged to provide a dynamic guard band with timing protection and / or a dynamic guard band with performance protection to a processor core on a processor. The terms processor core, core, or core unit may be used synonymously. The terms processor, chip, processor chip, and integrated circuit may be used synonymously. Timing guard band protection allows the timing guard band to be reduced in some cases, which provides the core with improved yield, improved power dissipation, and / or improved timing margin. The timing margin may be described herein, but note that one or more embodiments are equally applicable to timing and / or voltage margins. The digital loop sensor may be digital or analog and may be a timing sensor or a voltage sensor. In one or more embodiments, the dynamic guard band with timing protection allows the processor to operate at its nominal voltage in a state close to a state without any voltage droop under normal conditions such as a steady-state workload, nominal temperature, etc. In particular, since the power supply noise is minimal and there is no large voltage droop, the processor operates with a reduced guard band (i.e., reduced voltage margin and / or reduced timing margin). In the case where the workload switches directly from an idle state to a high-activity workload, this change in activity appears as the worst-case voltage droop (as further described herein).

[0030] Typically, a core has a number of critical circuit paths that result in malfunction and errors when the voltage of that circuit drops below a critical value. In a core designed for high robustness, there is an error checking circuit that detects these errors. If an error is detected, the system can return to a checkpoint state prior to the error for a retry attempt. The result is that most errors are recoverable. Despite the fact that most circuit errors are recoverable, a high rate of error recovery can affect performance. Additionally, if an error exists during the error recovery process itself, this can result in an irrecoverable error that can lead to a more severe system interruption as a result.

[0031] Without the technical advantages of one or more embodiments of the present invention, a way to consider is to always operate at a constant voltage regulator set point voltage high enough to account for its worst-case voltage droop. The voltage set point required for each desired operating frequency is set during the manufacturing test of each chip and stored in a non-volatile memory called VPD (vital product data, important product data). Even when the voltage set point is kept constant, it is impossible to keep the voltage at the circuit level constant due to voltage regulator limitations and the resistance and inductance of the unpowered substrate, socket, and package. When the VDD current increases rapidly over time (also known as di / dt), the power supply droops at the on-chip circuit location. The voltage difference (i.e., delta) from the voltage set point that results in an error with respect to the actual voltage set point is called the voltage margin, as shown in FIGS. 7A and 7B described herein.

[0032] Generally, the critical path speeds up as the voltage increases, and thus the increase in voltage increases the timing margin. In manufacturing tests, when the VDD setting point is at or above the minimum value Vmin, it has been confirmed that the Vmin - workload operates without any circuit errors. To add margin during manufacturing tests to account for different workloads, temperature variations, device degradation at the end of life, etc., the VDD setting point is increased by N% to Vmin + N * 0.01V, resulting in a timing margin of N% (in units of V%) for the Vmin - workload in the manufacturing environment for the Vmin - workload. Next, any droop sensor is calibrated when executing this Vmin - workload, and as a result, the minimum output value of each droop sensor is calibrated to the desired value corresponding to the N% margin. Next, the worst - case droop - workload (with a large di / dt event that causes the worst - case droop) is executed, and the droop sensor is adjusted to mitigate these worst - case droops, such that the output of the minimum droop - sensor never drops below the desired calibrated value, and thus, an N% margin is maintained for each droop - sensor position during the droop - workload. This droop sensing adjustment is adjusted to provide the desired N% margin across various VDD setting point values. At lower VDD setting points, when a higher current workload with a larger di / dt event is executed, the droop sensor detects the droop more frequently, and droop mitigation is required more frequently to maintain the desired N% timing margin for each sensor position. Each droop - mitigation event, or a period of constant droop mitigation, generally results in a clock frequency reduction or instruction - throttle that can reduce performance. Thus, after droop - sensor calibration and adjustment, the next step is to select a VDD setting point high enough such that droop - mitigation events are rare, so that an unacceptable performance loss does not occur for the selected performance - workload. The calibration and adjustment parameters for each droop sensor and the VDD setting point that results in acceptable performance are stored in the VPD.When the Vmin - workload, droop - workload, and performance - workload accurately reflect the customer's environment, and when the power delivery network (PDN) and thermal environment in the manufacturing test environment exactly match the customer's environment, there is also an N% timing margin in the customer application. Unfortunately, it is difficult to predict and account for the characteristics of all customer workloads, PDNs, and thermal environments during manufacturing tests. Therefore, to ensure the reliability of the system, the timing margin of N% is typically increased. This results in higher voltage and higher power. Voltage is typically limited due to concerns about device and dielectric long - term reliability, and power is also limited by cooling capacity constraints. Therefore, increasing the N% to increase the timing margin generally reduces the chip yield and the achievable system performance. One or more embodiments are configured to provide a reduction in the timing margin that is beneficial for static and dynamic power consumption and chip yield. In other words, the reduced timing margin allows the processor to be executed at a higher clock frequency or, alternatively, more cores or processors can be configured while maintaining within the voltage and power constraints, thereby improving the functionality of the computer system. In particular, one or more embodiments use dynamic guardbands to account for idle workloads (or small workloads) that require little or no processing and extreme workloads that require intensive processing. The dynamic guardbands use droop sensor trip points to account for any variations in the devices on the chip, the chip itself, the power delivery network, the thermal environment of the chip, or the workload being executed on the chip. As a result, the dynamic guardbands can change automatically (continuously) in - flight in the computing environment.

[0033] The droop sensor can be digital or analog, can directly sense voltage, or they can sense the delay of a circuit that is sensitive to voltage and cycle time. In one or more embodiments, a digital droop sensor that is sensitive to both voltage and cycle time is used. The digital delay sensor is calibrated by adding or subtracting delay elements from a delay line. Any type of analog or digital droop sensor can be used to calibrate and adjust the droop sensor. In one embodiment, the droop sensor is calibrated using the Vmin workload, and then a separate adjustment process is used to select a threshold to trigger the droop relaxation response in the case of the largest and fastest droop in the worst-case scenario. In other embodiments, different methods and sequences can be used to calibrate and / or adjust the droop sensor to provide the desired droop-relaxation behavior. Further, the droop sensor can be any type of margin sensor such as an analog timing sensor, a digital voltage sensor, or an analog voltage sensor. In general, any type of margin sensor can be utilized in one or more embodiments. Since the digital droop sensor is a timing margin sensor, the system can adjust the threshold of this timing margin sensor by adjusting / calibrating the delay of the digital droop sensor. It should be understood that other margin sensors with various types of thresholds can be used in one or more embodiments. In one or more embodiments, it may be confirmed that the timing or voltage margin is temperature-sensitive. For this reason, the system can adjust the margin threshold as a function of temperature to avoid recoverable errors even before they occur at high temperatures.

[0034] According to one or more embodiments, a dynamic guard band with performance protection prevents and / or reduces core performance degradation. A chip (e.g., a processor) has a given digital loop sensor trip point. Each time a workload on the core crosses that digital loop sensor trip point at a voltage level, a given performance degradation occurs. According to one or more embodiments, with the configuration / assumption that the voltage of the core is increased and the digital loop sensor trip point just maintains that voltage level, the distance between the new voltage setting point of the chip and the digital loop sensor trip point is increased as shown in FIGS. 8A and 8B. Next, this means that for a workload that had a performance hit earlier because it crossed the digital loop sensor trip point prematurely, the same workload no longer crosses the digital loop sensor trip point when using the new voltage setting point, and thus no longer exhibits performance degradation (e.g., a performance hit). Therefore, a dynamic guard band with performance protection can dynamically change the voltage setting point (also referred to as the VDD voltage, drain voltage, positive supply voltage) to provide dynamic performance protection.

[0035] In one or more embodiments, a dynamic guard band with timing protection that dynamically increases / decreases the calibration and adjustment of the digital loop sensor within each core can integrate a dynamic guard band with performance protection that dynamically increases / decreases the voltage setting point (e.g., the VDD voltage) of the core. For purposes of explanation and ease of understanding, the dynamic guard band with timing protection and the dynamic guard band with performance protection can be described separately, but it is envisioned that both functions are integrated for use in improving a computer system.

[0036] One or more embodiments of the present invention provide improvements to a processor, particularly improvements in cores on the processor. Optimizing the timing guard band reduces the probability or rate of margin-related circuit errors while minimizing voltage and power for higher efficiency, and at the same time, the performance guard band prevents performance degradation in the cores of the processor caused by an excessive amount of droop-relaxation action. This operation of the core results in an improvement in its own computer system by finely tuning the operation of the core on the processor during runtime, when the processor core executes instructions. Moreover, the dynamic guard band with timing protection and / or the dynamic guard band with performance protection are configured to operate the processor strongly at a high level while reducing the probability or rate of recoverable or non-recoverable circuit errors.

[0037] Referring to FIG. 1, computer system 100 is generally shown in accordance with one or more embodiments of the present invention. Computer system 100 can be an electronic computer framework that includes and / or employs computing devices and networks using various communication technologies in any number and combination, as described herein. Computer system 100 can be easily scalable, extensible, modular, and can have the ability to change to different services or reconfigure some features independently from other features. Computer system 100 can be, for example, a server, a desktop computer, a laptop computer, a tablet computer, or a smartphone. In some examples, computer system 100 can be a cloud computing node. Computer system 100 can be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, and data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system 100 may be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may be arranged on both a local computer system storage medium including a memory storage device and a remote computer system storage medium.

[0038] As shown in FIG. 1, computer system 100 has one or more central processing units (CPUs) 101a, 101b, 101c, etc. (collectively or generically referred to as processor 101). Processor 101 can be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 101, also referred to as a processing circuit, is coupled to system memory 103 and various other components via system bus 102. System memory 103 can include read-only memory (ROM) 104 and random access memory (RAM) 105. ROM 104 is coupled to system bus 102 and can include a basic input / output system (BIOS) that controls certain basic functions of computer system 100, or a successor such as the Unified Extensible Firmware Interface (UEFI). RAM is a read-write memory coupled to system bus 102 for use by processor 101. System memory 103 provides a temporary memory space for the operation of the above instructions during operation. System memory 103 can include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0039] Computer system 100 includes an input / output (I / O) adapter 106 and a communication adapter 107 coupled to system bus 102. I / O adapter 106 can be a small computer system interface (SCSI) adapter that communicates with hard disk 108 and / or any other similar component. I / O adapter 106 and hard disk 108 are collectively referred to herein as mass storage 110.

[0040] Software 111 for execution on computer system 100 may be stored in mass storage 110. Mass storage 110 is an example of a tangible storage medium readable by processor 101, where software 111 is stored as instructions for execution by processor 101 to cause computer system 100 to operate as described hereinafter in this specification with respect to the various figures. Examples of computer program products and execution of such instructions are described in more detail herein. Communication adapter 107 interconnects system bus 102 with network 112, which may be an external network, enabling computer system 100 to communicate with other such systems. In one embodiment, a portion of system memory 103 and mass storage 110 are collectively stored in an operating system, which may be any suitable operating system, to coordinate the functions of the various components shown in FIG. 1.

[0041] Additional input / output devices are shown as being connected to system bus 102 via display adapter 115 and interface adapter 116. In one embodiment, adapters 106, 107, 115, and 116 may be connected to one or more I / O buses that are connected to system bus 102 via an intermediate bus bridge (not shown). Display 119 (e.g., a screen or display monitor) is connected to system bus 102 by a display adapter 115 that may include a graphics controller to improve the performance of graphics-intensive applications and video controllers. Keyboard 121, mouse 122, speaker 123, etc. may be interconnected to system bus 102 via an interface adapter 116 that may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit. Appropriate I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI) and Peripheral Component Interconnect Express (PCIe). Thus, as configured in FIG. 1, computer system 100 includes processing capabilities in the form of processor 101, storage capabilities including system memory 103 and mass storage 110, input means such as keyboard 121 and mouse 122, and output capabilities including speaker 123 and display 119.

[0042] In some embodiments, communication adapter 107 can transmit data using any suitable interface or protocol, such as, among other things, an Internet Small Computer System Interface. Network 112 can be, among other things, a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet. An external computing device can be connected to computer system 100 through network 112. In some examples, the external computing device can be an external web server or a cloud computing node.

[0043] It should be understood that the block diagram of FIG. 1 is not intended to show that computer system 100 includes all of the components shown in FIG. 1. Rather, computer system 100 can include any suitable fewer or additional components not shown in FIG. 1 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Further, the embodiments described herein in connection with computer system 100 can be implemented with any suitable logic. The logic referred to herein can include, in various embodiments, any suitable hardware (e.g., among other things, a processor, an embedded controller, or an application specific integrated circuit), software (e.g., among other things, an application), firmware, or any suitable combination of hardware, software, and firmware.

[0044] FIG. 2 shows a block diagram of an exemplary computer system 202 configured to provide a dynamic guard band with timing protection and / or a dynamic guard band with performance protection to a processor core on a processor according to one or more embodiments of the present invention. There may be many connected processors 204 forming drawers, and there may be many interconnected drawers. A computer system 202 having a plurality of processors 204 may be regarded as a drawer. Many features of the computer system 100 including hardware and software may be integrated into the computer system 202. The computer system 202 includes a processor 204, where details of an exemplary processor are shown, and the processor 204 has a plurality of cores 220A through 220N, where N represents the last number of the foregoing elements. The processor cores 220A through 220N may be generally referred to as processor cores 220. Each of the processor cores 220A through 220N has its own digital loop sensor (DDS) 222A through 222N, throttle meter 224A through 224N, and firmware (FW) 226A through 226N. The digital loop sensors 222A through 222N may be generally referred to as digital loop sensors 222. The throttle meters 224A through 224N may be generally referred to as throttle meters 224. Similarly, the firmware 226A through 226N may be generally referred to as firmware 226.

[0045] One or more power circuits 230 are controlled by a controller 232 to provide power to each core 220A through 220N on the processor 204. Firmware 236 may be utilized to control one or more operations of the power circuit 230 and / or the controller 232. In one or more embodiments, any one or more of firmware 226A through 226N and firmware 236 may be configured as (separate) state machines. For example, firmware 226A through 226N and firmware 236 may be implemented as on-chip state machines. A circuit that operates according to a particular sequence of events is called a state machine or a sequential circuit. A state machine requires memory to store information about past actions, and it uses that memory to help determine what action to take next.

[0046] The computer system 202 may include and / or represent various software applications such as software 111 that may be executed as instructions on one or more processors 101 for execution according to one or more embodiments of the present invention. Although not shown, the processor 204 includes all hardware and software elements for functioning as understood by one of ordinary skill in the art, including logic units, caches, registers, fetch circuits, decode circuits, execution circuits, clocks, buses, and the like. The computer system 202 may represent one or more portions of the cloud computing environment 50 shown in FIG. 12. A dynamic guard band with timing protection and / or a dynamic guard band with performance protection may be incorporated and / or integrated into the hardware and software layer 60 shown in FIG. 13. FIGS. 12 and 13 are further described herein.

[0047] For ease of understanding and without limitation, the exemplary scenario uses core 220A to illustrate the use of a dynamic guard band with timing protection and / or performance protection. Similarly, it should be understood that a dynamic guard band with timing protection and / or performance protection can be executed simultaneously from core 220A to 220N according to one or more embodiments. Similarly, a dynamic guard band with timing protection and / or performance protection can be executed simultaneously in processor 204.

[0048] FIG. 3 is a flowchart of a process 300 that uses a dynamic guard band with timing protection in processor 204 according to one or more embodiments. Reference may be made to any of the figures described herein.

[0049] In block 302 of process 300, the firmware 226A of core 220A is configured to monitor the operation of core 220. By communicating with the digital loop sensor 222A, the firmware 226A can monitor the voltage droop (or decrease) in core 220A when core 220A processes workload instructions. By communicating with the throttle meter 224A, the firmware 226A can monitor the performance degradation of core 220A when the core processes a workload. FIG. 7A shows a voltage graph over time of core 220 executing a workload. As can be seen in FIG. 7A, core 220 has a default digital loop trip point at a set voltage level (e.g., VPD). In one or more embodiments, each of cores 220A through 220N can have the same digital loop trip point in their respective digital loop sensors 222A through 220N. In one or more embodiments, one or more of cores 220A through 220N can be set at different digital loop trip points, and / or the digital loop trip points of one or more cores can change over time according to their operation. When core 220 operates above the digital loop trip point, there is no performance hit and no action is taken. In other words, the voltage level of the core does not drop to the digital loop trip point. However, when the processor (or core 220) reaches or drops below the digital loop trip point, suspend execution events are inserted into some of the cores 220. When the execution event is interrupted for core 220, the effect is that those cores 220 no longer execute on each clock cycle and instead pause for a given cycle. This not only reduces the voltage droop but also affects performance. In other words, the execution of instructions is delayed during a given clock cycle, thereby being identified as a suspend execution event.

[0050] In FIG. 7A, the core 220 may be allowed to have a voltage droop (decrease) to a core recovery (zone) a predetermined number of times, but the core 220 is not allowed and / or is always prevented from drooping (decreasing) into a check stop or an irrecoverable error (zone). Core recovery is a process on the processor 202 that resets the core to the last known good architectural state (checkpoint state). Core recovery may include clearing the cache (i.e., array built-in self-test (ABIST)), resetting the state machine, and restoring any shadow copies of architectural registers to the last known good state. In other words, the processor 204 is configured to store the architectural state of a given register. When that is done, the processor 204 is configured to reset a given core 220. Therefore, the processor 204 is configured to clear the cache (done by ABIST), reset a given state machine to idle, reload the architectural state into a given register, and then continue execution therefrom. All of these occur while the core 220 remains in its executing state.

[0051] An irrecoverable error of the core occurs when core recovery fails. The irrecoverable error results in a check stop, which in turn stops the clock of that core 220 and the core 220 is unable to make forward progress. In some cases of the processor 204, there is a process of still evacuating the workload being executed on that core to a spare core or, if there is no available spare core, adding this workload to the core 220 on which it was already being executed.

[0052] Referring back to FIG. 3, in block 304, the firmware 226A of core 220A is configured to detect a core recovery event. A core recovery event occurs when a workload instruction is being processed, and the intensity or requirements of the workload cause the voltage of core 220 to droop to and / or below the core recovery voltage threshold of core recovery. Under normal conditions, such as a steady-state workload and nominal temperature, core 220 operates at its nominal voltage (e.g., the supply voltage or near it), and there is little or no voltage droop. In this case, when the workload switches from the idle state to the fully executing state (immediately), this change in activity appears as the worst-case voltage droop, as shown by a large voltage droop across the core recovery voltage threshold in FIG. 7A. The DDS trip point must be set to exceed the checkpoint threshold because adding the droop mitigation response time to the DDS sensing time allows the voltage to continue to drop after it passes the DDS trip point.

[0053] In response to detecting a core recovery event, the firmware 226A of core 220A is configured to perform a core recovery. The processor 204 is configured to perform a core recovery as described herein. Further, the processor 204 can perform any core recovery process as would be understood by one of ordinary skill in the art.

[0054] In block 306, if the number of core recovery events during the set period meets or exceeds the core recovery event threshold, the flow proceeds to block 308. If the number of core recovery events during the set period does not meet or exceed the core recovery event threshold, the flow proceeds to block 302.

[0055] In block 308, the firmware 226A of the core 220A is configured to check whether the value of one or more loop sensor calibrations or the adjustment parameters of the digital loop sensor 222A have reached their maximum values. In other words, the firmware 226A can check whether the loop sensor calibration or adjustment parameter is already at the maximum delay, which means that no further delay is desired. In one or more embodiments, block 308 may not be triggered until a predetermined number of core recovery events occur for the core. For example, two core recovery events may be utilized to trigger block 308 because the first recovery event may have had an anomaly, but the second recovery event indicates that further action is guaranteed for the core. In one or more embodiments, the predetermined number of core recovery events required to trigger block 308 may be in the range of about 1 to 5 core recovery events.

[0056] There can be various delay units in the loop sensor delay parameter. For example, the range of the delay unit can be in the range from 0 to 255, where each delay unit can be a delay of 5 picoseconds (ps), and / or where each delay unit corresponds to adding a delay element. For the purpose of illustration, if the core has a cycle time of 4 GHz, the nominal value of the loop sensor delay parameter can be 100 delay units or 500 ps corresponding to two clock cycles of 250 ps each. Although exemplary values are described, larger or lower values can be utilized due to the delay of the core's delay units and cycle time. For the purpose of illustration, FIG. 11 shows an exemplary digital loop sensor according to one or more embodiments. The programmable delay can be increased (or decreased) as described herein, where an increase in the programmable delay delays the workload instructions in their execution, while a decrease in the programmable delay causes the workload instructions not to be delayed (or be less delayed) in their execution. The programmable delay has a maximum value. The maximum delay can also be a set delay for limiting the resulting increase in voltage, current, and power that can occur when the delay of the loop sensor increases. When both timing protection and voltage protection are active, increasing the timing protection with a loop sensor delay increase can result in more performance loss, and thus, a dynamic margin with performance protection can be generated to increase VDD. Without a limit on the DDS delay, this can result in exceeding the voltage, current, or power limit and contributing to thermal runaway. Moreover, the larger the programmable delay setting, the less signal propagation (the lower the detected edge value) through the edge detector circuit shown in FIG. 11. The lower edge detection values are correlated with voltage droop events, and thus, they trigger the throttle of instruction execution. The programmable delay can thus be used to indirectly set the threshold for the voltage level at which the throttle is triggered.

[0057] In block 310, if the maximum value of the parameter has not been reached (NO), the firmware 226A of the core 220A is configured to increase the delay value or adjustment parameter of the loop sensor calibration in the digital loop sensor 220A. The digital loop sensor 222 (circuit) has a delay element. To increase the digital loop trip point to a higher voltage setting point as shown in FIG. 7B, the firmware 226A increments the loop sensor delay and / or trigger threshold in the digital loop sensor 222. By increasing the DDS delay, the voltage level of the trip point, or the threshold at which the instruction execution throttle is triggered, increases indirectly. An exemplary nominal delay value is 100. Next, to increase the sensitivity of the digital loop sensor trip point, the firmware 226A increases the value (of the digital loop sensor) from 100 to 101, 102, 103, 104, etc., as needed to control the circuit error ratio and recovery events. When the firmware 226A increases the digital loop sensor trip point, this triggers the execution throttle at a higher voltage for the loop relaxation reaction. This throttle stops the voltage from drooping and often increases it, which gives the core 220 more timing margin during voltage droop or during high current operation of a heavy workload. Additionally, the firmware 226A is configured to dynamically reduce the timing margin as described below in FIG. 4 if the rate of recovery events drops below a threshold. This reduces the performance provided by the loop-relaxation instruction throttle. Since the performance loss has decreased, this also results in a dynamic margin with a performance protection control loop that reduces the voltage, thereby reducing the current and power for improved efficiency.

[0058] As further seen in FIG. 7B, the voltage graph is shown for core 220 that executes a workload over time as the voltage set point is increased to a new digital loop sensor trip point as the digital loop sensor trip point. The new voltage set point corresponds to increasing the amount of delay for core 220. As seen in FIG. 7B, there is a maximum voltage at which the digital loop sensor trip point can be moved from the original DDS sensor input corresponding to the original DDS delay stored in the VPD. In one or more embodiments, the maximum voltage change of the voltage set point can be 10 millivolts (mV), 15 mV, 20 mV, 25 mV, 30 mV, etc. The firmware 226A can have a preset step / increment to move the DDS delay and the resulting DDS sensor trip point before stopping at the maximum DDS delay. Note that when the clock frequency changes, the relationship between the DDS delay and the trip point voltage changes, and thus these figures represent operation at a single frequency. For example, for each recovery event (or a preset number of recovery events), the firmware 226A can move the DDS trip point up to a voltage level of "J" mV until the amount of maximum voltage change reaches the digital loop sensor trip point, where J is the step / increment, and where J can be 5 mV, 10 mV, etc.

[0059] FIG. 4 is a flowchart of a process 400 using a dynamic guard band with timing protection for a processor 204 according to one or more embodiments. FIG. 4 can continue the process described in FIG. 3. In block 402 of process 400, the firmware 226A of core 220A is configured to monitor the operation of core 220. The firmware 226A can monitor the voltage droop (or decrease) in core 220A as core 220A processes a workload by communicating with the digital loop sensor 222A.

[0060] In block 404, the firmware 226A of core 220A is configured to determine / check the number of core recovery events within a predetermined time after increasing to a new / updated voltage level for a voltage set point. The predetermined time after the last increase of the voltage set point for the digital loop sensor trip point can range from about 3 minutes to about 50 minutes. As described herein, a core recovery event can occur when a workload instruction is being processed, and the intensity or requirements of the workload cause the voltage of core 220 to droop to and / or below the core recovery voltage threshold of core recovery.

[0061] In block 406, the firmware 226A of core 220A is configured to check whether the number of core recovery events at a predetermined time meets and / or drops below a reduced delay core recovery event threshold. In one or more embodiments, the reduced delay recovery event threshold can be 0 recovery events at a predetermined time. In one or more embodiments, the reduced delay recovery event threshold can be a number of core recovery events less than the number of core recovery events that caused an increase in the voltage set point for the digital loop sensor trip point. In one or more embodiments, the reduced delay recovery event threshold can be less than the predetermined number of core recovery events required to trigger block 308 in FIG. 3. If the number of core recovery events at a predetermined time does not meet and / or does not drop below the reduced delay core recovery event threshold (NO), the flow returns to block 402 and continues monitoring by processor 204.

[0062] In block 408, if the number of core recovery events at a predetermined time has met and / or fallen below the reduced delay core recovery event threshold (YES), the firmware 226A of core 220A is configured to check whether the values of one or more digital loop sensor delay parameters have reached their minimum values. The range of the delay unit can be in the range of 0 to 255, and as a result, the minimum value (or the lowest value) of the digital loop sensor delay parameter is 0, while the maximum value is 255. It should be understood that different ranges can be utilized. If the minimum value of the digital loop sensor delay parameter has been reached (YES), the flow returns to block 402.

[0063] In block 410, if the value of the digital loop sensor delay parameter has not reached its minimum value (NO), the firmware 226A of core 220A is configured to decrease the value of one or more digital loop sensor delay parameters by a predetermined amount, thereby decreasing the voltage setting point of the digital loop sensor trip point. In one or more embodiments, the sensor trip point of the digital loop sensor trip point can be decremented by the same stage / unit by which the DDS sensor point can be incremented. The firmware 226A can have a preset stage / decrement to move the digital loop sensor trip point before stopping at the minimum digital loop sensor trip point. For example, the firmware 226A can move the digital loop sensor trip point downward to a voltage level of "J" mV as the stage until the maximum amount of voltage change reaches the digital loop sensor trip point, where J can be 5 mV, 10 mV, etc. In one or more embodiments, the firmware 226A can decrement the voltage setting point of the digital loop sensor trip point by the amount of the overall maximum voltage change in one time. In one or more embodiments, the maximum voltage change can be 10 millivolts (mV), 15 mV, 20 mV, 25 mV, 30 mV, etc.

[0064] In one or more embodiments, the firmware 226 of the core 220 is configured to perform a digital loop sensor delay test on the digital loop sensor 222 as a manufacturing test or in the field, identify one or more digital loop sensor delay parameter sets, evaluate one or more digital loop sensor delay parameter sets, and load a preferred digital loop sensor delay parameter set. Evaluating one or more digital loop sensor delay parameter sets further includes the firmware 226 of the core 220 comparing one or more digital loop sensor delay parameter sets, identifying a particular digital loop sensor delay parameter, and selecting a digital loop sensor delay parameter set having the lowest particular digital loop sensor delay parameter as the preferred digital loop sensor delay parameter set. The firmware 226 of the core 220 is configured to use timing checks to detect a first number of core recovery events and a second number of core recovery events. The digital loop sensor delay parameters of the processor are selected from a group including yield and power.

[0065] FIG. 5 is a flowchart of a process 500 using a dynamic guard band with performance protection for a processor 204 according to one or more embodiments. Reference may be made to any of the figures described herein. In FIGS. 5 and 6, an exemplary scenario using the core 220A may be continued for ease of understanding and consistency. Again, it should be understood that all cores 220A through 220N of the processor 204 perform a dynamic guard band with performance protection and a dynamic guard band with timing protection simultaneously as described herein. Similarly, a dynamic guard band with performance protection and a dynamic guard band with timing protection may be performed simultaneously on the processor 204 in the computer system 202.

[0066] In block 502 of process 500, the firmware 226A of core 220A is configured to monitor the operation of core 220. By communicating with the digital loop sensor 222A, the firmware 226A can monitor the voltage droop (or decrease) in core 220A when core 220A processes a workload. By communicating with the throttle meter 224A, the firmware 226A can monitor the performance degradation of core 220A when the core processes a workload. In one or more embodiments, droop mitigation can be achieved using frequency reduction instead of instruction throttling. In this case, the performance loss is caused by the core frequency reduction instead of instruction throttling. In this embodiment, the droop event results in a frequency reduction instead of instruction throttling. In this embodiment, instead of monitoring instruction throttling to determine the performance loss, the firmware monitors the frequency reduction to determine the performance loss. In one or more embodiments, both instruction throttling and frequency reduction can be used simultaneously to reduce the droop. Therefore, the firmware monitors both instruction throttling and frequency reduction to determine the performance loss.

[0067] In block 504, the firmware 226A of core 220A is configured to detect a first amount of throttle within a predetermined time to measure the throttle. The throttle meter 224A measures the number of cycles in which the throttle meter is active at a predetermined time. In this case, the first throttle threshold can range from 1 to millions. In one or more embodiments, the throttle meter measures the number of throttle amounts at a predetermined time.

[0068] The throttle meter 224 is a circuit (which may include and / or be coupled to a counter) that provides an indication of how a suspend execution cycle can be asserted to each core in the processor. The read value of each throttle meter corresponds to a (single) suspend execution cycle. This number of suspend execution cycles scales with the performance degradation. Consequently, the level of performance degradation of core 220 directly corresponds to a predetermined number of suspend execution cycles being experienced by core 220.

[0069] In one or more embodiments, the predetermined time for checking the throttle amount can range from microseconds to minutes or hours. In one or more embodiments, the predetermined time for checking the throttle amount can range from about 1 minute to about 1 hour. In one or more embodiments, the predetermined time for checking the throttle amount can shift from a lower number such as 1 minute to a higher number such as 5 minutes since a lower throttle amount was detected or no throttle amount was detected since the previous check.

[0070] In block 506, the firmware 226A of core 220A is configured to check whether a first amount of throttle within a predetermined time for checking the throttle has an associated performance degradation greater than a first performance degradation threshold. The first performance degradation threshold can be set at a 1% performance degradation of core 220A. In one or more embodiments, the first performance degradation threshold can range from about 0.1% performance degradation to about 3% performance degradation of core 220A. The performance degradation for the first amount of throttle can correspond to a specific number of suspend execution cycles, and the firmware 226A can convert the number of suspend execution cycles of core 220A to a percent performance degradation, for example, using a table in the firmware or elsewhere. The firmware 226A is configured to check whether the (percent) performance degradation or the number of suspend execution cycles for the first amount of throttle is greater than the first performance degradation threshold, for example, greater than a 1% performance degradation.

[0071] In one or more embodiments, the first performance degradation threshold may correspond to the suspend execution cycle threshold. In one or more embodiments, the firmware 226A may check whether a first amount of throttle having a number of suspend execution cycles (which may be no suspend execution cycles in one case) is greater than the first performance degradation threshold which is the number of suspend execution cycles as a threshold.

[0072] In block 514, if the first amount of throttle within a predetermined time for checking the throttle amount has an associated performance degradation that is not greater than the first performance degradation threshold (NO), the firmware 226A of the core 220A is configured to maintain the supply voltage at its current voltage level (i.e., its current voltage setting). For purposes of example, FIG. 8A shows a voltage graph over time of the core 220 executing a workload. As can be seen, the workload has its crest or peak at the original / current supply voltage before the voltage droop to the core recovery (zone). Based on blocks 506 and 514, it is assumed that no change has been made to the supply voltage supplied to the core 220A.

[0073] In block 508, if the first amount of throttle within a predetermined time for checking the throttle amount has an associated performance degradation that is greater than the first performance degradation threshold (YES), the firmware 226A of the core 220A is configured to check whether the power usage condition is satisfied to increase the supply voltage.

[0074] Core 220A is on the processor (chip) 204. In the drawer (or computer system 202), there may be multiple processor chips 204. The drawer is interconnected to other drawers using known methods as understood by those skilled in the art. The power supply usage (PSU) condition is that the PSU of the drawer containing core 220A is less than the power supply usage threshold (i.e., the PSU of the drawer < PSU threshold). In one or more embodiments, the PSU threshold can range from about 3000 watts (W) to about 3900 W. If the power supply usage condition is not met (i.e., the PSU of the drawer > PSU threshold), the flow proceeds to block 514 without increasing the supply voltage of core 220A.

[0075] As an additional check for the power supply usage condition that can be optionally added to block 508, the power supply usage may also include verifying that the PSU of the drawer (computer system 202) containing core 220A is not greater than the maximum power supply usage of the drawer. If not greater, this part of the condition is satisfied or met to increase the supply voltage for core 220A. On the other hand, if the PSU of the drawer (computer system 202) containing core 220A is greater than the maximum power supply usage of that drawer, the firmware 226A of core 220A is configured to revert the firmware 236 of the power circuit 230 to the default settings for supplying power to all of cores 220A to 220N from core 220A within the processor 204.

[0076] Furthermore, it should be noted that the firmware 236 can be integrated with the controller 232 to control the supply voltages respectively supplied from cores 220A to 220N on the processor 204. In one or more embodiments, the firmware 226 operably communicates with the firmware 236 of the power circuit 240 to provide and vary the supply voltages provided from cores 220A to 220N.

[0077] In block 510, when the power usage condition is met to increase the supply voltage (i.e., the PSU of the drawer < PSU threshold), and optionally including that the PSU of the drawer including core 220A is not greater than the maximum power usage of that drawer, the firmware 226A of core 220A is configured to check whether the supply voltage supplied to core 220A has been increased to the maximum supply voltage for core 220A. As described herein, there are permitted changes in the maximum supply voltage as shown in FIGS. 8A and 8B. The firmware 226A of core 220A checks whether the supply voltage has already been increased to the permitted maximum supply voltage. If (YES), the supply voltage supplied to core 220A is increased to the maximum supply voltage for core 220A, and the flow proceeds to block 514.

[0078] In block 512, when (NO), the supply voltage supplied to core 220A is not increased to the maximum supply voltage of core 220A, and the firmware 226A of core 220A is configured to increase the supply voltage to core 220A by a predetermined amount / step. FIG. 8B shows a graph of the voltage over time of core 220 executing a workload with an increased supply voltage. In FIG. 8B, increasing the supply voltage vertically shifts the entire graph of the workload upward by the increased voltage setting point increase amount, and in these cases, no droop mitigation is required. In FIG. 8B, the dashed curve illustrates the old position of the graph of the workload, while the solid curve is the new position of the graph of the workload indicating that the crest is now at the new supply voltage (new VDD). In FIG. 8B, the digital loop sensor trip point remains at the voltage setting point. For this reason, the voltage in the DDS sensor crosses the DDS trip point later in time, and the droop mitigation stops the droop at approximately the same minimum voltage. As described herein, by increasing the supply voltage of the core 220 and assuming that the digital loop sensor trip point remains exactly at the fixed voltage level, as shown in FIG. 8B, the distance between the new supply voltage for the core 220 and the digital loop sensor trip point is increased. Then, this means that a workload that crossed the digital loop sensor trip point earlier (and thus suffered a performance hit) may no longer cross the digital loop sensor trip point here (using the new supply voltage setting), and thus, no longer exhibits a performance hit / deterioration. Generally, the performance loss decreases with an increase at the VDD setting point.

[0079] In one or more embodiments, the maximum change amount for increasing the supply voltage to the core 220 can be in the range of about 10 mV to 30 mV. In one or more embodiments, there are a predetermined number of steps for increasing the supply voltage of the core 220. In one or more embodiments, the predetermined amount / step for increasing the supply voltage to the core 220 can be four steps, each being 5 mV for a maximum change amount of 20 mV. In one or more embodiments, the processor 204 can have a total maximum change amount of about 20 mV (for all of the cores 220). In one or more embodiments, a drawer (or computer system 202) having a plurality of processors 204 can have the maximum number of predetermined amounts / steps. For example, if there are 20 predetermined steps of 5 mV each for the drawer, then the drawer can increase by a total of 100 mV.

[0080] FIG. 6 is a flowchart of a process 600 using a dynamic guard band with performance protection for a processor 204 according to one or more embodiments. FIG. 6 can continue the process described in FIG. 5. Reference may be made to any of the figures described herein. In block 602 of process 600, the firmware 226A of core 220A is configured to monitor the operation of core 220A. The firmware 226A can monitor the voltage droop (or decrease) in core 220A when core 220A processes a workload by communicating with the digital loop sensor 222A. The firmware 226A can monitor the performance degradation of core 220A when the core processes a workload by communicating with the throttle meter 224A.

[0081] In block 604, the firmware 226A of core 220A is configured to detect a second amount of throttle within a predetermined time to measure the throttle. The second amount of throttle is the same as or less than the first amount of throttle measured by throttle meter 224A. The second amount of throttle may be 1, 2, 3, 4, 5, 6 to 10 times less than the first amount of throttle. As described herein, the predetermined time for checking the throttle amount may be about every 2 minutes. In one or more embodiments, the predetermined time for checking the throttle amount may range from approximately (a number) microseconds to 24 hours. In one or more embodiments, the predetermined time for checking the throttle amount may shift from a lower number such as 2 minutes to a higher number such as 5 minutes because a smaller throttle amount has been detected or no throttle amount has been detected since the previous check.

[0082] In block 606, the firmware 226A of core 220A is configured to check whether there is an associated performance degradation in which the second amount of throttle within a predetermined time for checking the throttle amount is less than a second performance degradation threshold. The second performance degradation threshold may be set at a 0.1% performance degradation of core 220A. In one or more embodiments, the second performance degradation threshold may range from approximately 0.00% to approximately 1.0% performance degradation of core 220A. Similar to the above description, the performance degradation for the second amount of throttle may identify a specific number of suspend execution cycles, and the firmware 226A may convert the number of suspend execution cycles of core 220A to a percent performance degradation using, for example, a table in the firmware or elsewhere. The firmware 226A is configured to check whether the (percent) performance degradation or the number of suspend execution cycles for the second amount of throttle is less than the second performance degradation threshold, for example, less than a 0.1% performance degradation.

[0083] In one or more embodiments, the second performance degradation threshold may correspond to the suspend execution cycle threshold. In one or more embodiments, the firmware 226A may check whether the second amount of throttle having the number of suspend execution cycles (in one case there may be no suspend execution cycles) is less than the second performance degradation threshold which is the number of suspend execution cycles (as a threshold).

[0084] In block 608, if the second amount of throttle within a predetermined time for checking the throttle amount has an associated performance degradation that is less than the second performance degradation threshold (YES), the firmware 226A of the core 220A is configured to reduce the supply voltage. Similar to the maximum change amount for increasing the supply voltage to the core 220 and the predetermined amount / stage for each increase described in FIG. 5, the same may apply for reducing the supply voltage to the core. In one or more embodiments, the maximum change amount for reducing the supply voltage to the core 220 may range from about 10 mV to 30 mV. In one or more embodiments, there are a predetermined number of predetermined amounts / stages for reducing the supply voltage of the core 220. In one or more embodiments, the predetermined amount / stage for reducing the supply voltage to the core 220 may be four steps, each being 5 mV for a maximum change amount of 20 mV. In one or more embodiments, the processor 204 may collectively have a total maximum change amount of about 20 mV (for all of the cores 220).

[0085] In one or more embodiments, the supply voltage may be reduced to the default supply voltage setting. In one case, the default supply voltage setting may be the original supply voltage setting shown in FIG. 8B.

[0086] In block 610, if a second amount of throttle within a predetermined time for checking the throttle amount has an associated performance degradation greater than a second performance degradation threshold (NO), the firmware 226A of core 220A is configured to maintain the supply voltage at the current setting.

[0087] FIG. 9 is a flowchart of a computer-implemented method 900 of a dynamic guard band with timing protection for a processor core 220 of a processor 204 according to one or more embodiments. Reference may be made to any of the figures described herein. In block 902, the firmware 226 of core 220 (of computer system 202) is configured to detect a first number of core recovery events in processor 204 in response to monitoring processor 204 during operation. The first number of core recovery events is for core 220 such as core 220A. In one or more embodiments, the first number (and the following second number) may collectively be from core 220A to 220N.

[0088] In block 904, the firmware 226 of core 220 (of computer system 202) is configured to determine that the first number of core recovery events satisfies a first condition for a first core recovery event threshold. For example, a predetermined number of core recovery events may occur such that, as explained in block 308 in FIG. 3, a first condition for a first core recovery event threshold may be satisfied.

[0089] In block 906, the firmware 226 of the core 220 (of the computer system 202) is configured to modify the value of at least one digital loop sensor delay parameter of the processor 204 (of the digital loop sensor 222) by a first amount, and the at least one digital loop sensor delay parameter affects the execution of one or more instructions on the processor 204. For example, reference may be made to the description of block 310 in FIG. 3. As a technical solution / benefit, the firmware 226 adjusts the loop threshold (for example, by increasing the delay in the digital loop sensor 222), thereby increasing the voltage droop and sensitivity to low voltage accordingly, and thus is configured to reduce the probability or rate of recovery events. The digital loop sensor 222 has a delay adjustment for adjusting the loop threshold, but one or more embodiments may utilize a voltage adjustment knob (or parameter), or some other type of loop sensor having a method for adjusting some other loop threshold. For example, there may be an analog loop sensor that triggers a loop response for loop relaxation. Therefore, the digital loop sensor parameter may be implemented as a voltage adjustment (increase / decrease) that increases and decreases in the same manner as the delay in the digital loop sensor 222 according to one or more embodiments.

[0090] In block 908, the firmware 226 of the core 220 (of the computer system 202) is configured to detect a second number of core recovery events in the processor 204 in response to modifying the value of at least one digital loop sensor delay parameter of the digital loop sensor 222 by a first amount.

[0091] In block 910, the firmware 226 of the core 220 (of computer system 202) is configured to determine that a second number of core recovery events satisfy a second condition relative to a second core recovery event threshold. For example, as described in block 406 of FIG. 4, a second condition relative to a second core recovery event threshold (e.g., a reduced latency core recovery event threshold) is satisfied.

[0092] In block 912, the firmware 226 of the core 220 (of computer system 202) is configured to modify the value of at least one digital loop sensor delay parameter of the processor by a second amount. For example, reference may be made to block 410 of FIG. 4.

[0093] Modifying the value of at least one digital loop sensor delay parameter of the processor 204 by a first amount includes increasing the value of at least one digital loop sensor delay parameter of the processor by the first amount. For example, firmware 226A may instruct digital loop sensor 222A to increase the value of at least one digital loop sensor delay parameter. Modifying the value of at least one digital loop sensor delay parameter of the processor 204 by a second amount includes decreasing the value of at least one digital loop sensor delay parameter of the processor by the second amount. For example, firmware 226A may instruct digital loop sensor 222A to decrease the value of at least one digital loop sensor delay parameter.

[0094] Satisfying the first condition for the first core recovery event threshold includes that the first number of core recovery events is greater than the first core recovery event threshold. For example, as described using block 308, firmware 226 may determine that a predetermined number of core recovery events is greater than the first core recovery event threshold. Satisfying the second condition for the second core recovery event threshold includes that the second number of core recovery events is less than the second core recovery event threshold. For example, firmware 226 may determine that the number of core recovery events at a predetermined time has decreased below the reduced delay core recovery event threshold.

[0095] Modifying the value of at least one digital loop sensor delay parameter of processor 204 by a second amount includes returning at least one digital loop sensor delay parameter to its baseline value. Firmware 226 may instruct digital loop sensor 222 to return to the baseline value of at least one digital loop sensor delay parameter. The baseline value may be zero delay. The baseline value may be 100 delay elements. The second amount by which the value of at least one digital loop sensor delay parameter decreases may be greater than the first amount, equal to the first amount, or less than the first amount. The control loop described herein may continue indefinitely during operation of the processor. Also, while the recovery event may be for a core, it should be understood that the recovery event may be triggered by a recovery event in a circuit smaller than or larger than a "core".

[0096] FIG. 10 is a flowchart of a computer-implemented method 1000 of a dynamic guard band with performance protection for processor core 220 of processor 204 according to one or more embodiments. Reference may be made to any of the figures described herein.

[0097] In block 1002, the firmware 226 of the core 220 (of the computer system 202) is configured to detect a first amount of throttle in the processor 204 in response to monitoring the processor 204 during operation. The first amount of throttle is a predetermined number of throttle meter readings of the throttle meter 224. An example is illustrated in block 504 of FIG. 5.

[0098] In block 1004, the firmware 226 of the core 220 (of the computer system 202) is configured to determine that the first amount of throttle satisfies a first condition regarding a throttle amount threshold. The first amount of throttle has an associated performance degradation. The first condition is satisfied, which is because, for example, as illustrated using block 506 in FIG. 5, the performance degradation associated with the first amount of throttle is greater than a first performance degradation threshold. The first performance degradation threshold can be set to a performance degradation of 1%, 2%, 3%, etc. of the core 220. The performance degradation of the first amount of throttle can correspond to a specific number of suspended execution cycles.

[0099] In block 1006, the firmware 226 of the core 220 (of the computer system 202) is configured to modify the voltage level of the processor 204 by the first amount. The firmware 226 can instruct and / or communicate with the firmware 236 of the power supply circuit 230 to modify the voltage level. An example of modifying the voltage level is shown in block 512 of FIG. 5.

[0100] In block 1008, the firmware 226 of the core 220 (of the computer system 202) is configured to detect a second amount of throttle in the processor 204 in response to modifying the voltage level of the processor 204 by the first amount. The second amount of throttle is a predetermined threshold of the throttle meter 224 that follows modifying the voltage level (e.g., increasing it).

[0101] In block 1010, the firmware 226 of the core 220 (of computer system 202) is configured to determine that a second amount of throttle satisfies a second condition regarding a throttle amount threshold.

[0102] The second amount of throttle has an associated performance degradation. The second condition is satisfied, which is because, for example, as explained using block 606 in FIG. 6, the performance degradation associated with the second amount of throttle is less than a second performance degradation threshold. As an example, the second performance degradation threshold can be set at a 0.1% performance degradation of core 220, or the second performance degradation threshold can be any number within a range of approximately 0.0% to approximately 1.0% performance degradation of core 220.

[0103] In block 1012, the firmware 226 of the core 220 (of computer system 202) is configured to modify the voltage level of the processor 204 by a second amount.

[0104] The firmware 226 can instruct and / or communicate with the firmware 236 of the power supply circuit 230 to modify the voltage level. An example of modifying the voltage level is shown in block 608 of FIG. 6.

[0105] Modifying the voltage level of the processor 204 by a first amount includes, for example, increasing the voltage level of the processor by the first amount, as shown in block 512 of FIG. 5. Modifying the voltage level of the processor 204 by a second amount includes, for example, decreasing the voltage level of the processor by the second amount, as shown in block 608 of FIG. 6.

[0106] The firmware 226 of the core 220 is configured to confirm that the power consumption is less than the power consumption threshold before modifying the voltage level of the processor by a first amount. The firmware 226 of the core 220 is configured to check whether the power supply usage (PSU) is greater than the power consumption threshold (e.g., block 508), reject a request to modify the voltage level by a first amount (e.g., by firmware 236 and / or firmware 226), and maintain the current voltage level in response to the power consumption being greater than the power consumption threshold (e.g., block 514). The firmware 226 of the core 220 is configured to provide a condition for returning the voltage level to the default voltage level in response to determining that the power consumption is greater than the maximum power consumption threshold. To modify the voltage level of the processor 204, the first amount ranges from about 5 millivolts (mV) to 10 mV.

[0107] The present disclosure includes a detailed description regarding cloud computing, but it should be understood that the implementations of the teachings recited herein are not limited to cloud computing environments. Rather, embodiments of the present invention can be implemented in conjunction with any other type of computing environment, whether currently known or developed in the future.

[0108] Cloud computing is a service - delivery model that enables convenient on - demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0109] The characteristics are as follows.

[0110] On-demand self-service: Cloud consumers can unilaterally provision computing capabilities such as server time and network storage automatically as needed, without the need for human interaction with a service provider.

[0111] Broad network access: The capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs (trademark)).

[0112] Resource pooling: The provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with various physical and virtual resources dynamically assigned and reassigned according to demand. Consumers generally have no control or knowledge over the exact location of the provided resources, but may be able to specify location at a higher level of abstraction (e.g., country, state, or data center), providing a certain degree of location independence.

[0113] Rapid elasticity: Capabilities can be provisioned rapidly and elastically, in some cases automatically, scaling out quickly and also being released quickly and scaling in rapidly. In many cases, the capabilities available for provisioning appear to be unlimited to the consumer, who can purchase at any quantity at any point in time.

[0114] Measured service: Cloud systems automatically control and optimize resource use by leveraging measurement capabilities appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts) at some level of abstraction. Resource usage is monitored, controlled, and reported, providing transparency to both the provider and consumer of the utilized service.

[0115] The service model is as follows.

[0116] Software as a Service (SaaS): The ability provided to the consumer is to use the provider's applications running on cloud infrastructure. The applications are accessible from various client devices via a client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even the individual application capabilities, except for limited user-specific application configurations in some cases.

[0117] Platform as a Service (PaaS): The ability provided to the consumer is to deploy on cloud infrastructure the applications created or acquired by the consumer, using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but controls the deployed applications and, in some cases, the configuration of the application hosting environment.

[0118] Infrastructure as a Service (IaaS): The ability provided to the consumer is to provision processing, storage, networks, and other basic computing resources, and the consumer can deploy and run any software that may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but controls the operating systems, storage, deployed applications, and, in some cases, limitedly controls selected networking components (e.g., host firewalls).

[0119] The deployment model is as follows.

[0120] Private cloud: The cloud infrastructure is operated solely for an organization. It may be managed by the organization or a third party and may exist on-premises or off-premises.

[0121] Community cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with shared concerns (e.g., mission, security requirements, policies, and regulatory compliance considerations). The community cloud may be managed by those organizations or a third party and may exist on-premises or off-premises.

[0122] Public cloud: The cloud infrastructure is made available to the general public or a large industry group and is owned by an organization that sells cloud services.

[0123] Hybrid cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that remains a unique entity but is joined together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load distribution between clouds).

[0124] The cloud computing environment is service-oriented, emphasizing statelessness, loose coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0125] Referring now to FIG. 12, an exemplary cloud computing environment 50 is illustrated. As shown, cloud computing environment 50 includes one or more cloud computing nodes 10 with which local computing devices (e.g., a personal digital assistant (PDA) or cellular telephone 54A, desktop computer 54B, laptop computer 54C, and / or automotive computer system 54N, etc.) utilized by cloud consumers may communicate. The nodes 10 may communicate with one another. They may be physically or virtually grouped (not shown) in one or more networks (such as a private cloud, community cloud, public cloud, and / or hybrid cloud as described above herein, or combinations thereof). Thereby, cloud computing environment 50 can provide infrastructure, platform, and / or software as services such that a cloud consumer need not maintain resources on a local computing device therefor. The types of computing devices 54A - N shown in FIG. 12 are merely intended to be exemplary, and it is understood that cloud computing nodes 10 and cloud computing environment 50 can communicate with any type of computerized device via any type of network and / or network addressable connection (e.g., using a web browser).

[0126] Referring now to FIG. 13, a set of functional abstraction layers provided by cloud computing environment 50 (FIG. 12) is shown. It should be understood in advance that the components, layers, and functions shown in FIG. 13 are merely intended to be exemplary, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided.

[0127] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61; RISC (Reduced Instruction Set Computer) architecture-based server 62; server 63; blade server 64; storage device 65; and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0128] The virtualization layer 70 provides an abstraction layer that can provide the following examples of virtual entities: virtual server 71; virtual storage 72; virtual network 73 including a virtual private network; virtual applications and operating systems 74; and virtual client 75.

[0129] In one example, the management layer 80 may provide the functions described below. Resource provisioning 81 provides for the dynamic procurement of computing resources and other resources utilized to execute tasks within a cloud computing environment. Metering and pricing 82 provides for cost tracking when resources are utilized within a cloud computing environment and accounting or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks and protection of data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management such that the required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides for advance commitments for cloud computing resources where future requirements are expected to conform to the SLA and their procurement.

[0130] The workload layer 90 provides examples of functions that can be utilized in a cloud computing environment. Examples of workloads and functions that can be provided from this layer are: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analysis processing 94; transaction processing 95; and workloads and functions 96.

[0131] Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Various connection and positional relationships (e.g., over, below, adjacent, etc.) are described between elements in the following description and drawings, but those skilled in the art will recognize that many of the positional relationships described herein are not orientation-dependent if the described functions are maintained despite a change in orientation. These connections and / or positional relationships can be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this regard. Thus, the coupling between entities can refer to a direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, when it is said in this description that layer "A" is formed over layer "B", one or more intermediate layers (e.g., layer "C") are included in the situation existing between layer "A" and layer "B" as long as the relevant characteristics and functionality of layer "A" and layer "B" are not substantially altered by that intermediate layer.

[0132] For the sake of brevity, the prior art related to creating and using aspects of the present invention may or may not be described in detail herein. In particular, the computing systems and various aspects of the specific computer programs for implementing the various technical features described herein are well known. Thus, for the purpose of brevity, many details of conventional implementations are only briefly mentioned herein or are completely omitted without providing details of well-known systems and / or processes.

[0133] In some embodiments, various functions or operations may be performed at a given location and / or in connection with the operation of one or more devices or systems. In some embodiments, a portion of a given function or operation may be performed at a first device or location, and the remaining function or operation may be performed at one or more additional devices or locations.

[0134] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises" and / or "comprising", when used herein, specify the presence of stated features, integers, steps, operations, and / or component elements, but do not preclude the presence or addition of one or more other features, integers, steps, operations, component elements, and / or groups thereof.

[0135] The corresponding structures, materials, acts, and equivalents of any means-plus-function elements or step-plus-function elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. Although the present disclosure has been presented for purposes of illustration and description, it is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. Embodiments were chosen and described in order to best explain the principles of the present disclosure and its practical application, and to enable others of ordinary skill in the art to understand the present disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

[0136] The figures shown in this specification are illustrative. Without departing from the spirit of the present disclosure, many changes can be made to the figures or the steps (or operations) described therein. For example, actions can be performed in a different order, and actions can be added, deleted, or modified. Also, the term "coupled" describes that there is a signal path between two elements and does not imply a direct connection between elements without intervening elements / connections therebetween. All of these variations are considered to be part of the present disclosure.

[0137] The following definitions and abbreviations are used in the interpretation of the claims and the specification. As used herein, the terms "comprises", "comprising", "includes", "including", "has", "having", "contains", or "containing", or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed, or other elements inherent to such composition, mixture, process, method, article, or apparatus.

[0138] Furthermore, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or design described as "exemplary" in this specification is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term "plurality" is understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term "connected" can include both indirect "connection" and direct "connection".

[0139] The terms "about," "substantially," "approximately," and variations thereof are intended to include a degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing of this application. For example, "about" can include a range of ±8%, or 5%, or 2% of a given value.

[0140] The present invention can be a system, method, and / or computer program product integrated at any possible technical detail level. The computer program product can include one (or more) computer-readable storage media having computer-readable program instructions for causing a processor to execute aspects of the present invention.

[0141] A computer-readable storage media can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage media can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile discs (DVDs), memory sticks, floppy disks, punch cards, mechanically encoded devices such as a raised structure in a groove in which instructions are recorded, and any suitable combination of the foregoing. A computer-readable storage media should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0142] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium within the respective computing / processing device.

[0143] The computer-readable program instructions for carrying out the operations of the present invention may be source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk® or C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit in order to carry out aspects of the present invention.

[0144] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0145] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium containing the instructions comprises a manufacture including instructions for implementing the function / act mode specified in one or more blocks of the flowchart and / or block diagram.

[0146] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0147] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in an order different from that noted in the drawings. For example, two blocks shown in succession may, in fact, be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the related functionality. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0148] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.

Claims

1. In response to monitoring a processor during operation, the computer detecting a first number of throttle amounts in the processor; the computer determining that the first number of throttle amounts satisfies a first condition regarding a throttle amount threshold; the computer modifying the voltage level of the processor by a first amount; in response to modifying the voltage level of the processor by the first amount, the computer detecting a second number of throttle amounts in the processor; the computer determining that the second number of throttle amounts satisfies a second condition regarding the throttle amount threshold; and the computer modifying the voltage level of the processor by a second amount A computer-implemented method comprising.

2. The step of modifying the voltage level of the processor by the first amount includes increasing the voltage level of the processor by the first amount, the computer-implemented method according to claim 1.

3. The step of modifying the voltage level of the processor by the second amount includes decreasing the voltage level of the processor by the second amount, the computer-implemented method according to any of the preceding claims.

4. Before the step of modifying the voltage level of the processor by the first amount, further comprising the step of confirming that the power consumption is less than a power consumption threshold, the computer-implemented method according to any of the preceding claims.

5. Checking whether the power consumption is greater than a power consumption threshold; and in response to the power consumption being greater than the power consumption threshold, rejecting a request to modify the voltage level by the first amount and maintaining the current voltage level A computer-implemented method further comprising, according to any of the preceding claims.

6. Further comprising providing a condition for returning the voltage level to a default voltage level in response to determining that the power consumption is greater than a maximum power consumption threshold, the computer-implemented method according to any of the preceding claims.

7. The first amount ranges from about 5 millivolts (mV) to 10 mV, the computer-implemented method according to any of the preceding claims.

8. A memory having computer-readable instructions; and A computer for executing the computer-readable instructions, the computer-readable instructions being detecting a first number of throttle amounts in the processor in response to monitoring the processor during operation; determining that the first number of throttle amounts satisfies a first condition regarding a throttle amount threshold; modifying the voltage level of the processor by a first amount; detecting a second number of throttle amounts in the processor in response to modifying the voltage level of the processor by the first amount; determining that the second number of throttle amounts satisfies a second condition regarding the throttle amount threshold; and modifying the voltage level of the processor by a second amount controlling the computer to execute an operation having, A system comprising a computer.

9. The system according to claim 8, wherein the step of modifying the voltage level of the processor by the first amount includes increasing the voltage level of the processor by the first amount.

10. The system according to any one of the preceding claims 8 to 9, wherein the step of modifying the voltage level of the processor by the second amount includes decreasing the voltage level of the processor by the second amount.

11. The system according to any one of the preceding claims 8 to 10, further comprising a step of confirming that the power consumption is less than a power consumption threshold before the step of modifying the voltage level of the processor by the first amount.

12. checking whether the power consumption is greater than a power consumption threshold; and responding to the power consumption being greater than the power consumption threshold, rejecting a request to modify the voltage level by the first amount and maintaining the current voltage level The system according to any one of the preceding claims 8 to 11, further comprising.

13. The system according to any one of the preceding claims 8 to 12, further comprising providing a condition for returning the voltage level to a default voltage level in response to determining that the power consumption is greater than a maximum power consumption threshold.

14. The system according to any one of the preceding claims 8 to 13, wherein the first amount ranges from about 5 millivolts (mV) to 10 mV.

15. A computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions comprising: detecting, by a computer, a first number of throttle amounts in the processor in response to monitoring the processor during operation; determining, by the computer, that the first number of throttle amounts satisfies a first condition regarding a throttle amount threshold; modifying, by the computer, a voltage level of the processor by a first amount; detecting, by the computer, a second number of throttle amounts in the processor in response to modifying the voltage level of the processor by the first amount; determining, by the computer, that the second number of throttle amounts satisfies a second condition regarding the throttle amount threshold; and modifying, by the computer, the voltage level of the processor by a second amount The computer program product is executable by a computer to cause the computer to perform an operation having.

16. The computer program product according to claim 15, wherein the step of modifying the voltage level of the processor by the first amount includes increasing the voltage level of the processor by the first amount.

17. The computer program product according to any one of the preceding claims 15 to 16, wherein the step of modifying the voltage level of the processor by the second amount includes decreasing the voltage level of the processor by the second amount.

18. The computer program product according to any one of the preceding claims 15 to 17, further comprising checking that a power consumption is less than a power consumption threshold before the step of modifying the voltage level of the processor by the first amount.

19. checking whether a power consumption is greater than a power consumption threshold; and rejecting a request to modify the voltage level by the first amount and maintaining a current voltage level in response to the power consumption being greater than the power consumption threshold The computer program product according to any one of the preceding claims 15 to 18, further comprising.

20. The computer program product according to any one of the preceding claims 15 to 19, further comprising the step of providing a condition for returning the voltage level to a default voltage level in response to determining that the power consumption is greater than a maximum power consumption threshold.

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