Multi-layer integrated circuit routing tool

Abstract

A computer-implemented method for a multilayer integrated circuit routing tool that connects a source having a net to a sink in a hierarchical multilayer integrated circuit design environment, the method comprising: creating a cycle reach table including a first set of information parameters for a two-dimensional net for each combination of metal layers; creating a repeater reach table including a second set of information parameters for each constraint class; preparing a working list of nets; preparing a list of blocks larger than the repeater reach length; and connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on a selected constraint class.

Description

Technical Field

[0001] The present invention generally relates to a computer-implemented method for a multilayer integrated circuit routing tool that connects a source of a net to a sink in a hierarchical multilayer integrated circuit design environment. The present invention further relates to a data processing system and a computer program product for a multilayer integrated circuit routing tool that connects a source of a net to a sink in a hierarchical multilayer integrated circuit design environment.

Background Art

[0002] Current very complex semiconductor development uses tools such as electronic design automation (EDA) tools for the development of complex integrated circuit chips. The complexity of the chip is simplified and parallelized by hierarchically dividing the circuit into small blocks. In order to operate simultaneously at all these levels, the blocks are used as black boxes at the next hierarchical level, and the areas, metal layers and levels belonging to this block are protected by appropriate blockages.

[0003] The blocks are wired to each other from the next hierarchical level. In the process, they need to be connected to each other, and these connections can also extend across the blocks. The wiring problem includes that all timing requirements need to be met without overcrowding the wiring space. Each block is assigned a metal layer and constraints regarding the width and space to be routed through the design. The router then routes the nets on the available metal layers. A net consists of wiring implemented on the metal layer and vias connecting the metal layers. If the block is wide enough, thin wires can be routed over the block, but the use of thin wires may not be considered if ideal timing is assumed.

[0004] In this way, the defined physical characteristics, particularly the resistance-capacitance delay (RC delay), impose requirements regarding the placement of repeaters or inverters and their mutual distances. EDA constraint tools assume that the placement of these repeaters is possible anywhere, but this does not correspond to reality.

[0005] As the complexity and size of hierarchical blocks increase, these problems worsen further.

[0006] Semiconductor chips use metal layers to wire circuit components. Different metal layers can be used for different signal speeds and net lengths. In development, different methods are used to determine on which metal layer a net is routed based on a timing model or net length. The timing method considers how much delay time is available for routing a net. The net length method assigns short nets to lower, thinner, and thus slower metal layers with higher RC delays, and long nets to higher, thicker, and thus faster metal layers. Both methods assume that repeaters can be placed anywhere to refresh signals.

[0007] Neither model considers blockage in metal layer assignment. Blockage is caused by the currently used hierarchical design. The hierarchical design divides the chip into blocks of different sizes, such as cores, units, memories, etc., and then places them. These blocks are interconnected with nets via interfaces that connect between and across the blocks.

[0008] The block blocks completely or partially the wiring to a specific metal layer. It is impossible to place repeaters or inverters important for the net inside these blocks. If a metal layer is selected for nets lower than or equal to the topmost blocked layer of the block, these nets need to be routed around the block. If a thin net is routed on a block where a repeater is needed inside the area of the block, this repeater needs to be placed outside the block and thus the net needs to be extended.

Summary of the Invention

[0009] A computer-implemented method is proposed for a multilayer integrated circuit routing tool that connects a source with a net to a sink in a hierarchical multilayer integrated circuit design environment. The method includes creating a cycle reach table that includes a first set of information parameters for two-dimensional nets for each combination of metal layers; creating a repeater reach table that includes a second set of information parameters for each constraint class; starting from a first constraint class corresponding to a combination of the bottommost metal layers, creating a list of nets having the same constraint class, and preparing a working list of nets by extracting and checking blocked areas in the wiring area; marking all blocks whose length and width are greater than the repeater reach length, creating blockages on top of these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and preparing a list of blocks whose length is greater than the repeater reach length by creating blockages on higher metal layers up to the topmost metal layer; and connecting the source pin to the sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class.

[0010] Advantageously, the proposed method extends the calculation of the constraint class used by considering, in addition to a given timing model, the dimensions of all instantiated blocks existing under the mesh.

[0011] Routing constraints are calculated to route wires over the instantiated blocks without an intermediate amplifier or repeater. Starting from the bottommost metal layer and the narrowest wires, metal blockages are placed over all blocks having dimensions greater than the maximum repeater distance of the routing constraints. After routing, all nets greater than the Manhattan distance are assigned to the next constraint class, where the Manhattan distance between two points is the sum of the absolute values of the differences of each individual coordinate of the points.

[0012] In an embodiment of the invention, additionally or alternatively, the method comprises comparing the routed net length to the Steiner net length estimate for nets routed around the blockages; calculating the slack on the routed nets; removing nets having positive slack from the working list; removing nets having negative slack and net lengths similar to the Steiner net length; removing new wiring solutions for nets longer than the Steiner net length as the minimum length after moving those nets to the next constraint class depending on being part of a category of nets having positive slack; requesting alternative routing solutions for nets having net lengths longer than the Steiner net length based on the changed constraint class; expanding the wire width on the same metal layer based on the next constraint class from the repeater reach table to improve the slack for the nets, or changing to the next constraint class by switching the wiring metal layer to a higher metal layer, particularly repeating the steps for each constraint class in an N-1 routing session, where N is the number of given constraint classes; collecting the constraint classes from each of the N routing sessions; and further comprising running the N wiring sessions in a parallel approach. The Steiner length represents the shortest possible connection between two points.

[0013] The slack of a net is the time difference calculated from the required arrival time and the actual arrival time for a signal.

[0014] Advantageously, prior to wiring, all blocks instantiated in the floorplan are inspected to check whether their height or width is greater than the repeater reach of the constraint class. On blocks for which this is true, additional blocks are placed on top such that all upper metal layers are blocked. Next, all nets of this constraint class are routed as Steiner nets.

[0015] In embodiments of the present invention, additionally or alternatively, the nets in the working list can be further prioritized such that nets with high complexity are routed first and nets with low complexity are routed later. In particular, complexity is defined by the number of sink pins in the overall route of the net or by the use of a wider metal layer width. Advantageously, the efficiency of the proposed method can be enhanced when routing complex geometries.

[0016] In embodiments of the invention, additionally or alternatively, the first set of information parameters for two-dimensional wiring for each combination of metal layers can include the combination of metal layers, the metal layer width, and a specific delay time. The second set of information parameters for each constraint class can include the constraint class, the combination of metal layers, the metal layer width and space, and the repeater reach length. The specific delay time is defined as the delay time per unit length. Advantageously, information from the cycle reach table and the repeater reach table can be used to route nets over blocks.

[0017] In embodiments of the present invention, additionally or alternatively, to place repeaters, the required space between blocks is determined, and if the space exceeds a predetermined relative threshold, a portion of the net can be assigned to a higher constraint class. Advantageously, the next higher constraint class has a longer cycle reach and can thus be routed over wider or taller blocks.

[0018] In embodiments of the present invention, additionally or alternatively, routing for different constraint classes may be executed in parallel. This significantly enhances the speed of the routing process.

[0019] In embodiments of the present invention, additionally or alternatively, the determination of a specific delay time may be performed by any of a virtual timing model, an estimated timing model, and an extracted timing model. Since these timing models have different accuracies, it is useful to consider this when assigning net constraints.

[0020] In embodiments of the present invention, additionally or alternatively, the distance of the repeater bay from the edge of the block may be determined, and this distance may be compared with a specific delay time. Advantageously, how far the repeater bay is from the edge of the blocked area can be calculated. This can then be compared with the cycle reach value.

[0021] In embodiments of the present invention, additionally or alternatively, additional net lengths for connecting repeaters outside the blockage and nets with negative slack may be assigned to higher constraint classes. Advantageously, the next higher constraint class has a longer cycle reach and can thus be routed over a wider or higher block.

[0022] In embodiments of the present invention, additionally or alternatively, further, if the block is larger than the repeater reach length, the net may be assigned to a higher constraint class until sufficient repeater reach length and / or positive slack is found. Advantageously, the next higher constraint class has a longer cycle reach and can thus be routed over a wider or higher block.

[0023] In an embodiment of the present invention, additionally or alternatively, network routing is performed for the net of the actual constraint bucket, and if the bucket is not the first bucket, it can be performed for the nets of all the buckets present in the list.

[0024] The router is executed only on the current constraint bucket, and if it is no longer the first bucket, it is executed on the nets of all the preceding buckets in the list. This gives more accurate routing results.

[0025] A data processing system is proposed for a multilayer integrated circuit routing tool that connects a source comprising a net to a sink in a hierarchical multilayer integrated circuit design environment. The system includes a memory and a processing unit communicatively coupled to the memory. The data processing system creates a cycle reach table including a first set of information parameters for a two-dimensional net for each combination of metal layers; creates a repeater reach table including a second set of information parameters for each constraint class; starting from a first constraint class corresponding to a combination of the lowest metal layers, creates a list of nets having the same constraint class, and prepares a working list of nets by extracting and checking blocked areas in the wiring area; marks all blocks having a length and width greater than the repeater reach length, creates a blockage on these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and prepares a list of blocks having a length greater than the repeater reach length by creating a blockage on a higher metal layer up to the topmost metal layer; and executes a method including connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class.

[0026] The proposed data processing system can advantageously be used to execute the method for the multi-layer integrated circuit routing tool described above. The advantages of the proposed method can also be applied to different embodiments of the data processing system, but for reasons of expediency, the description will not be repeated.

[0027] In an embodiment of the present invention, additionally or alternatively, for a net routed around a blockage, the system compares the routed net length with a Steiner net length estimate; calculates the slack on the routed net; deletes nets having a positive slack from the working list; deletes nets having a negative slack and a net length similar to the Steiner net length; deletes a new wiring solution for a net longer than the Steiner net length as the minimum length, after moving those nets to the next constraint class depending on being part of a category of nets having a positive slack; requests an alternative routing solution for a net having a net length longer than the Steiner net length, based on the changed constraint class; to improve the slack for a net, expands the wiring width on the same metal layer based on the next constraint class from the repeater reach table, or changes to the next constraint class by switching the wiring metal layer to a higher metal layer, particularly repeating the steps for each constraint class in an N-1 routing session, where N is the number of given constraint classes; collects the constraint classes from each of the N routing sessions; and may further comprise executing the N wiring sessions in a parallel approach.

[0028] In an embodiment of the present invention, additionally or alternatively, further, the nets in the working list can be prioritized such that nets with higher complexity are routed first and nets with lower complexity are routed later, where complexity is defined in particular by the number of sink pins in the entire path of the net, or by the use of a wider wiring width. Also, when the number of sinks is higher than 1, the complexity increases.

[0029] In an embodiment of the invention, additionally or alternatively, the first set of information parameters for the two-dimensional wiring for each combination of metal layers may include the combination of metal layers, the metal layer width, and a specific delay time. The second set of information parameters for each constraint class may include the constraint class, the combination of metal layers, the metal layer width and space, and the repeater reach length.

[0030] In an embodiment of the present invention, additionally or alternatively, in order to place repeaters, the required space between blocks is determined, and if the space exceeds a predetermined relative threshold, a part of the net may be assigned to a higher constraint class.

[0031] In an embodiment of the invention, additionally or alternatively, routing for different constraint classes may be executed in parallel. For runtime reasons, the constraint classes are not processed sequentially but are executed simultaneously using a parallel approach. This parallel approach is also used for evaluation.

[0032] In an embodiment of the present invention, additionally or alternatively, the determination of the repeater reach timing may be performed by any one of a virtual timing model, an estimated timing model, and an extracted timing model.

[0033] In an embodiment of the present invention, additionally or alternatively, the distance of the repeater bay from the edge of the block may be determined, and this distance may be compared with a specific delay time.

[0034] In an embodiment of the present invention, additionally or alternatively, a net with an additional net length and negative slack for connecting a repeater outside the blockage may be assigned to a higher constraint class.

[0035] In an embodiment of the present invention, additionally or alternatively, further, if a block is larger than the repeater reach length, the net can be assigned to a higher constraint class until a sufficient repeater reach length and / or positive slack is found.

[0036] In an embodiment of the present invention, additionally or alternatively, the routing of the net is performed for the nets of the actual constraint buckets, and if the bucket is not the first bucket, it can be performed for the nets of all the buckets present in the list.

[0037] Furthermore, in a hierarchical multi-layer integrated circuit design environment, a computer program product for a multi-layer integrated circuit routing tool that connects a source including a net to a sink is proposed.

[0038] The computer program product includes a computer-readable storage medium in which program instructions are embodied, the program instructions being executable by a computer system, and causing the computer system to create a cycle reach table including a first set of information parameters for two-dimensional nets for each combination of metal layers; create a repeater reach table including a second set of information parameters for each constraint class; prepare a working list of nets by creating a list of nets having the same constraint class starting from a first constraint class corresponding to a combination of the lowest metal layers, and extracting and checking blocked areas in the wiring region; mark all blocks whose length and width are larger than the repeater reach length, create blockages on these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and create blockages on higher metal layers up to the topmost metal layer to prepare a list of blocks larger than the repeater reach length; and execute a method including connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class.

[0039] The proposed computer program product can advantageously be used to implement a method for a multilayer integrated circuit routing tool, as described above. The advantages of the proposed method can also apply to embodiments of the computer program product, but for the sake of brevity, the description will not be repeated.

[0040] A data processing system for the execution of a data processing program is proposed, which includes computer-readable program instructions for performing the method described above.

Brief Description of the Drawings

[0041] The present invention can be best understood from the following detailed description of the embodiments, together with the above-mentioned and other objects and advantages, but is not limited to the embodiments.

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DETAILED DESCRIPTION OF THE INVENTION

[0053] In the drawings, like elements are referenced with the same reference numerals. The drawings are only schematic representations and are not intended to depict specific parameters of the present invention. Further, the drawings are only intended to show exemplary embodiments of the present invention and should not be considered as limiting the scope of the present invention.

[0054] The exemplary embodiments described herein provide a method for a multilayer integrated circuit routing tool that connects a source comprising a net to a sink in a hierarchical multilayer integrated circuit design environment. The method includes creating a cycle reach table that includes a first set of information parameters for two-dimensional nets for each combination of metal layers, creating a repeater reach table that includes a second set of information parameters for each constraint class, starting from a first constraint class corresponding to a combination of the bottom-most metal layers, creating a list of nets having the same constraint class, preparing a working list of nets by extracting and checking blocked areas in a wiring area, marking all blocks having a length and width greater than a repeater reach length and creating blockages on top of these blocks on a metal layer assigned by a constraint class selected from the repeater reach table, preparing a list of blocks having a length greater than the repeater reach length by creating blockages on higher metal layers up to the top-most metal layer, and connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class.

[0055] Exemplary embodiments may further be used for a data processing system of a multilayer integrated circuit routing tool that connects a source with a net to a sink in a hierarchical multilayer integrated circuit design environment. The system includes a memory and a processing unit communicatively coupled to the memory. The data processing system creates a cycle reach table including a first set of information parameters for two-dimensional nets for each combination of metal layers, creates a repeater reach table including a second set of information parameters for each constraint class, starts from a first constraint class corresponding to a combination of the lowest metal layers, creates a list of nets having the same constraint class, prepares a working list of nets by extracting and checking blocked areas in a wiring area, marks all blocks having a length and width greater than a repeater reach length, creates a blockage on top of these blocks on a metal layer assigned by a constraint class selected from the repeater reach table, and creates a blockage on a higher metal layer up to the topmost metal layer to prepare a list of blocks having a length greater than the repeater reach length, and executes a method including connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class.

[0056] A semiconductor chip includes a transistor layer, an actual semiconductor, and various metal layers to which the transistors are connected and interconnected. The connections are made by different metal layers. The layer closer to the semiconductor and also the lower metal layers are thin due to small transistor connections and short bridge distances, have a small cross-sectional area, and high resistance and high RC delay

Number

[0057] Metal wires and metal layers are insulated from each other, for example, by silicon dioxide. During manufacturing, an insulating layer is applied, and then recesses for metal wires or vias are etched therein and later filled with metal.

[0058] FIG. 1 shows a wiring region 18 in an embodiment. The wiring region 18 includes a layout of nets, and each net includes different routings marked as 10a, 10b, and 10c. Each net 10a, 10b, and 10c consists of wirings mounted on a metal layer and vias connecting the metal layers. The layouts of nets 10a, 10b, 10c have different widths and cross block 14.

[0059] The names M1 to Mn of the metal layers refer to the vertical positions of these metal layers, and n is the index number of the metal layer. M1 is the lowest, followed by M2, etc. They may have different widths in the x or y direction or different heights in the vertical z direction as shown in FIG. 1; their cross-sectional areas may be larger than Mn in Mn+1. Guiding the M5 layer over block 14 means that it is routed within the boundaries of block 14. In the case of nets 10a and 10b, this means that they are routed over block 14.

[0060] The widths are marked as 2xW, 4xW, 6xW and are multiples of a single width 1xW. I Block marks the width of block 14. l Reach-3His the width required to place a repeater outside the area of block 14. This repeater reach length is defined in the repeater reach table 30 shown in FIG. 4. Since the metal layer is blocked in block 14, the routing of M1 to M4 including net 10c needs to be guided around block 14.

[0061] In the same metal layer M1 or M5, it is allowed to have different widths of the metal layer. In FIGS. 1 and 2, there are two metal layers M5 shown with different widths 4xW and 6xW.

[0062] The router routes nets 10a, 10b, 10c on the available metal layers M3, M4, M5, M6. Nets 10a, 10b, 10c are routed over block 14 without placing a repeater as shown for nets 10a and 10b. If block 14 is too wide, thin wires can also be routed over block 14. As shown in FIG. 1, net 10a has a width of metal layer M5 and 4xW. The repeater reach distance of this layer with a width of 4xW is less than the width l of block 14, while the repeater reach distance of layer M5 with net 10b having a width of 6xW is sufficient. Based on the timing requirements set for the routing of the nets and the requirement to maintain a non-overcrowded wiring space in this example of the prior art, this solution is sufficient as the timing is still assumed to be ideal. Block Physical characteristics defined in this way, for example as RC delay, result in requirements regarding the installation of repeaters 12 or inverters (shown in FIG. 2) and their mutual distances in order to overcome problems caused by the RC delay. Unfortunately, a greedy buffer as a repeater based on virtual timing in the prior art is assumed to be placeable anywhere within a blocked area for example. This does not correspond to reality. Specifically, a greedy buffer cannot actually be placed anywhere.

[0063] For example, physical characteristics defined in this way as RC delay result in requirements regarding the installation of repeaters 12 or inverters (shown in FIG. 2) and their mutual distances in order to overcome problems caused by the RC delay. Unfortunately, a greedy buffer as a repeater based on virtual timing in the prior art is assumed to be placeable anywhere within a blocked area for example. This does not correspond to reality. Specifically, a greedy buffer cannot actually be placed anywhere.

[0064] The hierarchical block 14 increases in complexity and thus size, and as a result, the problem is further exacerbated by the fact that it becomes difficult to route the wiring and meet all requirements.

[0065] FIG. 2 shows the wiring area 18 in an embodiment. FIG. 2 shows the layout of nets 10a, 10b, 10c of different widths 2xW, 4xW, 6xW including repeaters 12 across block 14 according to the prior art. Nets 10a, 10b, 10c are realized in different metal layers M3, M4, M5, M6.

[0066] FIG. 2 shows net 10a (4xW) with repeaters 12 installed before, after, and above block 14. This net 10a is longer than necessary, and this length is called the Manhattan distance, which can cause timing problems due to additional repeater delay and additional wiring.

[0067] Block 14 is blocked up to metal layer M4. It is impossible to place the repeaters 12, which are important for nets 10a, 10b, 10c, inside this block 14. For nets 10a and 10b with widths 4xW and 6xW on metal layers M5 and M6, the repeaters 12 are placed outside block 14, thus creating additional net length, so-called scenic nets. When metal layers are selected for nets 10 below or equal to the top block layer of block 14, these nets 10 need to be routed around the block with nets 10c on metal layers M3 and M4 with a width of 2xW as shown in FIGS. 1 and 2, or with nets 10c on metal layers M3 and M4 with a width of 2xW. When a thin net 10 is routed over block 14 and the repeater 12 required in the area of block 14 is routed over block 14, this repeater 12 needs to be placed outside block 14 and thus the net 10 needs to be extended.

[0068] When assigning a metal layer to net 10, it becomes easier if the block 14 over which net 10 is routed is considered.

[0069] The Steiner net length is the shortest possible net length obtained from the start and end points of net 10.

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[0070] Figure 3 shows the cycle reach table 20.

[0071] The 22 columns of the metal layer combinations show examples of different metal layers M1, M2, M3, M4, M5, M6, M7, and M8. Pairs of metal layers such as M1 / M2 are used for two-dimensional wiring in the orthogonal directions. The metal layers M1, M2, M3, M4, M5, M6, M7, M8 correspond to the references M1, M2, M3, M4, M5, M6, M7, M8 in Figures 1, 2 and 5, 6.

[0072] The metal layer combination 22 can be implemented with different widths 24 when compared with the "1xM1 / M2" row of the cycle reach table 20, for example from 1x, i.e., 1 times, to 12x, i.e., 12 times. The names of the metal layers in the cycle reach table 1xM1 / M2 mean multiplying the metal layer M1 or M2 by 1, where it is preferred to have the same width, although the width can vary. However, M2 is stacked on top of M1 in the z direction and can extend along different x or y directions (orthogonal to each other). The metal layers M1 and M2 also have the same height and thus the same cross-sectional area. Correspondingly, a specific delay time 28, Δt, is also shown as a fractional multiple of the first metal layer M1 or M2.

[0073] The cycle reach table 20 defines the reach 26 for combinations 22 of metal layers, which is the maximum distance that a net 10 on a combination 22 of metal layers having a defined width 24 can be routed before the signal is updated by a repeater. The reach 26 depends on the RC delay of the combination 22 of metal layers.

[0074] The cycle reach table 20 takes into account the RC delays of different combinations 22 of metal layers. FIG. 1 shows how different RC delays occur, where the lower metal layers (M1, M2) are thinner (1xH) and narrower (1xW) compared to the higher metal layers. As a result, they have a smaller cross-sectional area and thus higher resistance.

[0075] However, different widths 24 are possible on a single combination 22 of metal layers (M1: 1xW, 1.5xW, 2xW, 3xW). Due to these characteristics, when comparing different combinations 22 of metal layers, different specific delay times Δt delay 28 are brought about. These are listed in the cycle reach table 20. The specific delay time 28 indicates the delay time per unit length ps / μm associated with the combination 22 of metal layers.

[0076] FIG. 4 shows the repeater reach table 30.

[0077] The constraint class 32 combines a specific combination 22 of metal layers, width 24, and space 34. Here, the space 34 is the distance to an adjacent net 10. Different combinations of the combination 22 of metal layers, width 24, and space 34 result in different constraint classes 32. The method assigns one of the defined constraint classes 32 as a property to each net 10. This is later evaluated by the router, which then routes the net 10 on the corresponding combination 22 of metal layers having the defined width 24 and space 34 to other nets 10.

[0078] The delay time 28Δt can here be used to calculate the repeater spacing that needs to be maintained on the metal layer combination 22 in order not to fall below the steepness of a specific defined signal edge. This maximum repeater spacing then defines which metal layer combinations 22 and widths 24 and which size of block 14 can be routed over. The repeater spacing is important so that the signal edge at the receiver input does not fall below a defined value.

[0079] This repeater reach length 36 is enumerated in the repeater reach table 30 for each combination of constraint class 32, metal layer combination 22, width 24 and space 34. The repeater reach length 36 is different from the reach 26 enumerated in FIG. 3 in the cycle reach table 20. The repeater reach length 36 takes into account the smearing of the signal edge due to the width 24 of the net 10 and the space 34, which is the distance between adjacent nets 10. Thus, the repeater reach length 36 is the distance of the repeaters 12 necessary to maintain the defined steepness of the signal edge.

[0080] Blocks 14 instantiated in semiconductor designs often have dimensions corresponding to multiples of the repeater reach 26, which means that jumps to the next constraint class 32 are not sufficient to route over the corresponding block 14.

[0081] In addition, constraint classes 32 often actually overlap. Double-width wiring on metal layer Mn has a repeater reach 26 similar to single-width wiring on metal layer Mn+1, where n is the index number of the metal layer. These properties are then reflected in the repeater reach table 30. Since the total width / height is compared to the repeater reach 26, the method takes these properties into account. If the width / height of the instance is a multiple of the repeater reach 26, search until a repeater reach 26 over which it can be routed is found, or until the scenic net no longer results in a negative slack.

[0082] Advantageously, wiring constraints are assigned to these nets 10 before the router wires net 10 within the integrated circuit. The wiring constraints specify the combination of metal layers 22 used, the wiring width 24, and the wiring space 34. The available timing model for the chip and its sub-blocks makes it possible to determine the available RC delay for wiring each net 10 and then obtain the corresponding combination of metal layers 22 and width 24. To the nets 10 are assigned properties, constraint classes 32, encoded with the combination of metal layers 22, the width 24 used, and the distance maintained. This method extends the calculation of the constraint classes 32 used by taking into account, in addition to a given timing model, the dimensions of all the instantiated blocks 14 existing under the mesh. From the dimensions of the block 14, it is calculated whether the previously selected combination of metal layers 22 is higher than the highest blocked layer of the block 14 and whether, using this combination of metal layers 22 and wiring width 24, routing can be performed over all the blocks 14 without placing a repeater 12 within the block 14 (which is not allowed). This results in the fact that when the block size is not taken into account, the wiring of the net 10 needs to be routed in a different manner after the repeater 12 is inserted.

[0083] Determination of the repeater reach timing can be performed by one of a virtual timing model, an estimated timing model, and an extracted timing model.

[0084] FIG. 5 shows a wiring area 18 for selecting a layout of a net 10 with a blockage 64 on a block 14 according to an embodiment of the present invention. In block 14a, routing is blocked for metal layers M1, M2, M3, and M4. In block 14b, additionally, all metal layers above M4 are also blocked.

[0085] The proposed method takes advantage of the fact that instead of routing over the blockage 64, the router routes around the blockage 64. As a result, the routed net 10 becomes longer than the minimum Steiner length. Here, the Steiner length represents the shortest possible connection between two points.

[0086] Before routing, all the blocks 14 instantiated in the floorplan are inspected to confirm whether their height or width 24 is greater than the repeater reach 36 of the constraint class 32.

[0087] On the blocks 14 for which this holds true, such as block 14b, additional blocks are placed on top so that all combinations 22 of metal layers are blocked. Next, all the nets 10 of this constraint class 32 are routed as Steiner nets. The router is configured to use only the combinations 22 of metal layers defined in the constraint class 32. The blocked blocks 14 need to have the nets 10 routed around the outside of the block 14 by the router, and as a result, their lengths no longer match the Steiner minimum length. The unblocked blocks 14 are routed across by the router.

[0088] Next, the method excludes the routed nets 10 that are longer than the Steiner length or have a negative slack.

[0089] The slack of the net 10 is the time difference calculated from the required arrival time and the actual arrival time.

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[0090] For non-routed nets 10, the timing model uses the Steiner routing length and the cycle reach table 20 for the RC delay of the routing:

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[0091] In the routed net 10, the slack is the RC delay Δt of the actual wiring used RCdelay is calculated using:

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[0092] These excluded nets 10 are then assigned to the next higher constraint class 32. The method then deletes all the previously routed wiring and blockages 64 for those selected nets 10 and starts the analysis using the next constraint class 32.

[0093] In FIG. 5, two blocks 14a and 14b are shown. In the routing of net 10, there is a blockage 64 on the metal layer M4. The block 14 having the blockage 64 is referred to as the blocked region 16. Thus, net 10 is routed on the metal layers M5 and M6 around the block 14b where the reach 26, l Reach-4W is smaller than the width l of block 14 Block . Net 10 is routed over the other block 14a where the reach 26, l Reach-4W is larger than the width l of block 14 Block . At the top of block 14a, a deviated blockage 64 is created by the metal area at the levels of the metal layers M5 and M6.

[0094] The required space for 16 blocked areas can be determined for placing the repeater 12, and if the space exceeds a predetermined relative threshold, a part of the net 10 can be assigned to a higher constraint class 32. The repeater bay is a part of the blocked area 16 where the repeater can be placed from the outside. The distance of the repeater bay from the edge of the blocked area 16 can be determined, and this distance is then compared with the repeater reach timing.

[0095] Advantageously, the additional net length for connecting the repeater 12 outside the blockage 64, and the net 10 with negative timing delay, can be assigned to a higher constraint class 32.

[0096] Preferably, if the block 14 is larger than the repeater reach length 36, the net 10 can be assigned to a higher constraint class 32 until a sufficient repeater reach length 36 and / or positive timing delay is found.

[0097] The next higher constraint class 32 has a longer cycle reach 26, and as a result, can be routed over a wider or higher block 14. Similarly, it is analyzed which block 14 is wider and / or higher than the longer cycle reach 26 of the higher constraint class 32. The router can wire the Steiner length net since there is no blockage 64, but the method does not exclude it anymore as it is too long, and thus, this net 10 remains in the new constraint class 32. This ensures that when the repeaters 12 are inserted later, their maximum distance is not exceeded by the block 14.

[0098] FIG. 6 shows the layout of the net 10 on a higher constraint class 32 than that shown in FIG. 5 according to an embodiment, where the block 14 is not blocked.

[0099] The two blocks 14a and 14b are blocked up to the metal layer M4, but there is no blockage on the next two higher metal layers M5 and M6, so the net 10 can be routed across the two blocks 14a and 14b at the level of the metal layer M5.

[0100] Advantageously, the routing for different constraint classes 32 can be performed in parallel. For runtime reasons, the constraint classes 32 are not processed sequentially but are executed simultaneously using a parallel approach. This parallel approach is also used for evaluation.

[0101] Routers used in the industry check the routability of a unit by congestion analysis. The unit area is divided into small areas, g-cells. These are only partially filled with wiring in the case of lower and intermediate metal layers and are completely filled with wiring in the case of the topmost metal layer.

[0102] Regarding overcrowding of the layout, advantageously, it is investigated whether the space between the blocks 14 is sufficient to accommodate all the repeaters 12. The size of the space between the blocks 14 is calculated. This is compared with the required area of all the repeaters 12 required for the net 10 routed across this gap. Since the reach is known, the possible locations of the repeaters 12 can be calculated. Next, for each net 10 routed over the interstitial space, the area of the required repeaters 12 is summed. A suitable threshold is used to determine how much the interstitial space can be filled. If the required repeater area is greater than the maximum filling, a part of the net 10 needs to be assigned to a higher constraint class 32 in order to reduce the repeater area.

[0103] In a hierarchical design, blocks 14 such as a core, unit, memory, RAM, register, adder, RLM, etc. are used. These blocks 14 block up to a specific metal layer, for example M4. Units / cores using such blocks 14 need to define their wiring / nets 10 so that they can be routed by the wiring / nets 10 over these blocks 14 that do not allow the placement of repeaters 12 inside. Note that on blocks 14 of a specific size up to and including M4, they are not routed by nets / wirings 10 having a combination 22 of metal layers with a width of 1x or 1.5x M5 / M6, but are routed thereon, for example, by a wiring / net having a combination 22 of metal layers with a width of 2x M5 / M6. Therefore, in the method, before relying on the combination 22 of M7 / M8 metal layers, an attempt is made to find a routable width on the M5 / M6 metal layer over the said block. The same design may also include blocks 14 that block up to and including M3, for example M3, and thus may make more resources available to the unit.

[0104] FIG. 7 shows a flowchart of a method for a multilayer integrated circuit routing tool that connects a source with a net 10 to a sink for a single constraint class 32 in a hierarchical multilayer integrated circuit design environment according to an embodiment of the invention.

[0105] The algorithm uses a sorted list of constraint classes 32 that occur in the design. Each net 10 may have default constraints or predefined constraints generated, for example, according to timing aspects. This list of nets 10 with constraints is provided as input in step S102 before starting the process.

[0106] As shown in FIG. 3, a cycle reach table 20 is created that includes a first set of information parameters for the two-dimensional net 10 for each combination 22 of metal layers. This first set of information parameters includes at least the combination 22 of metal layers, the metal layer width 24, and the repeater reach timing 26 for each length.

[0107] Next, as shown in FIG. 4, based on the information in the cycle reach table 20, a repeater reach table 30 including a second set of information parameters for each constraint class 32 is created. The second set of information parameters includes at least the constraint class 32, the combination of metal layers 22, the metal layer width 24, and the repeater space 34 and the repeater reach length 36. This constraint class 32 in the repeater reach table 30 is provided as an input in step S104 of the flowchart in FIG. 7.

[0108] In step S106, a working list of nets is prepared by creating a list of nets 10 with the same constraint class 32.

[0109] In step S108, the process starts routing using the first constraint class 32 corresponding to the combination of the lowest metal layers 22.

[0110] The blocked area 16 in the wiring area 18 is extracted and checked.

[0111] Thereafter, in step S110, a list of blocks 14 larger than the repeater reach length is prepared by marking all blocks 14 having a length and width wider than the repeater reach length 36.

[0112] In step S112, a blockage 64 is created on the metal layers M1, M2, M3, M4, M5, M6, M7, M8 given by the selected constraint class 32 from the repeater reach table 30, and the blockage 64 is created on all the higher metal layers M1, M2, M3, M4, M5, M6, M7, M8 up to the top metal layer M8.

[0113] Next, in step S114, by routing the net 10 based on the given constraint class 32, the process continues by connecting the source pins to the sink pins on the pre-assigned metal layer defined by the constraint class.

[0114] FIG. 8 shows a flowchart of a method according to a further embodiment of the present invention.

[0115] As described with respect to FIG. 7, following steps S102 - S114, steps S202 - S214 are processed according to the flowchart for a single constraint class 32.

[0116] The process continues to step S216, where for all nets 10 routed around the blockage 64, a comparison is made between the routed net length and the Steiner net length estimate, which means that all the sink nets 10 of the current constraint class are searched.

[0117] Next, in step S218, the next constraint class 32 from the repeater reach table 30 is associated with the found sink net 10.

[0118] Next, all the wirings and all the blockages 64 of the found sink net 10 are deleted in step S220, and subsequently, in step S222, the next constraint class 32 is selected.

[0119] In step S224, it is checked whether this is the last constraint class 32. If this is the case, the process ends. If this is not the case, the process continues the loop at step S210 by marking the block 14.

[0120] According to a further embodiment, for all nets 10 routed around the blockage 64, the routed net length can be compared to the Steiner net length estimate. Next, the slack on the routed net 10 can be calculated.

[0121] Nets 10 with positive slack can be removed from the working list. Nets 10 with negative slack and a net length similar to the Steiner net length can also be removed.

[0122] Next, new wiring solutions for nets 10 longer than the Steiner net length as the minimum length can be removed after moving them to the next constraint class 32 according to whether they are part of the category of nets 10 with positive timing results.

[0123] For nets with a net length longer than the Steiner net length, in order to improve the timing delay for that net 10, either extend the wiring width on the same metal layers M1, M2, M3, M4, M5, M6, M7, M8 based on the next constraint class 32 from the repeater reach table 30, or change to the next wiring constraint class 32 by switching the wiring metal layers M1, M2, M3, M4, M5, M6, M7, M8 to the upper metal layers M1, M2, M3, M4, M5, M6, M7, M8. Based on the changed wiring constraints, an alternative routing solution can be requested.

[0124] Steps S210 - S222 can be repeated for each wiring constraint class 32, particularly in an N - 1 parallel routing session, where N is the number of given wiring constraint classes 32.

[0125] Subsequently, the wiring constraint classes from each of the N parallel routing sessions can be collected.

[0126] The net 10 of the working list can be prioritized such that nets 10 with higher complexity are routed first and nets with lower complexity are routed later. In particular, complexity can be defined by the number of sinks in the overall path of the net 10, or by the number of direction changes of the net 10, or by using a wider wiring width or space 34.

[0127] FIG. 9 shows a flowchart of a method for removing a net 10 having an additional net length according to a further embodiment of the invention.

[0128] The flowchart in FIG. 9 relates to sorting nets 10 with a positive slack having non-critical timing.

[0129] The net 10 is simple if it has a positive slack. In this method, it is then guaranteed that the scenic net 10 is accurately calculated by the "wiring detour" in its excess length. Next, if the slack is positive, this net 10 can be realized in this way. Since there is sufficient margin in timing, these nets 10 are then not assigned to the higher-level constraint class 32.

[0130] DC (direct current) nets, nets with scan signals can belong to these nets 10, for example.

[0131] In the flowchart of FIG. 9, the first steps S302 to S312 are equivalent to the steps S202 to S212 in FIG. 8. Next, in step S314, all nets 10 of the current constraint class 32 are selected and routed in step S316.

[0132] Next, in step S318, the scenic net 10 is excluded from the routed nets 10. In step S320, the scenic nets 10 with a positive slack are removed from the list of scenic nets 10.

[0133] Next, in step S322, the next constraint class 32 is associated with net 10 of the net list of scenic nets that are scenic nets with negative slack.

[0134] As in the previous flowchart shown in FIG. 8, next in step S324, all the wirings and all the blockages 64 of all the found nets 10 are deleted, and in step S326, the next constraint class 32 is selected.

[0135] In step S328, it is checked whether this is the last constraint class 32. If this is the case, the process ends. If this is not the case, the process continues and loops in step S310 by marking block 14.

[0136] FIG. 10 shows a flowchart of a method for considering the timing of net 10 according to a further embodiment of the present invention.

[0137] The flowchart in FIG. 10 is related to considering the net timing during routing for the timing-critical net 10.

[0138] Before wiring starts, all nets 10 having positive slack are screened out. Thus, only the timing-critical nets 10 are considered. The timing-critical nets 10 are distinguished from the non-timing-critical nets 10 by a threshold value. This can be set to 0 μs, but in that case, the method bears the risk that a net with a slightly positive value becomes negative due to the low scenic nets 10. Therefore, this threshold value is set to a slightly positive value, for example, 10 μs.

[0139] The routing of net 10 is performed for the nets 10 of the actual constraint bucket, and if the bucket is not the first bucket, it can be performed for the nets 10 of all the buckets present in the list.

[0140] The flowchart in FIG. 10 starts at the same step as the flowcharts in FIGS. 7 to 9 by creating a net list having the same constraint class 32 nets in step S406.

[0141] Next, in step S408, nets 10 having a slack greater than the threshold value are deleted from the net list.

[0142] Next, the process flow in steps S410 to S428 follows the process flow of steps S308 to S328 shown in FIG. 9.

[0143] In step S410, the process starts routing with the first constraint class 32. In step S412, all blocks 14 having a dimension greater than the repeater reach length of the constraint class 32 are marked, and in step S414, all metal layers M1, M2, M3, M4, M5, M6, M7, M8 above the marked blocks 14 are blocked.

[0144] Next, in step S416, net 10 is routed.

[0145] Next, in step S418, all the scenic nets 10 of the current constraint class 32 are searched.

[0146] Next, in step S422, the next constraint class 32 is associated with the nets 10 in the scenic net list.

[0147] Similar to the previous flowchart shown in FIG. 9, in step S424, next, all the wirings of all nets 10 and all blockages 64 are deleted, and in step S426, the next constraint class 32 is selected.

[0148] In step S428, it is checked whether this is the last constraint class 32. If this is the case, the process ends. If not, the process continues the loop at step S412 by marking block 14.

[0149] FIG. 11 shows a data processing system 210 for a multilayer integrated circuit routing tool that connects the source of net 10 to a sink in a hierarchical multilayer integrated circuit design environment according to a further embodiment of the present invention. The data processing system 210 can include at least a memory 228 and a processing unit 216 communicatively coupled to the memory 228. The data processing system 210 can execute the methods described above. To avoid unnecessary repetition, reference is made to the description of the methods described with FIGS. 1-10.

[0150] The data processing system 210 is merely an example of a suitable data processing system and is not intended to suggest any limitation as to the scope of use or functionality of the embodiments of the invention described herein. In any event, the data processing system 210 can implement and / or execute or both any and all of the functionality described above herein.

[0151] In the data processing system 210, there is a computer system / server 212 that operates with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use in the computer system / server 212 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices.

[0152] The computer system / server 212 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system / server 212 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules can be located in both local computer system storage media, including memory storage devices, and remote computer system storage media.

[0153] As shown in FIG. 11, the computer system / server 212 in the data processing system 210 is shown in the form of a general-purpose computing device. The components of the computer system / server 212 can include, but are not limited to, one or more processors or processing units 216, a system memory 228, and a bus 218 that couples various system components including the system memory 228 to the processing unit 216.

[0154] The bus 218 represents one or more of any of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus that uses any of a variety of bus architectures. By way of example and not limitation, such architectures can include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0155] The computer system / server 212 typically includes a variety of computer system-readable media. Such media can be any available media accessible by the computer system / server 212, including both volatile and non-volatile media, removable and non-removable media.

[0156] System memory 228 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 230 and / or cache memory 232. The computer system / server 212 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 234 for reading from and writing to a non-removable non-volatile magnetic medium (not shown, typically referred to as a "hard drive") can be provided. Although not shown, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 218 by one or more data media interfaces. As further depicted and described below, memory 228 may include at least one program product having a set of (e.g., at least one) program modules configured to execute the functions of embodiments of the present invention.

[0157] The program / utility 240 having a set (at least one) of program modules 242 may be stored in the memory 228, by way of example and not limitation, as may an operating system, one or more application programs, other program modules, and program data. Similarly, the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The program modules 242 generally execute the functions and / or methods of embodiments of the invention described herein.

[0158] The computer system / server 212 may communicate with one or more external devices 214, such as a keyboard, a pointing device, a display 224, etc.; one or more devices that enable a user to interact with the computer system / server 212; and / or any device that enables the computer system / server 212 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 222. Additionally, the computer system / server 212 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 220. As illustrated, the network adapter 220 communicates with other components of the computer system / server 212 via a bus 218. Although not shown, it should be understood that other hardware components and / or software components may be used in conjunction with the computer system / server 212. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

[0159] The present invention can be a system, method, and / or computer program product integrated at any possible technical detail level. The computer program product can include a computer-readable storage medium (or media) having computer-readable program instructions that cause a processor to execute aspects of the present invention.

[0160] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of these. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0161] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium in each respective computing / processing device.

[0162] The computer-readable program instructions for carrying out the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or any combination of source code or object code written in any one or more programming languages including object-oriented programming languages such as Smalltalk®, C++, or the like, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer as a stand-alone software package, may be executed partially on the user's computer, may execute a portion on the user's computer and a portion on a remote computer, or may be executed entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may utilize the state information of the computer-readable program instructions to execute the computer-readable program instructions to personalize the electronic circuit in order to carry out aspects of the present invention.

[0163] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0164] These computer-readable program instructions can be provided to a computer or to a processor of other programmable data processing apparatus to produce a machine, such that the instructions executed via the computer or the processor of the other programmable data processing apparatus create means for implementing the functions / operations specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored therein has a manufacture including instructions for implementing the aspects of the functions / operations specified in one or more blocks of the flowchart and / or block diagram.

[0165] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / operations specified in one or more blocks of the flowchart and / or block diagram.

[0166] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may be performed in an order different from that noted in the drawings. For example, two blocks shown in succession may in fact be implemented as one step, may be executed at the same time, may be executed in a partially or wholly overlapping manner in time, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or by a combination of dedicated hardware and computer instructions.

[0167] The description of the various embodiments of the present invention is presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or improvements made to the technology found in the marketplace, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

[0168] Further exemplary embodiments of the present disclosure are described in the numbered items below:

[0169] Item No. 1: A computer-implemented method for a multilayer integrated circuit routing tool that connects a source comprising a net (10) to a sink in a hierarchical multilayer integrated circuit design environment, the method comprising at least: · Creating a cycle reach table (20) that includes a first set of information parameters for the two-dimensional net (10) for each combination of metal layers (22); · Creating a repeater reach table (30) that includes a second set of information parameters for each constraint class (32); · Starting from the first constraint class (32) corresponding to the combination of the lowest metal layers (22), creating a list of nets (10) with the same constraint class (32), and preparing a working list of nets (10) by extracting and checking the blocked areas (16) in the wiring area (18); · Marking all blocks (14) whose length and width are greater than the repeater reach length (36), creating blockages (64) on these blocks (14) on the metal layers (M1, M2, M3, M4, M5, M6, M7, M8) assigned by the selected constraint class (32) from the repeater reach table (30), and preparing a list of blocks (14) with lengths greater than the repeater reach length by creating blockages (64) on all higher metal layers (M1, M2, M3, M4, M5, M6, M7, M8) up to the top metal layer (M8); · Connecting the source pin to the sink pin on the pre-assigned metal layers (M1, M2, M3, M4, M5, M6, M7, M8) by routing the net (10) based on the selected constraint class (32). including.

[0170] Numbered item 2: · Comparing the routed net length with the Steiner net length estimation for all nets (10) routed around the blockage (64); · Calculating the slack on the routed net (10); · Deleting the nets (10) with positive slack from the working list; · Deleting the nets (10) with negative slack and net lengths similar to the Steiner net length; ·Depending on a part of the category of nets (10) having a positive slack, after moving those nets to the following constraint class (32), deleting a new wiring solution for nets (10) that are longer than the Steiner net length as the minimum length; ·To improve the slack for nets (10), based on the following constraint class (32) from the repeater reach table (30), either expanding the wiring width on the same metal layer (M1, M2, M3, M4, M5, M6, M7, M8), or changing to the following constraint class (32) by switching the wiring metal layer (M1, M2, M3, M4, M5, M6, M7, M8) to a higher metal layer (M1, M2, M3, M4, M5, M6, M7, M8), for nets with a net length longer than the Steiner net length, requesting an alternative routing solution based on the changed constraint class (32); ·Particularly in the N - 1 routing sessions, for each constraint class (32), repeating the above steps, where N is the number of given constraint classes (32); ·Collecting constraint classes from each of the N routing sessions; ·Executing the routing sessions in a parallel approach The method according to item 1, further comprising.

[0171] Numbered item 3: Further comprising prioritizing the nets (10) in the working list such that nets (10) with high complexity are routed first and nets with low complexity are routed later, where complexity is defined by the number of sink pins in the overall path of the net (10) or by the use of a wider metal layer width (24), the method according to item 1 or 2.

[0172] Numbered item 4: The first set of information parameters for two - dimensional wiring for each combination of metal layers (22) is at least: ·The combination of metal layers (22), ·The metal layer width (24), ·A specific delay time (28) including The second set of information parameters for each constraint class (32) includes at least: · The constraint class (32), · The combination of metal layers (22), · The metal layer width (24) and space (34), · The repeater reach length (36) including The method according to any one of items 1 to 3.

[0173] Numbered item 5: The method according to any one of items 1 to 4, wherein, to place the repeater (12), the required space between the blocks (14) is determined, and if the space exceeds a predetermined relative threshold, a part of the net (10) is assigned to a higher constraint class (32).

[0174] Numbered item 6: The method according to any one of items 1 to 5, wherein routing for different constraint classes (32) is performed in parallel.

[0175] Numbered item 7: The method according to any one of items 1 to 6, wherein determining a specific delay time (28) is performed by at least one of at least a virtual timing model, an estimated timing model, and an extracted timing model.

[0176] Numbered item 8: The method according to any one of items 1 to 7, further including determining the distance of the repeater bay from the edge of the block (14) and comparing this distance with a specific delay time (28).

[0177] Numbered item 9: The method according to any one of items 2 to 8, including an additional net length for connecting the repeater (12) outside the blockage (64), and a net (10) with negative slack is assigned to a higher constraint class (32).

[0178] Numbered Item 10: The method according to any one of Items 1 to 9, further comprising that when the block (14) is larger than the repeater reach length (36), the net (10) is assigned to a higher constraint class (32) until a sufficient repeater reach length (36) and / or a positive slack is found.

[0179] Numbered Item 11: The method according to any one of Items 1 to 10, wherein the routing of the net (10) is performed for the net (10) of the actual constraint bucket, and if the bucket is not the first bucket, it is performed for the net (10) of all buckets existing in the list.

[0180] Numbered Item 12: A data processing system (210) for a multilayer integrated circuit routing tool that connects a source with a net (10) to a sink in a hierarchical multilayer integrated circuit design environment, wherein the system (210) comprises at least: a memory (228); and a processing unit (216) communicatively coupled to the memory (228) and the data processing system (210) comprises at least: · creating a cycle reach table (20) containing a first set of information parameters for the two-dimensional net (10) for each combination of metal layers (22); · creating a repeater reach table (30) containing a second set of information parameters for each constraint class (32); · starting from the first constraint class (32) corresponding to the combination of the lowest metal layers (22), creating a list of nets (10) with the same constraint class (32), and preparing a working list of the nets (10) by extracting and checking the blocked areas (16) in the wiring area (18); · Mark all blocks (14) whose length and width are greater than the repeater reach length (36); create a blockage (64) on these blocks (14) on the metal layers (M1, M2, M3, M4, M5, M6, M7, M8) assigned by the constraint class (32) selected from the repeater reach table (30); prepare a list of blocks (14) greater than the repeater reach length by creating blockages (64) on all higher metal layers (M1, M2, M3, M4, M5, M6, M7, M8) up to the top metal layer (M8); · Connect the source pin to the sink pin on the pre - assigned metal layers (M1, M2, M3, M4, M5, M6, M7, M8) by routing the net (10) based on the selected constraint class (32). A system that executes a method including the above.

[0181] Numbered item 13: · For all nets (10) routed around the blockage (64), compare the routed net length with the Steiner net length estimate; · Calculate the slack on the routed net (10); · Remove the nets (10) with positive slack from the working list; · Remove the nets (10) with negative slack and net lengths similar to the Steiner net length; · Depending on being part of the category of nets (10) with positive slack, move those nets to the next constraint class (32) and then delete the new wiring solutions for the nets (10) longer than the Steiner net length as the minimum length; · To improve the slack for a net (10), based on the following constraint class (32) from the repeater reach table (30), either expand the wiring width on the same metal layer (M1, M2, M3, M4, M5, M6, M7, M8), or change to the following constraint class (32) by switching the wiring metal layer (M1, M2, M3, M4, M5, M6, M7, M8) to a higher metal layer (M1, M2, M3, M4, M5, M6, M7, M8), and for a net whose net length is longer than the Steiner net length, request an alternative routing solution based on the changed constraint class (32); · Particularly in the N-1 routing session, for each constraint class (32), repeat the above steps, where N is the number of given constraint classes (32); · Collect constraint classes from each of the N routing sessions; · Execute the routing sessions in a parallel approach The system according to item 12, further comprising

[0182] Numbered item 14: Further include prioritizing the nets (10) in the working list such that nets (10) with high complexity are routed first and nets with low complexity are routed later, where complexity is defined by the number of sink pins in the overall route of the net (10), or by the use of a wider wiring width or space (34), the system according to item 12 or 13.

[0183] Numbered item 15: The first set of information parameters for two-dimensional wiring for each combination of metal layers (22) includes at least: · The combination of metal layers (22), · The metal layer width (24), · A specific delay time (28) including The second set of information parameters for each constraint class (32) includes at least: · The constraint class (32), · The combination of metal layers (22), · Metal layer width (24) and space (34), · Repeater reach length (36) including the system according to any one of items 12 to 14.

[0184] Numbered item 16: To place the repeater (12), the necessary space between the blocks (14) is determined. If the space exceeds a predetermined relative threshold, a part of the net (10) is assigned to a higher constraint class (32), the system according to any one of items 12 to 15.

[0185] Numbered item 17: For different constraint classes (32), routing is executed in parallel, the system according to any one of items 12 to 16.

[0186] Numbered item 18: The determination of the repeater reach timing is executed by at least one of at least a virtual timing model, an estimated timing model, and an extraction timing model, the system according to any one of items 12 to 17.

[0187] Numbered item 19: Further, determine the distance of the repeater bay from the edge of the block (14) and compare this distance with the repeater reach timing, the system according to any one of items 12 to 18.

[0188] Numbered item 20: The additional net length for connecting the repeater (12) outside the blockage (64), and a net (10) having a negative slack is assigned to a higher constraint class (32), the system according to any one of items 13 to 19.

[0189] Numbered item 21: Further, if the block (14) is larger than the repeater reach length (36), the net (10) is assigned to a higher constraint class (32) until a sufficient repeater reach length (36) and / or a positive slack is found, the system according to any one of items 12 to 20.

[0190] Numbered Item 22: A system according to any one of Items 12 to 21, wherein the routing of the net (10) is performed for the net (10) of the actual constraint bucket, and if the bucket is not the first bucket, it is performed for the net (10) of all the buckets existing in the list.

[0191] Numbered Item 23: A computer program product for a multilayer integrated circuit routing tool that connects a source including a net (10) to a sink in a hierarchical multilayer integrated circuit design environment, including a computer-readable storage medium in which program instructions are embodied, the program instructions being executable by a computer system (212), and the computer system (212) is caused to: · Create a cycle reach table (20) including a first set of information parameters for a two-dimensional net (10) for each combination of metal layers (22); · Create a repeater reach table (30) including a second set of information parameters for each constraint class (32); · Start from a first constraint class (32) corresponding to the combination of the lowest metal layers (22); create a list of nets (10) with the same constraint class (32); and prepare a working list of nets (10) by extracting and checking blocked areas (16) in the wiring area (18); · Mark all blocks (14) whose length and width are greater than the repeater reach length (36); create a blockage (64) on these blocks (14) on the metal layers (M1, M2, M3, M4, M5, M6, M7, M8) assigned by the constraint class (32) selected from the repeater reach table (30); and prepare a list of blocks (14) whose length is greater than the repeater reach length by creating a blockage (64) on all higher metal layers (M1, M2, M3, M4, M5, M6, M7, M8) up to the top metal layer (M8); Connecting source pins to sink pins on pre-assigned metal layers (M1, M2, M3, M4, M5, M6, M7, M8) by routing a net (10) based on a selected constraint class (32). A computer program product for causing a method including the above to be executed.

[0192] Item 24 numbered: A data processing system (210) for the execution of a data processing program (240) including computer-readable program instructions for performing the method according to any one of Items 1 to 11.

Claims

1. A computer-implemented method for a multilayer integrated circuit routing tool that connects a source having a net to a sink in a hierarchical multilayer integrated circuit design environment, comprising: creating a cycle reach table that includes a first set of information parameters for two-dimensional nets for each combination of metal layers; creating a repeater reach table that includes a second set of information parameters for each constraint class; starting from a first constraint class corresponding to a combination of the lowest metal layers, creating a list of nets having the same constraint class, and preparing a working list of nets by extracting and checking blocked areas in the wiring area; marking all blocks having a length and width greater than the repeater reach length, creating a blockage on top of these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and creating a blockage on a higher metal layer up to the top metal layer, thereby preparing a list of blocks having a length greater than the repeater reach length, where the metal layers include M1, M2, M3, M4, M5, M6, M7, M8, and where M8 is the top metal layer; and connecting a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class A method comprising the steps of:

2. comparing the net length with the Steiner net length estimate for a net routed around a blockage; calculating the slack on the routed net; deleting nets having a positive slack from the working list; deleting nets having a negative slack and a net length similar to the Steiner net length; deleting a new wiring solution for a net having a length longer than the Steiner net length as the minimum length after moving those nets to the next constraint class depending on being part of a category of nets having a positive slack; To improve the slack for a net, based on the next constraint class from the repeater reach table, either expand the wiring width on the same metal layer or change to the next constraint class by switching the wiring metal layer to a higher metal layer, and for a net whose net length is longer than the Steiner net length, request an alternative routing solution based on the changed constraint class; In particular, in the N-1 routing session, repeat the steps for each constraint class, where N is the number of given constraint classes; Collect the constraint classes from each of the N routing sessions; and Execute the N routing sessions in a parallel approach The method according to claim 1, further comprising.

3. Further comprising prioritizing the nets in the working list such that nets with high complexity are routed first and nets with low complexity are routed later, where complexity is defined by the number of sink pins in the overall path of the net or by the use of a wider metal layer width. The method according to claim 1 or 2.

4. The first set of information parameters for two-dimensional wiring for each combination of metal layers includes the combination of metal layers, the metal layer width, and a specific delay time. The second set of information parameters for each constraint class includes the constraint class, the combination of metal layers, the metal layer width and space, and the repeater reach length. The method according to any one of claims 1 to 3.

5. The method according to any one of claims 1 to 4, wherein to place a repeater, the required space between blocks is determined, and if the space exceeds a predetermined relative threshold, a part of the net is assigned to a higher constraint class.

6. The method according to any one of claims 1 to 5, wherein the routing for different constraint classes is executed in parallel.

7. The method according to any one of claims 1 to 6, wherein the determination of the specific delay time is executed by at least one of a virtual timing model, an estimated timing model, and an extracted timing model.

8. The method according to any one of claims 1 to 7, further comprising determining the distance of the repeater bay from the edge of the block and comparing this distance with a specific delay time.

9. The method according to any one of claims 2 to 8, wherein an additional net length for connecting a repeater to the outside of the blockage and a net with a negative slack are assigned to a higher constraint class.

10. The method according to any one of claims 1 to 9, further comprising that when the block is larger than the repeater reach length, the net is assigned to a higher constraint class until a sufficient repeater reach length and / or a positive slack is found.

11. The method according to any one of claims 1 to 10, wherein the routing of the net is performed for the nets of the actual constraint buckets, and when the bucket is not the first bucket, it is performed for the nets of all the buckets present in the working list.

12. A computer system for a multilayer integrated circuit routing tool that connects a source with a net to a sink in a hierarchical multilayer integrated circuit design environment, one or more computer processors, one or more computer-readable storage media, and program instructions stored in the one or more of the computer-readable storage media for execution by at least one of the one or more processors wherein the computer system: creating a cycle reach table including a first set of information parameters for two-dimensional nets for each combination of metal layers; creating a repeater reach table including a second set of information parameters for each constraint class; starting from a first constraint class corresponding to a combination of the lowest metal layers, creating a list of nets having the same constraint class, and preparing a working list of nets by extracting and checking blocked areas in the wiring region; marking all blocks having a length and width larger than the repeater reach length, creating blockages on these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and creating blockages on higher metal layers up to the topmost metal layer, thereby preparing a list of blocks larger than the repeater reach length, where the metal layers include M1, M2, M3, M4, M5, M6, M7, M8, and where M8 is the topmost metal layer; and Connecting source pins to sink pins on a pre - assigned metal layer by routing a net based on the selected constraint class A computer system capable of executing a method including this. **Claim 13** The method includes For a net routed around a blockage, comparing the net length with a Steiner net length estimate; Calculating the slack on the routed net; Deleting nets with positive slack from the working list; Deleting nets with negative slack and net lengths similar to the Steiner net length; Depending on being part of a category of nets with positive slack, moving those nets to the next constraint class and then deleting new wiring solutions for nets longer than the Steiner net length as the minimum length; To improve the slack for a net, based on the next constraint class from the repeater reach table, either expanding the wiring width on the same metal layer or changing to the next constraint class by switching the wiring metal layer to a higher - level metal layer, and for a net whose net length is longer than the Steiner net length, requesting an alternative routing solution based on the changed constraint class; Repeating the steps for each constraint class, particularly in the N - 1 routing sessions, where N is the number of given constraint classes; Collecting constraint classes from each of the N routing sessions; and Executing the N routing sessions in a parallel approach The computer system according to claim 12, further comprising this. **Claim 14** The method further includes prioritizing the nets in the working list such that nets with higher complexity are routed first and nets with lower complexity are routed later, where complexity is defined by the number of sink pins in the overall path of the net or by the use of a wider metal layer width, The computer system according to claim 12 or 13. **Claim 15** The first set of information parameters for two - dimensional wiring for each combination of metal layers includes the combination of metal layers, the metal layer width, and a specific delay time The information parameters of the second set for each constraint class include the constraint class, the combination of metal layers, the metal layer width and space, and the repeater reach length. The computer system according to any one of claims 12 to 14. **Claim 16** The method further includes determining a required space between blocks to place a repeater, and if the space exceeds a predetermined relative threshold, a part of the net is assigned to a higher constraint class, according to the computer system of any one of claims 12 to 15. **Claim 17** The routing for different constraint classes is executed in parallel, according to the computer system of any one of claims 12 to 16. **Claim 18** The determination of a specific delay time is executed by at least one of a virtual timing model, an estimated timing model, and an extracted timing model, according to the computer system of any one of claims 12 to 17. **Claim 19** The method further comprises determining a distance of a repeater bay from an edge of a block and comparing this distance with a specific delay time, according to the computer system of any one of claims 12 to 18. **Claim 20** An additional net length for connecting a repeater outside the blockage, and a net with a negative slack are assigned to a higher constraint class, according to the computer system of any one of claims 13 to 19. **Claim 21** The method further includes that when the block is larger than the repeater reach length, the net is assigned to a higher constraint class until a sufficient repeater reach length and / or a positive slack are found, according to the computer system of any one of claims 12 to 20. **Claim 22** The routing of the net is executed for the nets of the actual constraint buckets, and when the bucket is not the first bucket, it is executed for the nets of all the buckets present in the working list, according to the computer system of any one of claims 12 to 21. **Claim 23** A computer program product for a multilayer integrated circuit routing tool that connects a source with a net to a sink in a hierarchical multilayer integrated circuit design environment, the computer program product comprising: One or more computer-readable storage media, and program instructions stored on the one or more computer-readable storage media, the program instructions being executable by a computing system, the computing system to: Create a cycle reach table that includes a first set of information parameters for a two-dimensional net for each combination of metal layers; Create a repeater reach table that includes a second set of information parameters for each constraint class; Prepare a working list of nets by starting from a first constraint class corresponding to a combination of the lowest metal layers, creating a list of nets having the same constraint class, and extracting and checking blocked areas in the wiring region; Mark all blocks whose length and width are greater than the repeater reach length, create a blockage on top of these blocks on the metal layer assigned by the constraint class selected from the repeater reach table, and create a blockage on a higher metal layer up to the topmost metal layer, thereby preparing a list of blocks whose length is greater than the repeater reach length, where the metal layers include M1, M2, M3, M4, M5, M6, M7, M8, where M8 is the topmost metal layer; and Connect a source pin to a sink pin on a pre-assigned metal layer by routing the net based on the selected constraint class including, A computer program product.

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