Carbon hard mask opening using a boron nitride mask

Abstract

An exemplary semiconductor processing method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The method may include contacting a substrate contained in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron- and nitrogen-containing material overlying a carbon-containing material. The boron- and nitrogen-containing material includes a plurality of openings. The method may include etching the carbon-containing material.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 17 / 861,691, filed July 11, 2022, and entitled "CARBON HARDMASK OPENING USING BORON NITRIDE MASK," the contents of which are incorporated herein by reference in their entirety.

[0002] The present technology relates to semiconductor processing and manufacturing equipment, and more particularly to etching operations. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. Creating patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or narrowing the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than another, for example, facilitating the pattern transfer process. Such an etching process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes have evolved with selectivity to a variety of materials.

[0004] Etching processes can be referred to as wet or dry based on the materials used in the process. Wet HF etching preferentially removes one material over another. However, wet processes can have difficulty penetrating some restricted holes and can sometimes deform the remaining material. Dry etching, which occurs with a localized plasma formed within the substrate processing region, can penetrate more restricted holes and may exhibit less deformation of the remaining delicate structures. However, localized plasma can damage the substrate due to electric arcs that occur when the localized plasma discharges.

[0005] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0006] An exemplary semiconductor processing method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The method may include contacting a substrate contained in the processing region with the oxygen-containing plasma effluents. The substrate may include a boron- and nitrogen-containing material overlying a carbon-containing material. The boron- and nitrogen-containing material includes a plurality of openings. The method may include etching the carbon-containing material.

[0007] In some embodiments, the oxygen-containing precursor may be or may include diatomic oxygen. The openings in the boron- and nitrogen-containing material may be circular apertures. The substrate may include alternating layers of oxide and nitride materials. The carbon-containing material may be disposed on the alternating layers of oxide and nitride materials. The oxygen-containing plasma effluent may be formed at a source plasma power of less than or about 5,000 W. The method may include applying a bias power while forming the oxygen-containing plasma effluent, the bias power being greater than or about 2,000 W. The temperature in the semiconductor processing chamber may be maintained at about -50°C to about 250°C. The method may include stopping the flow of the oxygen-containing precursor, providing a fluorine-containing precursor to a processing region of the semiconductor processing chamber, forming a plasma of the fluorine-containing precursor to produce fluorine-containing plasma effluents, contacting the substrate with the fluorine-containing plasma effluents, and etching oxidized portions of the boron- and nitrogen-containing material, or oxidized portions of the carbon-containing material, or both. The fluorine-containing precursor may be or may include a hydrofluorocarbon.

[0008] Some embodiments of the present technology include a semiconductor processing method. The method may include i) forming a plasma of an oxygen-containing precursor to produce oxygen-containing plasma effluents. The method may include ii) contacting a carbon-containing material with the oxygen-containing plasma effluents. The discontinuous boron-containing material may be on the carbon-containing material. The method may include iii) selectively etching the carbon-containing material relative to the boron-containing material.

[0009] In some embodiments, the pressure may be maintained at less than or about 1 Torr. The oxygen-containing plasma effluent may be formed at a duty cycle of less than or about 70%. The etching may form a plurality of holes in the carbon-containing material. Each of the plurality of holes may be characterized by a circularity of less than or about 1.5. The boron-containing material may be characterized by a first thickness. The carbon-containing material may be characterized by a second thickness. The second thickness may be greater than the first thickness. The method may include iv) forming a plasma of a fluorine-containing precursor to produce fluorine-containing plasma effluents. The method may include v) contacting an oxidized portion of the boron-containing material, or an oxidized portion of the carbon-containing material, or both, with the fluorine-containing plasma effluents. The method may include vi) etching the oxidized portion of the boron-containing material, or the oxidized portion of the carbon-containing material. Operations i) to vi) may be repeated at least two times.

[0010] Some embodiments of the present technology include a semiconductor processing method. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The fluorine-containing precursor may be or may include a hydrofluorocarbon. The method may include forming a plasma of the fluorine-containing precursor to produce fluorine-containing plasma effluents. The method may include contacting a substrate with the fluorine-containing plasma effluents. The substrate may include a boron- and nitrogen-containing material overlying a carbon-containing material. The boron- and nitrogen-containing material may include a plurality of openings. The carbon-containing material may include a plurality of holes aligned with the plurality of openings. A portion of the boron- and nitrogen-containing material, a portion of the carbon-containing material, or both may be oxidized. The method may include etching the oxidized portion of the boron- and nitrogen-containing material, the oxidized portion of the carbon-containing material, or both.

[0011] In some embodiments, the carbon-containing material may be a carbon-containing hard mask. The method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The oxygen-containing precursor may be or include diatomic oxygen. The method may include forming a plasma of the oxygen-containing precursor to produce oxygen-containing plasma effluents. The method may include contacting a substrate contained in the processing region with the oxygen-containing plasma effluents. The method may include etching the carbon-containing material, where the etching forms oxidized portions of a boron- and nitrogen-containing material, oxidized portions of the carbon-containing material, or both. The plurality of holes may be characterized by a circularity of less than or about 1.5, a bow critical dimension (CD) of less than or about 125 nm, and a local critical dimension uniformity (LCDU) of less than or about 10 nm.

[0012] Such technology may provide numerous benefits over conventional systems and techniques. For example, the process uniformly etches the underlying material without substantial clogging of the overlying material. Additionally, operation of embodiments of the technology may maintain uniform etching while utilizing fewer flash processing steps, increasing overall throughput. These and other embodiments, along with many of the advantages and features of those embodiments, are described in more detail below in connection with the description and accompanying figures.

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and drawings. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 shows a top diagrammatic view of an exemplary processing system in accordance with some embodiments of the present technology. [Figure 2] FIG. 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technology. [Figure 3] 1A-1C illustrate selected operations in an etching method in accordance with some embodiments of the present technology. [Figure 4A] 1A-1C are cross-sectional views of substrate material on which selected operations are being performed in accordance with some embodiments of the present technology. [Figure 4B] 1A-1C are cross-sectional views of substrate material on which selected operations are being performed in accordance with some embodiments of the present technology. [Figure 4C] 1A-1C are cross-sectional views of substrate material on which selected operations are being performed in accordance with some embodiments of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0015] Some of the figures are included as schematics. It should be understood that the figures are for illustrative purposes and should not be considered to be to scale unless expressly stated to be to scale. Additionally, as schematics, the figures are provided to aid in comprehension and may not include all aspects or information compared to realistic representations, and may include more or exaggerated material than necessary for illustrative purposes.

[0016] In the accompanying figures, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes among the similar components. If only a first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0017] When transitioning from 2D NAND memory structures to 3D NAND memory structures, many operations are modified from vertical to horizontal processing. In addition, as the number of cells formed in 3D NAND structures increases, the aspect ratios of memory holes and other structures increase, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials can form inter-electrode dielectric layers or inter-poly dielectric ("IPD") layers. Various operations can be performed on these placeholder layers to place structures before the material is completely removed and replaced with metal. The IPD layer is often formed over a conductor layer, such as polysilicon. Before memory holes can be formed, an overlying mask must first have features etched into the material. The overlying mask can then serve as a mask to form memory holes in the IPD layer.

[0018] A reactive ion etching ("RIE") operation may be performed to create high aspect ratio features in a mask overlying the IPD layer in which memory holes will be formed. Unfortunately, this type of etching process may result in redeposition of etchant material on the mask overlying the material being etched. The redeposition of material may block access to the underlying material being etched.

[0019] Many conventional technologies utilize silicon-containing materials, such as SiON dielectric antireflective coatings, to pattern masks overlying the IPD layer. However, during etching of the mask material, the silicon-containing material tends to clog due to redeposition of materials, such as silicon oxide, adjacent to openings in the patterned silicon-containing material. Although the openings in the silicon-containing material tend to be tens or hundreds of nanometers in cross-sectional diameter, clogging can ultimately lead to the formation of memory moles in the IPD layer. Such clogging results in inconsistent and non-uniform etching of the underlying mask material. Thus, the clog can redirect the etchant, over-etching the mask material adjacent to the clog. To address clogging, flushing steps can be used to remove the redeposited material and maintain the circularity of the opening. However, these flushing steps increase wait times and reduce throughput.

[0020] The present technology overcomes these problems by utilizing a boron- and nitrogen-containing material over the mask material underlying the boron- and nitrogen-containing material. By replacing conventional silicon-containing materials with boron- and nitrogen-containing materials, clogging problems can be reduced. In this way, circularity and uniformity can be increased or maintained during etching. Furthermore, reducing redeposition of material adjacent to openings in the boron- and nitrogen-containing material requires the use of fewer flash processing steps, increasing overall throughput.

[0021] While the remainder of this disclosure will routinely highlight specific etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes such as those that may occur in the chambers described. Accordingly, the technology should not be considered limited for use solely with etching processes or chambers. Also, while an exemplary chamber is described to provide a foundation for the technology, it should be understood that the technology is applicable to virtually any semiconductor processing chamber that can enable the single-chamber operation described. Similarly, while a specific contact cleaning operation is described, it should be understood that the process may be equally applicable to other processes in which selective etching may be performed. Accordingly, the examples given should not be considered to limit the scope of the described technology.

[0022] 1 shows a top diagrammatic view of one embodiment of a deposition, etch, bake, and / or cure chamber processing system 10, according to embodiments. The tool or processing system 10 depicted in FIG. 1 may contain multiple process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chambers may include any number or combination of processing chambers, as well as any number of structures or components.

[0023] To transport substrates between chambers, the transfer chamber 20 may contain a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a attached to the distal end of each of extendable arms 22b. The blades 22a may be used to transport individual substrates to and from the process chambers. In operation, one of the substrate transport blades, such as blade 22a of the transport mechanism 22, may remove a substrate W from one of the load lock chambers, such as chambers 16a-b, and transport the substrate W to chambers 24a-d for processing, e.g., the first stage of a treatment process, as described below. The chambers may be included to perform individual or combined operations of the described technology. For example, one or more chambers may be configured to perform deposition or etching operations, while one or more other chambers may be configured to perform pre-treatment operations and / or one or more post-treatment operations, as described. Any number of configurations, which may further perform any number of additional manufacturing operations typically performed in semiconductor processing, are encompassed by the present technology.

[0024] If a chamber is occupied, the robot may wait until processing is complete and then remove the processed substrate from the chamber with one blade 22a and insert a new substrate with a second blade. Once the substrate has been processed, it may then be moved to a second stage of processing. For each movement, the transport mechanism 22 may generally have one blade carrying the substrate and one blade free to perform a substrate swap. The transport mechanism 22 may wait in each chamber until the swap can be accomplished.

[0025] Once processing is completed in a process chamber, the transport mechanism 22 may remove the substrate W from the last process chamber and transport the substrate W to a cassette in the load lock chambers 16a-b. From the load lock chambers 16a-b, the substrate may move into the factory interface 12. The factory interface 12 may generally operate to transfer substrates between the pod loaders 14a-d and the load lock chambers 16a-b in an atmospheric pressure clean environment. The clean environment within the factory interface 12 may generally be provided by an air filtration process, such as HEPA filtration. The factory interface 12 may also include a substrate orienter / aligner that may be used to properly align the substrates prior to processing. At least one substrate robot, such as robots 18a-b, may be positioned within the factory interface 12 to transport substrates between various locations within the factory interface 12 and to other locations in communication with the factory interface 12. The robots 18a-b may be configured to travel along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0026] The processing system 10 may further include an integrated metrology chamber 28 for providing control signals that may provide adaptive control over any of the processes being performed in the processing chambers. The integrated metrology chamber 28 may include any of a variety of metrology devices for measuring various film characteristics such as thickness, roughness, composition, etc., and the metrology devices may also be capable of characterizing lattice parameters such as critical dimensions, sidewall angles, and feature heights under vacuum in an automated manner.

[0027] Each of the processing chambers 24a-d may be configured to perform one or more process steps in the fabrication of semiconductor structures, and any number and combination of processing chambers may be used on the multichamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing operations, including any number of deposition processes, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, and physical vapor deposition, as well as other operations, including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers, or in any combination of chambers, may be metal deposition, surface cleaning and preparation, thermal annealing, such as rapid thermal processing, and plasma treatment. Any other processes, including any of the processes described below, may likewise be performed in the specific chambers incorporated into the multichamber processing system 10, as will be readily apparent to a skilled artisan.

[0028] 2 illustrates a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 within the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that aspects of the present technology may be performed in any number of chambers, and that a substrate support according to the present technology may be included in an etch chamber, a deposition chamber, a treatment chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber space 101 in which a substrate may be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 coupled to ground 126. The sidewalls 112 may have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limited and may generally be proportionally larger than the size of the substrate 302 to be processed in the plasma processing chamber 100. Example substrate sizes, such as display substrates or even solar cell substrates, include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others.

[0029] The chamber body 105 may support a chamber lid assembly 110 for enclosing the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. A substrate access port 113 may be formed through a sidewall 112 of the chamber body 105 to facilitate transfer of a substrate 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled to a transfer chamber and / or other chambers of a substrate processing system as previously described. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to evacuate the processing space and control the pressure therein. The pumping device may include one or more pumps and a throttle valve.

[0030] A gas panel 160 may be coupled to the chamber body 105 by gas lines 167 to supply process gases into the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert, non-reactive, and reactive gases that may be utilized for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon-containing gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon gas, chlorine, nitrogen, helium, or oxygen gas, as well as any number of additional materials. Additionally, the process gas may include nitrogen-, chlorine-, fluorine-, oxygen-, and hydrogen-containing gases such as BCl, CF, C2F, C4F, C4F, C4F, CHF, CH2F, CH3F, NF, NH, CO, SO, CO, N2, NO, N2O, and H2, among any number of additional precursors.

[0031] A valve 166 may control the flow of process gas from sources 161, 162, 163, and 164 from a gas panel 160 and may be managed by a controller 165. The flow of gas supplied to the chamber body 105 from the gas panel 160 may include a combination of gases from one or more sources. The lid assembly 110 may include a nozzle 114. The nozzle 114 may be one or more ports for introducing process gas from the sources 161, 162, 164, and 163 of the gas panel 160 into the chamber volume 101. After the process gas is introduced into the plasma processing chamber 100, the gas may be energized to form a plasma. An antenna 148, such as one or more inductor coils, may be provided near the plasma processing chamber 100. An antenna power supply 142 may power the antenna 148 through a match circuit 141 to inductively couple energy, such as RF energy, to the process gas to maintain a plasma formed from the process gas within the chamber volume 101 of the plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, a process electrode below and / or above the substrate 302 may be used to capacitively couple RF power to the process gas to maintain a plasma within the chamber volume 101. The operation of the power supply 142 may be controlled by a controller, such as controller 165, which in turn controls the operation of other components in the plasma processing chamber 100.

[0032] A substrate support pedestal 135 may be disposed within the chamber volume 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for securing the substrate 302 during processing. The electrostatic chuck (“ESC”) 122 may use electrostatic attraction to secure the substrate 302 to the substrate support pedestal 135. The ESC 122 may be powered by an RF power supply 125 integrated with a match circuit 124. The ESC 122 may include an electrode 121 embedded within a dielectric body. The electrode 121 may be coupled to the RF power supply 125 and may provide a bias to the ESC 122 and the substrate 302 mounted on the pedestal that attracts plasma ions formed by the process gas within the chamber volume 101. The RF power supply 125 may be cycled on and off, or pulsed, during processing of the substrate 302. The ESC 122 may have an isolator 128 for the purpose of making the sidewalls of the ESC 122 less attractive to the plasma in order to extend the maintenance lifecycle of the ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from plasma gases and to extend the time between maintenance of the plasma processing chamber 100.

[0033] The electrode 121 may be coupled to a power supply 150. The power supply 150 may provide a chucking voltage of about 200 volts to about 2000 volts to the electrode 121. The power supply 150 may further include a system controller for controlling the operation of the electrode 121 by directing DC current to the electrode 121 to chuck and dechuck the substrate 302. The ESC 122 may include a heater disposed in the pedestal and connected to a power supply to heat the substrate, while the cooling base 129 supporting the ESC 122 may include conduits for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 302 disposed thereon. The ESC 122 may be configured to operate within a temperature range required by the thermal budget of the device being fabricated on the substrate 302. For example, the ESC 122 may be configured to maintain the substrate 302 at a temperature of about −150° C. or lower to about 500° C. or higher, depending on the process being performed.

[0034] A cooling base 129 may be provided to help control the temperature of the substrate 302. To reduce process drift and time, the temperature of the substrate 302 may be kept substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained at a temperature between about −150° C. and about 500° C. throughout the subsequent cleaning process, although any temperature may be utilized. A cover ring 130 may be disposed over the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine the etching gas to a desired portion of the exposed top surface of the substrate 302, while protecting the top surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. The lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism, as previously described.

[0035] The controller 165 may be utilized to modulate gas flow from the gas panel 160 into the plasma processing chamber 100 and other process parameters to control the process sequence. The software routines, when executed by the CPU, transform the CPU into a special-purpose computer, such as a controller, that may control the plasma processing chamber 100 so that processes are performed according to the present disclosure. The software routines may also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 100.

[0036] The chambers discussed above can be used in performing exemplary methods, including etching and processing methods. Turning to FIG. 3 , exemplary operations in method 300 according to an embodiment of the present technology are shown. Prior to the first operation of the method, a substrate can be processed in one or more ways before being placed in a processing region of a chamber in which method 300 can be performed. For example, an IPD layer can be formed on the substrate, and one or more layers above the IPD layer can be processed. The IPD layer can include any number of materials and can include alternating layers of placeholder and dielectric materials. In embodiments, the dielectric material can be or include silicon oxide, and the placeholder material can be or include silicon nitride. While the remainder of this disclosure discusses silicon nitride and silicon oxide, any other known material used in these two layers can be substituted for one or more of the layers. Some or all of these operations can be performed in a chamber or system tool as described above, or in various chambers on the same system tool, including the chamber in which the operations of method 300 are performed.

[0037] Method 300 may include several optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described to provide a broader range of structure formation, but are not required for the present technology or may be performed by alternative methodologies, as will be discussed further below. Method 300 represents operations shown generally in Figures 4A-4C, illustrations of which will be described in conjunction with the operations of method 300. It should be understood that Figures 4A-4C show only partial schematic views, and that a substrate may include any number of structural portions having the features shown in the figures, as well as alternative structural features that may still benefit from the operations of the present technology.

[0038] Method 300 may or may not involve optional operations that advance the semiconductor structure to a specific manufacturing operation. It should be understood that method 300 can be performed on any number of semiconductor structures, and FIGS. 4A-4C illustrate one exemplary structure on which an etching process may be performed. As shown in FIG. 4A, processed semiconductor structure 400 may include a substrate 405, which may have multiple stacked layers thereon, which may be silicon-containing materials such as polysilicon, silicon germanium, or other substrate materials and may be conductors for contacts in subsequent metallization. As just one non-limiting example, the layers may include an IPD layer including a dielectric material 410, which may be silicon oxide, in alternating layers with a placeholder material 415, which may be silicon nitride. Placeholder material 415 may be or include a material that will be removed to create individual memory cells in subsequent operations. Although only four layers of material are shown, it should be understood that the exemplary structure may include any number of layers discussed above, which may include tens or hundreds of layers, and the figures are merely schematic diagrams to illustrate aspects of the present technology.

[0039] A mask material 420 may be formed overlying the IPD layer and may be a carbon-containing material, such as an amorphous carbon carbon-containing hard mask, or any other carbon-containing material that may be formed on an underlying layer during subsequent cleaning and / or etching operations. A boron- and nitrogen-containing material 425 may be disposed over the mask material 420. The boron- and nitrogen-containing material 425 may include a plurality of openings or apertures 430. The openings or apertures 430 may extend through the entire thickness of the boron- and nitrogen-containing material 425 to expose the underlying mask material 420.

[0040] As shown, multiple materials may be present and may be exposed to an etchant material that may be used in an etching process. Method 300 is performed to etch or remove portions of mask material 420 exposed in opening 430 to minimize etching of boron and nitrogen containing material 425. By utilizing process conditions and precursors according to embodiments of the present technology, etching of boron and nitrogen containing material 425 may be limited or prevented during etching of mask material 420.

[0041] Method 300 may include, in operation 305, providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The processing region may contain a substrate, such as processed semiconductor structure 400, which may have exposed boron- and nitrogen-containing material, such as boron- and nitrogen-containing material 425, and exposed carbon-containing material, such as mask material 420, which may be a carbon-containing hard mask. The boron- and nitrogen-containing material may be discontinuous such that the material includes opening 430. Mask material 420 may be exposed in recessed features, such as opening 430, which may pose a problem with conventional technologies that may clog or block opening 430 while simultaneously etching mask material 420. Opening 430 may be a circular aperture.

[0042] The boron-containing material, such as boron- and nitrogen-containing material 425, may be characterized by a first thickness. The carbon-containing material, such as mask material 420, may be characterized by a second thickness. The second thickness may be greater than the first thickness. The etching operation may be selective to the carbon-containing material, such that features or holes etched into the carbon-containing material are formed before the boron- and nitrogen-containing material 425 is completely removed.

[0043] The method 300 may also include flowing a secondary precursor into a processing region of the semiconductor processing chamber in operation 305. The secondary precursor may be, for example, a halogen-containing precursor, such as a chlorine-containing precursor.

[0044] Method 300 may include forming a plasma in a processing region of a semiconductor processing chamber in operation 310. The plasma may generate plasma effluents of the oxygen-containing precursor and, if present, the secondary precursor. Operations 305 and 310 may occur sequentially or may be performed substantially simultaneously in some embodiments. Additionally, a plasma may be first formed from either the precursor or one or more inert precursors before adding the oxygen-containing precursor and / or the secondary precursor in various embodiments.

[0045] Semiconductor structure 400 may be contacted with plasma effluents in operation 315, which may perform etching or removal of mask material 420 in operation 320. As shown in FIGS. 4B-4C , the plasma effluents may contact semiconductor structure 400 and all exposed surfaces, including surfaces to be etched, such as mask material 420, and surfaces to be retained, such as boron and nitrogen-containing material 425. The etching in operation 320 may form features 440, sometimes referred to as holes, in mask material 420. The aspect ratio of features 440 may be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater than or about 50:1.

[0046] Due to the nature of plasma etching, the boron- and nitrogen-containing material 425 may be susceptible to etching, albeit at a reduced rate compared to the mask material 420. However, when an oxygen-containing precursor is provided, the local plasma may produce an etchant material that may be relatively selective to carbon materials and may therefore be more likely to etch the mask material 420 rather than the boron- and nitrogen-containing material 425. Thus, etching of the mask material 420 may be performed, while etching of the boron- and nitrogen-containing material 425 may be unaffected or may be only limitedly affected.

[0047] Precursors used in the etching process may include oxygen-containing precursors and secondary precursors, as previously described. An exemplary oxygen-containing precursor may be diatomic oxygen (O), which may flow into the processing region. Other oxygen sources may be used in conjunction with or in place of diatomic oxygen. For example, oxygen-containing precursors may include one or more materials containing water, diatomic oxygen, ozone, hydroxyl-containing precursors such as hydrogen peroxide or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen containing locally or remotely enhanced oxygen, or any other material containing oxygen that may be supplied to the processing region to facilitate the first etching operation, or any other oxygen-containing material. The precursor may also include any number of carrier gases, which may include nitrogen, helium, argon, or other rare, inert, or useful precursors. The carrier gas may be used to dilute the precursor, thereby reducing the etch rate to allow proper diffusion through the opening. Additionally, as previously discussed, the precursor may include a secondary precursor, such as a chlorine-containing precursor or any other halogen-containing precursor.

[0048] In embodiments, the precursors may include a passivation precursor, such as carbonyl sulfide (COS). The addition of the passivation precursor may reduce bowing in the feature as material is removed. The passivation precursor may form a passivation layer 435, such as a carbon sulfide material, on the sidewalls of the feature that is resistant to etching against the mask material 420.

[0049] Process conditions can affect the operations performed in method 300. While each of the operations of method 300 can be performed during a constant temperature in embodiments, in some embodiments, the temperature can be adjusted during various operations. For example, the temperature of the substrate, pedestal, or chamber during processing can be maintained at temperatures below or about 250°C, below or about 200°C, below or about 150°C, below or about 100°C, below or about 90°C, below or about 80°C, and in some embodiments, temperatures can be maintained at or below 70°C, below or about 60°C, below or about 50°C, below or about 30°C, below or about 20°C, below or about 10°C, below or about 0°C, below or about -10°C. Maintaining the temperature of the substrate, pedestal, or chamber at a lower relative temperature may minimize warping in the feature 440 as the mask material 420 is etched. However, as the temperature decreases, the circularity of the aperture 430 and / or feature 440 may also decrease. Therefore, a higher relative temperature may increase the uniformity of the etching and redeposition of material, which may maintain the circularity of the aperture 430 and / or feature 440. Thus, in embodiments, the temperature of the substrate, pedestal, or chamber may be maintained at a temperature of about −50° C. to about 250° C., e.g., about −30° C. to about 150° C., about −20° C. to about 100° C., or about −15° C. to about 50° C.

[0050] The pressure in the processing chamber can be controlled during method 300. For example, while forming the localized plasma and performing the removal operation, the pressure in the processing chamber can be maintained at less than or about 5 Torr. Additionally, in embodiments, the pressure in the processing chamber can be less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 200 mTorr, less than or about 150 mTorr, less than or about 100 mTorr, less than or about 80 mTorr, less than or about 60 mTorr, or less than or about 100 mTorr. The pressure may be maintained at about 60 mTorr, below or about 50 mTorr, below or about 45 mTorr, below or about 40 mTorr, below or about 35 mTorr, below or about 30 mTorr, below or about 25 mTorr, below or about 20 mTorr, or lower, although the pressure may also fall within a range between any two of these stated numbers or within any smaller range encompassed by any of the stated ranges. The pressure may affect the critical dimensions of the feature 440 etched into the mask material 420. For example, increased pressure may result in insufficient passivation on the sidewalls of the feature 440, increasing lateral etching, and depleting the shoulder of the boron- and nitrogen-containing material 425. Additionally, the pressure within the processing chamber can affect the ability to flow into the aperture 430. For example, as the pressure increases, it can become increasingly difficult for plasma effluents to penetrate the aperture 430 and reach the underlying mask material 420. Thus, in some embodiments, the pressure can be maintained below or about 1 Torr to allow effluents to flow into the recessed feature 440 on the semiconductor structure 400.

[0051] The local plasma formed from the precursors can provide directionality for plasma effluents to flow toward the mask material 420. Thus, etchant can be directed into the openings 443035, facilitating the effluent reaching and etching the mask material 420. The plasma can be low-level to limit the amount of bombardment, sputtering, and surface deformation. In embodiments, the plasma power can be less than or about 5,000 W, less than or about 4,500 W, less than or about 4,000 W, less than or about 3,500 W, less than or about 3,000 W, less than or about 2,500 W, less than or about 2,000 W, less than or about 1,500 W, less than or about 1,000 W, or less. For example, by utilizing a plasma power that is less than about 4,000 W, plasma effluents may be better controlled as they are delivered through apertures 430, but sputtering of other exposed surfaces may be limited.

[0052] In embodiments, a dual frequency plasma power source may be used to maintain the circularity of the aperture 430 and / or feature 440. For example, a dual frequency mixed plasma power source may provide a high frequency power in the range of about 10 MHz to about 60 MHz and a low frequency power in the range of about 10 KHz to about 1 MHz. A second plasma source, which may provide bias power, may operate at a similar level to the first plasma source. However, in embodiments, the bias power may operate at a higher level than the source power. For example, the bias power may operate at greater than or about 2,000 W, e.g., greater than or about 2,500 W, greater than or about 3,000 W, greater than or about 3,500 W, greater than or about 4,000 W, greater than or about 4,500 W, or greater than or about 4,500 W. Increased bias power can maintain circularity and etch rate.

[0053] Additional adjustments can be made to further enhance etching of deposited material along the sidewalls of feature 440 by adjusting one or more characteristics of the supplied plasma power or bias power. For example, in some embodiments, both the plasma power source and the bias power source can be operated in a continuous wave mode. In addition, one or both of the power sources can be operated in a pulsed mode. In some embodiments, the source power can be operated in a continuous wave mode or a pulsed mode, while the bias power is operated in a pulsed mode. The pulsed frequency of the source power, the bias power, or both can be less than or about 500 Hz, less than or about 450 Hz, less than or about 400 Hz, less than or about 350 Hz, less than or about 300 Hz, less than or about 250 Hz, less than or about 200 Hz, less than or about 150 Hz, less than or about 100 Hz, less than or about 75 Hz, less than or about 50 Hz, or lower. The duty cycle of the source power, bias power, or both may be less than or about 75%, such as less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 25%, less than or about 20%, or a duty cycle of less than these. By operating the source power, bias power, or both at a reduced duty cycle, such as an on-time duty of less than or about 50%, improved isotropic etching within the feature 440 may be performed for a longer time per cycle, which may result in better material removal from the mask material 420 and better maintenance of etch rate, circularity, and uniformity. Additionally, a duty cycle of less than or about 50% may reduce warping of the material during etching.

[0054] During the etching operation, intermittent flash processing steps may be performed to maintain the feature 440 and / or remove material from the feature 440 or the boron- and nitrogen-containing material 425 being etched. The flash processing steps may prevent clogging of the openings 430 in the boron- and nitrogen-containing material 425, which may be clogged by oxidation emissions from the etching deposition / formation of boron oxide material on the material. Additionally, the flash processing steps may prevent or reduce blocking of the openings 430 and remove any bottom obstructions in the feature 440, such as boron oxide material. During the flash processing steps, the flow of the oxygen-containing precursor may be stopped or reduced in optional operation 325. By stopping the flow of the oxygen-containing precursor, interactions between the precursors used in the flash etching may be eliminated or reduced.

[0055] In operation 330, a halogen-containing precursor may be provided. The halogen-containing precursor may be any halogen-containing material that can provide a halogen during plasma dissociation to remove material from the openings 430 in the boron and nitrogen-containing material 425, such as the oxidized material in the openings 430 or the oxidized material in the openings 440 in the mask material 420. For example, exemplary halogen-containing materials may include fluorine, chlorine, or bromine. Exemplary halogen-containing materials may include fluorine and fluorocarbons such as CF4, CF6, hydrofluorocarbons, or any other material that may include one or more halogen atoms in its structure.

[0056] In operation 335, method 300 may include forming plasma effluents of a halogen-containing precursor. Semiconductor structure 400 may be contacted with the plasma effluents in operation 340, which may etch or remove oxidized portions of boron- and nitrogen-containing material 425 and / or mask material 420 in operation 345. The plasma effluents may also remove portions of boron that have redeposited at the bottom of feature 440. CF xPlasma radicals of halogen-containing precursors or fluorine-containing precursors, such as radicals, can etch boron- and oxygen-containing materials that may form on the boron- and nitrogen-containing material 425 during the etching process. Fluorine atoms also etch boron- and oxygen-containing materials, but CF x Hydrogen from hydrofluorocarbon gases can suppress the formation of free fluorine, which can make them less effective at removing oxygen. CF x The radicals and fluorine atoms may also etch the front oxidation into features 440 that extend into the mask material 420 .

[0057] Depending on the thickness of the mask material 420, multiple flash processing steps may be necessary to ensure efficient etching and removal of the material. However, compared to conventional masks for etching the mask material 420, such as silicon oxynitride antireflective coatings, fewer flash processing steps may be required in this embodiment, which may increase throughput. For example, at a thickness of mask material 420 greater than or about 3,000 nm, fewer than five flash processing steps, e.g., fewer than four flash processing steps, fewer than three flash processing steps, fewer than two flash processing steps, or one flash processing step may be required to maintain the openings 430 and / or features 440 during etching. However, it is contemplated that the method 300 may be repeated multiple times, such as at least two times.

[0058] The process conditions during the flash processing step of method 300 may be the same as the process conditions for the etch operation of method 300. However, it is contemplated that the process conditions may be adjusted within the ranges previously described. Additionally, the flash processing step may be performed in the same processing chamber as the etch operation or in a different processing chamber than the etch operation.

[0059] Process parameters, including but not limited to precursor selection, temperature, pressure, and plasma power, can allow the total etch time, warpage critical dimension, local critical dimension uniformity (LCDU), and roundness to be adjusted during the process. For example, depending on the depth to be etched, the total etch time can be less than 30 minutes for depths greater than or about 3,000 nm. The warpage critical dimension of feature 440 can be less than or about 125 nm, e.g., less than or about 120 nm, less than or about 115 nm, less than or about 110 nm, less than or about 105 nm, or less than or about 100 nm. The LDCU of feature 440 can be less than or about 10 nm, e.g., less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm. The circularity of feature 440 can be less than or about 1.5, e.g., less than or about 1.4, less than or about 1.3, less than or about 1.2, less than or about 1.1, less than or about 1.09, less than or about 1.08, less than or about 1.07, less than or about 1.06, less than or about 1.05, less than or about 1.04, less than or about 1.03, or less.

[0060] In the preceding description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0061] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be interpreted as limiting the scope of the present technology. Additionally, while a method or process may be described sequentially or stepwise, it should be understood that operations may be performed in parallel or in an order different from the order listed.

[0062] When a range of values is provided, it is understood that each intervening value between the upper and lower limits of that range, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, is also specifically disclosed. Any narrower range between any stated or unstated intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either limit is included, neither limit is included, or both limits are included in the smaller range is also encompassed within the technology, subject to any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0063] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to a "precursor" includes a plurality of such precursors, a reference to a "layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0064] Furthermore, the words "comprise (present tense)," "comprise (present participle)," "include / contain (present tense)," "include / contain (present participle)," "include (present tense)," and "comprise (present participle)," when used in this specification and in the claims that follow, are intended to specify the presence of stated features, integers, components, or operations, but these words do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber; forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent; contacting a substrate contained in the processing region with the oxygen-containing plasma effluents, the substrate comprising a boron and nitrogen containing material overlying a carbon-containing material, the boron and nitrogen containing material comprising a plurality of openings; Etching the carbon-containing material; A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the oxygen-containing precursor comprises diatomic oxygen.

3. 10. The semiconductor processing method of claim 1, wherein said opening in said boron and nitrogen containing material comprises a circular aperture.

4. the substrate further comprising alternating layers of oxide and nitride materials; The semiconductor processing method of claim 1 , wherein the carbon-containing material is disposed on the alternating layers of oxide and nitride materials.

5. 10. The semiconductor processing method of claim 1, wherein said oxygen-containing plasma effluents are formed at a source plasma power of less than or about 5,000 Watts.

6. 6. The semiconductor processing method of claim 5, further comprising applying a bias power while forming said oxygen-containing plasma effluents, said bias power being greater than or about 2,000 W.

7. 10. The semiconductor processing method of claim 1, wherein the temperature in the semiconductor processing chamber is maintained at about -50°C to about 250°C.

8. stopping the flow of the oxygen-containing precursor; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent; contacting the substrate with the fluorine-containing plasma effluents; etching the oxidized portion of the boron and nitrogen containing material, or the oxidized portion of the carbon containing material, or both; 10. The semiconductor processing method of claim 1, further comprising:

9. 9. The semiconductor processing method of claim 8, wherein the fluorine-containing precursor is a hydrofluorocarbon.

10. 1. A semiconductor processing method comprising: i) forming a plasma of an oxygen-containing precursor to produce an oxygen-containing plasma effluent; ii) contacting a carbon-containing material with said oxygen-containing plasma effluents, wherein discontinuous boron-containing material is on said carbon-containing material; iii) selectively etching said carbon-containing material relative to a boron-containing material; and A semiconductor processing method comprising:

11. 11. The semiconductor processing method of claim 10, wherein the pressure is maintained at less than or about 1 Torr.

12. 11. The semiconductor processing method of claim 10, wherein the oxygen-containing plasma effluents are formed at a duty cycle of less than or about 70%.

13. the etching forms a plurality of pores in the carbon-containing material; 11. The semiconductor processing method of claim 10, wherein each of the plurality of holes is characterized by a circularity of less than or about 1.

5.

14. the boron-containing material is characterized by a first thickness; the carbon-containing material is characterized by a second thickness; 11. The semiconductor processing method of claim 10, wherein said second thickness is greater than said first thickness.

15. iv) forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent; v) contacting the oxidized portion of the boron-containing material, or the oxidized portion of the carbon-containing material, or both, with the fluorine-containing plasma effluent; vi) etching the oxidized portion of the boron-containing material, or the oxidized portion of the carbon-containing material, or both; 11. The semiconductor processing method of claim 10, further comprising:

16. 16. The semiconductor processing method of claim 15, wherein operations i) to vi) are repeated at least twice.

17. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, the fluorine-containing precursor comprising a hydrofluorocarbon; forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent; contacting a substrate with the fluorine-containing plasma effluents, the substrate comprising a boron and nitrogen-containing material overlying a carbon-containing material, the boron and nitrogen-containing material comprising a plurality of openings, the carbon-containing material comprising a plurality of holes aligned with the plurality of openings, wherein a portion of the boron and nitrogen-containing material, a portion of the carbon-containing material, or both, are oxidized; etching the oxidized portion of the boron and nitrogen containing material, or the oxidized portion of the carbon containing material, or both; A semiconductor processing method comprising:

18. 20. The semiconductor processing method of claim 17, wherein the carbon-containing material comprises a carbon-containing hardmask.

19. providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber, the oxygen-containing precursor comprising diatomic oxygen; forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent; contacting the substrate contained in the processing region with the oxygen-containing plasma effluents; etching the carbon-containing material, wherein the etching forms the oxidized portion of the boron and nitrogen containing material, or the oxidized portion of the carbon-containing material, or both; 20. The semiconductor processing method of claim 17, further comprising:

20. The plurality of holes are Circularity of less than or about 1.5; a warpage critical dimension (CD) of less than or about 125 nm, and Local critical dimension uniformity (LCDU) of less than or about 10 nm 20. The semiconductor processing method of claim 17, characterized by:

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