Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer, a circuit pattern layer disposed on the insulating layer and including a pad, and a protective layer disposed on the insulating layer and including an opening vertically overlapping the pad, wherein the pad includes a recess recessed from an upper surface of the pad toward a lower surface of the pad, the protective layer includes a first region including the opening and vertically overlapping the pad, and a second region excluding the first region, the pad includes a first portion including the recess and a second portion connected to the first portion and not including the recess, the first portion of the pad includes a first sub-portion vertically overlapping the opening in the protective layer and a second sub-portion vertically overlapping the lower surface of the first region of the protective layer, and the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a board with limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which the semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). Therefore, the semiconductor package includes an interposer for connecting multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in response to the trend toward higher integration. Here, high performance includes the ability to transmit signals at high speeds, integration of the semiconductor package, and a high allowable current for transmittable signals.

[0005] In order to achieve miniaturization and integration of semiconductor packages, the pad size is reduced. The pad may be a mounting pad connected to a chip or a bump pad connected to various substrates. Here, the various substrates may include an additional package such as a memory substrate, an interposer connecting a chip and a circuit board, and a main board of an electronic device to which the semiconductor package is applied.

[0006] In this case, if the size of the pad is reduced, the integration density of the semiconductor package can be improved. However, in the semiconductor package of the related art, the contact area between the pad and the solder bump is reduced in response to the reduction in the size of the pad, which results in a problem of reduced adhesion between the pad and the solder bump. As a result, there are problems with physical reliability and electrical reliability, such as the solder bump being separated from the pad during the manufacturing process or in the usage environment of the semiconductor package.

[0007] (Patent Document 1) KR10-2152865B Summary of the Invention [Problem to be solved by the invention]

[0008] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0009] Furthermore, the embodiments provide a circuit board with improved integration and a semiconductor package including the same.

[0010] Furthermore, the embodiments provide a circuit board capable of improving the adhesive strength between the pads and the connection members, and a semiconductor package including the same.

[0011] Furthermore, the embodiments provide a circuit board capable of increasing the contact area between the pad and the connection member, and a semiconductor package including the same.

[0012] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0013] A circuit board according to an embodiment includes an insulating layer, a circuit pattern layer disposed on the insulating layer and including a pad, and a protective layer disposed on the insulating layer and including an opening vertically overlapping the pad, wherein the pad includes a recess recessed from an upper surface of the pad toward a lower surface of the pad, the protective layer includes a first region including the opening and vertically overlapping the pad, and a second region excluding the first region, the pad includes a first portion including the recess and a second portion connected to the first portion and not including the recess, the first portion of the pad includes a first sub-portion vertically overlapping the opening in the protective layer and a second sub-portion vertically overlapping the lower surface of the first region of the protective layer, and the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

[0014] Additionally, an upper surface of the second sub-portion of the pad is spaced apart from a lower surface of the first region of the protective layer, and an upper surface of the second portion of the pad is in direct contact with a lower surface of the first region of the protective layer.

[0015] The top surface of the first portion of the pad has an uneven shape.

[0016] The width of the second sub-portion of the pad is in the range of 2 to 50 times the width of the second portion of the pad.

[0017] Furthermore, the vertical distance from the lower surface of the first region of the protective layer to the upper surface of the first portion of the pad is in the range of 5% to 55% of the vertical distance from the lower surface of the first region of the protective layer to the lower surface of the pad.

[0018] The pad also includes a side surface, and at least a portion of the top surface of the first portion of the pad is connected to the side surface of the pad.

[0019] Additionally, the recess of the pad is connected to a side surface of the pad.

[0020] The pad also includes a first side and a second side opposite the first side, and a width of the second sub-portion of the pad adjacent the first side of the pad is different from a width of the second sub-portion of the pad adjacent the second side of the pad.

[0021] The recess includes a first part provided on the upper surface of the pad and a second part connected to the first part and provided on the side surface of the pad.

[0022] Additionally, the side of the pad including the second part is spaced apart from the protective layer.

[0023] The opening in the protective layer also includes a region whose width varies vertically.

[0024] The circuit pattern layer further includes a trace disposed on the insulating layer, the upper surface of the trace being higher than the upper surface of the first portion of the pad.

[0025] Meanwhile, a semiconductor package according to an embodiment includes an insulating layer, a pad disposed on the insulating layer and having a recess on an upper surface thereof, a protective layer disposed on the insulating layer and including an opening vertically overlapping with the pad, and a connecting member disposed to fill the opening in the protective layer and the recess in the pad, wherein an uneven interface is provided between the connecting member and the pad, the protective layer includes a first region including the opening and vertically overlapping with the pad, and a second region excluding the first region, the pad includes a first portion including the recess and a second portion connected to the first portion and not including the recess, the first portion of the pad includes a first sub-portion vertically overlapping with the opening in the protective layer and a second sub-portion vertically overlapping with a bottom surface of the first region of the protective layer, and the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

[0026] The connecting member also includes a portion disposed within the recess and in direct contact with a lower surface of the first region of the protective layer and an upper surface of the second sub-portion of the pad.

[0027] Further, the recess is connected to at least a portion of the side of the pad, and the connection member is disposed within the recess connected to the side of the pad and includes a portion that directly contacts the inner surface of the second region of the protective layer.

[0028] The recess further includes a first part provided on the upper surface of the pad and a second part connected to the first part and provided on the side of the pad, and the connecting member is disposed in the first part and the second part of the recess and includes portions that respectively contact the lower surface of the first region of the protective layer, the inner surface of the second region of the protective layer, the upper surface of the first part of the pad, and the side of the pad.

[0029] The semiconductor package further includes a semiconductor element disposed on the connecting member.

[0030] The device further includes a substrate disposed on the connection member.

[0031] The substrate may include at least one of an interposer connected to a semiconductor device, a memory substrate on which memory chips are arranged, a main board of an electronic device, and a bridge substrate connecting a plurality of semiconductor devices. [Effects of the Invention]

[0032] The circuit board and semiconductor package of the embodiment can improve the adhesion and bonding strength between the pad and the connection member, thereby solving the problem of cracks occurring in the connection member and thereby improving the physical and electrical reliability of the connection member.

[0033] To this end, the circuit board of the embodiment includes an insulating layer, a pad, and a protective layer. The protective layer includes an opening that vertically overlaps at least a portion of the pad. The protective layer includes a first region adjacent to the opening and vertically overlapping the pad, and a second region excluding the first region. The pad also includes a recess. The recess may be a concave recess that extends from the upper surface to the lower surface of the pad. The pad includes an upper surface having an uneven shape corresponding to the recess. The pad includes a first portion including the recess and a second portion not including the recess. The first portion of the pad includes a first sub-portion that vertically overlaps the opening of the protective layer and a second sub-portion that vertically overlaps the first region of the protective layer. A connecting member is disposed on the pad. The connecting member is disposed to fill the recess of the pad. As a result, the connecting member is disposed on not only the first sub-portion but also the second sub-portion of the pad. A portion of the connection member disposed in the second sub-portion may have a structure located between the lower surface of the first region of the protective layer and the upper surface of the second sub-portion of the pad.

[0034] As a result, the connecting member of the embodiment includes a first part disposed on the second sub-portion. The first part of the connecting member can function as an anchor that improves adhesive strength and adhesion to the pad. Through this, the embodiment can solve the reliability problem of the connecting member being separated from the pad. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0035] In addition, the embodiment may increase the contact area between the pad and the connection member through an anchor structure of the connection member. Therefore, the embodiment does not need to increase the size of the pad to increase the contact area. Therefore, the embodiment may reduce the size of the pad, thereby improving the integration density of the circuit. Furthermore, the embodiment may reduce the overall volume of the circuit board and the semiconductor package.

[0036] Meanwhile, the recess provided in the pad according to the embodiment may include multiple parts, for example, a first part provided on the top surface of the pad and a second part connected to the first part and provided on the side surface of the pad.

[0037] Therefore, at least a portion of the side surface of the pad may not contact the protective layer through the second part of the recess. A connecting member may be disposed in the second part of the recess of the pad. The connecting member may be disposed in the first part of the recess and contact the lower surface of the first region of the protective layer and the upper surface of the pad. The connecting member may also be disposed in the second part of the recess and contact the inner surface of the second region of the protective layer and the side surface of the pad. This may further increase the contact area between the pad and the connecting member. Therefore, the embodiment may further improve the adhesion and bonding strength between the pad and the connecting member. [Brief explanation of the drawings]

[0038] [Figure 1a] FIG. 10 is a cross-sectional view showing a circuit board according to a comparative example. [Figure 1b] FIG. 1b shows a scanning electron microscope photograph of the actual product of FIG. 1a. [Figure 2a] FIG. 1 is a diagram illustrating a semiconductor package according to a first embodiment. [Figure 2b] FIG. 10 is a diagram illustrating a semiconductor package according to a second embodiment. [Figure 2c] FIG. 10 is a diagram showing a semiconductor package according to a third embodiment. [Figure 2d] FIG. 10 is a diagram showing a semiconductor package according to a fourth embodiment. [Figure 2e] FIG. 10 is a diagram showing a semiconductor package according to a fifth embodiment. [Figure 2f] FIG. 10 is a diagram showing a semiconductor package according to a sixth embodiment. [Figure 3]FIG. 1 is a cross-sectional view showing a circuit board according to an embodiment. [Figure 4a] 2 is an enlarged cross-sectional view of a partial region of the circuit board according to the first embodiment. FIG. [Figure 4b] FIG. 4b is a plan view of the circuit board of FIG. 4a. [Figure 4c] 4b is a cross-sectional view showing a state in which a connecting member is arranged on the circuit board of FIG. 4a. FIG. [Figure 5a] FIG. 4b shows a first modified example of the circuit board of FIG. 4a. [Figure 5b] FIG. 4b shows a second modified example of the circuit board of FIG. 4a. [Figure 6] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 8a] FIG. 10 is a diagram showing a circuit board according to a fourth embodiment. [Figure 8b] 8b is a cross-sectional view showing a state in which a connecting member is arranged on the circuit board of FIG. 8a. FIG. [Figure 9] FIG. 10 is a cross-sectional view showing a circuit board according to a fifth embodiment. [Figures 10a-10d] 4A to 4C are cross-sectional views for explaining a method for manufacturing the circuit board shown in FIG. 3 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0039] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] However, the technical concept of the present invention is not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0041] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings that can be commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms such as dictionary-defined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to explain the embodiments and are not intended to limit the present invention.

[0042] In this specification, unless otherwise specified, the singular can also include the plural, and when it is stated as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. Furthermore, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0043] Such terms are used merely to distinguish a component from other components, and do not limit the nature, order, or sequence of the components. Furthermore, when a component is described as being "connected," "coupled," or "connected" to another component, it includes not only the case where the component is directly connected, coupled, or connected to the other component, but also the case where the component is "connected," "coupled," or "connected" by another component between the other component and the component.

[0044] Furthermore, when it is stated that something is formed or placed "above or below" a component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above" or "below," it can mean not only the upper direction but also the lower direction based on one component.

[0045] -Comparative Example (Conventional Structure and Its Problems)-

[0046] FIG. 1a is a cross-sectional view showing a circuit board according to a comparative example, and FIG. 1b is a scanning electron microscope photograph of the actual product of FIG. 1a.

[0047] Referring to FIG. 1 a, the circuit board of the comparative example includes an insulating layer 10 , a pad 20 , a protective layer 30 , and a connecting member 40 .

[0048] In the circuit board of the comparative example, a pad 20 is disposed on the insulating layer 10. The pad 20 is either a first pad on which a chip is mounted or a second pad to be coupled to an external substrate.

[0049] A protective layer 30 including an opening that vertically overlaps the pad 20 is disposed on the insulating layer 10. The protective layer 30 includes an opening formed corresponding to an area where the connecting member 40 is to be disposed.

[0050] The connection member 40 is disposed on the pad 20. Specifically, the connection member 40 is disposed on the pad 20 so as to vertically overlap the opening of the protection layer 30.

[0051] At this time, the contact area between the connection member 40 of the comparative example and the pad 20 corresponds to the area of the opening of the protective layer 30 .

[0052] Specifically, the contact area between the connecting member 40 and the pad 20 in the comparative example is determined by the area of the opening in the protective layer 30 that vertically overlaps the pad 20. The contact area between the connecting member 40 and the pad 20 is the same as the area of the opening in the protective layer 30 that vertically overlaps the pad 20.

[0053] Therefore, in the comparative example, the area of the opening in the protective layer 30 is increased to increase the contact area between the connection member 40 and the pad 20. However, when the area of the opening in the protective layer 30 is increased, the size of the pad 20 needs to be increased accordingly. Furthermore, when the size of the pad 20 is increased, there is a problem that the degree of circuit integration decreases.

[0054] On the other hand, in the comparative example, the size of the pad 20 is reduced to improve the circuit integration density, and the area of the opening in the protective layer 30 is correspondingly reduced.

[0055] However, if the area of the opening in the protective layer 30 is reduced, the contact area between the connection member 40 and the pad 20 is correspondingly reduced. If the contact area between the connection member 40 and the pad 20 is reduced, problems may arise with the physical or electrical reliability of the connection member 40 in the manufacturing environment or the use environment of the semiconductor package.

[0056] 1b, when the contact area between the connection member 40 and the pad 20 is reduced, cracks may occur at the interface CR between the connection member 40 and the pad 20. The cracks may cause the connection member 40 to separate from the pad 20, which may cause problems with the physical and electrical reliability of the semiconductor package.

[0057] For example, thermal stress may occur in the use or manufacturing environment of the semiconductor package, and the thermal stress may be concentrated at the interface between the connection member 40 and the pad 20. When the thermal stress is concentrated at the interface, the rate of crack occurrence at the interface may increase.

[0058] -Electronic Devices-

[0059] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various chips may be mounted in the semiconductor package.

[0060] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0061] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0062] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0063] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0064] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0065] FIG. 2a is a diagram showing a semiconductor package according to a first embodiment.

[0066] Referring to FIG. 2 a, the semiconductor package of the first embodiment includes a first substrate 100 .

[0067] The first substrate 100 may refer to a package substrate. For example, the first substrate 100 may provide a space to which at least one external substrate is coupled. For example, the first substrate 100 may provide a space to which a main board included in an electronic device is coupled.

[0068] As described below, the first substrate 100 may include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, a through electrode penetrating the at least one insulating layer, and a protective layer that protects the insulating layer and the circuit pattern layer.

[0069] The first substrate 100 may include a plurality of pads. Here, the plurality of pads may refer to parts of a circuit pattern layer disposed on the outermost layer of the first substrate 100. For example, the pads may refer to parts of a circuit pattern layer disposed on the uppermost side of the first substrate 100. For example, the pads may refer to parts of a circuit pattern layer disposed on the lowermost side of the first substrate 100. The protective layer may include openings exposing surfaces (e.g., upper or lower surfaces) of the pads.

[0070] Meanwhile, the semiconductor package may include a plurality of connecting members.

[0071] For example, the first substrate 100 may include a plurality of pads, and the plurality of connection members may be disposed on the plurality of pads, respectively.

[0072] Specifically, the first substrate 100 may include a plurality of first pads, and the semiconductor package may include a first connection member 110 disposed on the plurality of first pads.

[0073] The first substrate 100 may also include a plurality of second pads, and the semiconductor package may also include a second connection member 140 disposed on the plurality of second pads.

[0074] The first substrate 100 may also include a plurality of third pads, and the semiconductor package may also include a third connection member 160 disposed on the plurality of third pads.

[0075] In this case, the first pad may be disposed on the upper surface of the first substrate 100, and the second and third pads may be disposed on the lower surface of the first substrate 100.

[0076] Meanwhile, a semiconductor package can include multiple semiconductor devices.

[0077] For example, the semiconductor package may include a first semiconductor device 120 disposed on the first connection member 110. In this case, the first pads of the first substrate 100 may be divided into a plurality of groups. The first connection member 110 may be disposed on each of the first pads of the plurality of groups. The first semiconductor devices 120 may be mounted on each of the first pads of the plurality of groups. Therefore, a plurality of the first semiconductor devices 120 may be mounted on the upper side of the first substrate 100 at regular intervals. In this case, the first semiconductor device 120 may refer to a semiconductor device mounted on the upper side of the first substrate 100. A plurality of first semiconductor devices may be disposed on the upper side of the first substrate 100, spaced apart from each other.

[0078] The semiconductor package may also include a second semiconductor device 140 disposed below the second connecting member 140. The second semiconductor device 140 may refer to a semiconductor device mounted below the first substrate 100 among the semiconductor devices included in the semiconductor package. A plurality of second semiconductor devices may be disposed below the first substrate 100, spaced apart from one another.

[0079] In this case, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a logic chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an application processor chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an analog-to-digital converter or an application-specific IC (ASIC). For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0080] In addition, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include at least one of a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC (Multilayer Ceramic Condenser) chip, a BGA (Ball Grid Array) chip, and a chip capacitor.

[0081] The semiconductor package may also include a third connecting member 160. The third connecting member 160 may be disposed under a third pad of the first substrate 100. The third connecting member 160 may connect the first substrate 100 to a main board of an electronic device. The third connecting member 160 may have a larger diameter than the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 10 to 200 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 20 to 180 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 40 to 150 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. That is, the third connecting member 160 may be connected to a main board of an electronic device and have a diameter larger than the other connecting members so as to correspond to the width of a pad portion of the main board, and the first connecting member 110 and the second connecting member 140 may be connected to a semiconductor device and have a diameter smaller than the third connecting member 160 so as to correspond to the terminals of the semiconductor device.

[0082] The semiconductor package may include a molding layer.

[0083] For example, the semiconductor package may include a first molding layer 130 disposed on the first substrate 100. The first molding layer 130 may mold components disposed on the outermost layer of the first substrate 100. For example, the first molding layer 130 may mold a surface of a protective layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed on the uppermost side of the first substrate 100. The first molding layer 130 may also mold the first connecting member 110 and the first semiconductor element 120 disposed on the first substrate 100. In this case, the semiconductor package may further include an underfill (not shown) surrounding the periphery of the first connecting member 110 and the first semiconductor element 120. If the semiconductor package includes the underfill, the first molding layer 130 may mold the periphery of the underfill.

[0084] The semiconductor package may also include a second molding layer 170 disposed below the first substrate 100. The second molding layer 170 may mold a surface of a protective layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed on the bottom side of the first substrate 100. The second molding layer 170 may also mold a second connecting member 140 and a second semiconductor element 140 disposed below the first substrate 100. The second molding layer 170 may also mold the third connecting member 160.

[0085] In this case, the second molding layer 170 may expose at least a portion of the lower surface of the second semiconductor chip 140. For example, the lower surface of the second molding layer 170 may be positioned not lower than the lower surface of the second semiconductor chip 140. For example, the lower surface of the second molding layer 170 may be positioned on the same plane as the lower surface of the second semiconductor chip 140.

[0086] Furthermore, the second molding layer 170 may be positioned not lower than the lower surface of the third connecting member 160. For example, the lower surface of the second molding layer 170 may be flush with the lower surface of the third connecting member 160 or may be positioned higher than the lower surface of the third connecting member 160. Therefore, the lower surface of the third connecting member 160 may not be covered by the second molding layer 170. Furthermore, at least a portion of the third connecting member 160 may protrude downward from the second molding layer 170.

[0087] The first molding layer 130 and the second molding layer 170 may be, but are not limited to, EMC (Epoxy Mold Compound). The first molding layer 130 and the second molding layer 170 may have a low dielectric constant. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.8 to 5. Thus, in this embodiment, the first molding layer 130 and the second molding layer 170 have a low dielectric constant, thereby improving the heat dissipation characteristics of the heat generated in the first semiconductor element 120 and the second semiconductor element 140.

[0088] The semiconductor package of the first embodiment may have a double-sided molding structure as described above, that is, the semiconductor package of the first embodiment may have a structure in which at least one first semiconductor device 120 and at least one second semiconductor device 140 are mounted on the upper and lower sides of the first substrate 100, respectively.

[0089] FIG. 2b is a diagram showing a semiconductor package according to a second embodiment.

[0090] Referring to FIG. 2b, the semiconductor package according to the second embodiment may differ from the semiconductor package according to the first embodiment of FIG. 2a in that it has a one-side molding structure.

[0091] For example, the semiconductor package of the second embodiment may include a first substrate 100 , a first connecting member 110 , a first semiconductor element 120 , a first molding layer 130 , and a third connecting member 160 .

[0092] The semiconductor package of the second embodiment may have a structure in which a semiconductor element is mounted only on the upper side of the first substrate 100. Thus, the molding layer of the semiconductor package of the second embodiment may be disposed only on the upper side of the first substrate 100.

[0093] FIG. 2c is a diagram showing a semiconductor package according to a third embodiment.

[0094] Referring to FIG. 2c, the semiconductor package according to the third embodiment is different from the semiconductor package according to the second embodiment of FIG. 2b in that it further includes an additional package.

[0095] The semiconductor package of the third embodiment may further include a fourth pad disposed on the upper side of the first substrate 100. That is, a circuit pattern layer is disposed on the upper surface of the first substrate 100. A portion of the circuit pattern layer may function as a first pad on which the first semiconductor element 120 is mounted, and another portion may function as a fourth pad.

[0096] The semiconductor package of the third embodiment may further include a fourth connection member 180 disposed on the fourth pad.

[0097] The top surface of the fourth connection member 180 may not be covered by the first molding layer 130 .

[0098] The semiconductor package of the third embodiment may include a second substrate 200 disposed on the fourth connection member 180. The second substrate 200 may be, but is not limited to, a memory substrate.

[0099] The semiconductor package of the third embodiment may include a third semiconductor device 210 mounted on the second substrate 200. The third substrate 210 may be, but is not limited to, a memory substrate.

[0100] In addition, the semiconductor package of the third embodiment may further include a connecting member 220 connecting the second substrate 200 and the third semiconductor device 210. That is, the semiconductor package of the third embodiment of FIG. 2c may have a package-on-package structure.

[0101] FIG. 2d is a diagram showing a semiconductor package according to a fourth embodiment.

[0102] Referring to FIG. 2d, the semiconductor package of the fourth embodiment differs from the semiconductor package of the third embodiment of FIG. 2c in that the first semiconductor element 120 includes multiple logic chips and an additional third substrate 190 is disposed on the first substrate 100.

[0103] For example, a plurality of logic chips may be arranged on the first substrate 100. For example, a plurality of logic chips of the same type may be arranged on the first substrate 100, or alternatively, a plurality of logic chips of different types may be arranged on the first substrate 100.

[0104] In this case, a connecting member for connecting the plurality of first semiconductor chips 120 may be disposed on the first substrate 100. The connecting member may refer to the third substrate 190.

[0105] The third substrate 190 may be a bridge substrate. The third substrate 190 may include a redistribution layer. The third substrate 190 is disposed on the first substrate 100. The third substrate 190 may electrically connect a plurality of first semiconductor devices 120 corresponding to a plurality of logic chips. Although the third substrate 190 is embedded in the first substrate 100 in the drawings, the present invention is not limited thereto. For example, the third substrate 190 may be disposed on the first substrate 100.

[0106] The third substrate 190 may be a silicon bridge substrate, or alternatively, the third substrate 190 may be an organic bridge substrate including an organic material.

[0107] FIG. 2e is a diagram showing a semiconductor package according to a fifth embodiment.

[0108] Referring to FIG. 2e, the semiconductor package according to the fifth embodiment differs from the semiconductor packages of the previous embodiments in that a fourth substrate 300 is disposed between the first substrate and the first semiconductor element.

[0109] The semiconductor package according to the fifth embodiment may include a fourth substrate 300 disposed on the first substrate 100 .

[0110] To this end, a first connection member 110 for connecting the first substrate 100 and the fourth substrate 300 may be disposed on the first substrate 100 .

[0111] The semiconductor package according to the fifth embodiment may also include a fifth connecting member 320 disposed on the fourth substrate 300. The semiconductor package according to the fifth embodiment may also include a semiconductor element 320 disposed on the fifth connecting member 320. The semiconductor element 320 may be one or, alternatively, may be configured to include a plurality of semiconductor elements 320.

[0112] Meanwhile, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may function to connect the first substrate 100 and the semiconductor device 320. In addition, the fourth substrate 300 may function to connect a plurality of semiconductor devices 320 to each other.

[0113] In this case, the fourth substrate 300 can be regarded as an interposer connecting the first substrate 100 and the semiconductor device 320 .

[0114] In one embodiment, the fourth substrate 300 may be an active interposer that functions as a semiconductor device. When the fourth substrate 300 functions as a semiconductor device, the package of the fifth embodiment may have a vertically stacked structure on the first substrate 100 and have multiple logic chips mounted thereon. A first logic chip among the logic chips that corresponds to the active interposer may perform a signal transmission function between the first substrate 100 and a second logic chip disposed thereon while performing the function of the logic chip.

[0115] According to another embodiment, the fourth substrate 300 may be a passive interposer. For example, the fourth substrate 300 may perform a signal relay function between the semiconductor device 320 and the first substrate 100. For example, the number of terminals on the semiconductor device 320 is gradually increasing due to factors such as 5G, Internet of Things (IoT), improved image quality, and increased communication speed. That is, as the number of terminals on the semiconductor device 320 increases, the width of the terminals and the spacing between the terminals are reduced. In this case, the first substrate 100 is connected to a main board of an electronic device. Therefore, in order for the pads on the first substrate 100 to have the width and spacing required for connection to the semiconductor device 320 and the main board, respectively, the thickness of the first substrate 100 increases or the layer structure of the first substrate 100 becomes complex. Therefore, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may include pads having fine widths and intervals corresponding to the terminals of the semiconductor devices 320 .

[0116] FIG. 2f is a diagram showing a semiconductor package according to a sixth embodiment.

[0117] Referring to FIG. 2F, the semiconductor package according to the sixth embodiment is different from the semiconductor package according to the fifth embodiment in that a fifth substrate 330 is further disposed on the fourth substrate 300.

[0118] The semiconductor devices 320 may be arranged on the fourth substrate 300 and spaced apart from one another in the horizontal direction. The semiconductor devices 320 may be active devices of the same type or different types. Exemplarily, the semiconductor devices 320 may represent AP chips of different types. Furthermore, one of the semiconductor devices 320 may be an AP chip and the other may be a memory chip.

[0119] The semiconductor package of the sixth embodiment further includes a fifth substrate 330. The fifth substrate 330 may be embedded in the fourth substrate 300, but is not limited to this. For example, the fifth substrate 330 may be disposed on the fourth substrate 300 and function to connect the semiconductor devices 320 together.

[0120] The fifth substrate 330 may include a redistribution layer. For example, the fifth substrate 330 may be a bridge. The fifth substrate 330 may include a silicon bridge. Alternatively, the fifth substrate 330 may be an organic bridge including an organic material.

[0121] On the other hand, each of the semiconductor packages of the first to sixth embodiments includes a connecting member as described above.

[0122] In this case, the connection member may be a member that electrically connects a plurality of components using at least one bonding method selected from the group consisting of wire bonding, solder bonding, and direct intermetal bonding.

[0123] In other words, since the connecting member has the function of electrically connecting multiple components, when using metal-to-metal direct bonding, the semiconductor package can be understood as the electrically connected part, rather than the solder or wire.

[0124] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using materials such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a connecting member connecting a substrate and a semiconductor device. In this case, the connecting member in the direct bonding method may refer to a metal layer formed between the multiple components by the recrystallization.

[0125] The circuit board of the embodiment will be described below.

[0126] Before describing the circuit board of the embodiment, the circuit board described below may refer to any one of the substrates included in the semiconductor package.

[0127] For example, the circuit board described below may refer to the first substrate 100 included in the semiconductor package of Figures 2a to 2c. When the circuit board refers to the first substrate 100, the pad described below may refer to any one of the first pad on which the first connecting member 110 is disposed, the second pad on which the second connecting member 140 is disposed, and the third pad on which the third connecting member 160 is disposed.

[0128] Furthermore, the circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2d, or alternatively, may refer to the second substrate 200, or alternatively, may refer to the third substrate 190.

[0129] Furthermore, the circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2e, or alternatively, may refer to the fourth substrate 300.

[0130] Furthermore, the circuit board described below may refer to the first substrate 100 included in the semiconductor package of FIG. 2f, or may alternatively refer to the fourth substrate 300, or may alternatively refer to the fifth substrate 330.

[0131] That is, the circuit board of the embodiment is characterized by the structure of the pad on which the connection member is disposed. In one embodiment, the pad on which the connection member is disposed may be a pad connected to a semiconductor device. In another embodiment, the pad on which the connection member is disposed may be a pad connected to a main board of an electronic device. In yet another embodiment, the pad on which the connection member is disposed may refer to a pad connected to the fourth substrate 300. In yet another embodiment, the pad on which the connection member is disposed may refer to a pad connected to the fifth substrate 330.

[0132] In summary, the pads of the circuit board described below may refer to any one or more of the pads included in the first substrate 100. Differently, the pads of the circuit board described below may refer to any one or more of the pads included in the second substrate 200. Differently, the pads of the circuit board described below may refer to any one or more of the pads included in the third substrate 190. Differently, the pads of the circuit board described below may refer to any one or more of the pads included in the fourth substrate 300. Differently, the pads of the circuit board described below may refer to any one or more of the pads included in the fifth substrate 330.

[0133] In the following description, the circuit board of the embodiment is the first substrate 100 of the semiconductor package of the third embodiment shown in FIG. 2c.

[0134] Thus, as an example, the pad described below may refer to a first pad connected to a first semiconductor element 120, and the connecting member described below may refer to a first connecting member 110 connecting the first semiconductor element 120 and the first pad.

[0135] As another example, the pad described below may refer to a second pad connected to the second substrate 200, and the connecting member described below may refer to a fourth connecting member 180 connecting between the second substrate 200 and the second pad.

[0136] As another example, the pad described below may refer to a third pad connected to a main board of an electronic device, and the connecting member described below may refer to a third connecting member 160 connecting the main board and the third pad.

[0137] FIG. 3 is a cross-sectional view showing a circuit board according to an embodiment.

[0138] Referring to FIG. 3, a circuit board 400 includes an insulating layer 410 .

[0139] The insulating layer 410 may have one or more layers, and preferably has a multi-layer structure.

[0140] Although the insulating layer 410 of the circuit board 400 is shown in the drawings as having a single layer structure, the present invention is not limited thereto. For example, the insulating layer 410 may have a structure in which multiple layers are stacked vertically. Preferably, the circuit board 400 may have a multi-layer structure of at least two layers.

[0141] For the sake of convenience, the following description will be given assuming that the insulating layer of the circuit board 400 is composed of a single layer.

[0142] The insulating layer 410 can be rigid or flexible.

[0143] For example, the insulating layer 410 may include a prepreg, for example, a prepreg in which glass fibers are impregnated in a resin, and the resin may be, but is not limited to, an epoxy resin.

[0144] The insulating layer 410 may also include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the insulating layer 410 may include reinforced or ductile plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 410 may include sapphire. For example, the insulating layer 410 may include an optically isotropic film. For example, the insulating layer 410 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 410 may be formed of a material containing an inorganic filler and an insulating resin. For example, the insulating layer 410 may have a structure in which inorganic fillers such as silica or alumina are disposed in a thermosetting resin or a thermoplastic resin. For example, the insulating layer 410 may be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imagable Dielectric resin (PID), BT, etc. For example, the insulating layer 410 may include Resin Coated Copper (RCC).

[0145] The insulating layer 410 may have a thickness in the range of 10 μm to 60 μm. For example, when the insulating layer 410 includes multiple layers, the thickness of each of the multiple layers may be in the range of 10 μm to 60 μm. Preferably, the insulating layer 410 may have a thickness in the range of 15 μm to 55 μm. More preferably, the insulating layer 410 may have a thickness in the range of 18 μm to 52 μm.

[0146] The thickness of the insulating layer 410 may refer to the vertical distance between a plurality of circuit pattern layers disposed adjacent to each other in the thickness direction. For example, the thickness of the insulating layer 410 may refer to the vertical distance between the first circuit pattern layer 420 and the second circuit pattern layer 430. For example, the thickness of the insulating layer 410 may refer to the vertical distance between the lower surface of the first circuit pattern layer 420 and the upper surface of the second circuit pattern layer 430.

[0147] If the thickness of the insulating layer 410 is less than 10 μm, the warpage characteristics of the circuit board 400 may be reduced. For example, if the thickness of the insulating layer 410 is less than 10 μm, the first circuit pattern layer 420 and the second circuit pattern layer 430 disposed on the surface of the insulating layer 410 may not be stably protected, which may result in problems with electrical reliability and / or physical reliability. Furthermore, if the thickness of the insulating layer 410 is less than 10 μm, the processability of forming the first circuit pattern layer 420 or the second circuit pattern layer 430 on the insulating layer 410 may be reduced.

[0148] Furthermore, if the thickness of the insulating layer 410 exceeds 60 μm, the overall thickness of the circuit board 400 increases, which may result in an increase in the thickness of the semiconductor package. Furthermore, if the thickness of the insulating layer 410 exceeds 60 μm, it may be difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 430. For example, if the thickness of the insulating layer 410 exceeds 60 μm, it may be difficult to form the width of the first circuit pattern layer and / or the second circuit pattern layer 430 and the spacing between adjacent patterns to 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. Furthermore, if it is difficult to miniaturize the first circuit pattern layer and / or the second circuit pattern layer 430, the degree of circuit integration may decrease, which may increase the signal transmission distance and signal transmission loss.

[0149] Meanwhile, when the circuit board 400 of the embodiment has a multi-layer structure, at least one of the plurality of insulating layers may contain an insulating material different from at least one of the other insulating layers. For example, when the circuit board 400 includes a plurality of insulating layers, at least one insulating layer may be an insulating layer containing reinforcing fibers, and at least one other insulating layer may be an insulating layer not containing reinforcing fibers. The insulating layer containing reinforcing fibers may be a core layer. Thus, the circuit board 400 may be a core substrate including a core layer, but is not limited thereto.

[0150] In addition, when the circuit board 400 is a core board, the thickness of the insulating layer 410 may refer to the thickness of the insulating layer excluding the reinforcing fibers.

[0151] The circuit board 400 includes a circuit pattern layer disposed on an insulating layer 410 .

[0152] For example, the circuit board 400 includes a first circuit pattern layer 420 disposed on the upper surface of the insulating layer 410. The circuit board 400 also includes a second circuit pattern layer 430 disposed on the lower surface of the insulating layer 410.

[0153] The first circuit pattern layer 420 may be divided into a plurality of circuit patterns according to their positions or functions. For example, the first circuit pattern layer 420 may include at least one pad. For example, the first circuit pattern layer 420 may include a pad on which a semiconductor device is mounted. For example, the first circuit pattern layer 420 may include a pad to which an external substrate is bonded. For example, the first circuit pattern layer 420 may include a pad to be coupled to an interposer. For another example, the first circuit pattern layer 420 may include a pad to be coupled to a bridge substrate. For still another example, the first circuit pattern layer 420 may include a pad to be coupled to a memory substrate including a memory chip.

[0154] The first circuit pattern layer 420 may refer to a first outermost circuit pattern layer of the circuit board 400. Specifically, when the circuit board 400 has a multi-layer structure including a plurality of insulating layers, the first circuit pattern layer 420 may refer to a circuit pattern layer disposed on an uppermost insulating layer among the plurality of insulating layers.

[0155] The first circuit pattern layer 420 may include multiple metal layers. For example, the first circuit pattern layer 420 may include a first metal layer disposed on the upper surface of the insulating layer 410 and a second metal layer disposed on the first metal layer. The first metal layer of the first circuit pattern layer 420 may serve as a seed layer for electrolytic plating of the second metal layer of the first circuit pattern layer 420. The thickness of the first metal layer of the first circuit pattern layer 420 may be in the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer of the first circuit pattern layer 420 may be in the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer of the first circuit pattern layer 420 may be in the range of 0.5 μm to 2.5 μm.

[0156] If the thickness of the first metal layer of the first circuit pattern layer 420 is less than 0.2 μm, the first metal layer of the first circuit pattern layer 420 may not function as a seed layer. If the thickness of the first metal layer of the first circuit pattern layer 420 is less than 0.2 μm, it may be difficult to form a first metal layer with a uniform thickness on the upper surface of the insulating layer 410.

[0157] If the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the process time for forming the first metal layer of the first circuit pattern layer 420 may increase, resulting in a reduced yield. Furthermore, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the etching time for the first metal layer in the process of forming the first circuit pattern layer 420 may increase. Furthermore, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, deformation of the second metal layer of the first circuit pattern layer 420 may occur during etching of the first metal layer of the first circuit pattern layer 420. Here, deformation of the second metal layer of the first circuit pattern layer 420 may mean an increase in the difference between the width of the top surface and the width of the bottom surface of the second metal layer because the sides of the second metal layer are also etched during etching of the first metal layer. For example, deformation of the second metal layer of the first circuit pattern layer 420 may mean a change in the vertical cross-sectional shape of the second metal layer from a rectangular shape to a trapezoidal shape.

[0158] Furthermore, if the thickness of the first metal layer of the first circuit pattern layer 420 exceeds 3.0 μm, the etching depth of the first metal layer increases, thereby increasing the depth of recesses (e.g., undercuts) formed on the sides of the first metal layer and the second metal layer. For example, if the etching depth of the first metal layer increases, the difference between the width of the first metal layer and the width of the second metal layer may increase. If the difference between the width of the first metal layer and the width of the second metal layer increases, signal transmission loss may increase, resulting in degradation of electrical characteristics. Furthermore, if the difference between the width of the first metal layer and the width of the second metal layer increases, dendrites may form due to electromigration, which may degrade the electrical and / or physical characteristics of the first circuit pattern layer 420.

[0159] The second metal layer of the first circuit pattern layer 420 may be an electroplated layer formed by electroplating using the first metal layer as a seed layer. The second metal layer of the first circuit pattern layer 420 may be formed to a certain thickness on the first metal layer. The second metal layer of the first circuit pattern layer 420 may include, but is not limited to, the same metal as the first metal layer of the first circuit pattern layer 420. For example, the first and second metal layers of the first circuit pattern layer 420 may each include copper.

[0160] The thickness of the second metal layer of the first circuit pattern layer 420 may be greater than the thickness of the first metal layer of the first circuit pattern layer 420 .

[0161] The thickness of the second metal layer of the first circuit pattern layer 420 may be in the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be in the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer of the first circuit pattern layer 420 may be in the range of 4.5 μm to 22 μm.

[0162] If the thickness of the second metal layer of the first circuit pattern layer 420 is less than 3.5 μm, the etching of the second metal layer may be performed simultaneously with the etching of the first metal layer. If the thickness of the second metal layer of the first circuit pattern layer 420 is less than 3.5 μm, the allowable current of signals transmitted through the first circuit pattern layer may decrease, resulting in degraded electrical characteristics. If the thickness of the second metal layer of the first circuit pattern layer 420 is more than 25 μm, it may be difficult to miniaturize the first circuit pattern layer 420. For example, if the thickness of the second metal layer of the first circuit pattern layer 420 is more than 25 μm, the width and spacing of the patterns constituting the first circuit pattern layer 420 may not meet the required conditions. This may result in a reduced circuit integration level or an increased volume of the circuit board and semiconductor package.

[0163] The circuit board 400 of the embodiment may include a second circuit pattern layer 430 disposed on the lower surface of the insulating layer 410. The second circuit pattern layer 430 may have a structure corresponding to that of the first circuit pattern layer 420. The second circuit pattern layer 430 may include at least one pad. For example, the second circuit pattern layer 430 may include a pad on which a semiconductor device is mounted. For example, the second circuit pattern layer 430 may include a pad to which an external board is coupled. For example, the second circuit pattern layer 430 may include a pad to which a main board of an electronic device is coupled.

[0164] The second circuit pattern layer 430 may refer to a second outermost circuit pattern layer of the circuit board 400. For example, if the circuit board 400 has a multi-layer structure including a plurality of insulating layers, the second circuit pattern layer 430 may refer to a circuit pattern layer disposed on the lower surface of the lowermost insulating layer among the plurality of insulating layers.

[0165] Each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may include a recess.

[0166] For example, the first circuit pattern layer 420 may include a first recess 420-1.

[0167] Specifically, the first circuit pattern layer 420 includes pads and traces connected to the pads. The pads of the first circuit pattern layer 420 include a first recess 420-1. The first recess 420-1 may be recessed from an upper surface of the pad of the first circuit pattern layer 420 toward a lower surface of the pad of the first circuit pattern layer 420.

[0168] The first recess 420-1 may refer to a concave portion formed on the upper surface of the pad of the first circuit pattern layer 420.

[0169] The first recesses 420-1 may have different depths in the horizontal direction. For example, the bottom surface of the first recess 420-1 may have an uneven shape. Therefore, the top surface of the pad of the first circuit pattern layer 420 may have an uneven shape corresponding to the bottom surface of the first recess 420-1.

[0170] In this case, the first recess 420-1 may be provided on the entire upper surface of the pad of the first circuit pattern layer 420, or alternatively, may be provided on a portion of the upper surface of the pad of the first circuit pattern layer 420.

[0171] At least a portion of the first recess 420-1 vertically overlaps the first protective layer 450 disposed on the insulating layer 410. Thus, at least a portion of an upper surface of the pad of the first circuit pattern layer 420 may vertically overlap the first protective layer 450 and not contact the first protective layer 450. For example, a crevice corresponding to the first recess 420-1 may be provided between the upper surface of the pad of the first circuit pattern layer 420 and the lower surface of the first protective layer 450.

[0172] Meanwhile, the first circuit pattern layer 420 includes patterns other than pads. In this case, the pads of the first circuit pattern layer 420 may refer to patterns of the first circuit pattern layer 420 that vertically overlap with openings 440-1 of the first protective layer 450, which will be described later. For example, the pads of the first circuit pattern layer 420 may refer to patterns of the first circuit pattern layer 420 that include an area that vertically overlaps with openings 440-1 of the first protective layer 450.

[0173] The patterns other than the pads of the first circuit pattern layer 420 may refer to patterns of the first circuit pattern layer 420 that do not vertically overlap the openings 440-1 of the first protective layer 450. For example, the top surfaces of the patterns other than the pads of the first circuit pattern layer 420 may be entirely covered by the first protective layer 450. The patterns other than the pads of the first circuit pattern layer 420 may include traces.

[0174] The first recess may not be formed on the upper surface of the trace of the first circuit pattern layer 420. That is, the first recess 420-1 may be formed by processing a portion of the first circuit pattern layer 420 exposed through the opening 440-1 of the first protective layer 450 while the first protective layer 450 is formed. In this case, the trace of the first circuit pattern layer 420 is not exposed through the opening 440-1 of the first protective layer 450. That is, the trace of the first circuit pattern layer 420 may be entirely covered by the first protective layer 450. Therefore, the first recess may not be formed on the upper surface of the trace of the first circuit pattern layer 420.

[0175] Therefore, the first circuit pattern layer 420 may include patterns having different heights. For example, at least a portion of the top surface of the pads of the first circuit pattern layer 420 may be located lower than the top surface of the traces of the first circuit pattern layer 420. For example, the top surface of the pads of the first circuit pattern layer 420 having the first recess 420-1 may be located lower than the top surface of the traces of the first circuit pattern layer 420 without the first recess. For example, the top surface of the pads of the first circuit pattern layer 420 may be located lower than the top surface of the traces of the first circuit pattern layer 420 by the depth of the first recess 420-1.

[0176] Additionally, the second circuit pattern layer 430 may include a second recess 430-1.

[0177] Specifically, the second circuit pattern layer 430 includes a pad and a trace connected to the pad. The pad of the second circuit pattern layer 430 includes a second recess 430-1. The second recess 430-1 may be formed in a convex shape extending from a lower surface of the pad of the second circuit pattern layer 430 toward an upper surface of the pad of the second circuit pattern layer 430.

[0178] The second recess 430-1 may refer to a protrusion formed on the lower surface of the pad of the second circuit pattern layer 430.

[0179] The second recesses 430-1 may have different depths in the horizontal direction. For example, the bottom surface of the second recess 430-1 may have an uneven shape. Therefore, the lower surface of the pad of the second circuit pattern layer 430 may have an uneven shape corresponding to the bottom surface of the second recess 430-1.

[0180] In this case, the second recess 430-1 may be provided on the entire lower surface of the pad of the second circuit pattern layer 430, or alternatively, may be provided on a part of the lower surface of the pad of the second circuit pattern layer 430.

[0181] At least a portion of the second recess 430-1 vertically overlaps the second protective layer 460 disposed under the insulating layer 410. Thus, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 vertically overlaps the second protective layer 460 and may not be in contact with the second protective layer 460. For example, a crevice corresponding to the second recess 430-1 may be provided between the lower surface of the pad of the second circuit pattern layer 430 and the upper surface of the second protective layer 460.

[0182] Meanwhile, the second circuit pattern layer 430 includes patterns other than pads. In this case, the pads of the second circuit pattern layer 430 may refer to patterns of the second circuit pattern layer 430 that vertically overlap with openings 460-1 of the second protective layer 460, which will be described later. For example, the pads of the second circuit pattern layer 430 may refer to patterns including an area of the second circuit pattern layer 430 that vertically overlaps with openings 460-1 of the second protective layer 460.

[0183] The patterns other than the pads of the second circuit pattern layer 430 may refer to patterns of the second circuit pattern layer 430 that do not vertically overlap the openings 460-1 of the second protective layer 460. For example, the lower surfaces of the patterns other than the pads of the second circuit pattern layer 430 may be entirely covered by the second protective layer 460. In addition, the patterns other than the pads of the second circuit pattern layer 430 may include traces.

[0184] The second recess may not be formed on the lower surface of the trace of the second circuit pattern layer 430. That is, the second recess 430-1 may be formed by processing a portion of the second circuit pattern layer 430 exposed through the opening of the second protective layer 460 while the second protective layer 460 is still formed. In this case, the trace of the second circuit pattern layer 430 is not exposed through the opening 460-1 of the second protective layer 460. That is, the trace of the second circuit pattern layer 430 may be entirely covered by the second protective layer 460. Therefore, the second recess may not be formed on the lower surface of the trace of the second circuit pattern layer 430.

[0185] Therefore, the second circuit pattern layer 430 may include patterns having different heights. For example, at least a portion of the lower surface of the pad of the second circuit pattern layer 430 may be located higher than the lower surface of the trace of the second circuit pattern layer 430. For example, the lower surface of the pad of the second circuit pattern layer 430 having the second recess 430-1 may be located higher than the lower surface of the trace of the second circuit pattern layer 430 without the second recess. For example, the lower surface of the pad of the second circuit pattern layer 430 may be located lower than the lower surface of the trace of the second circuit pattern layer 430 by the depth of the second recess 430-1.

[0186] The recesses formed in the pads of the first circuit pattern layer 420 and the second circuit pattern layer 430 will be described in further detail below.

[0187] The circuit board 400 of the embodiment may include a through electrode 440. The through electrode 440 may penetrate the insulating layer 410. Preferably, the through electrode 440 may penetrate the insulating layer 410 to electrically connect the first circuit pattern layer 420 and the second circuit pattern layer 430. In this case, when the circuit board 400 has a multi-layer structure, the through electrode 440 may be spaced apart in the vertical direction and electrically connect adjacent circuit pattern layers.

[0188] The through electrode 440 may be formed by filling a through hole penetrating the insulating layer 410 with a conductive material.

[0189] The through-holes may be formed by any one of mechanical, laser, and chemical processing. When the through-holes are formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through-holes are formed by laser processing, UV or CO2 laser methods may be used. When the through-holes are formed by chemical processing, chemicals including aminosilanes, ketones, etc. may be used.

[0190] The through electrode 440 includes a plurality of metal layers.

[0191] The through electrode 440 may include a first metal layer and a second metal layer corresponding to the first circuit pattern layer 420 and the second circuit pattern layer 430 .

[0192] Meanwhile, in the above description, the first circuit pattern layer 420 and the second circuit pattern layer 430 of the embodiment are manufactured by the SAP process, and therefore are described as including the first metal layer and the second metal layer, but are not limited thereto.

[0193] For example, the first circuit pattern layer 420 and the second circuit pattern layer 430 may be manufactured by an MSAP process. Therefore, each of the first circuit pattern layer 420 and the second circuit pattern layer 430 may further include a third metal layer disposed between the first metal layer and the insulating layer. The third metal layer may refer to, but is not limited to, a copper foil layer that was attached during lamination of the insulating layer.

[0194] Meanwhile, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may include a conductive material. For example, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, each of the first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0195] The first circuit pattern layer 420, the second circuit pattern layer 430, and the through electrode 440 can be formed using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0196] Meanwhile, the circuit board 400 of the embodiment may include a protective layer.

[0197] For example, the circuit board 400 may include a first protective layer 450 disposed on the insulating layer 410. For example, the circuit board 400 may include a second protective layer 460 disposed below the insulating layer 410.

[0198] The first protective layer 450 and the second protective layer 460 may be resist layers. Preferably, the first protective layer 450 and the second protective layer 460 may be solder resist layers including an organic polymer material. For example, the first protective layer 450 and the second protective layer 460 may include an epoxy acrylate resin. More specifically, the first protective layer 450 and the second protective layer 460 may include a resin, a hardener, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0199] The total thickness of each of the first protective layer 450 and the second protective layer 460 may be greater than the thickness of each of the first circuit pattern layer 420 and the second circuit pattern layer 430. The total thickness may refer to the vertical distance between the lower surface and the upper surface of the first protective layer 450 and the second protective layer 460.

[0200] The total thickness of the first protective layer 450 may be in the range of 6.7 μm to 35.0 μm. Preferably, the total thickness of the first protective layer 450 may be in the range of 7.3 μm to 32 μm. More preferably, the total thickness of the first protective layer 450 may be in the range of 8.0 μm to 30 μm.

[0201] If the total thickness of the first protective layer 450 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase, and if the total thickness of the first protective layer 450 is less than 6.7 μm, the first circuit pattern layer may not be stably protected, which may result in a decrease in electrical or physical reliability.

[0202] In addition, the second protective layer 460 may have a thickness corresponding to the thickness of the first protective layer 450, but is not limited thereto.

[0203] The first protective layer 450 and the second protective layer 460 may each include an opening.

[0204] For example, the first protective layer 450 may include a first opening 450-1. The first opening 450-1 may vertically overlap at least a portion of the first circuit pattern layer 420. Thus, the first opening 450-1 of the first protective layer 450 may expose at least a portion of the upper surface of the first circuit pattern layer 420. Preferably, the first protective layer 450 may include a first opening 450-1 vertically overlapping a pad of the first circuit pattern layer 420. In this case, the width of the first opening 450-1 may be smaller than the width of the pad of the first circuit pattern layer 420. Therefore, at least a portion of the pad of the first circuit pattern layer 420 may vertically overlap the first opening 450-1 of the first protective layer 450, and the remaining portion may not vertically overlap the first opening 450-1 of the first protective layer 450.

[0205] At least a portion of the first protective layer 450 may vertically overlap the pads of the first circuit pattern layer 420 and not contact the pads of the first circuit pattern layer 420. For example, the first protective layer 450 may include an overlapping region that vertically overlaps the pads of the first circuit pattern layer 420. At least a portion of a lower surface of the overlapping region of the first protective layer 450 may not contact the pads of the first circuit pattern layer 420. For example, at least a portion of a lower surface of the overlapping region of the first protective layer 450 may vertically overlap a first recess 420-1 formed in an upper surface of the pad of the first circuit pattern layer 420. Therefore, a crevice may be formed between at least a portion of the lower surface of the overlapping region of the first protective layer 450 and an upper surface of the pad of the first circuit pattern layer 420.

[0206] The second protective layer 460 may also include a second opening 460-1. The second opening 460-1 may vertically overlap at least a portion of the second circuit pattern layer 430. Through this, the second opening 460-1 of the second protective layer 460 may expose at least a portion of the lower surface of the second circuit pattern layer 430. Preferably, the second protective layer 460 may include a second opening 460-1 vertically overlapping a pad of the second circuit pattern layer 430. The width of the second opening 460-1 may be smaller than the width of the pad of the second circuit pattern layer 430. Therefore, at least a portion of the pad of the first circuit pattern layer 430 may vertically overlap the second opening 460-1 of the second protective layer 460, and the remaining portion may not vertically overlap the second opening 460-1 of the second protective layer 460.

[0207] At least a portion of the second protective layer 460 may vertically overlap the pads of the second circuit pattern layer 430 and not contact the pads of the second circuit pattern layer 430. For example, the second protective layer 460 may include an overlapping region that vertically overlaps the pads of the second circuit pattern layer 430. At least a portion of an upper surface of the overlapping region of the second protective layer 460 may not contact the pads of the second circuit pattern layer 430. For example, at least a portion of an upper surface of the overlapping region of the second protective layer 460 may vertically overlap a second recess 430-1 formed in a lower surface of the pad of the second circuit pattern layer 430. Therefore, a crevice may be formed between at least a portion of the upper surface of the overlapping region of the second protective layer 460 and the lower surface of the pad of the second circuit pattern layer 430.

[0208] 4a is an enlarged cross-sectional view of a portion of the circuit board according to the first embodiment, FIG. 4b is a plan view of the circuit board of FIG. 4a, and FIG. 4c is a cross-sectional view showing the state in which a connecting member is arranged on the circuit board of FIG. 4a.

[0209] Hereinafter, the pads provided on the circuit board of the first embodiment, the recesses formed in the pads, and the protective layer including the openings will be described in detail with reference to FIGS. 4a to 4c.

[0210] The pads described below may refer to the pads of the first circuit pattern layer 420, or may refer to the pads of the second circuit pattern layer 430. However, for the sake of convenience, the pads will be denoted by the same reference numerals as those of the first circuit pattern layer 420.

[0211] The circuit board of the first embodiment includes an insulating layer 410 and a pad 420 disposed on the insulating layer 410. The pad 420 may refer to a pad of either the first circuit pattern layer or the second circuit pattern layer.

[0212] The pad 420 is disposed on the insulating layer 410. The upper surface of the pad 420 may have a step.

[0213] For example, the pad 420 may have a recess 420-1 formed from the upper surface of the pad 420 toward the lower surface of the pad 420. The recess 420-1 may also be referred to as a recessed portion formed from the upper surface of the pad 420 toward the lower surface.

[0214] The recess 420-1 may be provided in a portion of the upper surface of the pad 420. For example, the pad 420 may include a first portion P1 including the recess 420-1 and a second portion P2 not including the recess 420-1.

[0215] An upper surface of the first portion P1 of the pad 420 may be positioned lower than an upper surface of the second portion P2 of the pad 420. For example, the upper surface of the first portion P1 of the pad 420 may be positioned lower than an upper surface of the second portion P2 of the pad 420 by a depth corresponding to the recess 420-1.

[0216] The pad 420 may have a first thickness T1. Here, the first thickness T1 may refer to the thickness of a portion of the pad 420 that has the maximum thickness. For example, the first thickness T1 of the pad 420 may refer to the thickness of the second portion P2 of the pad 420. For example, the first thickness T1 of the pad 420 may refer to the sum of the thickness of the first portion P1 of the pad 420 and the depth of the recess 420-1.

[0217] The first thickness T1 of the pad 420 may be in the range of 3.7 μm to 28 μm. For example, the first thickness T1 of the pad 420 may be in the range of 4.3 μm to 25.8 μm. For example, the first thickness T1 of the pad 420 may be in the range of 5 μm to 24.5 μm. Preferably, the first thickness T1 of the pad 420 may refer to the sum of the thicknesses of the first metal layer and the second metal layer of the first circuit pattern layer 420. If the first thickness T1 of the pad 420 is outside the above range, the above-mentioned problems may occur.

[0218] In this case, the recess 420-1 may be formed on the top surface of the first portion P1 of the pad 420 to have a certain depth.

[0219] The recess 420-1 may have a first depth T2. The first depth T2 may refer to a difference between the thickness of the first portion P1 and the thickness of the second portion P2 of the pad 420. In this case, the first portion P1 of the pad 420 has an uneven shape. As a result, the first portion P1 of the pad 420 has different thicknesses or heights in the horizontal direction. As a result, the thickness of the first portion P1 of the pad 420 may refer to the thickness of a region having the smallest thickness among the entire region of the first portion P1. Alternatively, the thickness of the first portion P1 of the pad 420 may refer to an average thickness of the entire region of the first portion P1.

[0220] Furthermore, the first depth T2 of the recess 420-1 and the difference value may refer to the vertical separation distance from the lower surface of a first region R1 of the protective layer 450 (described below) to the upper surface of the first portion P1 of the pad 420. The vertical separation distance may refer to the maximum vertical separation distance. For example, the vertical separation distance may refer to the vertical distance from the upper surface of the first portion P1 of the pad 420, which has the lowest height, to the lower surface of the first region R1 of the protective layer 450. However, embodiments are not limited thereto, and the vertical separation distance may refer to an average separation distance.

[0221] Therefore, the first depth T2 of the recess 420-1 may have the same meaning as the difference in thickness between the first portion P1 and the second portion P2 of the pad 420 and the vertical separation distance.

[0222] The first depth T2 may be in the range of 5% to 55% of the first thickness T1. Preferably, the first depth T2 may be in the range of 7% to 52% of the first thickness T1. More preferably, the first depth T2 may be in the range of 8% to 50% of the first thickness T1.

[0223] If the first depth T2 is less than 5% of the first thickness T1, the effect of the recess 420-1 may be insufficient. That is, the recess 420-1 is provided to improve the bonding strength and adhesion between the connection member 500 and the pad 420. In this case, if the first depth T2 is less than 5% of the first thickness T1, the effect of improving the bonding strength or adhesion may be insufficient. This may cause physical and / or electrical reliability problems, such as cracks occurring in the connection member 500 or separation of the connection member 500 from the pad 420.

[0224] If the first depth T2 exceeds 55% of the first thickness T1, the amount of the connecting member 500 filling the recess 420-1 may increase. Furthermore, if the amount of the connecting member 500 increases, the rigidity of the connecting member 500 may decrease, which may result in cracks. Furthermore, if the first depth T2 exceeds 55% of the first thickness T1, the thickness of the connecting member 500 may become more variable, which may result in reduced connection reliability. Furthermore, if the first depth T2 exceeds 55% of the first thickness T1, the thickness of each region of the pad 420 may become more variable, which may result in electrical reliability issues. For example, if the thickness of each region becomes more variable, the transmission loss of signals passing through the pad 420 may increase, or the allowable current of signals that can be provided through the pad 420 may decrease.

[0225] The protective layer 450 may include multiple regions.

[0226] For example, the protective layer 450 includes a first region R1 adjacent to the opening 450-1. That is, the protective layer 450 includes the first region R1 including the opening 450-1 and vertically overlapping the pad 420. The protective layer 450 may also include a second region excluding the first region R1.

[0227] The lower surface of the first region R1 of the protective layer 450 may be divided into a plurality of lower surfaces. For example, the lower surface of the first region R1 of the protective layer 450 may include a first lower surface that does not contact the upper surface of the pad 420 and a second lower surface that contacts the upper surface of the pad 420.

[0228] Specifically, the lower surface of the first region R1 of the protective layer 450 vertically overlaps the first portion P1 of the pad 420 and includes a first lower surface that is not in contact with the first portion P1 of the pad 420 due to the recess 420-1.

[0229] The lower surface of the first region R1 of the protective layer 450 vertically overlaps the second portion P2 of the pad 420 and includes a second lower surface in contact with the upper surface of the second portion P2.

[0230] That is, a crevice due to the recess 420-1 may be formed between an upper surface of the first portion P1 of the pad 420 and a first lower surface of the first region R1 of the protective layer 450. In addition, an upper surface of the second portion P2 of the pad 420 and a second lower surface of the first region R1 of the protective layer 450 may be in direct contact with each other.

[0231] The protective layer 450 may have a third thickness T3, which may refer to the thickness of the first region R1 of the protective layer 450.

[0232] Preferably, the third thickness T3 of the protective layer 450 may refer to the vertical distance between the top surface of the pad 420 and the top surface of the protective layer 450.

[0233] The third thickness T3 of the protective layer 450 may be in the range of 1 μm to 25 μm, and more preferably in the range of 3 μm to 18.5 μm. More preferably, the third thickness T3 of the protective layer 450 may be in the range of 3 μm to 16.5 μm. If the third thickness T3 of the protective layer 450 is outside the above range, problems may occur, such as the circuit pattern layer not being stably protected or the overall thickness of the circuit board increasing, as described above.

[0234] Meanwhile, the first portion P1 of the pad 420 may be divided into a plurality of sub-portions, which may be divided based on a plurality of regions of the protective layer 450.

[0235] An upper surface of the first portion P1 of the pad 420 does not contact the protective layer 450. However, the upper surface of the first portion P1 of the pad 420 may include a first sub-portion P1-1 that does not vertically overlap the first protective layer 450 and a second sub-portion P1-2 that is connected to the first sub-portion P1-1 and does not vertically overlap the first portion P1.

[0236] That is, the first sub-portion P1-1 of the pad 420 may vertically overlap an opening 450-1 provided in the protective layer 450. And, the second sub-portion P1-2 of the pad 420 may vertically overlap a first region R1 of the protective layer 450 adjacent to the opening 450-1.

[0237] Expressed differently, the pad 420 includes a first sub-portion P1-1 of a first portion P1 that vertically overlaps the opening 450-1 of the protective layer 460. The pad 420 also includes a second portion P2 and a second sub-portion P1-2 of the first portion P1 that vertically overlap the first region R1 of the protective layer 450.

[0238] At this time, the second sub-portion P1-2 of the first portion P1 and the second portion P2 vertically overlap the first region R1 of the protective layer 450. At this time, the second sub-portion P1-2 of the first portion P1 includes the recess 420-1. Therefore, the upper surface of the second sub-portion P1-2 of the first portion P1 does not contact the lower surface of the first region R1 of the protective layer 450. The second portion P2 of the pad 420 does not include the recess 420-1. Therefore, the upper surface of the second portion P2 of the pad 420 directly contacts the lower surface of the first region R1 of the protective layer 450.

[0239] In summary, the second sub-portion P1-2 and the second portion P2 of the pad 420 of the embodiment vertically overlap the first region R1 of the protective layer 450. In this case, the second sub-portion P1-2 of the pad is spaced apart from the protective layer 450, and the second portion P2 of the pad 420 is in direct contact with the protective layer 450.

[0240] In this case, the width W1 of the second sub-portion P1-2 of the pad 420 may be different from the width W2 of the second portion P2 of the pad 420. Preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be greater than the width W2 of the second portion P2 of the pad 420.

[0241] The width W1 of the second sub-portion P1-2 of the pad 420 may be in the range of 2 to 50 times the width W2 of the second portion P2 of the pad 420. Preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be in the range of 3 to 48 times the width W2 of the second portion P2 of the pad 420. More preferably, the width W1 of the second sub-portion P1-2 of the pad 420 may be in the range of 5 to 40 times the width W2 of the second portion P2 of the pad 420.

[0242] If the width W1 of the second sub-portion P1-2 of the pad 420 is less than twice the width W2 of the second portion P2 of the pad 420, the effect of increasing the adhesive strength and adhesion of the connecting member 500 will be insufficient, which may result in reliability issues such as the connecting member 500 being separated from the pad 420.

[0243] Furthermore, if the width W1 of the second sub-portion P1-2 of the pad 420 is more than 50 times the width W2 of the second portion P2 of the pad 420, the overall width of the pad 420 may increase accordingly. If the overall width of the pad 420 increases, the circuit integration density may decrease, and therefore the overall volume of the circuit board may increase.

[0244] On the other hand, when the vertical center of the opening 450-1 of the protective layer 450 and the vertical center of the pad 420 coincide with each other, the second sub-portions P1-2 of the pad 420 may have widths that correspond to each other across the entire area. Correspondingly, the second portions P2 of the pad 420 may also have widths that correspond to each other across the entire area. Here, "having corresponding widths" may mean that the width deviation across the entire area is 30% or less, 20% or less, 15% or less, 10% or less, 5% or less, or 2% or less. For example, "having corresponding widths" may mean that the difference between the maximum width and the minimum width across the entire area is 3 μm or less, 2 μm or less, 1 μm or less, or 0.5 μm or less.

[0245] Alternatively, if the vertical center of the opening 450-1 of the protective layer 450 is misaligned with the vertical center of the pad 420, the widths of the second sub-portion P1-2 and the second portion P2 of the pad 420 may vary across the entire area. In this case, the width W1 of the second sub-portion P1-2 and the width W2 of the second portion P2 may refer to widths at adjacent side portions of the vertical cross section.

[0246] For example, the width W1 of the second sub-portion P1-2 may refer to the width of the region adjacent to the first side of the first sub-portion P1-1 in the vertical cross section, and the width W2 of the second portion P2 may refer to the width of the region adjacent to the first side of the second sub-portion P1-2.

[0247] Meanwhile, the connection member 500 is disposed in the recess 420-1 and the opening 450-1.

[0248] Therefore, the connection member 500 can be divided into a plurality of parts.

[0249] For example, the connecting member 500 may include a first part disposed in the recess 420-1 of the pad 420. In this case, the first part of the connecting member 500 may be located between the first region R1 of the first protective layer 450 and the first portion P1 of the pad 420. Thus, the first part of the connecting member 500 may contact a portion 450LS of the lower surface of the first region R1 of the protective layer 450 and an upper surface of the first portion P1 of the pad 420.

[0250] Furthermore, the connecting member 500 may include a part located on the first part and arranged in the opening 450-1 of the protective layer 450. The second part of the connecting member 500 may have a shape corresponding to the shape of the opening 450-1. The second part of the connecting member 500 may contact an inner surface 450IS of the first region R1 of the protective layer 450 that constitutes the opening 450-1. In this case, the width of the opening 450-1 at a portion adjacent to the upper surface of the protective layer 450 may be the same as the width at a portion adjacent to the lower surface of the protective layer 450. As a result, the second part of the connecting member 500 may have a columnar shape with the same width at the upper and lower surfaces.

[0251] The connecting member 500 may include a third part disposed on the second part. The third part of the connecting member 500 may protrude above the upper surface of the protective layer 450. The upper surface of the third part of the connecting member 500 may have an upwardly convex curve. At least a portion of the third part of the connecting member 500 may be located on the first region R1 of the protective layer 450. Therefore, the third part of the connecting member 500 may contact the upper surface 450US of the first region R1 of the protective layer 450.

[0252] That is, a concave-convex interface may be provided between the connection member 500 and the pad 420. In this case, the concave-convex interface may refer to the lower surface of the connection member 500. Alternatively, the concave-convex interface may correspond to the upper surface of the first portion P1 of the pad 420. As a result, the concave-convex interface may have a structure that the first sub-portion P1-1 and the second sub-portion P1-2 of the first portion P1 of the pad 420 have.

[0253] In the embodiment, as described above, the pad 420 is provided with the recess 420-1. The provided recess 420-1 can be used to improve adhesion between the pad 420 and the connection member 500. Specifically, in the embodiment, the recess 420-1 can be used to allow the connection member 500 to have an anchor structure and be coupled to the pad 420. As a result, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board.

[0254] Meanwhile, although the recess 420-1 has been described above as being applied to all pads of the first circuit pattern layer 420 and the second circuit pattern layer 430, this is not limiting. For example, only some pads that are relatively small in size or have low adhesion to the connecting member 500 may have an anchor structure including the recess 420-1.

[0255] The circuit board and semiconductor package of the embodiment can improve the adhesion and bonding strength between the pad and the connection member, thereby solving the problem of cracks occurring in the connection member and thereby improving the physical and electrical reliability of the connection member.

[0256] To this end, the circuit board of the embodiment includes an insulating layer, a pad, and a protective layer. The protective layer includes an opening that vertically overlaps at least a portion of the pad. The protective layer includes a first region that includes the opening and vertically overlaps the pad, and a second region excluding the first region. The pad also includes a recess. The recess may be a concave recess that is recessed from the upper surface to the lower surface of the pad. The pad includes an upper surface having an uneven shape corresponding to the recess. The pad includes a first portion that includes the recess and a second portion that does not include the recess. The first portion of the pad includes a first sub-portion that vertically overlaps the opening of the protective layer and a second sub-portion that vertically overlaps the first region of the protective layer. Meanwhile, a connecting member is disposed on the pad. The connecting member is disposed to fill the recess of the pad. As a result, the connecting member is disposed on not only the first sub-portion but also the second sub-portion of the pad. A portion of the connection member disposed in the second sub-portion may have a structure located between the lower surface of the first region of the protective layer and the upper surface of the second sub-portion of the pad.

[0257] As a result, the connecting member of the embodiment includes a first part disposed on the second sub-portion. The first part of the connecting member can function as an anchor that improves adhesive strength and adhesion to the pad. Through this, the embodiment can solve the reliability problem of the connecting member being separated from the pad. Therefore, the embodiment can improve the overall product reliability of the circuit board and the semiconductor package.

[0258] In addition, the embodiment may increase the contact area between the pad and the connection member through an anchor structure of the connection member. Therefore, the embodiment does not need to increase the size of the pad to increase the contact area. Therefore, the embodiment may reduce the size of the pad, thereby improving the integration density of the circuit. Furthermore, the embodiment may reduce the overall volume of the circuit board and the semiconductor package.

[0259] FIG. 5a is a diagram showing a first modified example of the circuit board of FIG. 4a, and FIG. 5b is a diagram showing a second modified example of the circuit board of FIG. 4a.

[0260] 5a and 5b, first and second modified examples of the circuit board of the first embodiment will be described below. In the description of the first and second modified examples, however, descriptions of configurations that are substantially the same as those of the circuit board of the first embodiment will be omitted.

[0261] The protective layer 450 of the circuit board of the first embodiment includes openings 450-1 that vertically overlap the pads 420. In this case, the openings 450-1 have a shape whose width does not change in the vertical direction. For example, the width of adjacent openings 450-1 on the upper surface of the protective layer 450 is the same as the width of adjacent openings 450-1 on the lower surface of the protective layer 450.

[0262] Alternatively, the openings in the protective layer 450 may have width variations in the vertical direction. For example, the openings in the protective layer 450 are formed through an exposure and development process. At this time, the width variations of the openings may vary depending on the exposure conditions. For example, the exposure conditions may be positive or negative. The openings in the protective layer 450 may have different shapes depending on the exposure conditions.

[0263] Referring to FIG. 5a, the protective layer 450 may include an opening 450-1a.

[0264] The opening 450-1a in the protective layer 450 may include a region of varying width.

[0265] For example, the width of the opening 450-1 a of the protective layer 450 may vary from a region adjacent to the upper surface of the protective layer 450 to a region adjacent to the lower surface of the protective layer 450. For example, the width of the opening 450-1 a of the protective layer 450 may decrease from a region adjacent to the upper surface of the protective layer 450 to a region adjacent to the lower surface of the protective layer 450.

[0266] The pad 420 in the first modification includes a first portion P1 including a recess 420-1 and a second portion P2 not including a recess, and the first portion P1 of the pad 420 includes a first sub-portion P1-1 and a second sub-portion P1-2.

[0267] In this case, the opening 450-1a has a width that varies vertically. Therefore, in the first modified example, the division of the pad 420 into the first sub-portion P1-1 and the second sub-portion P1-2 may be performed based on the lower surface of the first region R1 of the protection layer 450.

[0268] The second sub-portion P1-2 of the pad 420 may refer to a portion that includes the recess 420-1 and vertically overlaps the lower surface of the first region R1 of the protective layer 450. The first sub-portion P1-1 of the pad 420 may refer to a portion that vertically overlaps the opening 450-1a of the protective layer 450 and does not vertically overlap the lower surface of the first region R1 of the protective layer 450.

[0269] Referring to FIG. 5b, the protective layer 450 may include an opening 450-1b.

[0270] The opening 450-1b in the protective layer 450 may include a region of varying width.

[0271] For example, the width of the opening 450-1b of the protective layer 450 may vary from a region adjacent to the upper surface of the protective layer 450 to a region adjacent to the lower surface of the protective layer 450. For example, the width of the opening 450-1b of the protective layer 450 may increase from a region adjacent to the upper surface of the protective layer 450 to a region adjacent to the lower surface of the protective layer 450.

[0272] The pad 420 in the second modification includes a first portion P1 including a recess 420-1 and a second portion P2 not including a recess, and the first portion P1 of the pad 420 includes a first sub-portion P1-1 and a second sub-portion P1-2.

[0273] In this case, the opening 450-1a has a width that varies vertically. Therefore, in the first modified example, the division of the pad 420 into the first sub-portion P1-1 and the second sub-portion P1-2 may be performed based on the lower surface of the first region R1 of the protection layer 450.

[0274] The second sub-portion P1-2 of the pad 420 may refer to a portion that includes the recess 420-1 and vertically overlaps the lower surface of the first region R1 of the protective layer 450. The first sub-portion P1-1 of the pad 420 may refer to a portion that vertically overlaps the opening 450-1b of the protective layer 450 and does not vertically overlap the lower surface of the first region R1 of the protective layer 450.

[0275] The following describes circuit boards according to other embodiments.

[0276] The circuit board described below has a structure similar to that of the circuit board of the first embodiment, and may have differences in the recesses provided in the pads.

[0277] FIG. 6 is a cross-sectional view showing a circuit board according to the second embodiment.

[0278] Referring to FIG. 6, the circuit board of the second embodiment includes an insulating layer 410, a pad 420a disposed on the insulating layer 410, and a protective layer 450 disposed on the insulating layer 410 and including an opening 450-1.

[0279] At this time, the pad 420a includes the recess 420-1a.

[0280] The recess 420-1a may be provided over the entire upper surface of the pad 420a.

[0281] That is, the pad 420 of the circuit board of the first embodiment includes a first portion P1 having a recess and a second portion P2 having no recess.

[0282] Alternatively, the pad 420a of the circuit board of the second embodiment may include only the first portion P1 with the recess 420-1a.

[0283] Thus, the pad 420a may include a first sub-portion P1-1 that vertically overlaps the opening 450-1 of the protective layer 450, and a second sub-portion P1-2 that vertically overlaps the lower surface of the first region R1 of the protective layer 450.

[0284] The lower surface of the first region R1 of the protective layer 450 may be vertically overlapped with the pad 420a and may not be in contact with the pad 420a.

[0285] For example, the entire area of the top surface of the pad 420 a may not be in contact with the protective layer 450 .

[0286] FIG. 7 is a cross-sectional view showing a circuit board according to the third embodiment.

[0287] Referring to FIG. 7, the circuit board of the third embodiment includes an insulating layer 410, a pad 420b disposed on the insulating layer 410, and a protective layer 450 disposed on the insulating layer 410 and including an opening 450-1.

[0288] At this time, the pad 420b includes a recess 420-1b.

[0289] The recess 420-1b may be partially provided on the upper surface of the pad 420b.

[0290] The pad 420b includes a first portion P1 including the recess 420-1b and a second portion P2 not including the recess 420-1b, and the second portion P2 of the pad 420b may be located only on one side of the first portion P1 of the pad 420b.

[0291] For example, the pad 420b may include a first side and a second side opposite the first side.

[0292] The second portion P2 of the pad 420b may not be present in the region adjacent to the first side of the pad 420b. For example, only the first portion P1 of the pad 420b may be located in the region adjacent to the first side of the pad 420b. For example, the first side of the pad 420b may be connected to the recess 420-1b. For example, the first side of the pad 420b may be directly connected to the second sub-portion P1-2 of the first portion P1 of the pad 420b. That is, the second portion P2 may not be located between the first side of the pad 420b and the second sub-portion P1-2.

[0293] Alternatively, a second portion P2 of the pad 420b may be present in a region adjacent to a second side of the pad 420b opposite the first side. For example, a second portion P2 connected to the second sub-portion P1-2 of the pad 420b may be present in a region adjacent to the second side of the pad 420b. Therefore, the second side of the pad may not be connected to the recess 420-1b. For example, the second side of the pad 420b may not be directly connected to the first portion P1 of the pad 420b.

[0294] FIG. 8a is a diagram showing a circuit board according to a fourth embodiment, and FIG. 8b is a cross-sectional view showing a state in which a connecting member is arranged on the circuit board of FIG. 8a.

[0295] Referring to Figures 8a and 8b, the circuit board of the fourth embodiment includes an insulating layer 410, a pad 420c disposed on the insulating layer 410, and a protective layer 450 disposed on the insulating layer 410 and including an opening 450-1.

[0296] At this time, the pad 420c includes a recess.

[0297] The recess may be provided entirely on the top surface of the pad 420c.

[0298] That is, the recess may include a first part 420-1c1 that is provided on the entire upper surface of the pad 420c.

[0299] In contrast, the pad 420c of the circuit board of the fourth embodiment includes a first recess part 420-1c1, so that the pad 420c includes only the first portion P1, and therefore the upper surface of the pad 420c may not be in contact with the lower surface of the first region R1 of the protective layer 450 as a whole.

[0300] Meanwhile, the recess may include a second part 420-1c2 connected to the first part 420-1c1.

[0301] The second part 420-1c2 may be connected to the first part 420-1c1 and formed on a side of the pad 420c.

[0302] In other words, the recesses in the previous embodiments were only provided on the top surface of the pad.

[0303] Differently from this, the recess of the fourth embodiment includes a first part 420-1c1 provided on the upper surface of the pad 420c and a second part 420-1c2 provided on the side surface of the pad 420c.

[0304] In this case, the recess of the fourth embodiment may be provided over the entire side surface of the pad 420c.

[0305] Therefore, the second part 420-1c2 of the recess prevents at least a part of the side surface of the pad 420c from contacting the first region R1 and the second region R2 of the protective layer 450, respectively.

[0306] The connection member 500 is disposed in the first part 420-1c1 and the second part 420-1c2 of the recess 420-1b, respectively. The connection member 500 may contact at least a portion of the side surface of the pad 420c while contacting the upper surface of the pad 420c.

[0307] That is, the connecting member 500 may contact the upper surface of the pad 420c and the lower surface of the first region R1 of the protective layer 450. In addition, the connecting member 500 may contact the side surface of the pad 420c and the inner surface of the second region R2 of the protective layer 450. As a result, the embodiment may further improve the adhesion and bonding strength between the pad and the connecting member.

[0308] Meanwhile, the recess provided in the pad according to the embodiment may include multiple parts, for example, a first part provided on the top surface of the pad and a second part connected to the first part and provided on the side surface of the pad.

[0309] Therefore, at least a portion of the side surface of the pad may not contact the protective layer through the second part of the recess. A connecting member may be disposed in the second part of the recess of the pad. The connecting member may be disposed in the first part of the recess and contact the lower surface of the first region of the protective layer and the upper surface of the pad. The connecting member may also be disposed in the second part of the recess and contact the inner surface of the second region of the protective layer and the side surface of the pad. This may further increase the contact area between the pad and the connecting member. Therefore, the embodiment may further improve the adhesion and bonding strength between the pad and the connecting member.

[0310] FIG. 9 is a cross-sectional view showing a circuit board according to a fifth embodiment.

[0311] Referring to FIG. 9, the circuit board of the fifth embodiment includes an insulating layer 410, a pad 420d disposed on the insulating layer 410, and a protective layer 450 disposed on the insulating layer 410 and including an opening 450-1.

[0312] At this time, the pad 420d includes a recess.

[0313] The recess may be partially provided in the upper surface of the pad 420d.

[0314] The recess may also be provided on the side of the pad 420d.

[0315] That is, the pad 420d may include a first part 420-1d1 partially provided on the upper surface of the pad 420d and a second part 420-1d2 connected to the first part 420-1d1 and provided on the side of the pad 420d.

[0316] Meanwhile, the circuit board of the embodiment may include a plurality of pads, and the plurality of pads may include recesses having different shapes. For example, the circuit board of the embodiment may include the recesses having different shapes described in at least two of the first to fifth embodiments. As an example, the circuit board may include a first pad and a second pad. The first pad of the circuit board may include recess 420-1 of the first embodiment, and the second pad may include recesses 420-1d1 and 420-1d2 of the fifth embodiment.

[0317] The method for manufacturing a circuit board according to the embodiment will be described below in the order of steps.

[0318] 10a to 10d are cross-sectional views for explaining the manufacturing method of the circuit board shown in FIG. 3 in the order of steps.

[0319] Referring to FIG. 10a, in an embodiment, the insulating layer 410 is provided.

[0320] Then, in this embodiment, through holes VH are formed through the upper and lower surfaces of the insulating layer 410 .

[0321] 10b, in an embodiment, through electrodes 440 filling the through holes VH may be formed on the insulating layer 410. In addition, in an embodiment, a first circuit pattern layer 420 including at least one pad may be formed on an upper surface of the insulating layer 410. In addition, in an embodiment, a second circuit pattern layer 430 including at least one pad may be formed on a lower surface of the insulating layer 420.

[0322] 10c, in an embodiment, a first protective layer 450 may be formed on an upper surface of the insulating layer 410. In addition, in an embodiment, a second protective layer 460 may be formed on a lower surface of the insulating layer 410.

[0323] 10d, an embodiment may expose and develop each of the first protective layer 450 and the second protective layer 460. Through this, an embodiment may form openings 450-1 in the first protective layer 450 that vertically overlap the pads of the first circuit pattern layer 420. Also, an embodiment may form openings 460-1 in the second protective layer 460 that vertically overlap the pads of the second circuit pattern layer 430.

[0324] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0325] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0326] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0327] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a circuit pattern layer disposed on the insulating layer and including pads; a protective layer disposed on the insulating layer and including an opening that vertically overlaps the pad; The pad includes a recess recessed from an upper surface of the pad toward a lower surface of the pad, The protective layer is a first region including the opening and vertically overlapping the pad; a second region excluding the first region, The pad is a first portion including the recess; a second portion coupled to the first portion and not including the recess; the first portion of the pad includes a first sub-portion that vertically overlaps the opening in the protective layer and a second sub-portion that vertically overlaps a lower surface of the first region of the protective layer; A circuit board, wherein the width of the second sub-portion of the pad is greater than the width of the second portion of the pad.

2. an upper surface of the second sub-portion of the pad spaced apart from a lower surface of the first region of the protective layer; The circuit board of claim 1 , wherein an upper surface of the second portion of the pad is in direct contact with a lower surface of the first region of the protective layer.

3. The circuit board according to claim 1 , wherein the top surface of the first portion of the pad has an uneven shape.

4. The width of the second sub-portion of the pad is: The circuit board of claim 1 , wherein the width of the second portion of the pad is in the range of 2 to 50 times the width of the second portion.

5. The vertical distance from the lower surface of the first region of the protective layer to the upper surface of the first portion of the pad is:

2. The circuit board according to claim 1, wherein the distance between the lower surface of the first region of the protective layer and the lower surface of the pad is in the range of 5% to 55%.

6. the pad includes a side surface; 6. The circuit board according to claim 1, wherein at least a part of the top surface of the first portion of the pad is connected to a side surface of the pad.

7. 6. The circuit board according to claim 1, wherein the recess of the pad is connected to a side surface of the pad.

8. the pad includes a first side and a second side opposite the first side; The width of a second sub-portion of the pad adjacent the first side of the pad is:

6. The circuit board of claim 1, wherein the width of the second sub-portion of the pad adjacent the second side of the pad is different from the width of the second sub-portion of the pad adjacent the second side of the pad.

9. The recess is a first part provided on an upper surface of the pad; 6. The circuit board according to claim 1, further comprising: a second part connected to the first part and provided on a side of the pad.

10. The circuit board according to claim 9 , wherein a side surface of the pad comprising the second part is spaced apart from the protective layer.

Images