Optical computing system with separate memory.

Abstract

Described herein are embodiments of a photonic computing system that includes one or more processors in communication with a separate memory over one or more optical channels, the separate memory including multiple memory units disposed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processors.

Description

[Technical Field]

[0001] Aspects of the present disclosure relate to an optical computing system that includes one or more processors in communication with one or more separate memory blocks, each of which may include multiple memory units interconnected through a photonic network. [Background technology]

[0002] The memory unit may be a chip including an integrated circuit capable of storing data. The memory unit may include a random access memory (RAM) or a read-only memory (ROM). For example, the memory unit may be a dynamic RAM (DRAM) chip, a static RAM (SRAM) chip, a programmable ROM (PROM) chip, or an erasable PROM (EPROM). A processor may use the memory unit to store information. For example, a processor may use a RAM chip to temporarily store information (e.g., software application program instructions and / or data). As another example, a ROM chip may store firmware for operating a device. Summary of the Invention [Means for solving the problem]

[0003] Described herein are embodiments of a photonic computing system that includes one or more processors in communication with a separate memory over one or more optical channels, the separate memory including multiple memory units disposed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processors.

[0004] Some embodiments provide a photonic computing system including at least one processor, at least one optical channel, and at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for providing the at least one processor with access to the plurality of memory units, the at least one photonic network communicating with the at least one processor through the at least one optical channel, and the at least one photonic network being programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor may access through the at least one optical channel.

[0005] Some embodiments provide a method of using a photonic network to perform parallelized data processing using multiple memory units. The photonic network is programmable to configure which of the multiple memory units can be accessed by a first processor and a second processor. The photonic network is programmed to allow access to a first memory unit of the multiple memory units by the first processor and to allow access to a second memory unit of the multiple memory units by the second processor. The method includes programming the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor; performing, by the first processor, an operation using data stored in the second memory unit to obtain an output; and performing, by the second processor, an operation using the data stored in the first memory unit in parallel with the execution of the first processor.

[0006] Some embodiments provide a photonic network disposed on a photonic substrate, the photonic network being accessible through at least one optical channel, the photonic network including a plurality of memory units, at least one configurable optical switch that controls which of the plurality of memory units are accessible through the at least one optical channel, and at least one electrical / optical (E / O) transceiver for transmitting data to and from the plurality of memory units through the at least one optical channel.

[0007] Some embodiments provide a method of fabricating a photonic computing system, the method comprising fabricating the photonic computing system to include at least one processor, at least one optical channel, and at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for connecting the at least one processor to the plurality of memory units, the at least one photonic network communicating with the at least one processor over the at least one optical channel, and the at least one photonic network being programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor may access over the at least one optical channel.

[0008] The above is a non-limiting summary. Various aspects and embodiments are described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Items that appear in more than one figure are designated by the same or similar reference numerals in all the figures in which they appear. [Brief explanation of the drawings]

[0009] [Figure 1A]1 is an exemplary photonic computing system in accordance with some embodiments of the technology described herein. [Figure 1B] 1B is a first programmed configuration of a photonic network in the photonic computing system of FIG. 1A in accordance with some embodiments of the technology described herein. [Figure 1C] 1B is a second programmed configuration of the photonic network in the photonic computing system of FIG. 1A in accordance with some embodiments of the technology described herein. [Figure 2A] 1 is a side view of a photonic substrate in accordance with some embodiments of the techniques described herein. [Figure 2B] 2B is an overhead view of the photonic substrate of FIG. 2A in accordance with some embodiments of the techniques described herein. [Figure 2C] FIG. 1B is a side view of another photonic substrate in accordance with some embodiments of the techniques described herein. [Figure 2D] FIG. 1B is a side view of another photonic substrate in accordance with some embodiments of the techniques described herein. [Figure 3] 1 is an exemplary processor of a photonic computing system in accordance with some embodiments of the technology described herein. [Figure 4] 1 illustrates an exemplary parallelization paradigm that may be used by some embodiments of the techniques described herein. [Figure 5A] 1 illustrates virtualization that can be performed using a computing system of some embodiments of the technology described herein. [Figure 5B] 5B illustrates reallocation of processors and memory to the virtual machines of FIG. 5A in accordance with some embodiments of the techniques described herein. [Figure 6A] 1 illustrates an exemplary photonic computing system in accordance with some embodiments of the technology described herein. [Figure 6B]6B illustrates an exemplary set of connections from a fiber connector of a memory tile to memory controllers of all memory tiles of FIG. 6A in accordance with some embodiments of the techniques described herein. [Figure 6C] 6B illustrates another exemplary set of connections from a fiber connector of another memory tile to the memory controllers of all the memory tiles of FIG. 6A in accordance with some embodiments of the techniques described herein. [Figure 7A] 6A-6C illustrate exemplary configurations of photonic networks of the memory tiles according to some embodiments of the techniques described herein. [Figure 7B] 6A-6C illustrate another exemplary configuration of the photonic network of memory tiles 604A-604H of FIGS. 6A-6C, in accordance with some embodiments of the technology described herein. [Figure 8] 6B illustrates an example configuration of the photonic computing system of FIG. 6A in which each of the processors is designated for a different application, according to some embodiments of the technology described herein. [Figure 9] 1 illustrates an exemplary photonic computing system in which a set of processors can access multiple disjointed memory pools, in accordance with some embodiments of the technology described herein. [Figure 10] 1 illustrates an exemplary photonic computing system in which the memory of the computer system is extended by multiple disjointed sets of memory units, according to some embodiments of the technology described herein. [Figure 11] 1 is an exemplary process for programming a photonic network in accordance with some embodiments of the techniques described herein. [Figure 12] 1 is an exemplary process for executing software applications in parallel, according to some embodiments of the techniques described herein. [Figure 13] FIG. 1 is a block diagram of an illustrative computing system that may be used in implementing some embodiments of the techniques described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] Described herein are embodiments of a photonic computing system that includes one or more processors in communication with a separate memory over one or more optical channels, the separate memory including multiple memory units disposed on a photonic substrate that includes a photonic network that can be programmed to configure which of the memory units can be accessed by each of the processors.

[0011] Typically, a processor must make a trade-off between (1) memory capacity and (2) memory bandwidth / latency and resources (e.g., power and space on a chip). This trade-off often limits memory capacity to maintain a target bandwidth / latency, shrink chip size, and reduce power consumption. Conventional high bandwidth memory (HBM) can provide memory bandwidth as high as 800 gigabytes per second (GB / s), but consumes a significant amount of power (e.g., approximately 6 pJ / bit) and requires a large amount of space on a chip. HBM memory units must be located several millimeters away from the processor (e.g., compute die) that accesses them. Conventional HBM only offers a maximum density of 48 GB within a memory unit (e.g., a stack of one or more memory dies). Size and spacing constraints limit the number of stacks within a chip to just two stacks, which equates to a total of 96 GB of HBM. High-speed double data rate (DDR) memory requires less space on a chip than HBM and consumes less power than HBM, but DDR offers lower bandwidth (up to 32 GB / s) and worse latency than HBM.

[0012] Restricting processors to a specific set of attached high-density memory (e.g., HBM and / or DDR) necessitates communication between processors when executing parallelizable applications. Parallelization often requires multiple processors to access a shared data set. This data must therefore be transferred between the memories of the multiple processors. This transfer reduces the efficiency of parallel execution and introduces data redundancy. If the memory storing the data could be accessed by all processors, the processors could access the data more efficiently because the data would not need to be transferred between different memories. Conventional techniques for enabling this functionality include building multi-chip packages that require several tapeouts, which creates complexity in managing multiple different products. Furthermore, power and area resource constraints limit the performance of certain applications. This necessitates more application-specific chip designs.

[0013] Decoupling memory from processors allows for more efficient parallelization, so that memory units can be reconfigured to connect to different processors. However, conventional techniques for decoupling memory from processors consume power, have low bandwidth, and have high latency. As a result, conventional decoupled memory systems are limited to decoupling disk drives and / or solid-state drives because this storage hardware already has a high power cost, exceeding 10 pJ / bit. Furthermore, conventional decoupled memory systems provide low bandwidth with high latency, making them unsuitable for running applications that require high bandwidth and low latency.

[0014] To address the above-mentioned shortcomings in memory design for processors, the inventors have developed a technique that utilizes photonics to decouple memory from processors in a computing system. This technique allows for an increase in memory density accessible to processors without sacrificing memory bandwidth. This technique places an isolated pool of memory units on a photonic substrate with a programmable photonic network to configure which memory units can be accessed by each processor. The processors communicate with the pool of memory units through one or more optical channels. This technique can support memory bandwidths in excess of 15 terabytes per second (TB / s).

[0015] Some embodiments include a photonic substrate that includes, separate from the processors, multiple memory units (e.g., memory stacks) and a programmable photonic network. The photonic network can be programmed into various configurations to change which processors are connected to corresponding ones of the memory units. This allows the computing system to use a paradigm for parallel execution of operations that does not rely on data transfer between different memories. The photonic network can be programmed to reconfigure the connections between the memory units and the processors, thereby reducing or even eliminating the need to transfer data between memory units to parallelize operations. This allows for more efficient parallelization of operations.

[0016] In some embodiments, a programmable photonic network can dynamically reconfigure the amount of memory allocated to a processor. Thus, the photonic network can be programmed according to application execution requirements. For example, applications that require more memory to run can be allocated more memory from a memory pool, while applications that require less memory to run can be allocated less memory from a memory pool. Furthermore, the photonic network increases the amount of memory (e.g., high-density memory) that can be attached to a high-bandwidth processor without being constrained by the size and space limitations of traditional HBM. For example, the present technique no longer requires that an HBM memory unit be within a few millimeters of the processor (e.g., compute die) that accesses the HBM memory unit.

[0017] Some embodiments enable a processor to communicate with one or more sets of memory units through one or more optical channels (e.g., fiber optic cables). The optical channels enable decoupling of the processor from the set of memory units. While conventional techniques typically require placing the processor on a chip (e.g., a silicon interposer) with high-density memory units (e.g., HBM units), some embodiments herein enable decoupling of the processor from the chip that includes the set of memory units. For example, the present techniques enable the processor to connect to memory units housed in a package or chassis separate from the processor.

[0018] Some embodiments provide a photonic computing system. The photonic computing system includes one or more processors, one or more optical channels, and a photonic substrate separate from the processors. The photonic substrate includes a plurality of memory units and a photonic network for connecting the processors to the memory units. The photonic network communicates with the processors through the optical channels. The photonic network is programmable to configure which memory units in the photonic substrate can be accessed by the processors through the optical channels.

[0019] Some embodiments provide a photonic computing system. The photonic computing system includes at least one processor, at least one optical channel (e.g., one or more optical fibers), and at least one photonic substrate (e.g., a photonic interposer) separate from the at least one processor, the at least one photonic substrate including multiple memory units (e.g., HBM units, SRAM units, DDR SDRAM units), and at least one photonic network for providing the at least one processor with access to the multiple memory units. The at least one photonic network communicates with the at least one processor through the at least one optical channel. The at least one photonic network is programmable to configure which of the multiple memory units in the at least one photonic substrate the at least one processor may access through the at least one optical channel.

[0020] In some embodiments, the at least one processor includes a first processor and a second processor, and the first processor and the second processor are configured to process the dataset using a plurality of memory units. In some embodiments, the at least one photonic network is programmed to allow the first processor to access a first memory unit of the plurality of memory units and the second processor to access a second memory unit of the plurality of memory units, and processing the dataset includes performing, by the first processor, an operation using data stored in the first memory unit to obtain a first output and storing the first output in the first memory unit. In some embodiments, after storing the first output in the first memory unit, the at least one photonic network is programmed to enable access to the first memory unit by a second processor and to enable access to the second memory unit by the first processor, and processing the dataset further includes: performing, by the first processor, an operation using data stored in the second memory unit to obtain a second output; performing, by the second processor, in parallel with execution by the first processor, an operation using the first output stored in the first memory unit to obtain a first result; storing the second output in the second memory unit; and outputting the first result from the first memory unit.In some embodiments, the at least one photonic network is programmed to allow access to the first memory unit by a first processor and to allow access to the second memory unit by a second processor, and processing the datasets stored in the plurality of memory units of the at least one photonic network further includes: performing, by the first processor, an operation using the data stored in the first memory unit to obtain a third output; performing, by the second processor, in parallel with execution by the first processor, an operation using the second output stored in the second memory unit to obtain a second result; storing the third output in the first memory unit; and outputting the second result from the second memory unit.

[0021] In some embodiments, the at least one photonic network includes at least one optical switch configurable to connect / disconnect the at least one processor to each of the plurality of memory units, and the at least one photonic network is programmable by configuring the at least one optical switch.

[0022] In some embodiments, at a first point in time, the at least one photonic network is programmed to enable access by the at least one processor to a first memory unit of the plurality of memory units over at least one optical channel, and at a second point in time subsequent to the first point in time, the at least one photonic network is programmed to disable access by the at least one processor to the first memory unit over the at least one optical channel and to enable access by the at least one processor to a second memory unit of the plurality of memory units over the at least one optical channel.

[0023] In some embodiments, the at least one processor includes a first processor and a second processor, the plurality of memory units includes a first memory unit and a second memory unit, and the at least one photonic network is programmed to enable access to the first memory unit by the first processor and access to the second memory unit by the second processor.

[0024] In some embodiments, the at least one photonic substrate further includes at least one memory controller configured to program the at least one photonic network. In some embodiments, the at least one processor is configured to program the at least one photonic network.

[0025] In some embodiments, the at least one processor includes a plurality of processors, the plurality of processors being organized into a plurality of sets of processors, and the at least one photonic network being programmed to enable each of the sets of processors to access a different subset of the plurality of memory units through at least one optical channel. In some embodiments, each of the sets of processors and each subset of the plurality of memory units accessible by the set of processors forms a corresponding virtual processor assigned to a corresponding virtual machine. In some embodiments, the at least one processor includes a plurality of processors, the at least one optical channel includes a plurality of optical channels, and each of the plurality of processors communicates with at least one photonic network through a corresponding one of the plurality of optical channels. In some embodiments, the at least one photonic network includes a plurality of photonic networks, and the at least one photonic substrate includes a plurality of photonic modules, each including a corresponding one of the plurality of photonic networks, a subset of the plurality of memory units, and a memory controller. In some embodiments, each of the plurality of processors is connected to the memory controller of the plurality of photonic modules through a corresponding one of the plurality of optical channels.

[0026] In some embodiments, at least one photonic network is programmed with a configuration for allocating memory units among a plurality of processors based on memory requirements for executing a plurality of software applications, the configuration enabling access to a first set of the plurality of memory units by a first processor of the plurality of processors configured to execute a first software application (e.g., software applications using machine learning models such as large language models (LLMs), computer vision models, software development and testing applications, and / or other types of software applications) and enabling access to a second set of the plurality of memory units by a second processor of the plurality of processors configured to execute a second software application (e.g., software applications using machine learning models such as large language models (LLMs), computer vision models, software development and testing applications, and / or other types of software applications).

[0027] In some embodiments, the at least one photonic substrate includes a plurality of photonic substrates, each of the plurality of photonic substrates including a set of memory units and a corresponding photonic network, the photonic networks of the plurality of substrates being programmable to configure which of the corresponding sets of memory units may be accessed by the at least one processor. In some embodiments, the photonic computing system includes an optical switch, the optical switch being configurable to provide the at least one processor with access to a plurality of memory units distributed across the plurality of photonic substrates of the plurality of photonic substrates.

[0028] In some embodiments, the at least one photonic substrate includes at least one memory controller, and the at least one photonic network includes an optical circuit interconnecting the at least one memory controller with the plurality of memory units, hi some embodiments, the at least one photonic network includes a plurality of electrical / optical (E / O) transceivers connecting a corresponding one of the plurality of memory units to the optical circuit.

[0029] In some embodiments, the at least one photonic substrate includes at least one memory controller, at least one fiber connector connected to the at least one optical channel, and at least one E / O transceiver, and the at least one photonic network includes optical circuitry connecting the at least one memory controller to the at least one fiber connector, the E / O transceiver configured to convert signals transmitted between the at least one memory controller and the at least one fiber connector. In some embodiments, the at least one photonic network includes a plurality of electrical connections between the at least one memory controller and the plurality of memory units, and data signals are transmitted between the at least one memory controller and the plurality of memory units through the plurality of electrical connections.

[0030] Some embodiments provide a photonic network disposed on a photonic substrate, the photonic network being accessible through at least one optical channel, the photonic network including a plurality of memory units, at least one configurable optical switch that controls which of the plurality of memory units are accessible through the at least one optical channel, and at least one electrical / optical (E / O) transceiver for transmitting data to and from the plurality of memory units through the at least one optical channel.

[0031] In some embodiments, at a first time point, the at least one optical switch is configured to enable access to a first memory unit of the plurality of memory units through the at least one optical channel, and at a second time point subsequent to the first time point, the at least one optical switch is configured to enable access to a second memory unit of the plurality of memory units through the at least one optical channel. In some embodiments, at the second time point, the at least one optical switch is programmed to disable access to the second memory unit through the at least one optical channel.

[0032] In some embodiments, the photonic network further includes a memory controller, and the at least one optical switch is configurable by the memory controller. In some embodiments, the photonic network includes an optical circuit, and the optical circuit includes the at least one configurable optical switch. In some embodiments, the at least one E / O transceiver includes a plurality of E / O transceivers connected to corresponding ones of the plurality of memory units, and the optical circuit connects the memory controller to the plurality of memory units through the plurality of E / O transceivers. In some embodiments, the photonic network further includes a fiber connector, and the optical circuit connects the memory controller to the fiber connector through the at least one E / O transceiver.

[0033] The techniques described herein are not limited to any particular implementation method and may be implemented in any of numerous ways. Detailed examples of implementation forms are provided herein for illustrative purposes only. Furthermore, aspects of the techniques described herein are not limited to the use of any particular technique or combination of techniques, and the techniques disclosed herein may be used individually or in any suitable combination.

[0034] 1A is an exemplary photonic computing system in accordance with some embodiments of the techniques described herein. The photonic computing system includes processors 100A, 100B, a photonic substrate 102, and a set of one or more optical channels 112A, 112B through which corresponding processors 100A, 100B are connected to the photonic substrate 102. The processors 100A, 100B may be configured to access a memory unit 104 disposed on the photonic substrate 102 through the corresponding set of optical channels 112A, 112B.

[0035] Each of processors 100A, 100B may be any suitable processor. In some embodiments, the processor may include a central processing unit (CPU) including logic circuitry for executing instructions. The CPU may be configured to perform arithmetic operations, logical operations, and input / output (I / O) operations. In some embodiments, the processor may include a graphics processing unit (GPU). The GPU may be configured to perform graphics processing. For example, the GPU may perform image processing operations. In some embodiments, the processor may include a neural processing unit (NPU) configured to perform neural network processing. For example, the NPU may process inputs to a neural network model using weights of the neural network model to determine the output of the neural network model in response to the input. In some embodiments, the processor may include an analog processor. For example, the analog processor may be a photonic processor. An exemplary photonic processor that may be used in some embodiments is described in U.S. Pat. No. 11,218,227, incorporated herein by reference.

[0036] In some embodiments, one or more of processors 100A, 100B may be a multi-core processor. For example, a processor may have 2, 4, 6, 8, 10, or 12 cores. A multi-core processor may be configured to process multiple instruction sets simultaneously. In some embodiments, each of processors 100A, 100B may be a virtualized processor core (e.g., a vCPU).

[0037] As shown in FIG. 1A , processors 100A, 100B include corresponding optical interfaces 110A, 110B through which processors 100A, 100B may transmit and / or receive data as optical transmissions. In some embodiments, optical interfaces 110A, 110B may each include a fiber connector for connecting to a set of one or more optical fibers. In some embodiments, the optical fibers may be attached vertically through the use of vertical grating couplers and lenses. In some embodiments, the optical fibers may be attached through an edge connector using an edge coupler, V-groove, or evanescent coupler. In some embodiments, the optical fibers may be pluggable through the use of a plug-in glass module. Processors 100A, 100B may each send and receive optical transmissions through a set of optical fibers.

[0038] The photonic computing system of FIG. 1A includes a photonic substrate 102. The photonic substrate includes memory units 104A, 104B, 104C, 104D, 104E, 104F, 104G, and 104H and two photonic networks 108A and 108B. A first set of memory units 104A, 104B, 104C, and 104D can be accessed through the photonic network 108A. A second set of memory units 104E, 104F, 104G, and 104H can be accessed through the photonic network 108B. Examples of memory units include HBM, DRAM, non-volatile random access memory (NVRAM), and / or NAND flash. The photonic substrate 102 also includes electrical / optical (E / O) transceivers 114A and 114B and optical interfaces 110C and 110D. In some embodiments, the photonic substrate 102 includes memory controllers 106A, 106B connected to corresponding photonic networks 108A, 108B. The memory controllers 106A, 106B may be configured to program the corresponding photonic networks to select one or more memory units for connection to each processor, thereby enabling read and write operations.

[0039] It should be noted that instead of having separate photonic networks as shown in FIG. 1A, in some embodiments, a common photonic network may be used across all memory units. A common memory controller may program the common photonic network. Furthermore, in some embodiments, the photonic substrate 102 may not include memory controllers 106A, 106B. In such embodiments, a memory controller external to the photonic substrate 102 may program the photonic network. One or more of the processors 100A and 100B may function as an external memory controller.

[0040] In some embodiments, the photonic network may include multiple photonic modules. Each photonic module may be uniquely associated with a particular memory unit (or a particular subset of memory units) and may be programmed to enable or disable access to that memory unit or subset. For example, each photonic module may include one or more programmable photonic switches configured to connect to or disconnect from a corresponding memory unit or subset of memory units. In some embodiments, the photonic modules forming the photonic substrate 102 may be fabricated using microfabrication techniques (e.g., complementary metal-oxide-semiconductor (CMOS) microfabrication techniques). For example, the photonic modules may be patterned as multiple copies of a template photonic module using fabrication techniques based on step-and-repeat lithography. A detailed description of photonic modules is provided in U.S. Pat. No. 11,036,002, which is incorporated herein by reference in its entirety.

[0041] In some embodiments, each of photonic networks 108A, 108B may be a programmable photonic network. Each of photonic networks 108A, 108B may be programmable to configure which of memory units 104A-104H are accessible by each of processors 100A, 100B. For example, photonic network 108A, when programmed into a particular configuration, may provide processor 100A with access to one or more of memory units 104A, 104B, 104C, and 104D and / or processor 100B with access to one or more of memory units 104A, 104B, 104C, and 104D. As another example, photonic network 108B, when programmed into a particular configuration, may provide processor 100A with access to one or more of memory units 104E, 104F, 104G, and 104H and / or processor 100B with access to one or more of memory units 104E, 104F, 104G, and 104H. Thus, each of photonic networks 108A, 108B may be programmed to selectively cause processor 100A, 100B to communicate with a corresponding subset of memory units 104A-104H.

[0042] In some embodiments, the configuration of each of the photonic networks 108A, 108B may be dynamic. As such, the photonic networks 108A, 108B may be programmed multiple times. For example, the photonic networks 108A, 108B may be programmed during execution of instructions to provide the processors 100A, 100B to different ones of the memory units 104A-104H. In some embodiments, the photonic networks 108A, 108B may be programmed as part of the execution of parallelized operations. Exemplary techniques for performing parallelized execution of operations are described herein. In some embodiments, the photonic networks 108A, 108B may be programmed to allocate memory to virtual machines (e.g., virtual CPUs). For example, memory may be allocated to virtual machines based on the requirements of applications executed by the virtual machines.

[0043] As shown in the example of FIG. 1A , in some embodiments, a photonic network can interconnect memory units and memory controllers within an optical circuit. For example, photonic network 108A can include optical circuitry interconnecting memory units 104A, 104B, 104C, and 104D and memory controller 106A. As another example, photonic network 108B can include optical circuitry interconnecting memory units 104E, 104F, 104G, and 104H and memory controller 106B. In such embodiments, each memory unit can be connected to the photonic network through a corresponding E / O transceiver for converting data read and write signals between electrical and optical signals. For example, the E / O transceiver can be connected to the optical circuitry of the photonic network through which the E / O transceiver can send and receive optical signals. While the example embodiment of FIG. 1A shows a single E / O transceiver associated with the photonic network, in some embodiments, photonic substrate 102 can include multiple E / O transceivers, each associated with a memory unit.

[0044] In some embodiments, the photonic network may include optical circuitry connecting the memory controller to an optical interface (e.g., a fiber connector) and electrical connections between the memory controller and the memory units. For example, memory controller 106A may be connected to a fiber connector through optical circuitry and connected to memory units 104A, 104B, 104C, and 104D through electrical connections. Memory controller 106A may send and receive data signals (e.g., read and write signals) to and from memory units 104A, 104B, 104C, and 104D through the electrical connections. In such embodiments, E / O transceivers may convert data signals to and from the memory controller between electrical and optical signals. For example, E / O transceiver 114A may convert data signals to and from memory controller 106A between electrical and optical signals.

[0045] FIG. 1B illustrates a first programmed configuration 120A of photonic networks 108A and 108B in accordance with some embodiments of the techniques described herein. For example, configuration 120A of FIG. 1B may be for execution of one or more instructions by each of processors 100A and 100B. In first programmed configuration 120A, photonic network 108A is programmed to provide processor 100A with access to memory units 140A and 140C and processor 100B with access to memory units 104B and 104D. Photonic network 108B is programmed to provide processor 100A with access to memory unit 104E and processor 100B with access to memory units 104F, 104G, and 104H. As illustrated in FIG. 1B, processor 104A and all memory units accessible to it within configuration 120A are shaded with horizontal lines. Processor 100B and all memory units it can access within configuration 120A are shaded with diagonal lines.

[0046] FIG. 1C illustrates a second programmed configuration 120B of photonic networks 108A and 108B in accordance with some embodiments of the techniques described herein. For example, configuration 120B of FIG. 1C may be for execution of one or more instructions by each of processors 100A and 100B following configuration 120A of FIG. 1B. In second programmed configuration 120B, photonic network 108A is programmed to provide processor 100A with access to memory units 104A, 104B, 104C, and 104D. Photonic network 108B is programmed to provide processor 100A with access to memory units 104D and 104E, and processor 100B with access to memory units 104F and 104G. As shown in FIG. 1B, processor 104A and all memory units accessible to it in configuration 120A are shaded with horizontal lines. Processor 100B and all memory units it can access within configuration 120A are shaded with diagonal lines.

[0047] In some embodiments, each of the photonic networks 108A, 108B includes one or more photonic switches. Each of the photonic networks 108A, 108B can be programmed by configuring one or more photonic switches of the photonic network. Examples of optical switches that can be included in each of the photonic networks 108A, 108B include Mach-Zehnder interferometers, optical resonators, multi-mode interference (MMI) waveguides, arrayed waveguide gratings (AWGs), thermo-optic switches, acousto-optic switches, magneto-optic switches, micro-electromechanical switches (MEMS), optical switches, nonlinear optical switches, liquid crystal switches, piezoelectric beam steering switches, grating switches, distributed switches, and / or other suitable optical switches. In some embodiments, one or more optical switches of the photonic network can be implemented in an optical circuit. The one or more optical switches can be configured to control a path within the optical circuit. In some embodiments, one or more optical switches may be integrated within the photonic substrate 102 .

[0048] In embodiments in which the photonic substrate 102 includes memory controllers 106A, 106B, the photonic networks 108A, 108B can be programmed by the corresponding memory controllers 106A, 106B. The memory controller 106A can be configured to program the photonic network 108A, and the memory controller 106B can be configured to program the photonic network 108B. In some embodiments, each of the memory controllers 106A, 106B can be configured to program a corresponding one of the photonic networks 108A, 108B by configuring one or more switches in the photonic network. The memory controller 106A can be connected to an optical circuit that includes an optical switch that can be controlled by the memory controller 106A. The memory controller 106A can configure the optical switch in the optical circuit to control which of the memory units 104A, 104B, 104C, 104D can be accessed through the optical circuit by the processor 100A. Memory controller 106B may be connected to an optical circuit that includes an optical switch that may be controlled by memory controller 106B. Memory controller 106A may configure the optical switch in the optical circuit to control which of memory units 104E, 104F, 104G, 104H may be accessed through the optical circuit by processor 100B.

[0049] In some embodiments, the photonic networks 108A, 108B may be programmed by the processors 100A, 100B. In some embodiments, the photonic networks 108A, 108B may be programmed simultaneously by the processors 100A, 100B. The optical switches of the photonic networks 108A, 108B may be configured by the processors 100A, 100B to program the photonic networks 108A, 108B. For example, in embodiments in which the photonic substrate 102 does not include memory controllers 106A, 106B, the photonic networks 108A, 108B may be programmed by the processors 100A, 100B. Although not shown in the example of FIG. 1A , in some embodiments, the photonic networks 108A, 108B may be programmed by a separate host. For example, the host may be a CPU. For example, the CPU may have access to the configuration of some or all of the photonic networks within the photonic substrate 102.

[0050] In some embodiments, each of the E / O transceivers 114A, 114B may include an electrical-to-optical converter, such as an optical modulator, and an optical-to-electrical converter, such as an optical receiver. The electrical-to-optical converter may be configured to convert electrical data signals generated from reading a memory unit (e.g., by a memory controller) into optical signals that can be transmitted to a processor through an optical channel. The optical-to-electrical converter may be configured to convert optical signals received from a processor through an optical channel into electrical data signals for storing data in a memory unit (e.g., by a memory controller). In some embodiments, the E / O transceivers may include a shim that converts one electronic protocol to another. For example, the shim may convert signals / protocols used between the memory controller and the processor into one or more SerDes signals. These SerDes signals may then drive photonic transmission (TX) components within the large photonic interposer. The conversion may be a simple direct conversion of analog signals or a more sophisticated data conversion within the digital domain. For example, HBM3 has a bandwidth of 9.2 Gb / s per pin, but optical links can operate at even higher speeds (50-100 Gb / s per signal). Thus, multiple HBM3 pin signals can be serialized onto a single optical signal, which can then be deserialized at the receiver.

[0051] In some embodiments, each of the optical interfaces 110A, 110B can provide an interface for a corresponding optical channel 112A, 112B. In some embodiments, each of the optical channels 112A, 112B includes one or more sets of optical fibers. Each of the optical interfaces 110A, 110B can include a fiber connector and one or more ports through which the sets of optical fibers can connect to E / O transceivers. The fiber connector can include a fiber coupler (e.g., an out-of-plane coupler or an edge coupler) that can be coupled to the optical channel. The fiber coupler can enable a memory controller to communicate with a processor through the optical channel.

[0052] In some embodiments, each of memory controllers 106A, 106B may include digital circuitry for controlling the input and output of data from memory units. In some embodiments, each of memory controllers 106A, 106B may be configured to control access to a corresponding set of memory units (e.g., on-chip SRAM memory units). For example, memory controller 106A may read data from memory units 104A, 104B, 104C, 104D requested by processors 100A, 100B and write data transmitted from processors 100A, 100B to memory units 104A, 104B, 104C, 104D. In some embodiments, memory controllers 106A, 106B may be integrated memory controllers integrated with a corresponding set of memory units on the chip. In some embodiments, memory controllers 106A, 106B may be separate from memory units 104A-104H (e.g., in the case of DRAM, NVRAM, and flash memory units). Additionally, in some embodiments, the memory controllers 106A, 106B may be fabricated monolithically with the photonic substrate 102, the E / O transceivers 114A, 114B, the photonic networks 108A, 108B, and the memory units 104A-H.

[0053] In some embodiments, each of the memory controllers 106A, 106B may be configured to manage the allocation of memory units to the processors 100A, 100B. For example, the memory controller may be configured to allocate memory to the processor 100A based on a process (e.g., a software application) being executed by the processor. The memory controller may be configured to determine memory resources required for the process and allocate memory units to the processor 100A accordingly. In some embodiments, the memory controllers 106A, 106B may be configured to determine the allocation of memory units to the processors 100A, 100B based on a parallel programming model used by the process. The memory controllers 106A, 106B may allocate memory units to the processors 100A, 100B according to the parallel programming model to enable parallel execution of the process. The memory controllers 106A, 106B may be configured to program the corresponding photonic networks 108A, 108B based on the determined memory allocation.

[0054] As shown in the example of FIG. 1A , in some embodiments, processors 100A, 100B access memory units 104A-104H through corresponding optical channels 112A, 112B. In some embodiments, the optical channels may provide a path for the transmission of light. In some embodiments, the optical channels may include one or more optical fibers. For example, each optical fiber may be a strand of glass, plastic, or other suitable material that transmits light. Multiple such strands may be bundled into an optical fiber set (e.g., a fiber optic cable). In some embodiments, the optical channels may transmit data at a rate of at least 1-5, 5-10, 10-15, 15-20, 20-25, or 25-30 terabytes per second (TB / s). For example, the optical channels may transmit data between the processors and the photonic network at a rate of at least 15 TB / s. In some embodiments, each optical channel may carry one or more optical signals, for example, through the use of wavelength division multiplexing or polarization multiplexing.

[0055] In some embodiments, error correction may be used to enable higher bandwidth photonic communication. Error correction may be performed on data transmissions to and / or from memory units through a photonic network. For example, an error correction code (ECC) may be used to perform the error correction. In some embodiments, a memory controller may be configured to perform error correction on data transmissions to and from memory units. In some embodiments, processor 100A, 100B may be configured to perform error correction on data received from a memory unit. The use of error correction may enable higher bandwidth photonic communication at the expense of increased latency for performing the error correction.

[0056] FIG. 2A is a side view of a photonic substrate 200 in accordance with some embodiments of the techniques described herein. FIG. 2B is an overhead view of the photonic substrate 200. As shown in FIG. 2B, the photonic substrate 200 includes a memory controller 204, a memory stack 206A, a memory stack 206B, a memory stack 206C, and a memory stack 206D. For example, the photonic substrate 200 shown in FIG. 2A may be part of the photonic substrate 102 described herein with respect to FIGS. 1A-1C. The memory stacks 206A, 206B, 206C, and 206D may be memory units 104A, 104B, 104C, and 104D of FIGS. 1A-1C.

[0057] As shown in FIG. 2A , fiber connector 202, E / O transceiver 210, memory controller 204, memory stack 206A, and memory stack 108A are disposed on photonic substrate 200. Photonic substrate 200 further includes integrated optical circuitry 212 that can form a photonic network (e.g., photonic network 108A). Optical circuitry 212 can include integrated optical switches that can be configured to program the photonic network. As shown in FIG. 2A , optical circuitry 212 connects fiber connector 202 to E / O transceiver 210. Thus, optical signals can be transmitted to and from E / O transceiver 210 through optical circuitry 212.

[0058] In some embodiments, E / O transceiver 210 may include using wavelength division multiplexing (WDM), in which multiple signals, each at a different wavelength of light, are used to increase the transmission bandwidth within a single optical waveguide or optical fiber. Some embodiments may use dense WDM, in which wavelengths may be spaced apart at intervals of 100-200 GHz. Some embodiments may use coarse WDM, in which wavelengths may be spaced apart by more than 10 nm. Overall, WDM reduces the number of fibers that need to be attached to photonic substrate 200.

[0059] 2A, the photonic substrate includes electrical connections 214 through which electrical signals may be transmitted between E / O transceiver 210 and memory controller 204 and between memory controller 204 and memory stacks 206A, 206B, 206C, and 206D. Electrical connections 214 may be configured to transmit electrical data signals generated from reading from and writing to memory stacks 206A, 206B, 206C, and 206D. For example, electrical connections 214 may be used by memory controller 204 to derive electrical data signals from reading data from memory stacks 206A, 206B, 206C, and 206D and transmit the electrical data signals to E / O transceiver 210 (e.g., to transmit corresponding optical signals to a processor separate from photonic substrate 200). As another example, the electrical connection 214 may be used by the memory controller 204 to obtain electrical data signals from the E / O transceiver 210 corresponding to optical signals transmitted from an external processor and transmit the electrical data signals to the memory stacks 206A, 206B, 206C, 206D to write data into the memory.

[0060] In some embodiments, each of memory stacks 206A, 206B, 206C, and 206D may include a stack of dies. For example, each of memory stacks 206A, 206B, 206C, and 206D may be a stack of three dies, although other numbers of stacked dies are possible. The stack of dies may be mounted on photonic substrate 200. In some embodiments, the stack of dies may form a memory unit. In some embodiments, each of memory stacks 206A, 206B, 206C, and 206D may be any suitable type of memory. For example, each memory stack may be HBM, DDR, DDRAM, SRAM, DDR SDRAM, or other suitable type of memory.

[0061] In some embodiments, memory controller 204 may be a separate die mounted on photonic substrate 200. As described herein with respect to FIGS. 1A-1C, memory controller 204 may be configured to configure optical switches in optical circuitry 212 to configure which of memory stacks 206A, 206B, 206C, 206D are accessible by an external processor. In some embodiments, optical circuitry 212 may be configurable to allow one or more external processors to access a particular memory stack. In some embodiments, optical circuitry 212 may be configurable to allow only one external processor to access a particular memory stack at a time.

[0062] 2A, communication between fiber splice 202 and E / O transceiver 210 is performed photonically, while communication between E / O transceiver 210 and memory stack 206 is performed electrically. In other examples, as described below with respect to FIGS. 2C-2D, the fiber splice may be photonically coupled to the memory stack, and an optical switch module may be used to route the optical signals.

[0063] FIG. 2C is a side view of another photonic substrate 220 in accordance with some embodiments of the techniques described herein. As shown in FIG. 2C, the photonic substrate 220 includes a memory controller 204 and memory stacks 206A and 206B. For example, the photonic substrate 220 shown in FIG. 2C may be part of the photonic substrate 102 described herein with respect to FIGS. 1A-1C. The memory stacks 206A and 206B may be memory units 104A and 104B. The photonic substrate 220 may include other memory stacks (e.g., memory stacks 206C and 206D) not shown in FIG. 2C.

[0064] In the exemplary embodiment of FIG. 2C , the photonic substrate 220 includes a photonic network including optical circuitry 222 that provides optical channels for optical transmission between the memory stacks 206A, 206B. The optical circuitry 222 can be connected to the memory stacks of the photonic substrate 220. The optical circuitry 222 includes optical switch modules 224A, 224B that can be configured to control which of the memory stacks 206A, 206B are accessible (e.g., by a processor). The memory controller 204 can be configured to program the photonic network by configuring the optical switch modules 224A, 224B. The optical switch modules 224A, 224B are connected to the corresponding memory stacks 206A, 206B through corresponding electrical connections 230A, 230B. The electrical connections 230A, 230B can include, for example, a conductive material (e.g., metal wiring).

[0065] 2C illustrates exemplary components of an optical module. As shown within the enlarged box from optical module 224A, optical module 224A includes optical switch 226. Exemplary optical switches are described herein. Optical module 224A further includes E / O transceiver 228 for converting between optical and electrical signals. When optical switch 226 is configured to enable access to memory stack 206A, E / O transceiver 228 may be configured to convert optical signals received through optical circuit 222 (e.g., through a fiber splicer) into electrical signals that can be transmitted through electrical connection 230A. For example, E / O transceiver 228 can transmit optical data signals into electrical data signals (e.g., for writing data to memory stack 206A). E / O transceiver 228 may be further configured to convert electrical signals received through electrical connection 230A into optical signals that can be transmitted through optical circuit 222. For example, E / O transceiver 228 can convert electrical data signals obtained by reading data from memory stack 206A into optical data signals transmitted over optical circuit 222.

[0066] FIG. 2D is a side view of another photonic substrate 230 in accordance with some embodiments of the techniques described herein. As shown in FIG. 2D, the photonic substrate 230 includes memory stacks 206A and 206B. For example, the photonic substrate 230 shown in FIG. 2D may be part of the photonic substrate 102 described herein with respect to FIGS. 1A-1C. The memory stacks 206A and 206B may be memory units 104A and 104B. The photonic substrate 230 may include other memory stacks (e.g., memory stacks 206C and 206D) not shown in FIG. 2D.

[0067] In the exemplary embodiment of FIG. 2D , the photonic substrate 230 includes a photonic network including an optical circuit 222 that provides an optical channel for optical transmission between the memory stacks 206A, 206B. The optical circuit 222 can be connected to the memory stacks of the photonic substrate 220. The optical circuit 222 includes optical switch modules 224A, 224B that can be configured to control which of the memory stacks 206A, 206B are accessible (e.g., by a processor). The memory controller 204 can be configured to program the photonic network by configuring the optical switch modules 224A, 224B. The optical switch modules 224A, 224B are connected to the corresponding memory stacks 206A, 206B through corresponding electrical connections 230A, 230B. The electrical connections 230A, 230B can include, for example, a conductive material (e.g., metal wiring).

[0068] 2D , the photonic substrate 230 does not include a memory controller. In such an embodiment, the photonic network including the optical circuit 222 may be programmed by an external processor (e.g., an external memory controller or other processor connected to the photonic substrate 230). The external processor can program the photonic network by configuring the optical switches of the optical switch modules 224A, 224B. The external processor may transmit configuration instructions (e.g., over an optical channel) that are transmitted to the optical switch modules 224A, 224B through the optical circuit 222. For example, the configuration instructions may be included as prefixes and / or suffixes of data read and / or write signals.

[0069] 3 is an exemplary processor 300 of a photonic computing system in accordance with some embodiments of the techniques described herein. For example, processor 300 may be one of processors 100A, 100B described herein with respect to FIGS. 1A-1C. As shown in FIG. 3, processor 300 includes one or more compute cores 302, static RAM (SRAM) 304, E / O transceiver 308, and optional DDR or HBM 306.

[0070] In some embodiments, compute core 302 may include one or more CPUs, GPUs, NPUs, photonic processors, and / or other compute cores. SRAM 304 may be used by compute core 302 to execute instructions (e.g., as part of executing a software application program). For example, SRAM 304 may store instructions and / or data for execution by compute core 302.

[0071] In some embodiments, processor 300 may include DDR and / or HBM 306. For example, processor 300 may execute data-intensive applications and thus may use DDR and / or HBM 306. For example, processor 300 may be used to execute applications for training and / or performing inference using deep learning models. Deep learning models often use a large number of parameters (e.g., millions of weights and / or activations) and thus require additional storage capacity for processor 300. As another example, processor 300 may be used for graphics processing. Graphics processing may involve processing successive frames of thousands of pixels and thus require additional storage capacity.

[0072] 4 illustrates an exemplary parallelization paradigm that may be used by some embodiments of the techniques described herein. For example, the parallelization paradigm of FIG. 4 may be used by the photonic computing system described herein with respect to FIGS. 1A-1C. In the example of FIG. 4, the photonic computing system B (f A (x i )), where f A is an application executed by a first processor (e.g., processor 100A), and f B is an application executed by a second processor (e.g., processor 100B). i denotes the ith data point provided as input. A and f B Each of the may include one or more operations.

[0073] Execution of the process begins at step 402 by storing input x1 in memory unit 102A and input x2 in memory unit 102B. In some embodiments, inputs x1 and x2 may be loaded in parallel into corresponding memory units 104A, 104B. Processor 100A then performs a A(x1) and store the result in memory unit 104A.

[0074] Next, in step 404, photonic network 108A is programmed to provide first processor 100A with access to memory unit 104B and second processor 100B with access to memory unit 104A. First processor 100A uses input x2 stored in memory unit 104B to calculate f A In parallel with the execution of the first processor 100A, the second processor 100B executes f (x2) stored in the memory unit 104A. A Use the value of (x1) to B (f A (x1)) and stores the result in memory unit 104A.

[0075] Next, in step 406, f B (f A The result of the process f (x1) executed in step 404 is output from memory unit 104A. A The processor 104B is programmed to provide the processor 104B with access to the memory unit 104B that currently stores the result of (x2). B (f A (x2)) and stores the result in memory unit 104B.

[0076] Next, in step 408, the process f stored in memory unit 104B is B (f A The execution result of (x2)) is output from memory unit 104B. In some embodiments, a subsequent pair of inputs (e.g., x3 and x4) may be loaded into memory units 104A, 104B, and the execution process of steps 402-408 may be performed again.

[0077] In the parallelization paradigm illustrated by the example of FIG. 4, the execution of two applications is parallelized by programming the photonic network to dynamically configure which processors can access memory units through the photonic network. As a result, the input and output data of each application being executed by each processor resides in a single memory location (e.g., one or more memory units). Unlike traditional parallelization paradigms, data copying and transfer operations between memory locations can be omitted. Therefore, communication between memory units is not required. Furthermore, there is no need to allocate memory for data copying. Rather, both memory units are used to execute the applications. Furthermore, because there is only one copy of each input and the result of the application being executed using the input, coherency is automatically maintained in the parallelization paradigm.

[0078] 5A illustrates virtualization that may be performed using a computing system in accordance with some embodiments of the techniques described herein. As shown in FIG. 5A, virtualization system 500 determines the allocation of processors and corresponding sets of memory units for virtual machines 506A, 506B, and 506C. In some embodiments, virtualization system 500 may be configured to allocate processing power and memory to virtual machines 506A, 506B, and 506C using a virtual machine management software application. For example, virtualization system 500 may use VMware, Citrix Virtual Apps & Desktops, or another suitable virtual machine management software application.

[0079] The allocations of Figure 5A may be performed by programming one or more photonic networks to assign sets of memory units to sets of processors. Exemplary techniques for programming a photonic network to assign memory units to processors are described herein. In the example of Figure 5A, the photonic network is programmed to (1) assign processors 502A, 502B, 502E, and 502F of virtual machine 506A access to memory units 504A, 504B, 504C, 504D, 504E, 504F, 504G, and 504H, (2) assign processors 502C and 502G of virtual machine 506B access to memory units 504I, 504J, 504K, and 504L, and (3) assign processors 502D and 502H of virtual machine 506C access to memory units 504M, 504N, 504O, and 504P.

[0080] In some embodiments, the virtualization system 500 may be configured to assign virtual machines 506A, 506B, 506C to different users. This assignment may allow multiple different users to use virtual machines that run on a shared set of processing and memory resources. Each of the virtual machines 506A, 506B, 506C may be configured for each user by programming the photonic network to grant the virtual machine access to a set of memory units. In some embodiments, the photonic network may be dynamically reprogrammed while the virtual machines 506A, 506B, 506C are running to reallocate memory resources (e.g., based on changing memory needs of the virtual machines 506A, 506B, 506C).

[0081] 5B illustrates the reallocation of processors and memory to the virtual machines 506A, 506B, 506C of FIG. 5A in accordance with some embodiments of the techniques described herein. In some embodiments, the virtualization system 500 may be configured to reallocate resources (e.g., distribute computing resources (e.g., processing power and memory) based on the requirements of applications being executed by the virtual machines 506A, 506B, 506C and / or balance the load among the virtual machines 506A, 506B, 506C).

[0082] In some embodiments, the reallocation may be performed by programming the photonic network into a different configuration. The virtualization system 500 may be configured to determine the reallocation and trigger programming of the photonic network based on the reallocation. For example, a memory controller associated with the photonic network may program the photonic network into a new configuration based on the reallocation determined by the virtualization system 500. In the allocation of FIG. 5B, the photonic network is programmed to (1) assign processors 502A, 502B, 502E, and 502F of virtual machine 506A access to memory units 504A, 504B, 504C, and 504D, 92) assign processor 502G of virtual machine 506B access to memory units 504I and 504J, and (3) assign processors 502C, 502D, and 502H of virtual machine 506C access to memory units 504E, 504F, 504G, 504H, 504K, 504L, 504M, 504N, 504O, and 504P.

[0083] FIG. 6A illustrates an exemplary photonic computing system 600 in accordance with some embodiments of the techniques described herein. As shown in FIG. 6A, the photonic computing system includes processors 602A, 602B, and 602C connected to a photonic substrate containing photonic modules. In the example of FIG. 6A, the multiple photonic modules are memory tiles 604A, 604B, 604C, 604D, 604E, 604F, 604G, and 604H. The processors 602A, 602B, and 602C are connected to the photonic substrate by corresponding optical channels 606A, 606B, and 606C, respectively. Each of the optical channels 606A, 606B, and 606C is connected to an interface (e.g., a fiber connector) of a corresponding memory tile. As indicated by the three dots below the processors 602A, 602B, and 602C, in some embodiments, the photonic computing system 600 may include additional processors connected to the photonic substrate.

[0084] 6A, each of the memory tiles 604 (604A, 604B, 604C, 604D, 604E, 604F, 604G, 604H) includes a set of HBM memory units. Each tile has four HBM memory units. Each tile may include a photonic network that can be programmed (e.g., by a corresponding memory controller) to configure (e.g., by configuring optical switches) which of the processors 602A, 602B, 602C can access each of its HBM memory units.

[0085] FIG. 6B shows an exemplary set of connections 608A from a fiber connector of memory tile 604A to memory controllers of all memory tiles 604A-604H, in accordance with some embodiments of the techniques described herein. For example, set of connections 608A may be optical connections connecting to E / O transceivers associated with the memory controllers (e.g., co-located on the memory tile of the memory controller). As another example, set of connections 608A may be electrical connections from the E / O transceivers of memory tile 604A to the memory controllers. As shown in FIG. 6B, connections 608A enable processor 602A to communicate with each tile's memory controller through optical channel 606A. Thus, the photonic network of each of memory tiles 604A-604H may be programmed (e.g., by the tile's memory controller) to provide processor 602A with access to the tile's memory units.

[0086] FIG. 6C illustrates an exemplary set of connections 608B from a fiber connector in memory tile 604C to memory controllers in all memory tiles 604A-604H, in accordance with some embodiments of the techniques described herein. For example, set of connections 608B may be optical connections connecting to E / O transceivers associated with the memory controllers (e.g., co-located on the memory tile with the memory controller). As another example, set of connections 608B may be electrical connections from the E / O transceivers of memory tile 604B to the memory controllers. As shown in FIG. 6C, connections 608B enable processor 602B to communicate with each tile's memory controller through optical channel 606B. Thus, the photonic network of each of memory tiles 604A-604H may be programmed (e.g., by the tile's memory controller) to provide processor 602A with access to the tile's memory units.

[0087] 7A illustrates an example configuration of the photonic networks of the memory tiles 604A-604H of FIGS. 6A-6C, in accordance with some embodiments of the techniques described herein. As shown in FIG. 7A, the photonic network of each of the memory tiles 604A-604H is programmed to enable access to the HBM memory units of the tile by a processor 602A. The processor 602A can be configured to access each of the HBM memory units through the connections shown in FIG. 6B.

[0088] FIG. 7B illustrates another exemplary configuration of the photonic network of memory tiles 604A-604H of FIGS. 6A-6C in accordance with some embodiments of the techniques described herein. The exemplary configuration of the photonic network may be programmed after the configuration of FIG. 7A. As shown in FIG. 7B, the photonic network of each of memory tiles 604A-604H is programmed to allow processor 602B access to the tile's HBM memory units. Processor 602B may be configured to access each of the HBM memory units through the connections shown in FIG. 6C. In some embodiments, processor 602A may no longer have access to the HBM memory units. In some embodiments, processor 602A may have concurrent access to the HBM memory units with processor 602B.

[0089]

[0023] Figure 8 illustrates an example configuration 800 of the photonic computing system of Figure 6A in which each of the processors 602A, 602B, and 602C is designated for a different application, in accordance with some embodiments of the techniques described herein. As shown in the example of Figure 8, the processor 602A is configured to run a large-scale language model (LLM) application 802A, the processor 602B is configured to run a computer vision application 802B, and the processor 602C is configured to run a development and testing application 802C. As shown in Figure 8, each of the applications 802A, 802B, and 802C is assigned a corresponding set of memory units from the memory tiles 604A-604H. LLM application 802A is assigned two HBM memory units from tile 604A, three HBM memory units from tile 604B, one HBM memory unit from tile 604C, three HBM memory units from tile 604D, one HBM memory unit from tile 604E, three HBM memory units from tile 604F, zero HBM memory units from tile 604G, and zero HBM memory units from tile 604H. Computer vision model application 802B is assigned one HBM memory unit from tile 604A, one HBM memory unit from tile 604B, three HBM memory units from tile 604C, one HBM memory unit from tile 604D, zero HBM memory units from tile 604E, one HBM memory unit from tile 604F, one HBM memory unit from tile 604G, and three HBM memory units from tile 604H. Development and test application 802C is assigned one HBM memory unit from tile 604A, zero HBM memory units from tile 604B, zero HBM memory units from tile 604C, zero HBM memory units from tile 604D, three HBM memory units from tile 604E, zero HBM memory units from tile 604F, three HBM memory units from tile 604G, and one HBM memory unit from tile 604H.

[0090] In some embodiments, each of the applications 802A, 802B, 802C may be allocated HBM memory units based on the requirements of the applications 802A, 802B, 802C. For example, the memory units allocated to each application may be determined based on the amount of memory required to run the application.

[0091] FIG. 9 illustrates an exemplary photonic computing system 900 in which a set of processors 602A, 602B, and 602C can access multiple disjoint memory pools 904A, 904B, 904C, 904D, and 904E in accordance with some embodiments of the techniques described herein. In some embodiments, each of the memory pools 904A, 904B, 904C, 904D, and 904E can be a photonic substrate including multiple memory tiles (e.g., as shown in FIG. 6A). The processors 602A, 602B, and 602C can access the memory pools 904A-904E through an optical circuit switch 902. In some embodiments, the optical circuit switch 902 can be configured to configure which of the processors 602A, 602B, and 602C can access each of the memory pools 904A-904E. As shown in FIG. 9, each of the processors 602A, 602B, and 602C can be connected to the optical circuit switch 902 by a corresponding optical channel. Each of the processors 602A, 602B, 602C may be provided access to memory units from different ones of the memory pools 904A-904E through the optical circuit switch 902.

[0092] FIG. 10 illustrates an exemplary photonic computing system 1000 in which the memory of a computer system 1002 is augmented by multiple isolated sets of memory units 1004A, 1004B, and 1004C in accordance with some embodiments of the technology described herein. As shown in FIG. 10, the computer system 1002 is connected to each set of memory units 1004A, 1004B, and 1004C by a corresponding optical channel. In the example of FIG. 10, each set of memory units 1004A, 1004B, and 1004C includes four HBM banks as memory units. As shown in FIG. 10, the computer system 1002 has 96 GB of native memory. The computer system 1002 augmented with one set of memory units has 192 GB of memory. The computer system 1002 augmented with two sets of memory units has 288 GB of memory. The computer system 1002 augmented with three sets of memory has 384 GB of memory.

[0093] 11 is an exemplary process 1100 for programming a photonic network in accordance with some embodiments of the techniques described herein. In some embodiments, process 1100 may be performed using a programmable photonic network that controls which of a set of one or more processors may access memory units of memory separate from the processors. For example, process 1100 may be performed by the photonic computing system described herein with respect to FIGS. 1A-1C.

[0094] Process 1100 begins at block 1102, where a system determines a memory allocation indicating which memory units may be accessed by each of a set of processors. In some embodiments, the system may be configured to determine a memory allocation for a virtual CPU (e.g., a virtual machine as described herein with respect to FIGS. 5A-5B). In some embodiments, the system may be configured to determine a memory allocation based on the requirements of one or more processes (e.g., software applications) executed by the system. In some embodiments, the system may be configured to determine a memory allocation for a stage of parallelized execution of a process (e.g., as described herein with respect to FIG. 4). As an illustrative example, the system may determine, for each of a set of processors, a memory allocation indicating which memory units may be accessed by the processor.

[0095] Next, process 1100 proceeds to block 1104, where the system determines a configuration of the photonic network based on the memory allocation. In some embodiments, the photonic network may include an optical circuit including one or more configurable optical switches. The system may be configured to determine the configuration of the photonic network by determining a configuration of the one or more optical switches according to the memory allocation. The configuration of the one or more optical switches may configure the photonic network such that each of a set of processors has access to the memory units indicated by the memory allocation.

[0096] Process 1100 then proceeds to block 1106, where the system programs the photonic network to the determined configuration. In some embodiments, the system may be configured to program the photonic network to its configuration by configuring one or more optical switches of the photonic network. The system may be configured to configure one or more optical switches to enable optical circuits of the photonic network to communicate between each of a set of processors and its assigned memory unit. For example, the configuration may enable a set of processors to read data from and write data to their respective assigned memory units.

[0097] 12 is an exemplary process 1200 for executing software applications in parallel, according to some embodiments of the techniques described herein. In some embodiments, process 1200 may be performed by a photonic computing system described herein with respect to FIGS. 1A-1C. In some embodiments, process 1200 may be performed when two processors are each configured to execute a corresponding application (e.g., one or more operations) to parallelize the execution of the software applications (e.g., as described herein with respect to FIG. 4).

[0098] In some embodiments, prior to performing process 1200, input data may be loaded into one or more of the memory units used in executing the software application. The one or more memory units may include a first memory unit and a second memory unit. The first memory unit may have data stored therein. For example, inputs used in executing the software application may be stored in the first memory unit. In some embodiments, the photonic network of the system may be programmed into a particular configuration prior to performing process 1200. The photonic network may be programmed such that a first processor has access to the first memory unit and a second processor has access to the second memory unit.

[0099] Process 1200 begins at block 1202, where a first processor performs one or more operations using data stored in a first memory unit to obtain a first output. In some embodiments, the operations may be operations performed in response to execution of instructions of a software application program. For example, the first processor may perform one or more functions using one or more numerical values stored in the first memory unit. Process 1200 then proceeds to block 1204, where the system stores a first output resulting from execution of the operations at block 1202 in the first memory unit.

[0100] Process 1200 then proceeds to block 1206, where the system programs the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor. In some embodiments, the system may be configured to program the photonic network as described in process 1100 described herein with respect to Figure 11. For example, the system may configure optical switches of the optical circuit to program the photonic network.

[0101] Process 1200 then proceeds to block 1208, where the first processor performs an operation using the data stored in the second memory unit to obtain a second output. In some embodiments, the first processor may be configured to perform the same operation as performed in block 1202, but using the data stored in the second memory unit. For example, the first processor may perform one or more functions using values stored in the second memory unit.

[0102] At block 1210, the second processor performs operations using the first output stored in the first memory unit in parallel with the execution of the first processor at block 1208. In some embodiments, the second processor may be configured to execute another software application using the first output stored in the first memory unit. For example, the output of the operation performed by the first operation is further processed by the second processor to generate a final output.

[0103] Process 1200 then proceeds to block 1212, where the system stores in a second memory unit the second output obtained in block 1208. In block 1214, the system outputs from the first memory unit the result of the operation performed by the second processor in block 1210. The output result may be an output corresponding to the input originally stored in the first memory unit.

[0104] Process 1200 then proceeds to block 1216, where the system programs the photonic network to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor. Process 1200 then returns to block 1202, where the system processes subsequent inputs (e.g., more numerical values). Process 1200 can then proceed through blocks 1202-1216 of process 1200.

[0105] 13 is an exemplary computer system that may be used to implement some implementations of the techniques described herein. The computing device 1300 may include one or more computer hardware processors 1302 and non-transitory computer-readable storage media (e.g., memory 1304 and one or more non-volatile storage devices 1306). The processor 1302 may control the reading and writing of data from and to (1) the memory 1304 and (2) the non-volatile storage device 1306. To perform any of the functions described herein, the processor 1302 may execute one or more processor-executable instructions stored in one or more non-transitory computer-readable storage media (e.g., memory 1304), which may function as non-transitory computer-readable storage media storing processor-executable instructions for execution by the processor 1302.

[0106] As used herein, the terms "program" or "software" are used in a generic sense to refer to any type of computer code or set of processor-executable instructions that can be used to program a computer or other (physical or virtual) processor to implement various aspects of the embodiments discussed above. Additionally, according to one aspect, one or more computer programs that, when executed, perform the methods of the disclosure provided herein need not reside on a single computer or processor, but may be modularly distributed among different computers or processors to implement various aspects of the disclosure provided herein.

[0107] Processor-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform tasks or implement abstract data types. Typically, the functionality of program modules may be combined or distributed.

[0108] Some embodiments provide a photonic computing system including at least one processor, at least one optical channel, and at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for providing the at least one processor with access to the plurality of memory units, the at least one photonic network communicating with the at least one processor through the at least one optical channel, and the at least one photonic network being programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor may access through the at least one optical channel.

[0109] In some embodiments, a photonic computing system may include one or more of the following attributes: a. the at least one processor includes a first processor and a second processor, and the first processor and the second processor are configured to process the data set using a plurality of memory units.

[0110] b. the at least one photonic network is programmed to enable access by a first processor to a first memory unit of the plurality of memory units and to enable access by a second processor to a second memory unit of the plurality of memory units; Processing the stored data set includes: i. performing, by a first processor, an operation using data stored in a first memory unit to obtain a first output; ii. storing the first output in a first memory unit; and Includes:

[0111] c. after storing the first output in the first memory unit, the at least one photonic network is programmed to enable access to the first memory unit by a second processor and to enable access to the second memory unit by the first processor, and processing the stored data set includes: i. performing, by the first processor, an operation using data stored in the second memory unit to obtain a second output; ii. performing, by a second processor, in parallel with execution by the first processor, an operation using the first output stored in the first memory unit to obtain a first result; iii. storing the second output in a second memory unit; and iv. outputting the first result from the first memory unit; and Further includes:

[0112] d. the at least one photonic network is programmed to enable access to the first memory unit by the first processor and to enable access to the second memory unit by the second processor, and processing the data sets stored in the plurality of memory units of the at least one photonic network includes: i. performing, by the first processor, an operation using the data stored in the first memory unit to obtain a third output; ii. performing, by a second processor, in parallel with the execution of the first processor, an operation using the second output stored in the second memory unit to obtain a second result; iii. storing the third output in the first memory unit; and iv. outputting the second result from the second memory unit; and Further includes:

[0113] e. The at least one photonic network is programmed to enable access by the at least one processor to a subset of the plurality of memory units over at least one optical channel.

[0114] f. The at least one optical channel is configured to transmit data between the at least one processor and the at least one photonic network at a rate of at least 15 terabytes per second (TB / s).

[0115] g. the at least one photonic network includes at least one optical switch configurable to connect / disconnect the at least one processor to each of the plurality of memory units, and the at least one photonic network is programmable by configuring the at least one optical switch.

[0116] h. at a first point in time, the at least one photonic network is programmed to enable access by the at least one processor to a first memory unit of the plurality of memory units over at least one optical channel, and at a second point in time subsequent to the first point in time, the at least one photonic network is programmed to: i. disabling access by at least one processor to the first memory unit through at least one optical channel; and ii. enabling access by at least one processor to a second memory unit of the plurality of memory units over at least one optical channel; It is programmed as follows.

[0117] i. the at least one processor includes a first processor and a second processor, the plurality of memory units includes a first memory unit and a second memory unit, and the at least one photonic network is programmed to enable access to the first memory unit by the first processor and access to the second memory unit by the second processor.

[0118] j. The plurality of memory units includes a plurality of high bandwidth memory (HBM) units. k. The plurality of memory units includes a plurality of static random access memory (SRAM) units.

[0119] l. The plurality of memory units includes a plurality of double data rate (DDR) synchronous dynamic random access memories (SDRAMs).

[0120] m. The at least one photonic substrate further includes at least one memory controller configured to program the at least one photonic network. n. The at least one processor is configured to program the at least one photonic network.

[0121] o. the at least one processor includes a plurality of processors, the plurality of processors being organized into a plurality of sets of processors, and the at least one photonic network being programmed to enable each of the sets of processors to access a different subset of the plurality of memory units through at least one optical channel.

[0122] p. Each of the set of processors and a corresponding subset of the plurality of memory units accessible by the set of processors forms a corresponding virtual processor that is assigned to a corresponding virtual machine.

[0123] q. The at least one processor includes a plurality of processors, the at least one optical channel includes a plurality of optical channels, and each of the plurality of processors communicates with the at least one photonic network through a corresponding one of the plurality of optical channels.

[0124] r. the at least one photonic network includes a plurality of photonic networks, and the at least one photonic substrate includes: i. a corresponding one of the plurality of photonic networks; and ii. a subset of the plurality of memory units; iii. Memory controller and The photonic module includes a plurality of photonic modules each including:

[0125] s. Each of the plurality of processors is connected to a memory controller of the plurality of photonic modules through a corresponding one of the plurality of optical channels. t. At least one photonic network is programmed with a configuration for allocating memory units among a plurality of processors based on memory requirements for executing a plurality of software applications, the configuration comprising: i. enabling access to a first set of a plurality of memory units by a first processor of a plurality of processors configured to execute a first software application; and ii. enabling access to a second set of the plurality of memory units by a second processor of the plurality of processors configured to execute a second software application.

[0126] u. The first software application uses a machine learning model. v. The machine learning model is a large-scale language model (LLM). w. The machine learning model is a computer vision model.

[0127] x. The first software application is a software development and testing application. y. the at least one photonic substrate includes a plurality of photonic substrates, each of the plurality of photonic substrates including a set of memory units and a corresponding photonic network; i. Each of the photonic networks of the plurality of substrates is programmable to configure which of a corresponding set of memory units may be accessed by the at least one processor.

[0128] z. The optical computing system further includes an optical switch, the optical switch configurable to provide the at least one processor with access to a plurality of memory units distributed across a plurality of photonic substrates of the plurality of photonic substrates.

[0129] aa. The at least one photonic substrate includes at least one memory controller, and the at least one photonic network includes optical circuitry interconnecting the at least one memory controller with a plurality of memory units.

[0130] bb. The at least one photonic network includes a plurality of electrical / optical (E / O) transceivers connecting corresponding ones of the plurality of memory units to an optical circuit.

[0131] cc. The at least one photonic substrate includes at least one memory controller, at least one fiber connector connected to at least one optical channel, and at least one E / O transceiver, and the at least one photonic network includes optical circuitry connecting the at least one memory controller to the at least one fiber connector, and the E / O transceiver is configured to convert signals transmitted between the at least one memory controller and the at least one fiber connector.

[0132] dd. The at least one photonic network includes a plurality of electrical connections between the at least one memory controller and the plurality of memory units, and data signals are transmitted between the at least one memory controller and the plurality of memory units through the plurality of electrical connections.

[0133] Some embodiments provide a method of using a photonic network to perform parallelized data processing using multiple memory units. The photonic network is programmable to configure which of the multiple memory units can be accessed by a first processor and a second processor. The photonic network is programmed to allow access to a first memory unit of the multiple memory units by the first processor and to allow access to a second memory unit of the multiple memory units by the second processor. The method includes programming the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor; performing, by the first processor, an operation using data stored in the second memory unit to obtain an output; and performing, by the second processor, an operation using the data stored in the first memory unit in parallel with the execution of the first processor.

[0134] In some embodiments, the method may include one or more of the following attributes: a. The method further includes the steps of programming the photonic network to allow access to the first memory unit by a first processor and to allow access to the second memory unit by a second processor, performing, by the first processor, an operation using data stored in the first memory unit, and performing, by the second processor, an operation using data stored in the second memory unit in parallel with the execution of the first processor.

[0135] b. The method further includes storing in the second memory unit results of operations performed by the first processor using data stored in the second memory unit.

[0136] Some embodiments provide a photonic network disposed on a photonic substrate, the photonic network being accessible through at least one optical channel, the photonic network including a plurality of memory units, at least one configurable optical switch that controls which of the plurality of memory units are accessible through the at least one optical channel, and at least one electrical / optical (E / O) transceiver for transmitting data to and from the plurality of memory units through the at least one optical channel.

[0137] In some embodiments, a photonic network may have one or more of the following attributes: a. At a first time point, the at least one optical switch is configured to enable access to a first memory unit of the plurality of memory units through at least one optical channel, and at a second time point subsequent to the first time point, the at least one optical switch is configured to enable access to a second memory unit of the plurality of memory units through the at least one optical channel.

[0138] b. At a second point in time, the at least one optical switch is programmed to disable access to the second memory unit through the at least one optical channel. c. The photonic network further includes a memory controller, and the at least one optical switch is configurable by the memory controller.

[0139] d. The photonic network includes an optical circuit, the optical circuit including at least one configurable optical switch. e. The at least one E / O transceiver includes a plurality of E / O transceivers connected to corresponding ones of the plurality of memory units, and the optical circuit connects the memory controller to the plurality of memory units through the plurality of E / O transceivers.

[0140] f. The photonic network includes a fiber connector, and the optical circuit connects the memory controller to the fiber connector through at least one E / O transceiver. Some embodiments provide a method of fabricating a photonic computing system, the method comprising fabricating the photonic computing system to include at least one processor, at least one optical channel, and at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for connecting the at least one processor to the plurality of memory units, the at least one photonic network communicating with the at least one processor over the at least one optical channel, and the at least one photonic network being programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor may access over the at least one optical channel.

Claims

1. 1. A photonic computing system, comprising: at least one processor; at least one optical channel; at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for providing the at least one processor with access to the plurality of memory units; Including, the at least one photonic network communicating with the at least one processor over the at least one optical channel; the at least one photonic network is programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor can access through the at least one optical channel.

2. 10. The photonic computing system of claim 1, the at least one processor includes a first processor and a second processor; The photonic computing system, wherein the first processor and the second processor are configured to process a data set using the plurality of memory units.

3. 10. A photonic computing system according to claim 2 or any preceding claim, comprising: the at least one photonic network is programmed to enable access by the first processor to a first memory unit of the plurality of memory units and to enable access by the second processor to a second memory unit of the plurality of memory units; Processing the dataset includes: performing, by the first processor, an operation using data stored in the first memory unit to obtain a first output; storing the first output in the first memory unit; A photonic computing system comprising:

4. 10. A photonic computing system according to claim 3 or any preceding claim, comprising: after storing the first output in the first memory unit, the at least one photonic network is programmed to allow access to the first memory unit by the second processor and to allow access to the second memory unit by the first processor; Processing the dataset includes: performing, by the first processor, an operation using the data stored in the second memory unit to obtain a second output; performing, by the second processor, in parallel with execution by the first processor, an operation using the first output stored in the first memory unit to obtain a first result; storing the second output in the second memory unit; and outputting the first result from the first memory unit; and The photonic computing system further comprises:

5. 10. A photonic computing system according to claim 4 or any preceding claim, comprising: the at least one photonic network is programmed to enable access to the first memory unit by the first processor and to enable access to the second memory unit by the second processor; Processing the data sets stored in the plurality of memory units of the at least one photonic network comprises: performing, by the first processor, an operation using the data stored in the first memory unit to obtain a third output; performing, by the second processor, in parallel with execution by the first processor, an operation using the second output stored in the second memory unit to obtain a second result; storing the third output in the first memory unit; and outputting the second result from the second memory unit; and The photonic computing system further comprises:

6. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: The at least one photonic network is programmed to enable access by the at least one processor to a subset of the plurality of memory units over the at least one optical channel.

7. 10. A photonic computing system according to claim 1 or any preceding claim, comprising:

1. A photonic computing system, wherein the at least one optical channel is configured to transmit data between the at least one processor and the at least one photonic network at a rate of at least 15 terabytes per second (TB / s).

8. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: the at least one photonic network includes at least one optical switch configurable to connect / disconnect the at least one processor to / from each of the plurality of memory units; A photonic computing system, wherein the at least one photonic network is programmable by configuring the at least one optical switch.

9. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: at a first point in time, the at least one photonic network is programmed to enable access by the at least one processor to a first memory unit of the plurality of memory units over the at least one optical channel; At a second time point subsequent to the first time point, the at least one photonic network Disabling access by the at least one processor to the first memory unit over the at least one optical channel; and A photonic computing system programmed to enable access by the at least one processor to a second memory unit of the plurality of memory units over the at least one optical channel.

10. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: the at least one processor includes a first processor and a second processor; the plurality of memory units includes a first memory unit and a second memory unit; 1. A photonic computing system, wherein the at least one photonic network is programmed to enable access to the first memory unit by the first processor and to enable access to the second memory unit by the second processor.

11. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of memory units comprises a plurality of high bandwidth memory (HBM) units.

12. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of memory units comprises a plurality of static random access memory (SRAM) units.

13. 10. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of memory units comprises a plurality of double data rate (DDR) synchronous dynamic random access memories (SDRAMs).

14. 10. The photonic computing system of claim 1 or any preceding claim, wherein the at least one photonic substrate further comprises at least one memory controller configured to program the at least one photonic network.

15. 10. The photonic computing system of claim 1 or any preceding claim, wherein the at least one processor is configured to program the at least one photonic network.

16. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: the at least one processor includes a plurality of processors, the plurality of processors being organized into a plurality of sets of processors; The photonic computing system, wherein the at least one photonic network is programmed to enable each of the set of processors to access a different subset of the plurality of memory units through the at least one optical channel.

17. 19. A photonic computing system according to claim 16 or any preceding claim, comprising: Each of the set of processors and a corresponding subset of the plurality of memory units accessible by the set of processors forms a corresponding virtual processor that is assigned to a corresponding virtual machine.

18. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: the at least one processor includes a plurality of processors; the at least one optical channel includes a plurality of optical channels; A photonic computing system, wherein each of the plurality of processors communicates with the at least one photonic network over a corresponding one of the plurality of optical channels.

19. 19. A photonic computing system according to claim 18 or any preceding claim, comprising: the at least one photonic network includes a plurality of photonic networks; The at least one photonic substrate includes a plurality of photonic modules, each photonic module comprising: a corresponding one of the plurality of photonic networks; and a subset of the plurality of memory units; Memory controller and A photonic computing system comprising:

20. 20. The photonic computing system of claim 19 or any preceding claim, wherein each of the plurality of processors is connected to a memory controller of the plurality of photonic modules through a corresponding one of the plurality of optical channels.

21. 19. A photonic computing system according to claim 18 or any preceding claim, wherein the at least one photonic network is programmed with a configuration for allocating memory units among the plurality of processors based on memory requirements for executing a plurality of software applications, the configuration comprising: enabling access to a first set of the plurality of memory units by a first processor of the plurality of processors configured to execute a first software application; and A photonic computing system that enables access to a second set of the plurality of memory units by a second processor of the plurality of processors that is configured to execute a second software application.

22. 22. The photonic computing system of claim 21 or any preceding claim, wherein the first software application uses a machine learning model.

23. 23. The photonic computing system of claim 22 or any preceding claim, wherein the machine learning model is a large-scale language model (LLM).

24. 23. The photonic computing system of claim 22 or any preceding claim, wherein the machine learning model is a computer vision model.

25. 22. The photonic computing system of claim 21 or any preceding claim, wherein the first software application is a software development and testing application.

26. 10. The photonic computing system of claim 1 or any preceding claim, wherein the at least one photonic substrate comprises a plurality of photonic substrates, each of the plurality of photonic substrates comprising a set of memory units and a corresponding photonic network; A photonic computing system, wherein each of the photonic networks of the plurality of substrates is programmable to configure which of a corresponding set of the memory units can be accessed by the at least one processor.

27. 27. The photonic computing system of claim 26 or any preceding claim, comprising an optical switch configurable to provide at least one processor with access to a plurality of memory units distributed across a plurality of photonic substrates of the plurality of photonic substrates.

28. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: the at least one photonic substrate includes at least one memory controller; The at least one photonic substrate includes at least one memory controller, and the at least one photonic network includes optical circuitry interconnecting the at least one memory controller with the plurality of memory units.

29. 29. The photonic computing system of claim 28 or any preceding claim, wherein each of the at least one photonic network includes a plurality of electrical / optical (E / O) transceivers connecting a corresponding one of the plurality of memory units to the optical circuitry.

30. 10. A photonic computing system according to claim 1 or any preceding claim, comprising: The at least one photonic substrate comprises: at least one memory controller; at least one fiber connector connected to said at least one optical channel; at least one E / O transceiver; Including, 1. A photonic computing system comprising: a first interconnect; a second interconnect; and an E / O transceiver configured to convert signals transmitted between the first interconnect and the second interconnect;

31. 31. The photonic computing system of claim 30 or any preceding claim, wherein the at least one photonic network includes a plurality of electrical connections between the at least one memory controller and the plurality of memory units, and wherein data signals are transmitted between the at least one memory controller and the plurality of memory units through the plurality of electrical connections.

32. 1. A method of using a photonic network for parallelized data processing using a plurality of memory units, the photonic network being programmable to configure which of the plurality of memory units may be accessed by a first processor and a second processor, the photonic network being programmed to allow access to a first memory unit of the plurality of memory units by the first processor and to allow access to a second memory unit of the plurality of memory units by the second processor; The method comprises: programming the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor; performing, by the first processor, an operation using the data stored in the second memory unit to obtain a second output; performing, by the second processor, operations using data stored in the first memory unit in parallel with execution by the first processor; A method comprising:

33. 32. A method according to claim 32 or any preceding claim, comprising: programming the photonic network to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor; performing, by the first processor, an operation using data stored in the first memory unit; performing, by the second processor, operations using data stored in a second memory unit in parallel with execution of the first processor; The method further comprises:

34. 32. A method according to claim 32 or any preceding claim, comprising: The method further comprising storing in the second memory unit results of operations performed by the first processor using the data stored in the second memory unit.

35. A photonic network disposed on a photonic substrate, said photonic network being accessible through at least one optical channel, said photonic network comprising: a plurality of memory units; at least one configurable optical switch that controls which of the plurality of memory units are accessible through the at least one optical channel; at least one electrical / optical (E / O) transceiver for transmitting data to and from said plurality of memory units over said at least one optical channel.

36. 36. A photonic network according to claim 35 or any preceding claim, comprising: at a first time, the at least one optical switch is configured to enable access to a first memory unit of the plurality of memory units over the at least one optical channel; At a second time point subsequent to the first time point, the at least one optical switch is configured to enable access to a second memory unit of the plurality of memory units through the at least one optical channel.

37. 36. A photonic network according to claim 35 or any preceding claim, comprising: At the second point in time, the at least one optical switch is programmed to disable access to the second memory unit through the at least one optical channel.

38. 36. The photonic network of claim 35 or any preceding claim, further comprising a memory controller, wherein the at least one optical switch is configurable by the memory controller.

39. 39. The photonic network of claim 38 or any preceding claim, comprising an optical circuit, the optical circuit comprising at least one configurable optical switch.

40. 39. A photonic network according to claim 38 or any preceding claim, comprising: the at least one E / O transceiver includes a plurality of E / O transceivers connected to corresponding ones of the plurality of memory units; The optical circuit connects the memory controller to a plurality of memory units through the plurality of E / O transceivers.

41. The photonic network of claim 38 or any preceding claim, further comprising a fiber connector; The optical circuit connects the memory controller to the fiber connector through the at least one E / O transceiver.

42. 1. A method of manufacturing a photonic computing system, comprising: at least one processor; at least one optical channel; fabricating the photonic computing system to include at least one photonic substrate separate from the at least one processor, the at least one photonic substrate including a plurality of memory units and at least one photonic network for connecting the at least one processor to the plurality of memory units; the at least one photonic network communicating with the at least one processor over the at least one optical channel; a first optical channel for accessing a plurality of memory units in the at least one photonic substrate; a second optical channel for accessing a plurality of memory units in the at least one photonic substrate;

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