Method for optimizing post-deposition bake conditions for photoresist materials - Patents.com

Abstract

Embodiments disclosed herein include a method for optimizing a post-deposition bake of a photoresist layer. In one embodiment, the method includes depositing a photoresist layer on a substrate, baking the photoresist layer, and measuring properties of the photoresist layer with an optical tool.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 18 / 204,805, filed June 1, 2023, which claims priority to U.S. Provisional Patent Application No. 63 / 388,205, filed July 11, 2022, the entire contents of which are incorporated herein by reference.

[0002] Field FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of semiconductor processing, and more particularly to methods for depositing photoresist materials and optimizing post-apply bake (PAB) conditions to improve photoresist performance. [Background technology]

[0003] Lithography has been used for decades in the semiconductor industry to create 2D and 3D patterns in microelectronic devices. The lithography process involves spin-on deposition of a film (photoresist), irradiating (exposing) the film with a selected pattern by an energy source, and removing (etching) the exposed (positive tone) or unexposed (negative tone) areas of the film by dissolving in a solvent. A bake may be performed to remove any remaining solvent.

[0004] Photoresists must be radiation-sensitive materials, and upon irradiation, a chemical transformation occurs in the exposed portions of the film, which can change the solubility between the exposed and unexposed regions. This change in solubility can be used to remove (etch) the exposed or unexposed areas of the photoresist. The photoresist is then developed, and the pattern can be transferred by etching into the underlying thin film or substrate. After the pattern is transferred, the remaining photoresist is removed, and this process can be repeated multiple times to obtain 2D and 3D structures used in microelectronic devices.

[0005] Several properties are important in lithography processes. These properties include sensitivity, resolution, lower line-edge roughness (LER), etch resistance, and the ability to form thinner layers. The higher the sensitivity, the lower the energy required to change the solubility of the film during deposition. This can increase the efficiency of the lithography process. Resolution and LER determine how narrow features can be achieved by the lithography process. Pattern transfer that forms deep structures requires a material with higher etch resistance. Also, the higher the etch resistance of the material, the thinner the film can be obtained. Thinner films increase the efficiency of the lithography process. Summary of the Invention

[0006] Embodiments disclosed herein include a method for optimizing a post-deposition bake of a photoresist layer. In one embodiment, the method includes depositing a photoresist layer on a substrate, baking the photoresist layer, and measuring properties of the photoresist layer with an optical tool.

[0007] Embodiments may also include a method of optimizing a post-apply bake (PAB) of a photoresist layer. In one embodiment, the method includes depositing a first photoresist layer on a first substrate, baking the first photoresist layer with the first PAB, measuring material properties of the first photoresist layer with an optical tool during or after the first PAB, depositing a second photoresist layer on a second substrate, baking the second photoresist layer with the second PAB, measuring material properties of the second photoresist layer with an optical tool during or after the second PAB, and selecting a photoresist layer having material properties that provide the most desirable linewidth roughness, line edge roughness, and / or sensitivity to radiation exposure.

[0008] Embodiments also include a semiconductor processing tool that includes a deposition module configured to deposit a photoresist layer on a substrate using a dry deposition process, a post apply bake (PAB) module configured to bake the photoresist layer, and an optical tool for measuring one or more properties of the photoresist layer during or after baking. [Brief explanation of the drawings]

[0009] [Figure 1] 1A-1D are cross-sectional views illustrating various steps in a patterning process using a negative photoresist material formed by the processes described herein, according to embodiments of the present disclosure. [Figure 2] FIG. 1 is a process flow diagram of a process for optimizing the post-apply bake (PAB) of a photoresist layer to improve its post-exposure and development properties, according to an embodiment of the present disclosure. [Figure 3] 1 illustrates various resist microstructures associated with increasing bake temperatures, according to embodiments of the present disclosure. [Figure 4A] 1 is a graph of the reflectivity of a photoresist layer with and without a bake step according to an embodiment of the present disclosure. [Figure 4B] 1 is a graph of the extinction coefficient at different wavelengths at different PAB bake temperatures, according to an embodiment of the present disclosure. [Figure 4C] 1 is a graph of the change in thickness of a photoresist layer after different PAB bake temperatures according to an embodiment of the present disclosure. [Figure 5A] FIG. 1 is a flow diagram illustrating a process for developing a photoresist layer in different tools to optimize contrast curve performance of the photoresist layer according to an embodiment of the present disclosure. [Figure 5B] FIG. 1 is a flow diagram illustrating a process for analyzing optical properties of a photoresist layer within a single tool according to an embodiment of the present disclosure. [Figure 6] 1 is a cross-sectional view of a processing tool configured to deposit a photoresist layer and measure post-PAB optical properties according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a block diagram of an exemplary computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Described herein are methods for optimizing the post-apply bake (PAB) performance of a photoresist layer using in-situ or ex-situ optical metrology tools. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. It will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known aspects have not been described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments illustrated in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0011] To provide background, photoresist systems used in extreme ultraviolet (EUV) lithography suffer from low efficiency. Existing photoresist material systems for EUV lithography require high application rates to provide the solubility transitions required to enable development of the photoresist material. Traditionally, organic, carbon-based films called chemically amplified photoresists (CARs) have been used as photoresists. However, more recently, organic-inorganic hybrid materials (metal-oxo) have been used as photoresists using extreme ultraviolet (EUV) radiation. These materials typically contain metals (e.g., Sn, Hf, Zr), oxygen, and carbon. The transition from deep UV (DUV) to EUV in the lithography industry has made it easier to achieve narrow features with high aspect ratios. Metal-oxo organic-inorganic hybrid materials have been shown to exhibit lower line edge roughness (LER) and higher resolution, which are required to form narrow features. Furthermore, such films have higher sensitivity and etch resistance, and can be fabricated to produce relatively thin films.

[0012] Currently, metal-oxo photoresists are deposited by a wet spin-on method. A post-bake process is required to remove any remaining solvent from the film and stabilize the film. Wet methods can also produce large amounts of wet waste, which the industry desires to eliminate. Photoresist films deposited by spin-on methods often result in non-uniformity issues. Addressing one or more of the above issues, according to embodiments of the present disclosure, a process for vacuum deposition of metal-oxo positive photoresists is described herein.

[0013] More specifically, embodiments disclosed herein include methods for optimizing the performance of photoresist films. Optimization relies on optical inspection of the films during and / or after post-apply bake (PAB). Material properties, such as, but not limited to, refractive index, dielectric constant, thickness, reflectivity, and / or extinction coefficient, can be used as a guide to select optimal PAB conditions. Optical tools, such as reflectometry, ellipsometry, and other optical techniques, can be used to predict and optimize the best temperature and duration that allows reconfiguring the photoresist film to optimize its sensitivity to patterned radiation exposure. Additionally, correlations between optical properties and linewidth roughness and lineedge roughness can also be used to further optimize the photoresist film. In certain embodiments, the photoresist film can include a metal-oxo photoresist system, such as those described above. In other embodiments, the photoresist film can be any type of CAR material system.

[0014] In some embodiments, the optical inspection is implemented by an in-situ optical tool. The in-situ optical tool is integrated into a tool that implements the PAB process. In one embodiment, the PAB process is implemented in the same tool used to deposit the photoresist. For example, a resistive heater in the chuck may be used to bake the photoresist. An optical tool may be provided on the opposite side of the chuck to measure one or more optical properties and / or thickness of the photoresist. Such an embodiment is particularly advantageous because it does not require transferring a substrate (e.g., a wafer) between tools.

[0015] Additionally, embodiments disclosed herein enable optimization of a photoresist layer without the need to expose and develop the photoresist layer. The exposure and development process is a very time-consuming and expensive process. To generate a contrast curve typical of photoresist analysis, multiple substrates with photoresist layers must be formed, exposed, and developed. Such a process is expensive. In embodiments disclosed herein, the optical properties and / or thickness of the photoresist layer can be used to identify trends that can lead to a more optimal PAB process. Thus, the cost and duration of photoresist layer optimization are significantly reduced.

[0016] FIG. 1 is a cross-sectional view illustrating various steps in a patterning process using a negative photoresist material formed by the process described herein, according to an embodiment of the present disclosure.

[0017] As shown in portion (a) of Figure 1, the starting structure 100 includes a negative photoresist layer 104 on a substrate or underlayer 102. In one embodiment, the negative photoresist layer 104 is deposited using a dry deposition process. After the deposition process, a PAB can be implemented on the photoresist layer 104. The PAB can modify the material properties of the photoresist layer 104 to improve the performance of the subsequently developed photoresist layer 104.

[0018] In part (b) of Figure 1, the starting structure 100 is irradiated 106 at selected locations to form an irradiated photoresist layer 104A having irradiated areas 105B and non-irradiated areas 105A. In part (c) of Figure 1, a removal or etching process 108 is used to provide a developed photoresist layer in the non-irradiated areas 105A. In part (d) of Figure 1, an etching process 110, using the non-irradiated areas 105A as a mask, is used to pattern the substrate or underlayer 102 to form a patterned substrate or patterned underlayer 102A including etched features 112.

[0019] As shown in Figure 1, the negative photoresist 104 must be a radiation-sensitive material, and upon irradiation, a chemical transformation occurs in the exposed portions of the film, which can result in a change in solubility between the exposed and unexposed regions. The change in solubility is used to remove (etch) the exposed areas of the negative photoresist. The negative photoresist is then developed, and a pattern can be transferred by etching into the underlying thin film or substrate. After the pattern is transferred, the remaining negative photoresist is removed. This process can be repeated multiple times to fabricate 2D and 3D structures, for example, for use in microelectronic devices.

[0020] FIG. 2 illustrates a process flow diagram of a process 280 for optimizing a photoresist film, according to one embodiment. In one embodiment, process 280 begins at step 281, which includes depositing a photoresist layer on a substrate. In one embodiment, the photoresist layer is deposited using a dry deposition process, such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma-enhanced ALD (PE-ALD) process, or a plasma-enhanced CVD (PE-CVD) process. While embodiments using dry deposition processes are described herein, it should be noted that embodiments disclosed herein may also include the use of wet deposition processes. In certain embodiments, the photoresist layer may be a metal-oxo photoresist layer. In other embodiments, the photoresist layer may include any CAR material system. In one embodiment, the substrate may be a wafer, such as a semiconductor wafer. For example, the substrate may be a silicon wafer having any suitable form factor (e.g., 300 mm, 450 mm, etc.).

[0021] In one embodiment, process 280 may continue with step 282, which includes performing a PAB on the photoresist layer. The PAB process may include exposing the photoresist layer to an elevated temperature. For example, the temperature may be between 15° C. and 300° C. In certain embodiments, the temperature may be between 50° C. and 250° C. In one embodiment, the duration of the PAB may be between 30 seconds and 5 minutes. The elevated temperature may be provided by any heating architecture. In some embodiments, the chuck supporting the substrate may include a resistive heating element, or the like. In other embodiments, one or more lamps may be used to heat the photoresist layer.

[0022] In one embodiment, process 280 may continue at step 283, which includes measuring properties of the photoresist layer with an optical tool. In one embodiment, the optical tool may include single-lamp reflectance measurement, dual-lamp reflectance measurement, ellipsometry, or UV-Vis absorbance measurement. In one embodiment, the properties may include one or more of refractive index, dielectric constant, thickness, reflectance, and / or extinction coefficient. Different material properties may be correlated with properties of the photoresist layer, such as sensitivity to radiation exposure, line edge roughness, and line width roughness. That is, the measured material properties may not have a one-to-one relationship with sensitivity, line edge roughness, and line width roughness and can be used to determine trends in the photoresist layer.

[0023] In one embodiment, step 283 is performed simultaneously with the PAB. That is, changes to the photoresist layer can be determined in real time. Such an embodiment can be useful in determining the optimal duration of the PAB process. In one embodiment, step 283 may be performed after the PAB. Step 283 may be performed using an optical tool that is co-located with the tool that performs the PAB. In other embodiments, step 283 may be performed using an optical tool that is different from the tool that performs the PAB.

[0024] In certain embodiments described in process 280, a single substrate and photoresist layer are measured. However, embodiments can also include measuring material properties of multiple photoresist layers on different substrates. For example, a first photoresist layer can be provided on a first substrate and baked with a first PAB. Then, a second photoresist layer can be provided on a second substrate and baked with a second PAB. The second PAB can be different from the first PAB. The differences can include different bake temperatures and / or bake durations. Thus, data can be obtained from multiple different PAB conditions to find optimal PAB conditions.

[0025] FIG. 3 shows a schematic diagram of the microstructure of a photoresist layer as the temperature increases, according to one embodiment. As shown, at low temperatures, the microstructure 371 of the photoresist layer is substantially crystalline. At intermediate temperatures, the microstructure 372 may be polycrystalline, and at high temperatures, the microstructure 373 may be amorphous. Different microstructures result in different properties of the photoresist layer. For example, different crystalline structures may result in different radiation sensitivity, line edge roughness, and / or line width roughness. The microstructure of the photoresist layer may be determined, in part, by the optical properties of the photoresist film.

[0026] 4A illustrates a graph of the reflectivity of a pair of photoresist layers, according to one embodiment. The first line shows the reflectivity of an unbaked photoresist layer. In one embodiment, the second line shows the reflectivity of a baked photoresist layer. For example, the bake temperature can be approximately 160° C. As illustrated, the reflectivity of the second photoresist layer is greater than the reflectivity of the first photoresist layer. In particular, the peak of the second line is greater than the peak of the first line.

[0027] FIG. 4B shows a graph of extinction coefficient versus wavelength for several different bake temperatures, according to one embodiment. Of particular interest is the peak obtained around 240 nm. As shown, the peak typically rises from PAB temperatures between 18° C. and 160° C. and drops sharply at a PAB temperature of 220° C. Therefore, the optimal PAB temperature can be determined to be between 160° C. and 220° C. The low extinction coefficient seen at the 220° C. line may be due to microstructural changes at relatively high temperatures.

[0028] 4C shows a graph of thickness change at different bake temperatures, according to one embodiment. As shown, increasing the bake temperature up to 160° C. results in a small decrease in the thickness of the photoresist layer. Thereafter, a significant decrease in thickness is observed at a bake temperature of 220° C.

[0029] As discussed above, existing processes for optimizing PAB for photoresist materials are complex and expensive. An example of such a process is shown in FIG. 5A , which illustrates a lithography apparatus 550. In one embodiment, a wafer 501 is inserted into a coating track tool 551. In tool 551, a photoresist layer is deposited on wafer 501. The photoresist layer may then be baked in a resist PAB tool. In some embodiments, the deposition of the photoresist layer and the baking of the photoresist layer may be performed in the same processing tool.

[0030] The wafer 501 is then removed from the coating track tool 551 and inserted into an exposure tool 552. The exposure tool may be a DUV or EUV exposure tool. The exposure tool 552 may use a mask to selectively expose areas of the photoresist layer.

[0031] In one embodiment, the exposed wafer 501 is then moved to a development tool 553 where the photoresist layer is developed. The process of exposing and developing the photoresist layer is time consuming and expensive. In particular, the exposure tool 552 is an expensive tool and typically has a low throughput.

[0032] After the photoresist layer is developed, the wafer can be provided to a metrology tool 554 to analyze the developed photoresist layer. In some embodiments, a contrast curve is used to determine the optimal PAB conditions for the photoresist layer. A contrast curve requires exposing and developing multiple wafers. As such, the cost and time required to obtain a contrast curve is significant.

[0033] Therefore, embodiments disclosed herein include in-situ metrology tools that eliminate the need to transfer wafers between various tools. Additionally, photoresist layers, in some embodiments, do not need to be exposed and patterned. Thus, the cost and throughput of photoresist layer optimization are improved.

[0034] As shown in FIG. 5B, wafer 501 is inserted into tool 555. In one embodiment, tool 555 may include functionality for depositing a photoresist layer on the wafer. For example, the photoresist layer may be deposited using a dry deposition process or a wet deposition process (e.g., spin coating). In one embodiment, the photoresist layer may then be baked in a PAB process. The bake process may use a resistive heater on the chuck or one or more lamps on the opposite side of the chuck. In some embodiments, tool 555 may further include an exposure apparatus. In contrast to the embodiment shown in FIG. 5A, this exposure process may be a maskless exposure process, such as electron beam lithography.

[0035] In one embodiment, tools 555 may further include an in-situ metrology tool, which may include an optical metrology tool such as single-lamp reflectance measurement, dual-lamp reflectance measurement, ellipsometry, or UV-Vis absorbance measurement. The metrology tool may provide thickness measurements and / or optical properties of the photoresist layer. For example, graphs similar to those shown in FIGS. 4A-4C may be generated using the in-situ metrology tool.

[0036] In particular, it is not necessary to develop the photoresist layer to perform the metrology. In some embodiments, the photoresist layer may not even be exposed to light. This improves throughput and allows for further PAB condition analysis. In this manner, optimal photoresist PAB conditions can be obtained at low cost and in a short time. Additionally, because tool 555 is self-contained, there is no need to move wafer 501 between different tools, as is the case in the embodiment shown in FIG. 5A.

[0037] FIG. 6 illustrates a cross-sectional view of a processing tool 600, according to one embodiment. In one embodiment, the processing tool 600 can include a chamber 605. The chamber 605 can be any suitable chamber capable of supporting a sub-atmospheric pressure (e.g., vacuum pressure). In one embodiment, an exhaust system (not shown) including a vacuum pump can be coupled to the chamber 605 to provide the sub-atmospheric pressure. In one embodiment, a lid can seal the chamber 605. For example, the lid can include a showerhead assembly 640, etc. The showerhead assembly 640 can include fluid paths through which process gases and / or inert gases can flow into the chamber 605. In some embodiments, where the processing tool 600 is suitable for plasma-enhanced operation, the showerhead assembly 640 can be electrically coupled to an RF source and a matching circuit 650. In yet another embodiment, the tool 600 can be configured in an RF bottom-feed architecture. That is, the pedestal 630 is connected to an RF source and the showerhead assembly 640 is grounded. In such an embodiment, the filtering circuitry can remain connected to the pedestal. In one embodiment, the precursor gas is stored in an ampoule 699 .

[0038] In one embodiment, optical metrology tool 670 is provided through lid 640. Optical metrology tool 670 may include one or more of a single-lamp reflectance measurement tool, a dual-lamp reflectance measurement tool, an ellipsometry tool, or a UV-Vis absorbance measurement tool. While illustrated as passing through lid 640, it should be understood that optical metrology tool 670 may be provided through any component of processing tool 600 that enables measurement of a photoresist layer on wafer 601. For example, light 671 may be directed at wafer 601 and reflected back to optical metrology tool 670. Notably, optical metrology tool 670 is provided as an in-situ tool. Thus, wafer 601 does not need to be moved to another chamber to perform measurements necessary for optimizing PAB conditions.

[0039] In one embodiment, chamber 605 is provided with a replaceable column for supporting wafer 601. In one embodiment, wafer 601 can be any substrate on which photoresist material is deposited. For example, wafer 601 can be a 300 mm wafer or a 450 mm wafer, although other wafer diameters may be used. Additionally, in some embodiments, wafer 601 may be replaced with a substrate having a non-circular shape. The replaceable column can include pillars 614 protruding from chamber 605. Pillars 614 can have ports that provide electrical and fluid paths from outside chamber 605 to various components of the column.

[0040] In one embodiment, the column may include a base plate 610. The base plate 610 may be grounded. The base plate 610 may include fluid channels that allow for the flow of inert gas to provide an edge purge flow. In one embodiment, an insulating layer 615 is disposed on the base plate 610. The insulating layer 615 may be any suitable dielectric material. For example, the insulating layer 615 may be a ceramic plate, etc. In one embodiment, a pedestal 630 is disposed on the insulating layer 615. The pedestal 630 may comprise a single material or may be formed from different materials. In one embodiment, the pedestal 630 may utilize any suitable chucking system to secure the wafer 601. For example, the pedestal 630 may be a vacuum chuck or a monopolar chuck. In embodiments in which a plasma is not generated in the chamber 605, the pedestal 630 may utilize a bipolar chucking architecture.

[0041] The pedestal 630 may include a plurality of cooling channels 631. The cooling channels 631 may be connected to fluid inputs and fluid outputs (not shown) that pass through the pillars 614. In one embodiment, the cooling channels 631 allow for control of the temperature of the wafer 601 during operation of the processing tool 600. For example, the cooling channels 631 may allow for control of the temperature of the wafer 601 between approximately −40° C. and approximately 200° C. In one embodiment, the pedestal 630 may also include a resistive heating element (not shown). The resistive heating element may be used to set a PAB bake temperature of the wafer 601. In a particular embodiment, the PAB bake temperature may be provided between approximately 15° C. and 250° C. The resistive heating element allows the wafer 601 and the photoresist layer to be heated to a particular temperature for a desired duration. The optical metrology tool 670 may measure optical and / or thickness properties of the photoresist layer on the wafer 601. The optical metrology may be performed during or after the PAB process. In one embodiment, the pedestal 630 is connected to ground through a filtering circuit 645, which allows the pedestal to be DC and / or RF biased relative to ground.

[0042] In one embodiment, the edge ring 620 surrounds the insulating layer 615 and the pedestal 630. The edge ring 620 can be a dielectric material, such as ceramic. In one embodiment, the edge ring 620 is supported by the base plate 610. The edge ring 620 can support a shadow ring 635. The shadow ring 635 has an inner diameter that is smaller than the diameter of the wafer 601. Thus, the shadow ring 635 prevents photoresist from depositing on a portion of the outer edge of the wafer 601. A gap is provided between the shadow ring 635 and the wafer 601. The gap prevents the shadow ring 635 from contacting the wafer 601 and provides an outlet for the edge purge flow. In one embodiment, a dual-channel showerhead can be used to provide a positive photoresist manufacturing process.

[0043] The shadow ring 635 provides some protection to the top and edge of the wafer 601, allowing process gases to flow / diffuse along a path between the edge ring 620 and the wafer 601. Accordingly, embodiments disclosed herein may include a fluid path between the edge ring 620 and the pedestal 630 that enables an edge purge flow. By providing an inert gas in the fluid path, local pressure within the fluid path is increased, preventing process gases from reaching the edge of the wafer 601. Thus, photoresist deposition is prevented along the edge of the wafer 601.

[0044] FIG. 7 illustrates a schematic diagram of an exemplary form of a computer system 700 within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate as a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify operations to be performed by the machine. Furthermore, although a single machine is shown, the term "machine" should also be interpreted to include any collection of machines (e.g., computers) that, individually or together, execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methodologies described herein.

[0045] The exemplary computer system 700 includes a processor 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and a secondary memory 718 (e.g., a data storage device), which communicate with each other via a bus 730.

[0046] Processor 702 represents one or more general-purpose processing devices, such as a microprocessor or central processing unit. Specifically, processor 702 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), or a network processor. Processor 702 is configured to execute processing logic 726 for performing the operations described herein.

[0047] The computer system 700 may further include a network interface device 708. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generating device 716 (e.g., a speaker).

[0048] The secondary memory 718 may include a machine-accessible storage medium (or specifically a computer-readable storage medium) 732 on which is stored one or more sets of instructions (e.g., software 722) that embody any one or more of the methods or functions described herein. The software 722 may reside, completely or at least partially, within the main memory 704 and / or the processor 702 during execution by the computer system 700, with the main memory 704 and the processor 702 also constituting machine-readable storage media. This software 722 may also be transmitted or received over the network 720 via the network interface device 708.

[0049] Although in an exemplary embodiment, machine-accessible storage medium 732 is shown as a single medium, the term "machine-readable storage medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be interpreted to include any medium that can store or encode a set of instructions that are executed by a machine, causing the machine to perform any one or more of the methodologies of the present disclosure. Accordingly, the term "machine-readable storage medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0050] According to an embodiment of the present disclosure, a machine-accessible storage medium has stored thereon instructions that cause a data processing system to perform a method for forming a positive photoresist layer on a substrate in a vacuum chamber. The method includes providing a metal precursor vapor into the vacuum chamber. The method also includes providing an oxidant vapor into the vacuum chamber. A reaction between the metal precursor vapor and the oxidant vapor forms a positive photoresist layer on the surface of the substrate.

[0051] As discussed above, a method for forming a photoresist using a dry process has been disclosed.

Claims

1. 1. A method for optimizing a post-deposition bake of a photoresist layer, comprising: depositing said photoresist layer on a substrate; baking the photoresist layer; and measuring properties of said photoresist layer with an optical tool; A method comprising:

2. The method of claim 1 , wherein the optical tool comprises single lamp reflectance measurement, dual lamp reflectance measurement, ellipsometry, or UV-Vis absorbance measurement.

3. The method of claim 1 , wherein the optical tool uses electromagnetic radiation between 200 nm and 800 nm.

4. The method of claim 1 , wherein the properties of the photoresist layer include a refractive index, a dielectric constant, a thickness, a reflectivity, and / or an extinction coefficient.

5. The method of claim 4 , wherein the property correlates with the topography of the photoresist layer.

6. The method of claim 1 , wherein measuring the properties of the photoresist layer occurs after the baking.

7. The method of claim 6 , wherein the optical tool is a separate tool located remotely from a tool used to bake the photoresist layer.

8. The method of claim 1 , wherein measuring the properties of the photoresist layer occurs during the baking.

9. The method of claim 8 , wherein the optical tool is in the same location as the tool used for the baking.

10. The method of claim 1 , wherein the characteristic is correlated with one or more of line width roughness, line edge roughness, and sensitivity to radiation exposure.

11. The method of claim 1 , wherein the photoresist layer is a metal-oxo photoresist material.

12. 10. The method of claim 1, wherein the photoresist layer is a chemically amplified resist (CAR).

13. 1. A method for optimizing post-apply bake (PAB) of a photoresist layer, comprising: depositing a first photoresist layer on a first substrate; baking the first photoresist layer with a first PAB; measuring material properties of the first photoresist layer with an optical tool during or after the first PAB; depositing a second photoresist layer on the second substrate; baking the second photoresist layer with a second PAB; measuring the material properties of the second photoresist layer with the optical tool during or after the second PAB; and Selecting the photoresist layer having the material properties that provide the most desirable linewidth roughness, line edge roughness, and / or sensitivity to radiation exposure. A method comprising:

14. 14. The method of claim 13, wherein the first PAB and the second PAB are conducted at different temperatures.

15. The method of claim 13 , wherein the first PAB and the second PAB have different durations.

16. The method of claim 13 , wherein the optical tool is integrated with a tool that implements the PAB.

17. 14. The method of claim 13, wherein the PAB is optimized without exposing and developing the first photoresist layer or the second photoresist layer.

18. 1. A semiconductor processing tool comprising: a deposition module configured to deposit a photoresist layer on a substrate using a dry deposition process; a post apply bake (PAB) module configured to bake the photoresist layer; and Optical tool for measuring one or more properties of said photoresist layer during or after baking Semiconductor processing tools including:

19. 20. The semiconductor processing tool of claim 18, wherein the optical tool comprises single lamp reflectance measurement, dual lamp reflectance measurement, ellipsometry, or UV-Visible absorbance measurement.

20. 20. The semiconductor processing tool of claim 18, wherein the dry deposition process comprises atomic layer deposition (ALD), plasma-enhanced ALD (PE-ALD), chemical vapor deposition (CVD), or plasma-enhanced CVD (PE-CVD).

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