Dry Etching for Nitride Removal Process in 3D NAND Manufacturing

Abstract

Three-dimensional (3D) NAND memory structures can include alternating layers of materials (such as alternating oxide and nitride layers) arranged in vertical stacks on a silicon substrate. The alternating nitride layers can later be removed. The recesses can then be filled with a conductive material to form word lines for the memory array. To avoid pinching off these recesses with silicon byproducts from conventional wet etching, dry etching can instead be used to remove the nitride layers. To protect the silicon substrate, a first insulating layer can be deposited at the bottom of the slits to cover the exposed silicon substrate before performing the dry etching. After applying a second insulating layer to cover the alternating oxide and nitride layers, a directional etch can penetrate both insulating layers, re-exposing the silicon substrate, before applying a solid material to the slits.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 886,285, filed Aug. 11, 2022, entitled "DRY ETCH FOR NITRIDE EXHUME PROCESSES IN 3D NAND FABRICATION," the entire disclosure of which is incorporated herein by reference for all purposes as if fully set forth herein.

[0002] This disclosure generally describes three-dimensional (3D) NAND memory. More specifically, this disclosure describes structures and techniques for fabricating 3D NAND memory structures by using dry etching to remove (exhume) alternating nitride layers that are replaced with conductive layers, while the underlying silicon substrate may be protected by an insulating layer. [Background technology]

[0003]

[0003] The memory design known as NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain stored data. NAND flash memory is used in many products, including solid-state devices and portable electronics. To increase the density and reduce the size of NAND memory, traditional two-dimensional NAND architectures are transitioning to three-dimensional NAND stacks. Unlike 2D planar NAND technology, in which individual memory cells are stacked together on separate horizontal substrates, 3D NAND is stacked vertically using multiple alternating layers of conductive and dielectric materials with intersecting vertical channels. Summary of the Invention

[0004] In some embodiments, a three-dimensional (3D) NAND memory structure may include a silicon substrate and multiple alternating material layers that may be arranged in a vertical stack on the silicon substrate. Slits may extend through the multiple alternating material layers to the silicon substrate to separate the multiple channel holes into the memory array. The slits may be perpendicular to the multiple alternating material layers. The 3D NAND memory structure may also include a first insulating layer deposited at the bottom of the slits. The first insulating layer may include a material that protects the silicon substrate during a dry etching process that may selectively remove the first alternating material layer from the multiple alternating material layers.

[0005] In some embodiments, the 3D NAND memory structure may include a silicon substrate and multiple alternating material layers that may be arranged in a vertical stack on the silicon substrate. Slits may extend through the multiple alternating material layers to the silicon substrate to separate the multiple channel holes into the memory array. The slits may be perpendicular to the multiple alternating material layers. The 3D NAND memory structure may also include a first insulating layer covering a bottom sidewall of the slit and a second insulating layer covering an upper sidewall of the slit.

[0006] In some embodiments, a method for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate, etching a slit through the plurality of alternating material layers to the silicon substrate, depositing a first insulating layer at a bottom of the slit, and performing a dry etch to selectively remove the first alternating material layer from the plurality of alternating material layers in the vertical stack. The first insulating layer may include a material that protects the silicon substrate during the dry etch process.

[0007] In any embodiment, any and all of the following features may be implemented in any combination, without limitation: The alternating material layers may include alternating layers of oxide and nitride materials. A first material layer in the plurality of alternating material layers may be adjacent to the silicon substrate and may be thicker than the remaining material layers in the plurality of alternating material layers. The slit may extend to the surface of the silicon substrate without penetrating the surface of the silicon substrate. The slit may extend below the surface of the silicon substrate. The first insulating layer may extend below the surface of the silicon substrate. The top of the first insulating layer may be between the surface of the silicon substrate and the top of a first material layer in the plurality of alternating material layers may be adjacent to the silicon substrate. The first insulating layer may not cover sides of the slit above the top of the first insulating layer. The alternating material layers may include alternating layers of oxide and metal, where the metal may form gate electrodes of individual memory cells in the memory structure. The first insulating layer may include a silicon oxide material. The top of the first insulating layer may be between the surface of the silicon substrate and the top of a first material layer in the plurality of alternating material layers, which may be adjacent to the silicon substrate. The 3D NAND memory structure may also include a solid filler material within the first insulating layer and the second insulating layer. The dry etching process may use gases that can selectively remove portions of the silicon substrate if not protected by the first insulating layer. For example, the gases may include NF3 and O2, NF3 and H2, or ClF3 and H2. The method / process may also include filling recesses left after removing the first alternating material layer with a conductive material to form word lines of the memory structure. The method / process may also include depositing a second insulating layer on top of the first insulating layer such that the second insulating layer covers the top of the first insulating layer and coats the sides of the slits. The method / process may also include etching a hole through the top of the first insulating layer and the second insulating layer covering the first insulating layer to expose the silicon substrate using a directional etch to leave the second insulating layer covering the sides of the slit. The method / process may also include filling the hole with a solid fill material.

[0008] A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings. In the drawings, like reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label is associated with the reference numeral to indicate one of multiple similar components. When referring to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0009] [Figure 1]

[0009] FIG. 1 shows a top view of one embodiment of a processing system with a deposition chamber, an etch chamber, a bake chamber, and a cure chamber, according to some embodiments. [Figure 2A]

[0010] 1 illustrates steps for removing a nitride layer from a 3D NAND memory structure using wet etching, according to some embodiments. [Figure 2B] 1 illustrates steps for removing a nitride layer from a 3D NAND memory structure using wet etching, according to some embodiments. [Figure 2C] 1 illustrates steps for removing a nitride layer from a 3D NAND memory structure using wet etching, according to some embodiments. [Figure 3A]

[0011] 1 illustrates process steps for forming a 3D NAND memory structure using a protective insulating layer and a dry etching process for exhuming a nitride layer, according to some embodiments. [Figure 3B] 1 illustrates process steps for forming a 3D NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3C]1 illustrates process steps for forming a 3D NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3D] 1 illustrates process steps for forming a 3D NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3E] 1 illustrates process steps for forming a 3E NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3F] 1 illustrates process steps for forming a 3F NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3G] 1 illustrates process steps for forming a 3G NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 3H] 1 illustrates process steps for forming a 3H NAND memory structure using a protective insulating layer and a dry etching process to remove the nitride layer, according to some embodiments. [Figure 4]

[0012] 1 illustrates a flowchart of a method for manufacturing a 3D NAND memory structure, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0013] Three-dimensional (3D) NAND memory structures can include alternating layers of materials (such as alternating oxide and nitride layers) arranged in vertical stacks on a silicon substrate. The alternating nitride layers can be subsequently removed. The recesses can be filled with a conductive material to form word lines for the memory array. To avoid pinching off of these recesses due to silicon byproducts from conventional wet etching, dry etching can instead be used to remove the nitride layers. To protect the silicon substrate, a first insulating layer can be deposited at the bottom of the slits to cover the exposed silicon substrate before performing the dry etching. After applying a second insulating layer to cover the alternating oxide and nitride layers, a directional etch can penetrate both insulating layers, re-exposing the silicon substrate, before applying a solid material to the slits.

[0011]

[0014] FIG. 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to some embodiments. In this illustration, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104 and placed in a low-pressure holding area 106, which is then placed into one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform numerous substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processing, as well as the dry etching processes described herein.

[0012]

[0015] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit material on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to cure, anneal, or treat the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the illustrated fabrication system in different embodiments. It will be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films are contemplated by the processing system 100. Additionally, any number of other processing systems that may incorporate chambers for performing any of the specific steps may be utilized with the present technology. In some embodiments, a chamber system may provide access to multiple processing chambers while maintaining a vacuum environment in various sections, such as the holding area and transfer area described above, allowing operations to be performed in multiple chambers while maintaining a particular vacuum environment between individual processes.

[0013]

[0016] The processing system 100, and more specifically, the chambers incorporated therein or other processing systems, may be used to produce structures according to some embodiments of the present technique. For example, the processing system 100 may be used to produce memory arrays by performing processes such as deposition, etching, sputtering, polishing, and cleaning in various substrate processing chambers 108. Each of these processes may be separately controlled by a recipe or by a collection of recipes that control the environmental conditions and / or steps performed by the various processing chambers 108. For example, a computer system or controller may include a non-transitory computer-readable medium that stores instructions embodying the recipes to be executed. These instructions may control the loading / unloading of substrates into the processing chambers 108 and the various processes performed within the processing chambers 108. For example, each of the methods described below may be expressed as a recipe or as a set of instructions executed by one or more processors. Each of the methods described below may also be stored in one or more memory devices as instructions representing one or more recipes executed by the processing chambers 108.

[0014]

[0017] 2A-2C illustrate steps for removing nitride layers from a 3D NAND memory structure 200 using wet etching, according to some embodiments. These figures illustrate progressive stages for creating an array of 3D NAND flash memory cells. FIG. 2A illustrates a stack of alternating nitride layers 206 and oxide layers 208 that may be formed for a 3D NAND flash array. Each of the layers 206, 208 shown in FIG. 2A may be progressively formed, one layer on top of the previous layer, using any deposition or layer formation technique. In this example, the layers may be formed on a silicon substrate 202 of silicon material, such as polycrystalline silicon, epitaxial silicon, single crystal silicon, and / or any other type of substrate.

[0015]

[0018] The alternating oxide layers 206 and nitride layers 208 may collectively be referred to as a plurality of alternating material layers arranged in a vertical stack on the silicon substrate 202. In this example, the nitride layer 206 includes a first material, such as silicon nitride, and may collectively be referred to as a first alternating material layer in the plurality of alternating material layers. Similarly, the oxide layer 208 includes a second material, such as silicon dioxide, and may collectively be referred to as a second alternating material layer in the plurality of alternating material layers. Note that silicon nitride and silicon dioxide are exemplary only and are not intended to be limiting. Other materials exhibiting similar properties may also be used. Additionally, these layers may be removed and replaced with other layers later in the manufacturing process, such as by a conductive metal layer, as described below.

[0016]

[0019] In some embodiments, the first material layer 204 may represent a first oxide layer deposited on top of or adjacent to the silicon substrate 202. The first material layer 204 may be formed from silicon dioxide or other types of oxides. In some embodiments, the first material layer 204 may be thicker than the other oxide layers 208 in the 3D NAND memory structure 200. For example, the first material layer 204 may be at least twice, three times, four times, five times, ten times, fifteen times, or twenty times thicker than the other oxide layers 208. In some implementations, the first material layer 204 may be between two and four times, four and six times, six and eight times, eight and ten times, ten and fifteen times, fifteen and twenty times, etc., thicker than the other oxide layers 208, depending on the particular circuit design.

[0017]

[0020] As part of the 3D NAND memory structure 200, multiple channel holes 210 may be etched and formed in the 3D NAND memory structure 200 to form a vertical array of memory elements. These channel holes may be lined with tunneling layers and silicon layers to form channels for the storage elements of the memory device. The channel holes 210 may be filled using polycrystalline silicon or oxide cores. While the 3D NAND memory structure 200 shown in FIG. 2A shows only two channel holes 210-1, 210-2, it should be understood that numerous additional channel holes may exist within the 3D NAND memory structure 200. For example, additional channel holes may extend to the left or right of FIG. 2A outside the visible range of the figure. Furthermore, more channel holes may exist before or after the channel hole 210 that are not visible in the cross-sectional view of FIG. 2A.

[0018]

[0021] The 3D NAND memory structure 200 may also include one or more slits. The slits may be etched through multiple alternating material layers down to the silicon substrate 202. The slits may be filled with an insulating material, such as oxide, or may be left empty. One purpose of the slits may be to separate or divide the word lines of each layer surrounding the channel hole 210 to form sections or words in the memory array. Additionally, the slits may provide access to the alternating material layers to remove some layers and replace them with a conductive material, as described below.

[0019]

[0022] FIG. 2A shows slits 212 etched through multiple alternating materials down to the silicon substrate 202. In this example, the slits 212 extend completely below the top surface of the silicon substrate 202 and down into the silicon substrate 202. However, in other embodiments, the slits 212 may extend down to the surface of the silicon substrate 202 without necessarily penetrating the top surface of the silicon substrate 202. The slits 212 may extend through the vertical stack adjacent to multiple channel holes on either side of the slits 212, which is not visible in the cross-sectional view of FIG. 2A. In addition to isolating the channel holes 210-1 and 210-2 into separate portions of the memory array, the slits 212 may also be used to provide access to the alternating nitride layers 206 for purposes of removing the nitride layers 206 during the fabrication process.

[0020]

[0023] 2B illustrates a nitride removal process using wet etching, according to some embodiments. Access to nitride layer 206 may be provided through slits 212 to remove it. Nitride layer 206 may be a sacrificial layer used to build multiple alternating material layers in the initial stages of fabricating 3D NAND memory structure 200. Nitride layer 206 may be removed after channel holes 210 and other features are formed. After removal, nitride layer 206 may leave recesses that can be filled with a conductive material, such as tungsten, to provide conductive word lines for the memory array.

[0021]

[0024] In some processes, the nitride layer 206 may be removed using a wet etch. For example, the wet etch may be performed by applying a wet etchant, such as phosphoric acid, to the 3D NAND memory structure 200. The phosphoric acid can remove the nitride layer 206 from the slits 212. Wet etching is commonly used because it is highly selective to the nitride layer 206. Specifically, the phosphoric acid does not remove a significant amount of material from either the exposed silicon substrate 202 or the oxide layer 208 at the bottom of the slits 212, yet still effectively removes the nitride layer.

[0022]

[0025] However, the wet etching process has also been found to present several technical challenges that complicate the formation of metal word lines between the remaining oxide layers 208. Specifically, as nitride materials dissolve in the wet etching bath, non-uniform silicate by-products can accumulate in the solution. As the etching process progresses, the concentration of silicate by-products can continue to build up in the solution over time. When the concentration reaches a certain level, the silicate by-products can begin to solidify and accumulate on the surface of the oxide layers 208. This buildup can "pinch off" the horizontal trenches or recesses between the oxide layers 208.

[0023]

[0026] FIG. 2C shows a close-up view of a recess left after removing the first alternating material layer of nitride using a wet etching process, according to some embodiments. As shown in this figure, silicate by-products 220 begin to accumulate in the recess left during the etching process. In some cases, the silicate by-products 220 tend to accumulate most at the entrance to the recess, but the silicate by-products 220 can also extend along the entire length of the recess. The silicate by-products 220 can be problematic when the recess is later filled with a conductive material to form the word lines, leaving less space for metal fill. As a result, the metal word lines may not be uniform in thickness throughout their length and may include significantly thinner regions due to the silicate by-products 220. When the word lines become thinner due to the accumulation of silicate by-products 220, their conductance may decrease, thereby interfering with the operation of the memory array.

[0024]

[0027] 3A-3H illustrate process steps for forming a 3D NAND memory structure 300 using a dry etching process to remove a protective insulating layer 330 and a nitride layer, according to some embodiments. These figures may continue the process of fabricating the memory structure 300 from the stage illustrated in FIG. 2A. FIG. 3A illustrates an insulating layer 330 that may be formed to protect the silicon substrate 302, according to some embodiments. To overcome the problems associated with the wet etching process described above, a dry etching process may be used instead. Prior to the present disclosure, dry etching processes were not used to remove the nitride layer 306 because the dry etching process also removed some of the silicon within the silicon substrate 302. Specifically, while a dry etching process may be highly selective to etching away the nitride layer 306, leaving behind the oxide layer 308 and the first material layer 304, the dry etching process also removes a significant amount of silicon from the silicon substrate 302. The wet etching process was well suited to specifically targeting the nitride layer 306 without damaging the silicon substrate 302.

[0025]

[0028] The embodiments described herein enable the use of a dry etching process by depositing an insulating layer 330 at the bottom of the slit 312 to protect the silicon substrate 302 during the dry etching process. The material of the insulating layer 330 may include any dielectric, non-conductive, oxide material, such as silicon dioxide. Because multiple insulating layers may be used throughout the fabrication process, the insulating layer 330 may also be referred to herein as a first insulating layer 330 to distinguish it from other insulating layers that may be applied in later fabrication steps.

[0026]

[0029] The insulating layer 330 may be deposited at the bottom of the slit 312 using a directional deposition process. Specifically, a deposition process may be used to directionally deposit silicon at the bottom of the slit 312 and convert the silicon to silicon dioxide. This step may be repeated until the insulating layer 330 has a sufficient thickness. This directional deposition process is configured to deposit silicon dioxide only at the bottom of the slit 312 without covering the sides of the slit 312 with insulating material. Specifically, the nitride layer 306 and the oxide layer 308 may remain exposed even after the insulating layer 330 is fully deposited. This allows a dry etching process to access the nitride layer 306 even after the insulating layer 330 is deposited to protect the silicon substrate 302. Therefore, a dry etching process may be used to effectively remove the nitride layer 306 without damaging the silicon substrate 302.

[0027]

[0030] The insulating layer 330 may be deposited such that its height is above the top of the silicon substrate 302. Thus, once the slit 312 is etched deep enough to penetrate below the top of the silicon substrate 302, the insulating layer 330 may start below the top of the silicon substrate 302 and extend upward to a thickness above the top of the silicon substrate 302. For example, the insulating layer 330 may be deposited to a thickness near the midpoint of the thickness of the first material layer 304. Note that the thickness of the first material layer 304 may be greater than the thicknesses of the other nitride layers 306 and oxide layers 308. This increased thickness may allow the height of the insulating layer 330 to fit within the center of the first material layer 304 with a margin of error (which would be more difficult if the first material layer 304 were the same thickness as the other nitride layers 308). Depositing the insulating layer 330 to a thickness such that the top of the insulating layer 330 is within the first material layer 304 ensures that none of the nitride layer 306 is blocked during the dry etching process and that the silicon substrate 302 is completely covered by the insulating layer 330.

[0028]

[0031] FIG. 3B illustrates the 3D NAND memory structure 300 after a dry etching process has been completed, according to some embodiments. Similar to the wet etching process described above, the dry etching process may leave recesses where the nitride layer 306 has been removed. These recesses may later be filled with a conductive material to form word lines in the memory array. However, in contrast to the recesses shown in FIG. 2C, the recesses shown in FIG. 3B are free of silicate buildup, which tends to pinch off the recesses. Specifically, the recesses left from the dry etching process have sharper corners left by the oxide layer 308 and a more uniform thickness across the horizontal length of the recess. This provides uniform conductivity and geometry for the conductive material that will be subsequently deposited.

[0029]

[0032] Depending on the embodiment, various dry etching processes may be used. Some implementations may use a gas mixture applied to the processing chamber that reacts with the nitride layer 306 in multiple steps to remove the nitride layer. For example, a first gas may be applied to bond with the nitride layer to form an outer layer of material, and then a second gas may be applied to remove the outer layer. This process may be repeated to remove the nitride layer 306 in stages. These gas mixtures may be highly selective and may effectively remove silicon nitride without substantially removing silicon oxide. For example, some dry etching processes may use a mixture of NF3 and O2 gases. Other dry etching processes may use a mixture of NF3 and H2 gases. Other dry etching processes may use a mixture of ClF3 and H2 gases.

[0030]

[0033] FIG. 3C illustrates the application of a liner material to the recesses left by the dry etching process, according to some embodiments. The next step in the integrated process flow for fabricating the 3D NAND memory structure 300 may involve applying various thin layers to the recesses and exposed surfaces of the slits 312 before depositing the conductive material. For example, some embodiments may grow a thin layer of oxide on the silicon oxide fins 308 after the dry etching. Some embodiments may then add a liner, such as a TiN liner, on top of the oxide layer. As depicted in FIG. 3C, these layers 332 may be used to coat the silicon oxide surface before applying the conductive material.

[0031]

[0034] 3D illustrates the application of a conductive material to the recesses left by the dry etching process, according to some embodiments. A conductive material 334 may be formed on the exposed surfaces of the slits 312 and within the recesses left between the oxide layers 308 to form conductive word lines. For example, some embodiments may use a tungsten (W) fill to grow solid word lines between the oxide layers 308. Other conductive or metallic materials besides tungsten may also be used. Note that the deposition process for forming the conductive material 334 may not only fill the recesses between the oxide layers 308, but may also form a layer of conductive material 334 surrounding the interior of the slits 312. The conductive material 334 may also form a layer on the exposed top surface of the first insulating material 330 at the bottom of the slits 312.

[0032]

[0035] 3E illustrates a separation process for removing portions of the conductive material 334, according to some embodiments. To electrically isolate the individual word lines from one another, the conductive material 334 coating the interior of the slits 312 may be removed using, for example, a tungsten separation process, which etches away the coating of conductive material 334. Note that this removal process may extend somewhat into the recess, but not enough to damage the conductive word lines between the oxide layers 308. This removal process may also remove the conductive material 334 formed on top of the first material layer 304 and / or the first insulating layer 302.

[0033]

[0036] 3F illustrates the application of a second insulating layer 338 to the slit 312 according to some embodiments. This step may be referred to as an oxide filling step, in which an oxide layer is deposited as the second insulating layer 338. The second insulating layer 338 may cover the side surfaces surrounding the interior of the slit 312. The second insulating layer 338 may also cover the exposed top of the first insulating layer 330. Any type of oxide may be used for the second insulating layer 338. The second insulating layer may serve to electrically isolate different word lines between the oxide layers 308.

[0034]

[0037] FIG. 3G illustrates a directional etch that can be used to re-expose the silicon substrate 302, according to some embodiments. Some implementations of the 3D NAND memory structure 300 may benefit from contacting the slit material to the silicon substrate 302. For example, filling the slit 312 with material that extends downward into the silicon substrate 302 can provide a more rigid and supportive memory array structure. However, the first insulating material 330, previously formed to protect the silicon substrate 302, now blocks access to the silicon substrate 302. Therefore, a “bottom-punch” etch, providing a directional etch perpendicular to the bottom of the slit 312, can be used to remove the bottom of the second insulating layer 336 and the bulk of the first insulating layer 330. For example, a reactive ion etching (RIE) process can be used to directionally etch the first insulating layer 330 and the second insulating layer 336 at the bottom 338 of the slit 312, as shown in FIG. 3G. In some embodiments, the RIE process may etch down to the bottom of the first insulating layer 330 to just expose the silicon substrate 302. In other embodiments, the RIE process may continue to etch further into the silicon substrate 302 below the bottom surface of the first insulating layer 330.

[0035]

[0038] The resulting stack may leave the first insulating layer 330 covering the bottom side of the slit 312, as depicted in Figure 3G. Additionally, the second insulating layer 336 may cover the top side of the slit 312, as depicted in Figure 3G. Note that other materials may also cover portions of the sides or sidewalls of the slit 312, without limitation.

[0036]

[0039] 3H shows the solid fill material 342 and liner in the completed slit 312 according to some embodiments. After etching down to the silicon substrate 302, a liner 340, such as a TiN liner, may be applied inside the slit 312. The liner 340 may coat the sides of the slit 312, covering the first insulating material 330 and / or the second insulating material 336. The liner 340 may also coat the bottom 338 of the slit 312, covering the exposed portion of the silicon substrate 302. Next, the solid fill material 342 may be formed inside the slit 312. For example, some embodiments may use polycrystalline silicon as the solid fill material 342. Other embodiments may use tungsten or other metals as the solid fill material.

[0037]

[0040] 3H shows the final structure consisting of the silicon substrate 302, multiple alternating material layers (currently formed from alternating layers of silicon dioxide and tungsten), and the slit. A first insulating layer 330 may cover the bottom side of the slit, and a second insulating layer may cover the top side of the slit. A solid fill material may extend into the silicon substrate 302 from the top of the stack of alternating material layers.

[0038]

[0041] FIG. 4 shows a flowchart 400 of a method for fabricating a 3D NAND memory structure, according to some embodiments. Each of the operations described below may be performed by a semiconductor processing system such as that described above in FIG. 1. The semiconductor processing system may include multiple processing chambers configured to perform the etching, deposition, and / or other processes described below. In some implementations, these operations may be implemented in one or more instruction sets stored in one or more memory devices, which may be executed by one or more processors in one or more controllers that cause the processing chambers to perform these operations. For example, the instructions may be stored centrally in a central controller or in a distributed controller for each processing chamber.

[0039]

[0042] The method may include forming 402 a plurality of alternating material layers arranged in a vertical stack on a silicon substrate. The alternating material layers may be formed as described above in FIG. 2A and may include alternating material layers of nitride and oxide materials, such as silicon nitride and / or silicon dioxide. A first material layer positioned adjacent to or on top of the silicon substrate may be substantially thicker than similar material layers throughout the remainder of the stack.

[0040]

[0043] The method may also include etching 404 slits through the multiple alternating material layers to the silicon substrate. For example, as described above in FIG. 2A , a hard mask may be patterned on top of the alternating material layers to etch slits that extend through the material layers and down to the silicon substrate. The slits may extend down to the surface or top of the silicon substrate, or may extend below the top of the silicon substrate and into the silicon substrate itself.

[0041] The method may further include depositing a first insulating layer at the bottom of the slit (406). As described above in FIG. 3A, the first insulating layer may cover the exposed surface of the silicon substrate. The top of the first insulating layer may be below the first nitride layer in the alternating stack of materials within the stack. For example, the top of the first insulating layer may be positioned within the oxide first material layer above the silicon substrate. The first insulating layer may be directionally deposited at the bottom of the slit so that the material of the first insulating layer does not cover the interior sides of the slit, thereby leaving the alternating layer (e.g., the nitride layer that is removed) exposed. The first insulating layer may be composed of a dielectric material such as silicon dioxide or an oxide material.

[0042]

[0044] The method may also include performing a dry etch (408) to selectively remove a first alternating material layer from the plurality of alternating material layers in the vertical stack. The dry etch may be configured to selectively remove a first alternating material layer, such as a nitride layer, without removing a second material layer, such as an oxide layer. In some cases, the dry etch may also be configured to selectively remove a silicon substrate when the silicon substrate is not protected by a first insulating layer. Thus, the first insulating layer may protect the silicon substrate during the dry etching process by covering exposed areas of the silicon substrate. The dry etch process may be configured not to selectively remove the first insulating layer. The dry etch may be performed as an iterative two-gas process using gases such as NF3 and O2, NF3 and H2, ClF3 and H2, and / or other similar combinations.

[0043]

[0045] It should be understood that the specific steps illustrated in FIG. 4 provide a particular method for fabricating a three-dimensional (3D) NAND memory structure according to various embodiments. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, individual steps illustrated in FIG. 4 may include multiple sub-steps that may be performed in various sequences appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also within the scope of the present disclosure.

[0044]

[0046] As used herein, the terms "about" or "approximately" or "substantially" can be interpreted as being within the range expected by one of ordinary skill in the art in light of the present specification.

[0045]

[0047] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0046]

[0048] The above description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments provides an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0047]

[0049] In the foregoing description, specific details are given to facilitate a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0048]

[0050] Also, it should be noted that particular embodiments have been described as a process, which is depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. While a flowchart may describe steps as a sequential process, many of the steps may be performed in parallel or simultaneously. Moreover, the order of steps may be rearranged. A process terminates when a step is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to a calling function or a main function.

[0049]

[0051] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media that can store, contain, or carry one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or a hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0050]

[0052] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. One or more processors may perform the necessary tasks.

[0051]

[0053] While features have been described in the foregoing specification with reference to specific embodiments thereof, it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or together. Moreover, embodiments may be utilized in any number of environments and applications other than those described herein without departing from the broader spirit and scope of the specification. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0052]

[0054] Furthermore, for purposes of explanation, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the methods described above may be performed by hardware components or embodied in a sequence of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor, or a logic circuit programmed with the instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. 1. A three-dimensional (3D) NAND memory structure, comprising: A silicon substrate; a plurality of alternating material layers arranged in a vertical stack on the silicon substrate, with slits extending through the plurality of alternating material layers to the silicon substrate to separate a plurality of channel holes into a memory array, the slits being perpendicular to the plurality of alternating material layers; a first insulating layer deposited on the bottom of the slit, the first insulating layer comprising a material that protects the silicon substrate during a dry etching process that selectively removes the first layer of alternating material from the plurality of layers of alternating material; and 1. A 3D NAND memory structure comprising:

2. 10. The 3D NAND memory structure of claim 1, wherein the alternating material layers comprise alternating layers of oxide and nitride materials.

3. 10. The 3D NAND memory structure of claim 1, wherein a first layer of material in the plurality of alternating layers of material adjacent to the silicon substrate is thicker than the remaining layers of material in the plurality of alternating layers of material.

4. 10. The 3D NAND memory structure of claim 1, wherein the slits extend to the surface of the silicon substrate without penetrating the surface.

5. 10. The 3D NAND memory structure of claim 1, wherein the slits extend below a surface of the silicon substrate.

6. 10. The 3D NAND memory structure of claim 1, wherein the first insulating layer extends below a surface of the silicon substrate.

7. 10. The 3D NAND memory structure of claim 1, wherein a top of the first insulating layer is between a surface of the silicon substrate and a top of a first material layer in the plurality of alternating material layers adjacent to the silicon substrate.

8. 8. The 3D NAND memory structure of claim 7, wherein the first insulating layer does not cover sides of the slit above the top of the first insulating layer.

9. 1. A three-dimensional (3D) NAND memory structure, comprising: A silicon substrate; a plurality of alternating material layers arranged in a vertical stack on the silicon substrate, with slits extending through the plurality of alternating material layers to the silicon substrate to separate a plurality of channel holes into a memory array, the slits being perpendicular to the plurality of alternating material layers; a first insulating layer covering a side surface of the bottom of the slit; a second insulating layer covering the side surface of the upper portion of the slit; 1. A 3D NAND memory structure comprising:

10. 10. The 3D NAND memory structure of claim 9, wherein the alternating material layers comprise alternating layers of oxide material and metal, the metal forming gate electrodes for individual memory cells in the memory structure.

11. 10. The 3D NAND memory structure of claim 9, wherein the first insulating layer comprises a silicon oxide material.

12. 10. The 3D NAND memory structure of claim 9, wherein a top of the first insulating layer is between a surface of the silicon substrate and a top of a first material layer in the plurality of alternating material layers adjacent to the silicon substrate.

13. 10. The 3D NAND memory structure of claim 9, further comprising a solid filler material within the first insulating layer and the second insulating layer.

14. 1. A method for fabricating a three-dimensional (3D) NAND memory structure, comprising: forming a plurality of alternating layers of material arranged in a vertical stack on a silicon substrate; Etching slits through the plurality of alternating layers of material to the silicon substrate; depositing a first insulating layer at the bottom of the slit; performing a dry etching process to selectively remove a first layer of alternating material from the plurality of alternating layers of material in the vertical stack, wherein the first insulating layer comprises a material that protects the silicon substrate during the dry etching process; A method comprising:

15. 15. The method of claim 14, wherein the dry etching process uses gases that would also selectively remove portions of the silicon substrate if not protected by the first insulating layer.

16. The gas is NF ３ and O ２ , NF ３ and H ２ ,or ClF ３ and H ２ 16. The method of claim 15, comprising:

17. 15. The method of claim 14, further comprising filling recesses remaining after removing the first layer of alternating material with a conductive material to form word lines for the memory structure.

18. 15. The method of claim 14, further comprising depositing a second insulating layer on top of the first insulating layer such that the second insulating layer covers the top of the first insulating layer and coats sides of the slit.

19. 20. The method of claim 18, further comprising etching a hole through the top of the first insulating layer and the second insulating layer covering the first insulating layer to expose the silicon substrate using a directional etch to leave the second insulating layer covering the sides of the slit.

20. filling said holes with a solid filler material.

20. The method of claim 19, further comprising:

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