High aspect ratio etching using redeposited helmet masks.

Abstract

A method is provided for etching features in a stack, including forming a patterned mask over the stack, partially etching the stack through the patterned mask, depositing a helmet mask over the patterned mask, and etching the stack through the helmet mask.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Patent Application No. 63 / 401,041, filed August 25, 2022. The above application is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a method for forming semiconductor devices on a semiconductor wafer. [Background technology]

[0003] In the formation of semiconductor devices, etch layers may be etched to form memory holes, lines, or other semiconductor features. Some semiconductor devices may be formed by etching a single layer of silicon dioxide (also known as silicon oxide (SiO2)) to form, for example, capacitors for dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching a bilayer stack of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON) or bilayer stack of alternating silicon dioxide and polysilicon (OPOP). Other alternating layer stacks may also be etched. In some alternating layer stacks, one of the alternating layers may be silicon dioxide. Some alternating layers may even be triple-layer stacks. Such stacks may be used in memory applications or three-dimensional "NOT AND" gates (3D NAND). These stacks tend to require a relatively high aspect ratio (HAR) dielectric etch. Examples of etch characteristics required for high aspect ratio etching include high etch selectivity to the mask (such as an amorphous carbon mask), a small amount of sidewall etching while maintaining a linear profile, and a high etch rate at the etched surface. High aspect ratio etching can result in tapered features that are much wider at the top than at the bottom. Such features can increase device failure rates and limit device density, performance, and depth.

[0004] In the etching process of OPOP stacks using an amorphous carbon mask, a metal-containing passivation agent may be used during the etching process. The metal-containing passivation agent may be applied during the etching process so that passivation and etching occur simultaneously or alternately. The use of tungsten (W)-containing passivation agents has been shown to selectively deposit tungsten on polysilicon over silicon dioxide, resulting in less passivation of the silicon dioxide layer than the polysilicon. Reduced silicon dioxide passivation increases defects such as increased CD and notching. The ability of a passivation layer to protect the substrate is determined by the weakest or thinnest deposit. For example, if a thin deposit on the oxide layer degrades during additional etching, etching of the oxide layer may begin even if tungsten passivation remains on the silicon. As the oxide layer is etched, not only does the CD increase but new defects such as notching and keyholes are formed. Non-uniform passivation can also cause profile twisting, bending, and ionic side bowing.

[0005] The background art provided herein is intended to provide a general background to the present disclosure. Information contained in this background art, and aspects of the description that may not otherwise be admitted as prior art at the time of filing, are not admitted, explicitly or implicitly, as prior art to the present disclosure. Summary of the Invention

[0006] To achieve the above and in accordance with the objects of the present disclosure, a method is provided for etching features in a stack, including: forming a patterned mask over the stack; partially etching the stack through the patterned mask; depositing a helmet mask over the patterned mask; and etching the stack through the helmet mask.

[0007] These and other features of the present disclosure will be explained in more detail in the following detailed description, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which similar elements are numbered the same and in which:

[0009] [Figure 1] FIG. 1 is a simplified flow chart of a process used in some embodiments.

[0010] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2C] FIG. 2C is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2D] FIG. 2D is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2E] FIG. 2E is a schematic cross-sectional view of a laminate processed according to some embodiments.

[0011] [Figure 3A] FIG. 3A is a cross-sectional view of a helmet mask used in some embodiments. [Figure 3B] FIG. 3B is a cross-sectional view of a helmet mask used in some embodiments.

[0012] [Figure 4] FIG. 4 is a schematic diagram of an etching chamber that can be used in some embodiments.

[0013] [Figure 5] FIG. 5 is a schematic diagram of a computer system that can be used to implement some embodiments.

[0014] In the drawings, the same components may be denoted by the same reference numerals. Note that the drawings are schematic representations and are not drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present disclosure will now be described in detail with reference to several preferred embodiments illustrated in the accompanying drawings. In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, detailed descriptions of well-known process steps and / or structures are omitted to avoid unnecessarily obscuring the present disclosure.

[0016] Dry development of high-aspect-ratio contacts requires tight control of the sidewall taper angle. Various methods have been attempted to limit the difference in lateral critical dimension (CD) between the top and bottom of etched structures. The demand for tight control of the top and bottom shapes has become particularly acute with the recent development of 3D NAND memory, which features an increased number of layers in ONON or OPOP bilayer structures and thicker structures. An increase in profile (the difference between the top and bottom CDs) poses risks to subsequent device fabrication processes and impacts device performance. Current technology relies on sidewall deposition to prevent lateral CD erosion during reactive ion etching of high-aspect-ratio structures. Maintaining a delicate balance between etching and sidewall deposition is particularly challenging for high-aspect-ratio features. As a result, dry development of high-aspect-ratio structures is limited to thin structures, while etching thicker stacks requires significantly more complex development.

[0017] Embodiments described herein provide high aspect ratio features deeply etched into a stack, where the width near the top of the feature is approximately equal to the width near the bottom. For ease of understanding, FIG. 1 depicts a simplified flowchart that can be used in some embodiments. A mask is deposited on the stack (step 104). In some embodiments, the mask is a metal- or semi-metal-containing mask. In some embodiments, plasma-enhanced physical vapor deposition (PECVD) is used to deposit a metal-containing dielectric film that can be used as a mask. Methods for depositing tungsten carbide films by PECVD are described in U.S. Pat. No. 9,875,890, entitled "Deposition of Metal Dielectric Films for Hard Mask Applications," issued January 23, 2018, which is incorporated by reference herein for all purposes and may be used in some embodiments. In some embodiments, the deposited tungsten carbide film is patterned to form a mask. In some embodiments, the mask is an amorphous carbon mask containing carbon. In some embodiments, the mask is metal- and semi-metal-free.

[0018] 2A is a schematic cross-sectional view of a stack 204 that may be etched in some embodiments. In some embodiments, stack 204 includes a substrate 208 beneath multiple bilayers 212 disposed beneath a patterned mask 216. In some embodiments, one or more layers may be disposed between substrate 208 and multiple bilayers 212 and / or between multiple bilayers 212 and patterned mask 216. In some embodiments, patterned mask 216 is an amorphous carbon mask. In some embodiments, the pattern of the patterned mask provides mask features 220 for high aspect ratio contacts. In some embodiments, mask features 220 are formed before stack 204 is placed in an etch chamber. In other embodiments, mask features 220 are formed while stack 204 is placed in an etch chamber. In some embodiments, each bilayer 212 includes a silicon oxide layer 224 and a silicon nitride layer 228. Conductive contacts 232 are present in substrate 208.

[0019] The stack is partially etched (step 108). In some embodiments, an etching gas is supplied. In some embodiments, RF power is supplied to convert the etching gas into a plasma having etching ions. A voltage is applied to accelerate the etching ions in the plasma toward the stack. The etching ions partially etch the stack and also etch a portion of the mask. Etching the stack may include at least one of chemical etching and physical sputtering of the stack.

[0020] FIG. 2B is a schematic cross-sectional view of stack 204 after it has been partially etched to form etched feature 240. A portion of mask 216 has been etched away. During the partial etch, patterned mask 216 is partially etched and reshaped. In the example shown in FIG. 2B, deposition occurs on the sidewalls of patterned mask 216. This results in a necking of patterned mask 216, forming a narrow portion. This necking results in a tapered feature 240. If etching were to continue, feature 240 would become even more tapered.

[0021] The mask is shaped (step 112). In some embodiments where the mask is a carbon-containing mask, a hydrogen-based plasma chemistry is used to shape the mask. In some embodiments, an oxygen-based plasma chemistry is used to shape the mask. In some embodiments, shaping the mask tapers the top of the mask to a sharper (or pointy) shape and removes waist regions. Removing waist regions helps reduce the taper. Shaping the top facilitates deposition of the helmet mask. In some embodiments, mask shaping may not be performed.

[0022] 2C is a schematic cross-sectional view of stack 204 after mask 216 has been mask molded (step 112). In some embodiments, the necking is removed. In some embodiments, mask molding reduces the height of patterned mask 216.

[0023] A helmet mask is deposited over the mask (step 116). In some embodiments, the helmet is deposited by at least one of a chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) process. The helmet forms a vertically extending mask structure. This mask structure is an extension of the shape and structure of the original mask, with the new mask structure generally corresponding to a taller version of the original mask. The helmet shape and width can be narrower than the original mask, or it can be wider laterally, extending the shape of the new structure both vertically and laterally. The helmet height can vary depending on the application, and the required helmet height will determine the final helmet shape. In some embodiments, the helmet mask deposition forms a carbon sidewall liner on the sidewalls of the feature. If the helmet mask were deposited without a sidewall liner and mask shaping, the helmet mask deposition may block the waist region in some embodiments. The sidewall liner deposited during the helmet mask deposition process reduces CD and helps prevent bowing. In some embodiments, the helmet mask and the sidewall liner act synergistically to improve the profile of the feature. In some embodiments, the helmet mask is a carbon-containing helmet mask. In some embodiments, at least one of an alkane, an alkene, or an alkyne-based hydrocarbon is used as a precursor in a plasma process to form the carbon-containing helmet mask. In some embodiments, the helmet mask is a deposition layer that is selectively deposited with a selectivity ratio of deposition on top of the patterned mask 216 to deposition on the bottom of the feature in a range of 50:1 to 100:1. As a result, in some embodiments, the helmet mask has a thickness on top of the patterned mask 216 in a range of 30 nm to 1 micron. In some embodiments, the helmet mask is a carbon-based deposition. In some embodiments, the helmet mask has a metal or semi-metal dopant.Using at least one of an alkane, an alkene, and an alkyne hydrocarbon as a precursor and performing CVD or PECVD deposition on a carbon mask at a specific temperature and pressure can facilitate deposition selectivity and helmet mask shape. In addition to carbon, some helmet masks may further include hydrogen. In some embodiments, the percentage of hydrogen may achieve a desired helmet mask hardness.

[0024] 2D is a schematic cross-sectional view of stack 204 after a helmet mask 244 has been deposited (step 116) over patterned mask 216. In this example, helmet mask 244 has a pointed shape.

[0025] The stack is then further etched (step 120) using patterned mask 216 and helmet mask 244 as a mask. Figure 2E is a schematic cross-sectional view of stack 204 after stack 204 has been further etched (step 120). In some embodiments, the helmet mask 244 and a portion of patterned mask 216 shown in Figure 2D are etched away. In some embodiments, etching of the stack continues until the stack is completely etched, as shown in Figure 2E.

[0026] In some embodiments, the provision of a helmet mask allows for the completion of the etch while extending the bottom of the feature and reducing the taper of the feature. One of the major challenges in high aspect ratio (HAR) etching is CD scaling. In particular, as the desired feature is scaled vertically, there is a need to simultaneously maintain a constant lateral feature size. In practice, this is very difficult to achieve, and many current techniques involve trade-offs. In some embodiments, the use of a helmet mask allows for CD control and can prevent other defects such as notching.

[0027] Some embodiments may be used to target oxide / nitride (ONON) multilayer stacks to form features such as contact holes and trenches when manufacturing 3D NAND memory devices. Some embodiments may be used for capacitor etching in dynamic random access memories (DRAMs). Some embodiments may be used for etching silicon oxide and polysilicon bilayers (OPOPs). In some embodiments, the etch depth is greater than 1 micron. In some embodiments, the etch depth is greater than 10 microns.

[0028] An advantage of some embodiments is that they enable device manufacturers to more precisely control the profile of high aspect ratio features. Various embodiments enable enlarging the bottom CD of very high aspect ratio features. Various embodiments enable next generation devices that utilize deeper, higher aspect ratio structures. Various embodiments enable lower device manufacturing costs by reducing the number of steps required to develop high aspect ratio contacts. Various embodiments reduce feature width variation along the depth of the feature, such that the width difference between any two points along the depth of the feature 240 is less than 10%. In some embodiments, a helmet mask may be deposited to form a sidewall liner. In some embodiments, a helmet mask may be deposited to provide additional mask thickness to prevent complete removal of the patterned mask. In some embodiments, the helmet mask increases the mask, enabling deeper etching. Additionally, in some embodiments, a sidewall liner may also be deposited by depositing a helmet mask. In some embodiments, the helmet mask reduces mid-profile twist and mitigates sidewall roughness.

[0029] In some embodiments, the stack may be a single silicon-containing layer, such as a single layer of silicon dioxide, silicon nitride, or silicon. In some embodiments, the stack may include a single layer or multiple layers of other silicon-containing materials. In some embodiments, patterned mask 216 or helmet mask 244 may be a metal- or metalloid-containing mask. In some embodiments, to etch a stack having a silicon layer, the mask may further include oxygen. In some embodiments, to etch a silicon dioxide stack, the mask may further include silicon. In some embodiments, a metal or metalloid dopant may be present. In some embodiments, the metal in the metal or metalloid dopant is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, and aluminum. In other embodiments, the metalloid is boron.

[0030] In some embodiments, the feature 240 may be etched the full depth of the stack (i.e., nearly to touchdown) before the helmet mask 244 is deposited. In such embodiments, the helmet mask 244 is used as a mask for a process that enlarges the bottom of the feature 240 and reduces the taper. A stronger etch than a partial etch may be used to enlarge the bottom of the feature 240. The helmet mask 244 provides additional mask protection while enlarging the bottom of the feature 240.

[0031] In some embodiments, the helmet mask 244 has a tip, forming a pointed helmet shape, as shown in FIG. 2D . FIG. 3A is a cross-sectional view of a helmet mask 304 deposited in another embodiment. In the embodiment shown in FIG. 3A , the helmet mask 304 has a generally horizontal top and generally vertical sides. The helmet mask 304 may be defined as cylindrical or rectangular if it forms a cylindrical or rectangular cross section when deposited on a horizontal mask surface. FIG. 3B is a cross-sectional view of a helmet mask 308 deposited in another embodiment. In the embodiment shown in FIG. 3B , the helmet mask 308 has a generally horizontal top and sloping sides. The helmet mask 308 has a tip, but the tip is truncated. The helmet mask 308 may be defined as frustoconical or trapezoidal if it forms a truncated conical or trapezoidal cross section when deposited on a horizontal mask surface. In other embodiments, other helmet mask shapes may be used. In some embodiments, a pointed helmet mask has been found to provide the most advantages. The helmet shape can be configured depending on process requirements. A triangular helmet mask shape is preferred to prevent capping / blocking if the process is overpolymerizing. A cylindrical shape is preferred to provide a more stable structure if the process results in a more open neck shape after the initial partial etch and before the helmet mask deposition.

[0032] In some embodiments, sidewall liner deposition may occur after mask fabrication but before, during, or after helmet mask deposition. The sidewall liner deposition may be carbon-based or formed of another material, such as a metal- or metalloid-containing material. In some embodiments, sidewall liner deposition is part of the helmet formation process. In some embodiments, the sidewall liner is not deposited after mask fabrication but before, during, or after helmet deposition. In some embodiments, the timing and process of mask and sidewall liner deposition may tune the mask deposition to desired final features (such as reduced bow CD, improved bottom CD, reduced taper, reduced twist, reduced defect formation, etc.).

[0033] FIG. 4 is a schematic diagram of an etch reactor system 400 usable in some embodiments. In some embodiments, the etch reactor system 400 includes a gas distribution plate 406 providing a gas inlet into an etch chamber 409 surrounded by a chamber wall 452, and an electrostatic chuck (ESC) 408. Within the etch chamber 409, a stack 404 is disposed on the electrostatic chuck 408. The ESC 408 may receive a bias from an ESC source 448. An etch gas source 410 is connected to the etch chamber 409 through the gas distribution plate 406. An ESC temperature controller 450 is connected to the ESC 408. A radio frequency (RF) source 430 provides RF power to the lower electrode and / or upper electrode (in this embodiment, the ESC 408 and the gas distribution plate 406, respectively). In some embodiments, a 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz or 27 MHz power supply constitutes the RF source 430 and the ESC source 448. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, each generator may be provided in a separate RF source, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode, each connected to a different RF source. In other embodiments, other arrangements of RF sources and electrodes may be used. A controller 435 is controllably connected to the RF source 430, the ESC source 448, the exhaust pump 420, and the etching gas source 410. An example of such an etching chamber is the Flex™ Etch System (manufactured by Lam Research Corporation, Fremont, California). The process chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0034] FIG. 5 is a schematic block diagram illustrating a computer system 500 suitable for implementing the controller 435 used in the embodiments. The computer system 500 may take many physical forms, ranging from integrated circuits, printed circuit boards, small handheld devices, to large supercomputers. The computer system 500 includes one or more processors 502 and may further include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., random access memory (RAM)), storage devices 508 (e.g., hard disk drives), removable storage devices 510 (e.g., optical disk drives), user interface devices 512 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 514 (e.g., wireless network interfaces). The communications interface 514 enables software and data transfer between the computer system 500 and external devices via a link. The system may also include a communications infrastructure 516 (e.g., a communications bus, crossover bar, or network) to which the above-mentioned devices / modules are connected.

[0035] Information transferred via communications interface 514 may take the form of signals, such as electronic, electromagnetic, optical, or other signals, that can be received by communications interface 514 over a communications link that transmits the signals. The communications link may be implemented using wire or cable, fiber optics, telephone line, cellular phone link, radio frequency link, and / or other communications channel. It is contemplated that such communications interface 514 enables one or more processors 502 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, embodiments of the present methods may be performed solely on a processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0036] The term "non-transitory computer-readable medium" is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices (such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory), and should not be construed as including transitory objects such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. The computer-readable medium may also be computer code, represented by a computer data signal embodied in a carrier wave and representing sequences of instructions executable by a processor.

[0037] In some embodiments, the partial etch, subsequent etch, and mask formation may occur in one or more etch chambers, with selective deposition of the helmet and sidewall liner occurring in a separate CVD or PECVD chamber. In some embodiments, if an oxygen-containing plasma is used for mask formation, mask formation occurs in the etch chamber. In some embodiments, if a hydrogen-containing plasma is used for mask formation, mask formation occurs in the CVD or PECVD chamber. In some embodiments, the partial etch, subsequent etch, mask formation, and deposition of the helmet mask and sidewall liner occur in situ in a single process chamber.

[0038] While the present disclosure has been described with respect to several preferred embodiments, alterations, modifications, substitutions, and various substitute equivalents are encompassed within the scope of the present disclosure. It should also be noted that there are many alternative means of implementing the methods and apparatuses of the present disclosure. Therefore, the following appended claims are intended to be interpreted to encompass all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted to mean the logic ("A or B or C") using the non-exclusive logical "or," and not to mean "only one of A or B or C." Each step within a process may be optional and not required. In different embodiments, one or more steps may be omitted or steps may be performed in a different order. Furthermore, in various embodiments, different steps may be performed simultaneously rather than sequentially.

Claims

1. 1. A method for etching a feature in a stack, comprising: a) forming a patterned mask over the stack; b) partially etching the stack through the patterned mask; c) depositing a helmet mask over the patterned mask; d) etching the laminate through said helmet mask; A method comprising:

2. 10. The method of claim 1, The method further comprises shaping the helmet mask after partially etching the stack and before depositing the mask.

3. 3. The method of claim 2, The method further comprises depositing a sidewall liner after shaping the mask and before etching the stack.

4. 4. The method of claim 3, The method, wherein the sidewall liner comprises at least one of carbon, a metal, and a semi-metal.

5. 4. The method of claim 3, The method wherein the sidewall liner is provided simultaneously with the deposition of the helmet mask.

6. 3. The method of claim 2, The method, wherein forming the mask includes providing at least one of a hydrogen-based plasma and an oxygen-based plasma.

7. 3. The method of claim 2, The method, wherein shaping the mask comprises removing constrictions in the patterned mask.

8. 10. The method of claim 1, The method, wherein the stack is a silicon oxide-containing stack.

9. 10. The method of claim 1, The method, wherein the stack is a plurality of alternating layers, and at least one of the alternating layers is a silicon oxide-containing layer.

10. 10. The method of claim 1, The partial etching etches the feature until it touches down, and etching the stack through the helmet mask enlarges the bottom of the feature.

11. 10. The method of claim 1, The method wherein the partial etch does not etch until features touch down, and etching the stack through the helmet mask further etches the stack until touch down.

12. 10. The method of claim 1, The method, wherein the step of depositing a helmet mask deposits a helmet mask having a tip.

13. 10. The method of claim 1, The helmet mask comprises carbon.

14. 14. The method of claim 13, The method, wherein the helmet mask further comprises a metal or metalloid-containing dopant.

15. 10. The method of claim 1, The method of claim 1, wherein the helmet mask is deposited with a selectivity such that the ratio of the helmet mask deposition thickness on the top of the mask to the helmet mask deposition thickness at the bottom of a feature is in the range of 50:1 to 100:

1.

16. 10. The method of claim 1, The method wherein the helmet mask is deposited on top of the mask to a thickness ranging from 30 nm to 1 micron.

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