High aspect ratio etching using a liner

Abstract

A method is provided for etching a feature in a stack: a patterned mask is formed on the stack; a feature is partially etched in the stack through the patterned mask; a helmet mask is deposited on the patterned mask and a liner is deposited on the sidewalls of the feature; and the stack is etched through the helmet mask.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS: This application claims the benefit of priority to U.S. Patent Application No. 63 / 400,914, filed August 25, 2022. The above application is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a method for forming semiconductor devices on a semiconductor wafer. [Background technology]

[0003] In the formation of semiconductor devices, etch layers may be etched to form memory holes, lines, or other semiconductor features. Some semiconductor devices may be formed by etching a single layer of silicon dioxide (also known as silicon oxide (SiO2)) to form, for example, capacitors for dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching a bilayer stack of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON) or bilayer stack of alternating silicon dioxide and polysilicon (OPOP). Other alternating layer stacks may also be etched. In some alternating layer stacks, one of the alternating layers may be silicon dioxide. Some alternating layers may even be triple-layer stacks. Such stacks may be used in memory applications or three-dimensional "NOT AND" gates (3D NAND). These stacks tend to require a relatively high aspect ratio (HAR) dielectric etch. Examples of etch characteristics required for high aspect ratio etching include high etch selectivity to the mask (such as an amorphous carbon mask), a small amount of sidewall etching while maintaining a linear profile, and a high etch rate at the etched surface. High aspect ratio etching can result in tapered features that are much wider at the top than at the bottom. Such features can increase device failure rates and limit device density, performance, and depth.

[0004] In the etching process of OPOP stacks using an amorphous carbon mask, a metal-containing passivation agent may be used during the etching process. The metal-containing passivation agent may be applied during the etching process so that passivation and etching occur simultaneously or alternately. The use of tungsten (W)-containing passivation agents has been shown to selectively deposit tungsten on polysilicon over silicon dioxide, resulting in less passivation of the silicon dioxide layer than the polysilicon. Reduced silicon dioxide passivation increases defects such as increased CD and notching. The ability of a passivation layer to protect the substrate is determined by the weakest or thinnest deposit. For example, if a thin deposit on the oxide layer degrades during additional etching, etching of the oxide layer may begin even if tungsten passivation remains on the silicon. As the oxide layer is etched, not only does the CD increase but new defects such as notching and keyholes are formed. Non-uniform passivation can also cause profile twisting, bending, and ionic side bowing.

[0005] In another aspect, a method is provided for etching a feature in a stack: a patterned mask is formed over the stack; a feature is partially etched into the stack through the patterned mask; a tapered liner is deposited on the sidewalls of the feature; the tapered liner is thicker near the top of the feature and thinner near the bottom of the feature; and the stack is etched.

[0006] The background art provided herein is intended to provide a general background to the present disclosure. Information contained in this background art, and aspects of the description that may not otherwise be admitted as prior art at the time of filing, are not admitted, explicitly or implicitly, as prior art to the present disclosure. Summary of the Invention

[0007] To achieve the above and in accordance with the objects of the present disclosure, a method is provided for etching a feature in a stack: a patterned mask is formed over the stack; a feature is partially etched into the stack through the patterned mask; a helmet mask is deposited over the patterned mask, and a liner is deposited on sidewalls of the feature; and the stack is etched through the helmet mask.

[0008] These and other features of the present disclosure will be explained in more detail in the following detailed description, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which similar elements are numbered the same and in which:

[0010] [Figure 1] FIG. 1 is a simplified flow chart of a process used in some embodiments.

[0011] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2C] FIG. 2C is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2D] FIG. 2D is a schematic cross-sectional view of a laminate processed according to some embodiments. [Figure 2E] FIG. 2E is a schematic cross-sectional view of a laminate processed according to some embodiments.

[0012] [Figure 3A] FIG. 3A is a cross-sectional view of a laminate processed according to some embodiments. [Figure 3B] FIG. 3B is a cross-sectional view of a laminate processed according to some embodiments. [Figure 3C] FIG. 3C is a cross-sectional view of a laminate processed according to some embodiments.

[0013] [Figure 4] FIG. 4 is a schematic diagram of an etching chamber that can be used in some embodiments.

[0014] [Figure 5] FIG. 5 is a schematic diagram of a computer system that can be used to implement some embodiments.

[0015] In the drawings, the same components may be denoted by the same reference numerals. Note that the drawings are schematic representations and are not drawn to scale. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present disclosure will now be described in detail with reference to several preferred embodiments illustrated in the accompanying drawings. In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, detailed descriptions of well-known process steps and / or structures are omitted to avoid unnecessarily obscuring the present disclosure.

[0017] Dry development of high-aspect-ratio contacts requires tight control of the sidewall taper angle. Various methods have been attempted to limit the difference in lateral critical dimension (CD) between the top and bottom of etched structures. The demand for tight control of the top and bottom shapes has become particularly acute with the recent development of 3D NAND memory, which features an increased number of layers in ONON or OPOP bilayer structures and thicker structures. An increase in profile (the difference between the top and bottom CDs) poses risks to subsequent device fabrication processes and impacts device performance. Current technology relies on sidewall deposition to prevent lateral CD erosion during reactive ion etching of high-aspect-ratio structures. Maintaining a delicate balance between etching and sidewall deposition is particularly challenging for high-aspect-ratio features. As a result, dry development of high-aspect-ratio structures is limited to thin structures, while etching thicker stacks requires significantly more complex development.

[0018] [Non-touchdown embodiment] Embodiments described herein provide high aspect ratio features deeply etched into a stack, where the width near the top of the feature is approximately equal to the width near the bottom. For ease of understanding, FIG. 1 depicts a simplified flowchart that can be used in some embodiments. A mask is deposited on the stack (step 104). In some embodiments, the mask is a metal- or semi-metal-containing mask. In some embodiments, plasma-enhanced physical vapor deposition (PECVD) is used to deposit a metal-containing dielectric film that can be used as a mask. Methods for depositing tungsten carbide films by PECVD are described in U.S. Pat. No. 9,875,890, entitled "Deposition of Metal Dielectric Films for Hard Mask Applications," issued January 23, 2018, which is incorporated by reference herein for all purposes and may be used in some embodiments. In some embodiments, the deposited tungsten carbide film is patterned to form a mask. In some embodiments, the mask is an amorphous carbon mask containing carbon. In some embodiments, the mask is metal- and semi-metal-free to prevent contamination by metals or semi-metals.

[0019] 2A is a schematic cross-sectional view of a stack 204 that may be etched in some embodiments. In some embodiments, stack 204 includes a substrate 208 beneath multiple bilayers 212 disposed beneath a patterned mask 216. In some embodiments, one or more layers may be disposed between substrate 208 and multiple bilayers 212 and / or between multiple bilayers 212 and patterned mask 216. In some embodiments, patterned mask 216 is an amorphous carbon mask. In some embodiments, the pattern of the patterned mask provides mask features 220 for high aspect ratio contacts. In some embodiments, mask features 220 are formed before stack 204 is placed in an etch chamber. In other embodiments, mask features 220 are formed while stack 204 is placed in an etch chamber. In some embodiments, each bilayer 212 includes a silicon oxide layer 224 and a silicon nitride layer 228. Conductive contacts 232 are present in substrate 208.

[0020] The stack is partially etched (step 108). In some embodiments, an etching gas is supplied. In some embodiments, RF power is supplied to convert the etching gas into a plasma having etching ions. A voltage is applied to accelerate the etching ions in the plasma toward the stack. The etching ions partially etch the stack and also etch a portion of the mask. Etching the stack may include at least one of chemical etching and physical sputtering of the stack.

[0021] 2B is a schematic cross-sectional view of stack 204 after it has been partially etched to form etched feature 240. A portion of mask 216 has been etched away. During the partial etch, patterned mask 216 is partially etched. In some embodiments, the partial etch does not occur until touchdown, as shown in FIG. 2B.

[0022] Optionally, mask shaping may be performed (step 112). In some embodiments where the mask is a carbon-containing mask, a hydrogen-based plasma chemistry is used for mask shaping. In some embodiments, an oxygen-based plasma chemistry is used for mask shaping.

[0023] A liner is deposited on the sidewalls of the partially etched feature (step 116). In some embodiments, the liner is deposited by at least one of a chemical vapor deposition (CVD) or a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, no liner is deposited near the bottom of the partially etched feature. The sidewall liner helps prevent bowing. In some embodiments, the liner is a carbon-containing liner. In some embodiments, during the liner deposition, a portion of the deposition is deposited on a patterned mask, forming a helmet mask on the patterned mask. In some embodiments, to achieve deposition selectivity and a tapered liner profile, the CVD or PECVD deposition of the carbon-containing liner is performed using at least one of an alkane, an alkene, and an alkyne-based hydrocarbon as a precursor at a specific temperature and pressure. In some embodiments, the liner is tapered, being thicker near the top of the etched feature and thinning to zero thickness as it approaches the bottom of the etched feature. In some embodiments, the tapered liner is thickest at the top of the feature and thinnest near the bottom of the liner closest to the bottom of the etched feature. In addition to carbon, some liners also include hydrogen. In some embodiments, the percentage of hydrogen may achieve a desired liner hardness.

[0024] 2C is a schematic cross-sectional view of stack 204 after liner 244 has been deposited (step 116) on the sidewalls of partially etched feature 240. Liner 244 is tapered, being thicker near the top of partially etched feature 240.

[0025] The stack is then further etched (step 120). In some embodiments, this further etch is more intensive than the partial etch of the stack. Figure 2D is a schematic cross-sectional view of stack 204 after stack 204 has been further etched (step 120). In some embodiments, liner 244 and a portion of patterned mask 216 are etched away. In some embodiments, etching of the stack continues until the stack is completely etched, as shown in Figure 2D.

[0026] In some embodiments, the provision of a liner allows for a stronger etch, enlarging the bottom of the feature and reducing the taper of the feature. The liner protects the sidewalls near the top of the partially etched feature, allowing for a stronger etch. This allows for etching the sidewalls near the bottom of the feature to reduce taper while reducing bowing. One of the major challenges in high aspect ratio (HAR) etching is CD scaling. In particular, as the desired feature is scaled vertically, there is a need to simultaneously maintain a constant lateral feature size. In practice, this is very difficult to achieve, and many current technologies involve trade-offs. In some embodiments, the use of a liner allows for CD control and prevents other defects such as notching.

[0027] If further etching is required (step 124), the process may return to the optional mask shaping step (step 112) or to depositing a new sidewall liner (step 116). If no additional etching is required (step 124), an optional step is to remove the remaining sidewall liner 244 and / or the remaining patterned mask 216 (step 128). In some embodiments, an oxygen-containing plasma may be used to remove the carbon-containing liner (244) and patterned mask 216. Figure 2E is a schematic cross-sectional view of stack 204 after the remaining liner 244 and patterned mask 216 shown in Figure 2D have been removed.

[0028] Some embodiments may be used to target oxide / nitride (ONON) multilayer stacks to form features such as contact holes and trenches when manufacturing 3D NAND memory devices. Some embodiments may be used for capacitor etching in dynamic random access memories (DRAMs). Some embodiments may be used for etching silicon oxide and polysilicon bilayers (OPOPs). In some embodiments, the etch depth is greater than 1 micron. In some embodiments, the etch depth is greater than 10 microns.

[0029] An advantage of some embodiments is that they enable device manufacturers to more precisely control the profile of high aspect ratio features. Various embodiments enable enlarging the bottom CD of very high aspect ratio features. Various embodiments enable next generation devices that utilize deeper, higher aspect ratio structures. Various embodiments reduce device manufacturing costs by reducing the number of steps required to develop high aspect ratio contacts. Various embodiments reduce feature width variation along the depth of the feature, resulting in less than a 10% difference in width between any two points along the depth of the feature 240. In some embodiments, the deposition of the sidewall liner also deposits a helmet mask.

[0030] In some embodiments, the stack may be a single silicon-containing layer, such as a single layer of silicon dioxide, silicon nitride, or silicon. In some embodiments, the stack may include a single layer or multiple layers of other silicon-containing materials. In some embodiments, the patterned mask 216 or the liner 244 may include a metal or semimetal dopant. In some embodiments, for etching a stack having a silicon layer, the mask may further include oxygen. In some embodiments, for etching a silicon dioxide stack, the mask may further include silicon. In some embodiments, a metal or semimetal dopant may be present. In some embodiments, the metal in the metal or semimetal dopant is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, and aluminum. In other embodiments, the semimetal is boron.

[0031] [Touchdown type embodiment] In some embodiments, feature 240 may be etched to the full depth of the stack (i.e., nearly to touchdown) during the partial etch (step 108) before liner 244 is deposited. FIG. 3A is a schematic cross-sectional view of stack 204, starting with the stack shown in FIG. 2A , after it has been partially etched to touchdown to form etched feature 240. During the partial etch, patterned mask 216 is partially etched. Etched feature 240 is etched to touchdown, but is significantly tapered. In some embodiments, the touchdown etch extends to the substrate 208, etching the etched feature to its full depth. In some embodiments, the partial etch etched feature 240 nearly touches down to less than 1 micron. In some embodiments, the partial etch etched feature 240 nearly touches down to less than 1.5 microns.

[0032] A liner is deposited (step 116) on the sidewalls of the etched feature 240. Figure 3B is a schematic cross-sectional view of the stack 204 after liner 244 has been deposited (step 116) on the sidewalls of the partially etched feature 240. The liner 244 is tapered, being thicker near the top of the partially etched feature 240 and becoming thinner as it approaches the bottom of the etched feature 240.

[0033] The stack is further etched (step 120). Because the etched feature 240 was etched to touchdown in the partial etch (step 108), this further etch enlarges the tapered bottom of the etched feature 240 rather than etching the etched feature deeper. Figure 3C is a schematic cross-sectional view of the stack 204 after the partial etch (step 108). The bottom of the etched feature 240 has been enlarged. A portion of the liner 244 and the patterned mask 216 have been etched away.

[0034] If no additional etching is required (step 124), an optional step is to remove the remaining sidewall liner 244 and / or the remaining patterned mask 216 (step 128). In some embodiments, an oxygen-containing plasma may be used to remove the carbon-containing liner (244) and patterned mask 216. Figure 3D is a schematic cross-sectional view of stack 204 after the remaining liner 244 and patterned mask 216 shown in Figure 3D have been removed.

[0035] In some embodiments, the timing and process of the sidewall liner deposition may tailor the mask deposition to the desired final feature (reduced bow CD, improved bottom CD, reduced taper, reduced twist, reduced defect formation, etc.) In some embodiments, the helmet mask and sidewall liner act synergistically to improve the profile of the feature.

[0036] The liner allows for the use of thinner patterned masks 216. For example, in some embodiments, the liner allows for etching 2.5 micron deep features using a 0.5 micron thick mask. In some embodiments, the liner allows for etching 6 micron deep features using a 2 micron thick mask. In some embodiments, the use of the liner helps to avoid necking, thereby enabling a process that does not require mask shaping. In some embodiments, the mask thickness is no more than 34% of the stack thickness or the depth of the etched feature.

[0037] In some embodiments where the partial etch is performed to touchdown and the helmet is deposited, a process is provided that can reduce the thickness of the patterned mask 216 by approximately 100 nm over the prior art. In some embodiments where the partial etch is not performed to touchdown, depositing the helmet mask with a liner can reduce the thickness of the patterned mask by 200 nm to 600 nm over the prior art.

[0038] FIG. 4 is a schematic diagram of an etch reactor system 400 usable in some embodiments. In some embodiments, the etch reactor system 400 includes a gas distribution plate 406 providing a gas inlet into an etch chamber 409 surrounded by a chamber wall 452, and an electrostatic chuck (ESC) 408. Within the etch chamber 409, a stack 404 is disposed on the electrostatic chuck 408. The ESC 408 may receive a bias from an ESC source 448. An etch gas source 410 is connected to the etch chamber 409 through the gas distribution plate 406. An ESC temperature controller 450 is connected to the ESC 408. A radio frequency (RF) source 430 provides RF power to the lower electrode and / or upper electrode (in this embodiment, the ESC 408 and the gas distribution plate 406, respectively). In some embodiments, a 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz or 27 MHz power supply constitutes the RF source 430 and the ESC source 448. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, each generator may be provided in a separate RF source, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode, each connected to a different RF source. In other embodiments, other arrangements of RF sources and electrodes may be used. A controller 435 is controllably connected to the RF source 430, the ESC source 448, the exhaust pump 420, and the etching gas source 410. An example of such an etching chamber is the Flex™ Etch System (manufactured by Lam Research Corporation, Fremont, California). The process chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0039] FIG. 5 is a schematic block diagram illustrating a computer system 500 suitable for implementing the controller 435 used in the embodiments. The computer system 500 may take many physical forms, ranging from integrated circuits, printed circuit boards, small handheld devices, to large supercomputers. The computer system 500 includes one or more processors 502 and may further include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., random access memory (RAM)), storage devices 508 (e.g., hard disk drives), removable storage devices 510 (e.g., optical disk drives), user interface devices 512 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 514 (e.g., wireless network interfaces). The communications interface 514 enables software and data transfer between the computer system 500 and external devices via a link. The system may also include a communications infrastructure 516 (e.g., a communications bus, crossover bar, or network) to which the above-mentioned devices / modules are connected.

[0040] Information transferred via communications interface 514 may take the form of signals, such as electronic, electromagnetic, optical, or other signals, that can be received by communications interface 514 over a communications link that transmits the signals. The communications link may be implemented using wire or cable, fiber optics, telephone line, cellular phone link, radio frequency link, and / or other communications channel. It is contemplated that such communications interface 514 enables one or more processors 502 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, embodiments of the present methods may be performed solely on a processor or may be performed over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0041] The term "non-transitory computer-readable medium" is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices (such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory), and should not be construed as including transitory objects such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. The computer-readable medium may also be computer code, represented by a computer data signal embodied in a carrier wave and representing sequences of instructions executable by a processor.

[0042] In some embodiments, the partial etch, subsequent etch, and mask formation may occur in one or more etch chambers, while the selective deposition of the helmet and sidewall liner and mask formation occur in separate CVD or PECVD chambers. An oxygen-containing plasma may be used for mask formation in the etch chamber. A hydrogen-containing plasma may be used for mask formation in the CVD or PECVD chamber. In some embodiments, the partial etch, subsequent etch, mask formation, and deposition of the helmet mask and sidewall liner occur in situ in a single process chamber capable of performing both the etch and CVD or PECVD processes.

[0043] While the present disclosure has been described with respect to several preferred embodiments, alterations, modifications, substitutions, and various substitute equivalents are encompassed within the scope of the present disclosure. It should also be noted that there are many alternative means of implementing the methods and apparatuses of the present disclosure. Therefore, the following appended claims are intended to be interpreted to encompass all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted to mean the logic ("A or B or C") using the non-exclusive logical "or," and not to mean "only one of A or B or C." Each step within a process may be optional and not required. In different embodiments, one or more steps may be omitted or steps may be performed in a different order. Furthermore, in various embodiments, different steps may be performed simultaneously rather than sequentially.

Claims

1. 1. A method for etching a feature in a stack of layers, comprising: a) forming a patterned mask over the stack; b) partially etching features into the stack through the patterned mask; c) depositing a helmet mask over the patterned mask and depositing a liner on the sidewalls of the features; d) etching the laminate through the helmet mask; A method comprising:

2. 10. The method of claim 1, The method, wherein the liner comprises at least one of carbon, a metal, and a metalloid.

3. 10. The method of claim 1, The method wherein the deposition of the liner occurs simultaneously with the deposition of the helmet mask.

4. 10. The method of claim 1, The method further comprising shaping the patterned mask after partially etching features into the stack and before depositing the helmet mask.

5. 10. The method of claim 1, The method wherein the liner is tapered, being thicker near the top of the feature and thinner near the bottom of the feature.

6. 6. The method of claim 5, The method wherein the liner does not extend to the bottom of the feature.

7. 10. The method of claim 1, The method, wherein the helmet mask and tapered liner comprise amorphous carbon.

8. 10. The method of claim 1, The method wherein the stack is a silicon oxide-containing stack.

9. 10. The method of claim 1, The method, wherein the step of partially etching a feature etches the feature until it touches down, and the step of etching the stack through the helmet mask enlarges the bottom of the feature.

10. 10. The method of claim 1, The method of claim 1, wherein the step of partially etching a feature does not etch the feature until it touches down, forming a partially etched tapered feature, and the step of etching the stack through the helmet mask reduces the taper of the tapered feature.

11. 1. A method for etching a feature in a stack of layers, comprising: a) forming a patterned mask over the stack; b) partially etching features into the stack through the patterned mask; c) depositing a tapered liner on the sidewalls of the feature, the tapered liner being thicker near the top of the feature and thinner near the bottom of the feature; d) etching the stack; A method comprising:

12. 12. The method of claim 11, The method, wherein the tapered liner comprises at least one of carbon, a metal, and a metalloid.

13. 12. The method of claim 11, The method wherein the tapered liner does not extend to the bottom of the feature.

14. 12. The method of claim 11, The method wherein the tapered liner comprises amorphous carbon.

15. 12. The method of claim 11, The method wherein the stack is a silicon oxide-containing stack.

16. 12. The method of claim 11, The method wherein the step of partially etching a feature etches the feature until it touches down, and the step of etching the stack enlarges the bottom of the feature.

17. 12. The method of claim 11, The method, wherein the step of partially etching the feature does not etch until the feature touches down, forming a partially etched tapered feature, and the step of etching the stack reduces the taper of the tapered feature.

18. 12. The method of claim 11, The method wherein the patterned mask has a thickness of less than 0.5 microns and the laminate has a thickness of at least 2.5 microns.

19. 12. The method of claim 11, The method, wherein the step of etching the stack is performed to a greater extent than the step of partially etching the feature.

20. 12. The method of claim 11, The method, wherein the patterned mask has a thickness and the stack has a thickness, and the thickness of the patterned mask is no greater than 34% of the thickness of the stack.

Images