Process for reducing warpage and thinning composite structures supported by polycrystalline SiC carrier substrates

Abstract

The present invention relates to a process for processing a composite structure including a thin layer of monocrystalline silicon carbide (11) disposed on a polycrystalline silicon carbide carrier substrate, the composite structure having a front side on the side of the thin layer of monocrystalline silicon carbide and a back side opposite the front side. The process includes forming elements of an electronic component (30) on the front side of the composite structure, followed by grinding the composite structure from its back side, and removing a work-hardened layer (22) present on the surface of the back side after grinding.

Description

[Technical Field]

[0001] The field of the invention is that of processing composite structures supporting elements of electronic components produced on a monocrystalline silicon carbide layer disposed on a polycrystalline silicon carbide carrier substrate. [Background technology]

[0002] Silicon carbide (SiC) is being increasingly widely used in power electronics applications, especially to meet the application needs of new fields of electronics, such as electric vehicles. In particular, single-crystal SiC-based power devices and integrated power systems can handle much higher power densities and with smaller active area sizes than their conventional silicon counterparts.

[0003] Nevertheless, substrates for the microelectronics industry made of single-crystal SiC remain expensive and difficult to supply in large sizes. Therefore, it is advantageous to utilize solutions that typically result in the production of composite structures including a thin layer made of single-crystal SiC on a lower-cost carrier substrate. One such solution is the Smart Cut™ process, which allows for the large-scale production of composite structures including, for example, a thin layer made of single-crystal SiC (sampled from a donor substrate made of single-crystal SiC) in direct contact with a carrier substrate made of polycrystalline SiC. The composite structure has a front side on the side of the thin layer of single-crystal SiC and a back side opposite the front side.

[0004] During front-end processing, electronic component elements (e.g., elements that allow for the formation of vertical transistors) are formed on the front side of the composite structure through a combination of semiconductor film deposition or epitaxial growth, lithography, etching, doping, metal deposition, and passivation steps. The back side of the composite structure is then thinned by grinding, which reduces its thickness from 350 μm to 180 μm or even to 100 μm for a 150 mm diameter carrier substrate, for example. The target thickness reduction depends on the subsequent back-end processing, in which the chips are diced and encapsulated (packaged). This thickness is a compromise between the material's physical properties (needed to mechanically support the chip) and electrical performance (thinning reduces the contribution of the polycrystalline SiC carrier substrate to electrical losses).

[0005] Grinding causes the composite structure to warp. This warpage remains limited after backside grinding of a monocrystalline SiC carrier substrate, e.g., 400-600 μm for a 150 mm diameter carrier substrate. In contrast, this warpage can be significant after backside grinding of the same type of polycrystalline SiC carrier substrate, e.g., approaching 1000 μm for a 150 mm diameter carrier substrate. This significant warpage can exceed the acceptable level of warpage, e.g., 600 μm, that the equipment used during backend processing operations can handle for the composite structure after thinning. Summary of the Invention

[0006] The object of the present invention is to provide a solution that makes it possible to thin the back side of a composite structure comprising a thin layer of monocrystalline SiC supported by a polycrystalline SiC carrier substrate, on which elements of an electronic component are produced, while limiting the warpage to an acceptable level in the subsequent back-end processing.

[0007] To this end, the present invention provides a process for processing a composite structure including a thin layer of monocrystalline silicon carbide disposed on a polycrystalline silicon carbide carrier substrate, the composite structure having a front side on the side of the thin layer of monocrystalline silicon carbide and a back side opposite the front side, the process including forming elements of an electronic component on the front side of the composite structure, followed by thinning the composite structure from its back side by grinding the polycrystalline silicon carbide carrier substrate, and removing a work-hardened layer present on the surface of the back side after grinding.

[0008] Some preferred, but non-limiting aspects of this process are as follows:

[0009] the polycrystalline silicon carbide carrier substrate has a thickness of more than 300 μm before said thinning and a thickness of less than 200 μm after said thinning, preferably a thickness of 100 μm to 200 μm; The backside grinding includes rough grinding and fine grinding in sequence; Rough grinding is carried out using a grinding wheel characterized by an abrasive grit size of less than 5000 mesh; The fine grinding is carried out using a grinding wheel characterized by an abrasive grit size of more than 5000 mesh; The fine grinding is carried out to remove material between 1 μm and 3 μm thick. Rough grinding is performed to remove material with a thickness of more than 100 μm; The work-hardened layer is removed by grinding the backside. The polishing is mechanical polishing or chemical mechanical polishing. Polishing is performed for 5 to 30 minutes. The polishing is carried out to remove a material thickness of 0.2 μm to 2 μm. It further includes backside metallization followed by removal of the work-hardened layer. Following metallization, the composite structure undergoes final manufacturing operations, including chip dicing. [Brief explanation of the drawings]

[0010] Other aspects, objects, advantages and features of the present invention will become more clearly apparent from a reading of the following detailed description of preferred embodiments of the invention, given by way of non-limiting example with reference to the accompanying drawings, in which:

[0011] [Figure 1] FIG. 1 is a schematic cross-sectional view of a single-crystal SiC donor substrate. [Figure 2] 2 is a schematic cross-sectional view of the formation of a weakened surface in the donor substrate of FIG. 1 by implantation of ionic species for the purpose of defining a thin layer of single-crystal SiC to be transferred. [Figure 3] 3 is a schematic cross-sectional view of bonding the donor substrate of FIG. 2 to a polycrystalline SiC carrier substrate. [Figure 4] 1 is a schematic cross-sectional view of peeling off a donor substrate along a weakened plane for the purpose of transferring a thin single-crystalline SiC layer to a polycrystalline SiC carrier substrate, thereby forming a composite structure. [Figure 5] 5 is a schematic cross-sectional view of forming elements of an electronic component on the front side of the composite structure of FIG. 4. [Figure 6] 6 is a schematic cross-sectional view of thinning the backside of the composite structure of FIG. 5. FIG. [Figure 7] 10 is a schematic cross-sectional view of removing the work-hardened layer present on the backside surface after thinning. FIG. [Figure 8] 1 is a graph showing warpage measurements at various steps in the post-manufacturing processing of elements of an electronic component. DETAILED DESCRIPTION OF THE INVENTION

[0012] Detailed Description of Specific Embodiments The present invention relates to a process for processing a composite structure comprising a thin layer of monocrystalline SiC disposed on a polycrystalline SiC carrier substrate and elements of an electronic component formed on the thin layer of monocrystalline SiC.

[0013] This treatment may be preceded by the transfer of a thin layer of monocrystalline SiC from a donor substrate, at least a surface portion of which is made of monocrystalline SiC, to the carrier substrate according to the Smart-Cut™ process.

[0014] The donor substrate can be a bulk substrate of single-crystal SiC. In other embodiments, the donor substrate can be a composite substrate including a surface layer of single-crystal SiC and at least one other layer of another material. In this case, the layer of single-crystal SiC preferably has a thickness of 0.3 μm or greater.

[0015] Polycrystalline SiC carrier substrates are typically produced by chemical vapor deposition of polycrystalline SiC onto a growth substrate, such as a graphite substrate. The carrier substrate thus has columnar grains oriented in the growth direction of the deposition. Polycrystalline SiC carrier substrates preferably have an initial thickness greater than 300 μm. For example, polycrystalline SiC carrier substrates can be in the form of 150 mm diameter wafers with an initial thickness of 350±25 μm. Alternatively, polycrystalline SiC carrier substrates can be in the form of 200 mm diameter wafers with an initial thickness of approximately 500 μm.

[0016] 1, transfer via the Smart-Cut™ process begins with the preparation of a donor substrate 10, at least a surface portion of which is made of single crystal SiC. Illustrated is a single crystal SiC bulk substrate 10.

[0017] 2, the transfer further includes implanting ionic species into the donor substrate 10 to form a weakened surface 12 that defines the thin layer 11 of single crystal SiC to be transferred. The implanted species typically include hydrogen and / or helium. Those skilled in the art will be able to determine the required dose and energy.

[0018] If the donor substrate is a composite substrate, the implantation is carried out so as to form a weakened surface in the surface layer of the monocrystalline SiC of said donor substrate.

[0019] The thin layer 11 of monocrystalline SiC preferably has a thickness of less than 1 μm. In particular, such a thickness is achievable on an industrial scale by the SmartCut™ process. In particular, implantation devices available on industrial production lines make it possible to obtain such implantation depths.

[0020] 3, after the implantation, the transfer involves bonding the donor substrate to a carrier substrate 20, with a thin layer of single crystal SiC 11 at the interface. The bonding can be atomic diffusion bonding (ADB).

[0021] 4, the transfer then involves peeling off the donor substrate 10 along the weakened plane 12 to transfer the thin layer of single-crystal SiC 11 to the carrier substrate 20. In known manner, this peeling can be caused by heat treatment, mechanical action, or a combination of these means. The remaining portion 10′ of the donor substrate may optionally be recycled for another use.

[0022] One or more finishing operations may then be applied to the transferred layer of monocrystalline SiC 11. For example, smoothing, cleaning or further polishing, e.g., chemical mechanical polishing (CMP), may be performed to remove defects related to the implantation of ion species and to reduce the roughness of the transferred layer of monocrystalline SiC 11. A high-temperature heat treatment may also be performed, which has the effect of stabilizing the structure and thereby guaranteeing the geometry in subsequent steps, provided that no surface elements of the electrical transistor components are deposited on the surface.

[0023] Then, as shown in FIG. 5, elements 30 of an electronic component are formed on the thin layer of single-crystal SiC 11, typically through a combination of steps of semiconductor film deposition or epitaxial growth, lithography, etching, doping, metal deposition, and passivation. These elements 30 of the electronic component include, for example, elements of a vertical transistor. These elements 30 are disposed on a front side FF of the composite structure, on the side of the thin layer of single-crystal SiC 11. Additionally, the composite structure has a back side BF opposite the front side FF.

[0024] After these electronic component elements 30 are formed on the front side FF, the composite structure is processed, which includes thinning the composite structure from the back side BF to reduce its thickness to a target thickness that is compatible with the requirements of back-end processing, such as 180 μm or even less.

[0025] As shown in FIG. 6 , this process involves grinding the backside BF of the composite structure, i.e., grinding the free side of the polycrystalline SiC carrier substrate 20. The frontside FF, for its part, is typically covered with protective tape. After grinding the backside of the composite structure, the thinned composite structure preferably has a thickness of 100 μm to 200 μm. Alternatively, if precautions are taken to ensure the mechanical stability of the wafer after thinning, the thinned composite structure can have a thickness less than 100 μm. As noted above, this grinding generates warpage that can be more than twice the warpage observed when the same grinding is applied to the backside of a monocrystalline SiC carrier substrate supporting similar electronic component elements on its front side.

[0026] This considerable warpage is, according to the inventors, the use of the Smart-Cut™ process, which combines a thin layer of single-crystal SiC with a polycrystalline SiC carrier substrate, i.e., materials with slightly different thermal expansion coefficients, and therefore the bonding interface may exhibit residual stresses that can cause sensitivity to warpage; the contribution of the bulk carrier substrate, which may retain residual stress due to the fabrication process involving chemical vapor deposition and subsequent annealing; This can be due to the contribution of the surface of the carrier substrate, which under the influence of grinding ends up with a certain surface roughness or damaged surface areas, thereby inducing surface stresses.

[0027] In accordance with the present invention, grinding the backside of the composite structure can include a coarse grind followed by a fine grind.

[0028] Rough grinding allows for the removal of significant thicknesses of polycrystalline SiC, greater than 100 μm, at rates compatible with industrial processes. For example, rough grinding removes 150 to 250 μm of polycrystalline SiC for a 150 mm diameter substrate, and 300 to 400 μm of polycrystalline SiC for a 200 mm diameter substrate. Rough grinding can remove material at rates greater than 0.2 μm / min, e.g., 0.3 μm / min. It can be performed using a grinding wheel characterized by an abrasive grit size of less than 5000 mesh, e.g., 2000 mesh.

[0029] Rough grinding generates large surface stresses in polycrystalline SiC, which can lead to significant warpage. In particular, rough grinding generates lattice defects in the columnar microstructure of polycrystalline SiC down to a depth of several microns, leading to the formation of a work-hardened layer on the back surface of the carrier substrate.

[0030] Fine grinding can reduce pre-created stress, for example, by removing 1 μm to 3 μm of material. It can be performed using a grinding wheel characterized by an abrasive grit size of more than 5000 mesh, for example, 8000 mesh. Fine grinding is performed at a slower speed than coarse grinding, preferably at a speed of less than 0.2 μm / min. At the end of fine grinding, the warpage is significantly reduced, but remains above the acceptable warpage level for back-end processing. Therefore, fine grinding reduces the thickness of the work-hardened layer without completely removing it.

[0031] According to one particular embodiment of the coarse grinding, the coarse grinding can itself include a very coarse grinding and a less coarse grinding, in sequence. The very coarse grinding can be performed using a grinding wheel characterized by an abrasive grit size of less than 1000 mesh, for example, 300 mesh, and the less coarse grinding can be performed using a grinding wheel characterized by an abrasive grit size of less than 5000 mesh, for example, 2000 mesh. The very coarse grinding is preferably performed at a speed greater than the speed of the less coarse grinding. In this embodiment of the coarse grinding, the very coarse grinding removes most of the total thickness of the polycrystalline SiC removed by the coarse grinding, and the less coarse grinding removes the last few μm. For example, the less coarse grinding removes 20 μm of the total thickness of the polycrystalline SiC removed by the coarse grinding. Specifically, very coarse grinding shortens the total grinding time, but generates a very thick work-hardened layer, approximately 20 μm thick, on the rear surface of the carrier substrate. Grinding with a lower roughness allows the very thick work-hardened layer to be removed. Although less coarse grinding also generates a work-hardened layer, the thickness of the work-hardened layer generated by less coarse grinding is, as mentioned above, only a few μm thick.

[0032] In embodiments where rough grinding includes a very coarse grinding and a less coarse grinding in sequence, the coarse grinding is also followed by a fine grinding, as described above. The less coarse grinding allows for a less thick work-hardened layer than the very thick work-hardened layer generated by the very coarse grinding, which can then be thinned by fine grinding and finally removed in a time period compatible with industrial processes. Thus, as shown in FIG. 6, after backside thinning by grinding, the composite structure has a work-hardened layer 22 on the surface of the thinned polycrystalline SiC substrate 21, which has not been completely removed by the fine grinding.

[0033] According to the present invention, referring to FIG. 7, the work-hardened layer 22 present on the surface of the backside of the composite structure after thinning is then removed. This removal is achieved, for example, by polishing the thinned backside. This polishing can be carried out to remove a thickness of less than 3 μm, for example, less than 2 μm, or even 0.2 μm to 1 μm, or preferably 0.2 μm to 0.5 μm. In addition to reducing surface roughness, this polishing has the advantage of reducing warpage to a level acceptable for back-end processing implementations.

[0034] Polishing can be carried out for 5 minutes to 30 minutes, for example 10 minutes. Polishing can be carried out at a pressure of 5 to 100 decaN, preferably 7 decaN to 30 decaN. Polishing can be mechanical polishing (simple mechanical action without chemical action) or chemical mechanical polishing (CMP).

[0035] Following the removal of the work-hardened layer, the process includes a step of metallization, e.g., localized metallization, of the backside of the composite structure. This metallization is intended to form contacts or electrodes (e.g., vertical transistor drains) on the backside for elements of electronic components formed on the frontside. In this context, it is preferable to first remove the work-hardened layer by mechanical polishing. In particular, unlike chemical-mechanical polishing or purely chemical polishing, mechanical polishing has the advantage of avoiding the creation of additional roughness as a result of grain boundary decoration, resulting in a surface finish that is more favorable for metallization adhesion.

[0036] After this metallization is performed, the composite structure processed according to the present invention and having much lower warpage can undergo back-end processing, particularly the final manufacturing operations of chip dicing.

[0037] Figure 8 shows the measured warpage G (in μm) of five composite structures W1-W5, each consisting of a thin layer of single-crystal SiC on a carrier substrate made of polycrystalline SiC and supporting elements of an electronic component on its front side, and two bulk substrates W6-W7 made of single-crystal SiC and supporting the same elements of an electronic component on their front sides. More precisely, in Figure 8, squares represent the warpage before backside thinning, upward-pointing triangles represent the warpage after backside thinning including sequential rough grinding and fine grinding, downward-pointing triangles represent the warpage after removal of the work-hardened layer by mechanical polishing, and diamonds represent the warpage after removal of the work-hardened layer by chemical-mechanical polishing.

[0038] It can be seen that the warpage of bulk single crystal SiC substrates W6-W7 is already tolerable after thinning, while the warpage of composite structures W1-W5 is significantly larger after thinning, exceeding the maximum allowable value of 600 μm. However, after removal of the work-hardened layer, the warpage of composite structures W1-W5 is obviously reduced and is now below the allowable limit of 600 μm.

Claims

1. 1. A process for processing a composite structure comprising a thin layer (11) of monocrystalline silicon carbide disposed on a polycrystalline silicon carbide carrier substrate (20), the composite structure having a front side (FF) on the side of the thin layer of monocrystalline silicon carbide and a back side (BF) opposite the front side, the process comprising the steps of forming elements (30) of electronic components on the front side of the composite structure, followed by thinning the composite structure from its back side by grinding the polycrystalline silicon carbide carrier substrate (20), and removing a work-hardened layer (22) present on the surface of the back side after grinding.

2. 2. The process of claim 1, wherein the polycrystalline silicon carbide carrier substrate has a thickness of more than 300 μm before the thinning and a thickness of less than 200 μm after the thinning, preferably between 100 μm and 200 μm.

3. The process of claim 1 or 2, wherein the grinding of the backside comprises, in sequence, coarse grinding and fine grinding.

4. 4. The process of claim 3, wherein the coarse grinding is performed with a grinding wheel characterized by an abrasive grit size of less than 5000 mesh.

5. 5. The process according to claim 3 or 4, wherein the fine grinding is carried out using a grinding wheel in which the abrasive grit size is characterized by a mesh of more than 5000.

6. A process according to any one of claims 3 to 5, wherein the fine grinding is carried out to remove a material thickness of 1 μm to 3 μm.

7. The process according to any one of claims 3 to 6, wherein the rough grinding is carried out to remove a material thickness of more than 100 μm.

8. The process of any one of claims 1 to 7, wherein the work-hardened layer is removed by polishing the backside.

9. The process of claim 8 , wherein the polishing is mechanical polishing.

10. The process of claim 8 , wherein the polishing is chemical-mechanical polishing.

11. The process according to any one of claims 8 to 10, wherein the polishing is carried out for 5 to 30 minutes.

12. A process according to any one of claims 8 to 11, wherein the polishing is carried out to remove a material thickness of less than 3 μm.

13. The process of any one of claims 1 to 12, further comprising metallizing the backside following removal of the work-hardened layer.

14. The process of claim 13 , wherein following said metallization, said composite structure undergoes final manufacturing operations including chip dicing.

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