Method and apparatus for reducing inter-stage gain errors in analog-to-digital converters

Abstract

An exemplary analog-to-digital converter (ADC) (100) includes a sample-and-hold circuit element (120) coupled to an analog input (VIN), a first sub-ADC (130) coupled to the sample-and-hold circuit element, a multiplying digital-to-analog converter (M-DAC) (140) coupled to the first sub-ADC, a summing circuit element (160) coupled to the sample-and-hold circuit element and the M-DAC, an amplifier (170) coupled to the summing circuit element, a second sub-ADC (180) coupled to the amplifier (160), and a reference generation circuit element (150) coupled to the first sub-ADC, the M-DAC, and the second sub-ADC (180). The reference generation circuit element (150) includes a reference voltage circuit element coupled to the M-DAC, a first resistor coupled to the reference voltage circuit element, a second resistor coupled to the first resistor, and a capacitor coupled in parallel to the second resistor by a switch.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION This description relates generally to analog-to-digital conversion, and more particularly to methods and apparatus for reducing inter-stage gain errors in analog-to-digital converters. [Background technology]

[0002] Digital signal processing often uses analog-to-digital converters (ADCs) to convert analog inputs (e.g., external analog signals) to digital outputs. ADCs require time to perform such conversions, often limiting digital signal processing. Pipeline ADCs can convert analog inputs to digital outputs at relatively high speeds with relatively high accuracy. A pipeline ADC may include a first stage that determines at least one of the most significant bits (MSBs) of the digital output and a second stage that determines the remaining bits of the digital output. Summary of the Invention

[0003] Regarding a method and apparatus for reducing inter-stage gain error in an analog-to-digital converter, an exemplary analog-to-digital converter (ADC) includes a sample-and-hold circuit element coupled to an analog input, a first sub-ADC coupled to the sample-and-hold circuit element, a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC, a summing circuit element coupled to the sample-and-hold circuit element and the M-DAC, an amplifier coupled to the summing circuit element, a second sub-ADC coupled to the amplifier, and a reference generation circuit element coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuit element including a reference voltage coupled to the M-DAC, a first resistor coupled to the reference voltage, a second resistor coupled to the first resistor, and a capacitor coupled in parallel to the second resistor by a switch. [Brief explanation of the drawings]

[0004] [Figure 1]FIG. 1 is a block diagram of an example pipelined analog-to-digital converter including reference generation circuitry configured to generate a high voltage reference and a low voltage reference.

[0005] [Figure 2] 2 is a schematic diagram of the reference generation circuitry of FIG. 1 configured to generate a low voltage reference using a high voltage reference.

[0006] [Figure 3] FIG. 3 is a schematic diagram of a switch configured to use charge injection cancellation to reduce charge injection caused by switching of the reference generation circuitry of FIGS. 1 and 2.

[0007] [Figure 4] FIG. 3 is a schematic diagram of an example input stage of a reference amplifier including offset compensation circuitry and temperature compensation circuitry configured to trim a low voltage reference generated by the reference generation circuitry of FIGS. 1 and 2.

[0008] [Figure 5] 5 is a schematic diagram of the offset compensation circuitry of FIG. 4 configured to generate an offset voltage to compensate the low voltage reference generated by the reference generation circuitry of FIGS. 1 and 2 for direct current (DC) offsets.

[0009] [Figure 6] 5 is a schematic diagram of the temperature compensation circuitry of FIG. 4 configured to generate a temperature compensation voltage to compensate the low voltage reference generated by the reference generation circuitry of FIGS. 1 and 2 for variations in temperature.

[0010] [Figure 7] 3 is a timing diagram of an example switching operation of the reference generation circuitry of FIGS. 1 and 2 to generate a low-voltage reference.

[0011] [Figure 8]8 is a timing diagram of an example operation of the reference generation circuitry of FIGS. 1 and 2, including a low voltage reference and a high voltage reference, the low voltage reference being generated using the switching operation of FIG. 7;

[0012] [Figure 9] 1 is a flowchart illustrating an example method that may be implemented using hardware circuitry and / or executable machine-readable instructions and / or hardware configured to implement the reference generation circuitry of FIGS. 1 and 2 and / or, more generally, the pipelined ADC of FIG. 1.

[0013] [Figure 10] 10 is a block diagram of an example processing platform including processor circuitry configured to execute example machine-readable instructions and / or the example operations of FIG. 9 for implementing the reference generation circuitry of FIGS. 1 and 2.

[0014] In the drawings, the same reference numbers or other reference designators are used to indicate the same or similar (functionally and / or structurally) features. DETAILED DESCRIPTION OF THE INVENTION

[0015] The drawings are not necessarily to scale. Generally, like reference numbers in the drawings and this description refer to the same or similar parts. While the drawings show regions with neat lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be invisible, blended, and / or irregular.

[0016] Digital signal processing may use an analog-to-digital converter (ADC) to convert an analog input signal (such as a signal from a sensor or a signal received from a transmitter) into a digital output signal. For example, a microcontroller may include an ADC to convert a voltage provided by a sensor into a digital value so that the microcontroller can perform an operation on the digital value using processor circuitry. ADCs require time to perform such a conversion, which often limits digital signal processing. As digital signal processing becomes more advanced, some systems require ADCs that can convert analog inputs to digital outputs at relatively high speeds and with high resolution.

[0017] A pipeline ADC converts an analog input signal to a digital output signal at a relatively high speed and with high resolution. The pipeline ADC may include a first stage that determines at least one of the most significant bits (MSBs) of the digital output and a second stage that determines the remaining bits of the digital output. The digital output of the pipeline ADC is a combination of the MSB determined by the first stage and the remaining bits determined by the second stage.

[0018] The first stage includes a first sub-ADC and a multiplying digital-to-analog converter (M-DAC). The first sub-ADC is a relatively low-resolution ADC, so that the digital output of the sub-ADC generates fewer bits than the digital output of the pipeline ADC. The first sub-ADC determines at least one most significant bit (MSB) of the digital output of the pipeline ADC by comparing an input signal with a relatively large reference signal.

[0019] The first stage removes a voltage representing the MSB of the digital output from the analog input to reduce the voltage of the input to the second stage of the pipeline ADC. The MSB of the digital output corresponds to approximately half the potential voltage of the analog input. For example, a pipeline ADC capable of converting an analog input between plus and minus 48 volts sets the MSB equal to logic one when the analog input is approximately zero volts or greater. In such an example, the digital output of the first sub-ADC sets the MSB equal to logic zero (e.g., logic low or 0) when the analog input is less than zero volts and sets the MSB equal to logic one (e.g., logic high or 1) when the analog input is greater than approximately zero volts. The first sub-ADC may also determine one or more additional bits of the digital output to further reduce the voltage of the input to the second stage of the pipeline ADC.

[0020] The M-DAC generates an analog output based on the MSB determined by the first sub-ADC. For example, a pipelined ADC capable of converting an analog input between plus and minus 48 volts causes the M-DAC to generate an analog output of 36 volts when the analog input is greater than 24 volts. In this example, the first sub-ADC determines that the two MSBs of the digital output are logic 1, so that the MSB represents an analog input greater than zero volts and the second MSB represents an analog input greater than 24 volts.

[0021] The M-DAC uses a first reference input to convert the MSB from the first sub-ADC to an analog output. The M-DAC requires that the first reference input be supplied with a reference voltage equal to the voltage represented by the MSB of the pipeline ADC to ensure that the M-DAC can generate an analog output equal to the analog voltage represented by the MSB. For example, the first stage of the pipeline ADC, which determines the two MSBs of the digital output, requires a reference voltage of 48 volts when the two MSBs of the digital output are logic 1 and the analog output of the M-DAC is 36 volts. The pipeline ADC subtracts the analog output of the M-DAC from the analog input of the pipeline ADC to reduce the analog input by the analog output of the M-DAC. Advantageously, the pipeline ADC can use relatively lower voltage and higher speed circuitry in the second stage as a result of the first stage lowering the analog input.

[0022] The second stage determines the remaining bits of the digital output using a second sub-ADC. The second sub-ADC determines the remaining bits of the analog input using a second reference input coupled to a second reference voltage that is lower than the first reference voltage of the first stage. Advantageously, lower voltage circuitry included in the second stage reduces the conversion time and power dissipation of the second sub-ADC.

[0023] Inter-stage gain error occurs when there is a mismatch in the reference voltages between the first and second stages. Inter-stage gain error results from unaccounted differences in the reference voltages of the first and second stages. Inter-stage gain error causes inaccuracies in the digital output of a pipeline ADC, such as one or more incorrect bits. Inter-stage gain error reduces the signal-to-noise ratio (SNR) and, similar to residual amplifier gain error, increases harmonic distortion in the digital output.

[0024] Some systems prevent inter-stage gain errors by using the same reference input for the first and second stages. In these examples, the second stage is supplied with a first reference voltage capable of generating an analog value representing the MSB of the pipeline ADC, requiring the second stage to include circuitry capable of using the first reference voltage. Supplying this relatively high voltage circuitry to the second stage increases the duration required to convert the analog input to a digital output, resulting in increased power dissipation. Another method for preventing inter-stage gain errors is to use the reference voltage of the first stage as the first reference voltage for the least significant bits of the second stage. In this method, the second stage uses a second reference voltage for the most significant bits that is relatively lower than the first reference voltage. This method increases the speed of the second stage, requires the second stage to include circuitry capable of supporting the reference voltage of the first stage, and reduces inter-stage redundancy. Both methods of reducing inter-stage gain error can route the reference input from the first stage to the second stage to reduce the conversion rate and increase the likelihood of coupling between components.

[0025] Examples described herein include a pipeline ADC including a reference generation circuitry configured to reduce inter-stage gain error. In some described examples, the reference generation circuitry generates a relatively low voltage reference for a second stage of the pipeline ADC using a relatively high voltage reference supplied to the first stage. The reference generation circuitry supplies both a high voltage reference and a low voltage reference to the first stage and a low voltage reference to the second stage. The reference generation circuitry generates the low voltage reference using a voltage divider across the high voltage reference, so that a voltage sampled at the voltage divider is proportional to the high voltage reference. The reference generation circuitry samples the voltage divider using a first switch and a first capacitor. The first capacitor is configured to hold the sampled voltage while the first switch is open and the first capacitor is no longer coupled to the voltage divider. The reference generation circuitry samples the voltage held across the first capacitor using a second switch and a second capacitor to generate the low voltage reference. The capacitance of the second capacitor is larger than the first capacitor to reduce noise in the low voltage reference. Advantageously, generating the low voltage reference using reference generation circuitry in response to the low voltage reference being proportional to the high voltage reference reduces inter-stage gain errors in the pipelined ADC.

[0026] 1 is a block diagram of an example pipeline ADC 100. In the example of FIG. 1, the pipeline ADC 100 includes a buffer 110, sample-and-hold circuitry 120, a first sub-ADC 130, an M-DAC 140, a reference generation circuitry 150, a summing circuitry 160, an amplifier 170, and a second sub-ADC 180. The pipeline ADC 100 receives an analog input (V IN ) to digital output (D OUT ) (not shown) (for example, M+K bit length). The digital output of the pipeline ADC 100 is converted into the MSB (D OUT_MSB ) (for example, M bits) from the second sub-ADC 180 and the remaining bits (D OUT_LSB) (e.g., K bits). The pipelined ADC 100 includes a first low-voltage reference (V REFL1 ) and high voltage reference (V REFH A second low-voltage reference (V REFL2 ) and includes reference generation circuitry 150.

[0027] In the example of FIG. 1, a buffer 110 is connected to an analog input (V IN ) and sample-and-hold circuitry 120. Buffer 110 isolates the circuitry configured to generate the analog input from pipeline ADC 100, thereby preventing circuitry including pipeline ADC 100 from modifying the analog input. Buffer 110 provides the isolated analog input to sample-and-hold circuitry 120.

[0028] The sample and hold circuit element 120 is coupled to the buffer 110, the first sub-ADC 130, and the summing circuit element 160. The sample and hold circuit element 120 samples the isolated analog input from the buffer 110. The sample and hold circuit element 120 resamples the isolated analog input from the buffer 110 after a certain duration. For example, the sample and hold circuit element 120 samples the isolated analog input from the buffer 110 approximately every 100 microseconds (μS). Alternatively, the sample and hold circuit element 120 may sample the isolated analog input in response to an event such as an alert or enable signal. The duration between samples may be determined based on the analog-to-digital conversion speed of the pipeline ADC 100. The sample and hold circuit element 120 holds the sampled analog input between samples. The sample and hold circuit element 120 provides the sampled analog input to the first sub-ADC 130 and the summing circuit element 160.

[0029] The first sub-ADC 130 is coupled to the sample and hold circuitry 120, the M-DAC 140, the reference generation circuitry 150, and the summing circuitry 160. The first sub-ADC 130 receives the sampled analog input from the sample and hold circuitry 120 and the first low-voltage reference (V REFL1 ) and determines at least one of the MSBs of the digital output of the pipeline ADC 100. The first sub-ADC 130 determines the MSB (e.g., M bits, where M is greater than or equal to 1) of the digital output by determining whether the sampled analog input is greater than or equal to approximately half the voltage range of the pipeline ADC 100. The voltage range of the pipeline ADC 100 includes all voltages that can be represented using the digital output of the pipeline ADC 100. For example, a voltage range equal to twice the high voltage reference corresponds to a digital output of the pipeline ADC 100 that can represent voltages between plus and minus the high voltage reference. In such an example, the first low voltage reference may be approximately half the high voltage reference (approximately one-quarter of the voltage range) to determine the two MSBs of the digital output between plus and minus half the high reference voltage. The MSB of the digital output of the pipeline ADC 100 may represent the sign of the digital output. For example, if the analog input has a voltage range between +X volts and −X volts, the first sub-ADC 130 may determine that the MSB of the digital output of the pipeline ADC 100 is logic 1 when the sampled analog input is greater than or equal to zero volts, and the digital output of the pipeline ADC 100 may represent the analog input between plus and minus the high-voltage reference. The first sub-ADC 130 may scale the analog input by a gain less than one to reduce the low-voltage reference. For example, the first sub-ADC 130 may scale the analog input by half to represent a voltage equal to twice the low-voltage reference. In such an example, the first low-voltage reference may be one-quarter the high-voltage reference to represent a voltage between plus and minus one-half of the high-voltage reference, such as two MBS of the digital output.

[0030] The first sub-ADC 130 may determine multiple MSBs of the digital output. For example, the first sub-ADC 130 determines that the three MSBs (e.g., M=3) of the digital output of the pipeline ADC 100 are equal to logic one when the sampled analog input is greater than or equal to three-quarters of the high-voltage reference. In such an example, the first MSB represents the sampled analog input greater than a common potential (e.g., ground or zero volts), the second MSB represents the sampled analog input greater than one-half of the high-voltage reference, and the third MSB represents the sampled analog input greater than three-quarters of the high-voltage reference. The first sub-ADC 130 determines the MSBs (D OUT_MSB ) to the M-DAC 140. Advantageously, the first low-voltage reference allows the first sub-ADC 130 to include lower voltage and higher speed circuitry.

[0031] The M-DAC 140 is coupled to the first sub-ADC 130, the reference generation circuitry 150, and the summing circuitry 160. The M-DAC 140 receives the MSB of the digital output from the first sub-ADC 130 and the high voltage reference (V REFH) and generates an analog output based on the high-voltage reference. For example, the analog output of the M-DAC 140 is equal to one-half of the high-voltage reference when the two MSBs of the output of the first sub-ADC 130 are both logic 1. In such an example, the MSB being logic 1 represents a sampled analog input greater than a common potential (e.g., ground), and the second MSB being logic 1 represents a sampled analog input greater than one-half of the high-voltage reference. The analog output of the M-DAC 140 is an analog representation of the MSB of the digital output from the first sub-ADC 130. For example, the analog output of the M-DAC 140 is approximately equal to a common potential (e.g., ground) when the MSB of the digital output from the first sub-ADC 130 is logic 1 and any remaining bits of the output of the first sub-ADC 130 are zero. In such an example, the first sub-ADC 130 at a minimum (e.g., M=1) determines that the sampled analog input is greater than common, so that any subsequent ADC operation requires a reference voltage approximately half the high-voltage reference. The M-DAC 140 requires the high-voltage reference to be greater than or equal to half the difference between the highest and lowest voltages that can be represented by the MSB of the digital output. For example, the high-voltage reference needs to be at least 24 volts when the two MSBs of the digital output are logic 1 (corresponding to 24 volts). In such an example, the voltage range of the pipeline ADC 100 is plus / minus 48 volts, so that the MSB of the digital output corresponds to being greater than common, and the second MSB corresponds to being greater than or equal to half the difference between common and half the voltage range. The M-DAC 140 provides an analog output to the summing circuitry 160.

[0032] The reference generation circuitry 150 is coupled to the first sub-ADC 130, the M-DAC 140, and the second sub-ADC 180. The reference generation circuitry 150 generates a high voltage reference (V REFH ) and a first and second low-voltage reference (V REFL1 and V REFL2) to generate a low-voltage reference. Generating such a low-voltage reference reduces inter-stage gain error between the M-DAC 140 and the second sub-ADC 180. The reference generation circuitry 150 is further described below in connection with FIG. 2. The reference generation circuitry 150 provides a first low-voltage reference to a first reference input of the first sub-ADC 130. The reference generation circuitry 150 provides a high-voltage reference to a second reference input of the M-DAC 140. The reference generation circuitry 150 provides a second low-voltage reference to a third reference input of the second sub-ADC 180.

[0033] The summing circuit element 160 is coupled to the sample-and-hold circuit element 120, the M-DAC 140, and the amplifier 170. The summing circuit element 160 generates a subtracted analog output by subtracting the analog output of the M-DAC 140 from the sampled analog input of the sample-and-hold circuit element 120. For example, the subtracted analog output is 4 volts when the sampled analog input is 28 volts and the analog output of the M-DAC 140 is 24 volts (e.g., M=2 and MSB is 11). The summing circuit element 160 provides the subtracted analog output to the amplifier 170. The subtracted analog output may be referred to as a residue. Advantageously, the summing circuit element 160 reduces the sampled analog input to allow the amplifier 170 and the second sub-ADC 180 to include relatively lower voltage circuitry capable of relatively faster operation than the circuitry used by the M-DAC 140.

[0034] The amplifier 170 is coupled to the summing circuit element 160 and the second sub-ADC 180. The amplifier 170 amplifies the subtracted analog output from the summing circuit element 160 by a design gain (G). By amplifying the subtracted analog output, the amplifier 170 reduces the noise provided by the second sub-ADC 180. For example, noise in the range of +1 millivolt (mV) to −1 millivolt (mV) resulting from the second sub-ADC 180 has a significantly greater impact on a 10 millivolt (mV) signal than if the signal were amplified to 10 volts (V). Advantageously, the amplifier 170 reduces the noise resulting from the second sub-ADC 180.

[0035] The amplifier 170 may amplify the subtracted analog output to increase the number of bits that can be determined by the second sub-ADC 180 at a fixed resolution. For example, the number of bits determined by a sub-ADC capable of 10 millivolt (mV) accuracy may be increased to 1 millivolt (mV) accuracy by amplifying the subtracted analog input by a design gain of 10. In such an example, the bits determined by the second sub-ADC 180 may be scaled to match the MSB determined by the first sub-ADC 130. Advantageously, the accuracy of the second sub-ADC 180 may be increased as a result of the amplifier 170 amplifying the subtracted analog input. The amplifier 170 supplies the amplified subtracted analog input to the second sub-ADC 180.

[0036] The second sub-ADC 180 is coupled to the reference generation circuitry 150 and the amplifier 170. The second sub-ADC 180 determines multiple bits of the digital output of the pipeline ADC 100 based on a second low-voltage reference from the reference generation circuitry 150 and the amplified, subtracted analog input from the amplifier 170. The M-DAC 140 and the summing circuitry 160 reduce the voltage range of the second sub-ADC 180 by more than half the voltage range of the analog input. For example, the circuitry including the second sub-ADC 180 needs to accommodate a voltage range of plus or minus 25 percent of the voltage range of the analog input when the first sub-ADC 130 determines the two MSBs of the digital output. Advantageously, the circuitry including the second sub-ADC 180 can be a relatively lower-voltage circuitry, allowing for increased speed, compared to the circuitry including the first sub-ADC 130 and the M-DAC 140.

[0037] In exemplary operation of the pipeline ADC 100, the sample-and-hold circuit element 120 samples an isolated analog input and provides the sampled analog input to the first sub-ADC 130 and the summing circuit element 160 for a hold time. This hold time may be referred to as a hold phase. The first sub-ADC 130 determines the MSB of the digital output of the pipeline ADC 100 using a first low-voltage reference. The first sub-ADC 130 provides the determined MSB to the M-DAC 140. The M-DAC 140 converts the MSB to an analog output using a high-voltage reference. As described in more detail below, the M-DAC 140 includes circuitry (not shown) that creates a voltage swing at the high-voltage reference. For example, charge injection from switches internal to the M-DAC 140 may cause the high-voltage reference to swing above and / or below the average voltage being supplied. The voltage swing does not account for gain errors that cannot be trimmed using a one-time trim. The voltage swing at the high voltage reference prevents reference generation circuitry 150 from using a voltage divider to generate the low voltage reference. Such a voltage swing at the high voltage reference is illustrated and described in more detail below in connection with Figures 7 and 8. The voltage swing at the high voltage reference settles over time. However, the voltage swing causes the average voltage supplied to M-DAC 140 to fluctuate.

[0038] Reference generation circuitry 150 reduces inter-stage gain errors resulting from variations in the high-voltage reference by proportionally matching variations in the average voltage of the high-voltage reference on the low-voltage reference. Reference generation circuitry 150 generates the low-voltage reference using the high-voltage reference, so that the low-voltage reference is proportional to the high-voltage reference. Reference generation circuitry 150 samples the low-voltage reference from the high-voltage reference near the end of the hold phase, so that any voltage amplitude begins to settle. At the end of the hold phase, the low-voltage reference becomes proportional to the high-voltage reference as a result of the voltage amplitude settling. This method of sampling the high-voltage reference near the end of the hold phase reduces reference errors that cannot be trimmed using a one-time trim due to variations in voltage amplitude over process, voltage, and temperature (PVT). Alternatively, the voltage amplitude at the low-voltage reference can be mitigated using a large capacitor, which significantly increases the system-on-chip (SoC) size. Reference generation circuitry 150 is described in more detail below in connection with FIG. 2.

[0039] The summing circuitry 160 subtracts the analog output of the M-DAC 140 from the sampled analog input. The summing circuitry 160 provides the subtracted analog output to the amplifier 170. The amplifier 170 amplifies the subtracted analog output to reduce noise contributions from the second sub-ADC 180. The second sub-ADC 180 converts the amplified subtracted analog output to generate multiple LSBs of a digital output using a second low-voltage reference. Advantageously, the reference generation circuitry 150 reduces inter-stage gain errors caused by not considering the difference between the high-voltage reference and the low-voltage reference.

[0040] 2 is a schematic diagram of the reference generation circuitry 150 of FIG. 1. In the example of FIG. 2, the reference generation circuitry 150 includes a high voltage reference source 205, a first switch 210, a current source 215, a first resistor 220, a second resistor 225, a second switch 230, a first capacitor 235, a third switch 240, a second capacitor 245, a controller 250, a first reference amplifier 255, and a second reference amplifier 260. The reference generation circuitry 150 generates a high voltage reference (V REFH ) based on the first low voltage reference (V REFL1 ) and a second low-voltage reference (V REFL2 )

[0041] 2, the high-voltage reference source 205 is coupled to the first switch 210 and a common potential (e.g., ground). Alternatively, the high-voltage reference source 205 may be coupled to the first resistor 220. In such an example, the first switch 210 and the current source 215 may be removed from the reference generation circuit element 150. The high-voltage reference source 205 generates a high-voltage reference. The high-voltage reference source 205 may be referred to as a reference voltage circuit element or a reference voltage generation circuit element, which is a circuit element capable of supplying a reference voltage. The high-voltage reference source 205 may include a high-voltage reference amplifier circuit element (not shown) configured to generate a sparse high-voltage reference and a fine high-voltage reference. In such a configuration, the high-voltage reference source 205 may switch between supplying the sparse high-voltage reference and the fine high-voltage reference as the high-voltage reference. 1 , the high-voltage reference source 205 supplies a sparse high-voltage reference, and at a second time, the high-voltage reference source 205 supplies a fine high-voltage reference to the M-DAC 140. In such an example, the voltage swing produced by the M-DAC 140 affects the sparse high-voltage reference, and the fine high-voltage reference is used by the reference generation circuitry 150 to generate a low-voltage reference with a reduced voltage swing. Advantageously, such switching by the high-voltage reference source 205 between the sparse high-voltage reference and the fine high-voltage reference reduces input-dependent settling problems for the fine high-voltage reference caused by circuitry coupled to the sparse high-voltage reference (such as the M-DAC 140).

[0042] The first switch 210 is coupled to the high voltage reference source 205, the current source 215, the first resistor 220, and the controller 250. The first switch 210 couples the high voltage reference source 205 to the first resistor 220 based on the controller 250. The first switch 210 may be opened or closed by the controller 250. For example, the controller 250 may close the first switch 210 to couple the high voltage reference source 205 to the first resistor 220, or may open the first switch 210 to prevent the high voltage reference source 205 from applying the high voltage reference across the first resistor 220. The first switch 210 may be a transistor configured to be turned on (e.g., conducting) and off (e.g., non-conducting) by the controller 250. Advantageously, the first switch 210 increases the reliability of the high-voltage reference and the low-voltage reference in response to which the controller 250 can disable the low-voltage reference by disabling the first switch 210. The first switch 210 may be coupled to the M-DAC 140 to allow the reference generation circuitry 150 to disable both the high-voltage reference and the low-voltage reference by disabling (turning off so as to be non-conductive) the first switch 210. For example, the first switch 210 may be coupled to the M-DAC 140 such that when the first switch 210 is opened, the M-DAC 140 is disconnected from the high-voltage reference source 205.

[0043] The current source 215 is coupled to the first switch 210, the first resistor 220, and the controller 250. The current source 215 provides a compensation current (I) to the first resistor 220. The compensation current is supplied to the high voltage reference (V REFH2. The current source 215 corrects the voltage difference across the first switch 210 by supplying sufficient current to create a voltage difference across the combined resistance (R1+R2) of resistors 220 and 225 equal to R1 / R2. The current supplied by current source 215 is determined using equation (1) below. Current source 215 may be enabled (e.g., supplies current) or disabled (e.g., does not supply current) by controller 250. Advantageously, current source 215 reduces variations in the voltage across resistors 220 and 225 from high voltage reference source 205 caused by the internal resistance (not shown) of first switch 210.

[0044] I=V REFH / (R1+R2) Equation (1)

[0045] The first resistor 220 is coupled to the switches 210 and 230, the current source 215, and the second resistor 225. The first resistor 220 is coupled between the first switch 210 and the second resistor 225. The first resistor 220 has a first resistance (R1). The second resistor 225 is coupled to the first resistor 220, the second switch 230, and a common potential (e.g., ground). The second resistor 225 is coupled between the first resistor 220 and the common potential. The second resistor 225 has a second resistance (R2). The resistors 220 and 225 are configured as a voltage divider. The resistors 220 and 225 may be referred to as reference voltage circuit elements, which are circuit elements configured to provide a reference voltage. Alternatively, resistors 220 and 225 may be replaced with another method of generating a voltage based on a high-voltage reference in the teachings described herein. Resistors 220 and 225 may be positioned relatively close to M-DAC 140 to reduce errors caused by electrical traces, such as parasitic inductance, resistance, etc. For example, a system-on-chip (SoC) implementation of pipelined ADC 100 may position resistors 220 and 225 based on the location of M-DAC 140.

[0046] The resistance of resistors 220 and 225 creates a reference voltage (V REF), which is used to determine the compensation current in equation (1) above. The reference voltage is approximately equal to the second resistance multiplied by the high voltage reference divided by the sum of the first resistance and the second resistance. The reference voltage may be determined using equation (2) below. Advantageously, the reference voltage is generated using the high voltage reference and a voltage divider.

[0047] TIFF2025529181000002.tif515 formula (2)

[0048] The second switch 230 is coupled to the resistors 220 and 225, the first capacitor 235, the third switch 240, and the controller 250. The second switch 230 couples a reference voltage generated by the resistors 220 and 225 across the first capacitor 235 based on the controller 250. The second switch 230 may be opened (non-conducting) or closed (e.g., conducting) by the controller 250. The controller 250 may be configured to open and close the second switch 230 at a sampling frequency (F). The sampling frequency corresponds to the time during which the controller 250 keeps the second switch 230 open. The sampling frequency may be determined based on a duration determined for the sample-and-hold circuit element 120 of FIG. 1, such as between sampling and resampling. The second switch 230 is configured to set the voltage across the first capacitor 235 to be approximately (preferably exactly) equal to the reference voltage. This voltage across the first capacitor 235 is taken as the small capacitor reference (V REF_C1 )

[0049] A first capacitor 235 is coupled to switches 230 and 240 and to a common potential. The small capacitor reference of first capacitor 235 is approximately equal to the reference voltage generated across resistors 220 and 225 when second switch 230 couples first capacitor 235 to resistors 220 and 225. First capacitor 235 has a first capacitance (C small )

[0050] The third switch 240 is coupled to the second switch 230, the capacitors 235 and 245, the controller 250, and the reference amplifiers 255 and 260. The third switch 240 can be opened or closed by the controller 250. The third switch 240 sets the voltage across the second capacitor 245 equal to the voltage across the first capacitor 235 based on the controller 250. For example, the voltage across the second capacitor 245 is approximately equal to the small capacitor reference after the controller closes the third switch 240. This voltage across the second capacitor 245 is then compared to the large capacitor reference (V REF_C2 )

[0051] The second capacitor 245 is coupled to the third switch 240, the reference amplifiers 255 and 260, and a common potential. The large capacitor reference is approximately equal to the small capacitor reference after the third switch 240 couples the first capacitor 235 to the second capacitor 245. The second capacitor 245 has a second capacitance (C ) that is greater than the first capacitance of the first capacitor 235 to reduce noise. large ) for example, the second capacitance may be large enough to average out noise in the small capacitor reference. Advantageously, second capacitor 245 reduces errors resulting from noise, and the relatively large capacitance of second capacitor 245 reduces coupling to relatively small parasitic capacitances (not shown) at the inputs to reference amplifiers 255 and 260. The capacitances of capacitors 235 and 245 modify the effective bandwidth and sampling bandwidth of reference generation circuitry 150, as described below. The sampling bandwidth corresponds to generating a small capacitor reference on first capacitor 235 with the high voltage reference of high voltage reference source 205. The effective bandwidth corresponds to generating a large capacitor reference on second capacitor 245 with the high voltage reference of high voltage reference source 205.

[0052] The effective bandwidth of the reference generation circuitry 150 effThe sampling bandwidth (BANDWIDTH) of the reference generating circuitry 150 may be determined using equation (3) below: Samp ) is configured to be greater than the bandwidth of amplifier 170 to allow the voltage across first capacitor 235 to track the voltage generated by high voltage reference source 205. The sampling bandwidth of reference generation circuitry 150 is determined using equation (4) below. Advantageously, the difference between the bandwidths of reference generation circuitry 150 and amplifier 170 reduces the error between the voltages across first capacitor 235 and resistors 220 and 225.

[0053] TIFF2025529181000003.tif19114 formula (3)

[0054] TIFF2025529181000004.tif1698 formula (4)

[0055] The controller 250 is coupled to the switches 210, 230, and 240 and the current source 215. The controller 250 enables the reference generation circuitry 150 by closing the first switch 210 and enabling the current source 215. The controller 250 controls the clock hold signal (CLK HOLD ) to control the second switch 230. The controller 250 generates non-overlapping clock hold signals (CLK NOV_HOLD) to control the third switch 240. Clock-hold signals and non-overlapping clock-hold signals are further described below in connection with FIG. 7 . Controller 250 may include a dedicated reference source configured to enable and disable switches 210, 230, and 240. Controller 250 closes second switch 230 to couple first capacitor 235 to the reference voltage generated by resistors 220 and 225. Controller 250 ensures that third switch 240 is open during the time that second switch 230 is closed. Controller 250 opens second switch 230 to keep the small capacitor reference approximately equal to the reference voltage. Controller 250 closes third switch 240 to couple second capacitor 245 to first capacitor 235. Controller 250 ensures that second switch 230 remains open while third switch 240 couples capacitors 235 and 245. The controller 250 opens the third switch 240 to keep the large capacitor reference approximately equal to the small capacitor reference.

[0056] Reference amplifiers 255 and 260 are coupled to the third switch 240 and the second capacitor 245. The first reference amplifier 255 generates a first low-voltage reference based on the voltage across the second capacitor 245. The first reference amplifier 255 includes a first trim circuit element 265. The first trim circuit element 265 modifies the first reference amplifier 255 to compensate for variations in temperature and direct current (DC) offset of the voltage across the second capacitor 245 and the first reference amplifier 255. The first trim circuit element 265 is described below in connection with FIGS. 4-6. Advantageously, the first trim circuit element 265 reduces errors by reducing variations in the first low-voltage reference caused by temperature variations and / or DC offsets.

[0057] The second reference amplifier 260 generates a second low-voltage reference based on the voltage across the second capacitor 245. The first and second low-voltage references are approximately equal to the large capacitor reference. The second reference amplifier 260 includes a second trim circuit element 270. The second trim circuit element 270 modifies the second reference amplifier 260 to compensate for variations in temperature and DC offset of the voltage across the second capacitor 245 and the second reference amplifier 260. The second trim circuit element 270 is similar to the first trim circuit element 265. Advantageously, the second trim circuit element 270 reduces inter-stage gain error by reducing variations in the first low-voltage reference caused by temperature variations and / or DC offset.

[0058] FIG. 3 is a schematic diagram of the second switch 230 of FIG. 2 configured to use charge injection cancellation to reduce charge injection caused by switching of the reference generating circuit element 150 of FIGS. 1 and 2. Such charge injection can cause errors that cannot be corrected using a one-time trim. In the example of FIG. 3, the second switch 230 includes a first transistor 310, a second transistor 320, and a third transistor 330. The transistors 310-330 are p-channel transistors. Alternatively, with slight modifications to the second switch 230, the transistors can be n-channel transistors. The transistors 310-330 are configured to be turned on (e.g., conducting) or off (e.g., non-conducting) by the controller 250 of FIG. 2. The second switch 230 is said to be closed when the transistors 310 and 330 are turned off and the second transistor 320 is turned on. The second switch 230 is said to be open when the transistors 310 and 330 are turned on and the second transistor 320 is turned off.

[0059] The control terminal (e.g., gate) of the first transistor 310 is connected to a control signal CLK NOV_HOLD, and a current terminal (e.g., a source and / or a drain) of the first transistor 310 is coupled to one of the current terminals of the second transistor 320. The first transistor 310 is controlled by the controller 250. The first transistor 310 is configured to be turned on while the second transistor 320 is turned off. The first transistor 310 accumulates a current supplied by the second transistor 320 after the second transistor 320 is turned off. Such a current supplied by the second transistor 320 may result from the discharge of an internal capacitance (not shown) of the second transistor 320. When the first transistor 310 is turned off, it supplies the accumulated current to charge the internal capacitance of the second transistor 320. This current collecting and accumulating action may be referred to as charge injection cancellation. Advantageously, the first transistor 310 implements a method of charge cancellation to prevent changes to the reference voltage and the high voltage reference that occur as a result of current supplied by turning the second transistor 320 on and off.

[0060] The control terminal of the second transistor 320 is connected to a control signal CLK HOLD , and has one current terminal connected to the current terminal of transistor 310 and the other current terminal connected to the current terminal of transistor 330. Second transistor 320 is controlled by controller 250. Controller 250 is configured to turn on second transistor 320 at approximately (preferably exactly) the same time that transistors 310 and 330 are turned off. Controller 250 is configured to turn off second transistor 320 at approximately (preferably exactly) the same time that transistors 310 and 330 are turned on. For example, controller 250 may use a clock hold signal (CLK HOLD ), and an inverted version of the clock hold signal (CLK) to control transistors 310 and 330. HOLD_INV) The second transistor 320 includes an internal capacitance (not shown) that charges when the second transistor 320 is turned on and discharges when the second transistor 320 is turned off. Discharging this internal capacitor causes current to be sourced by the transistors 310 and 330. This current is called charge injection. The charge injection caused by the second transistor 320 can be reduced by reducing the size of the second transistor 320 to reduce the internal capacitance. The transistors 310 and 330 are configured to store the current released by the second transistor 320 when turned off and to source the collected current to the second transistor 320 when turned on. Advantageously, the effects of charge injection caused by turning off the second transistor 320 on the reference generating circuit element 150 are reduced by the transistors 310 and 330.

[0061] A control terminal of the third transistor 330 is coupled to the controller 250, and a current terminal of the third transistor 330 is coupled to one of the current terminals of the second transistor 320. The third transistor 330 is controlled by the controller 250. The third transistor 330 is configured to be turned on while the second transistor 320 is turned off. The third transistor 330 stores current provided by turning off the second transistor 320. When turned off, the third transistor 330 provides the stored current to charge the internal capacitance of the second transistor 320. Advantageously, the third transistor 330 implements a charge cancellation method to prevent changes to the small capacitor reference in response to the current provided by turning on and off the second transistor 320.

[0062] As shown in FIG. 2, transistors 310, 320, and 330 may be implemented using metal-oxide semiconductor field-effect transistors (MOSFETs). Preferably, each of transistors 310, 320, and 330 is implemented using a p-channel MOSFET (pMOSFET). Alternatively, transistors 310, 320, and / or 330 may be a PNP bipolar junction transistor (BJT), an N-channel field-effect transistor (FET), an N-channel insulated gate bipolar transistor (IGBT), an N-channel junction field-effect transistor (JFET), an N-channel MOSFET, a P-channel FET, a P-channel IGBT, a P-channel JFET, or an NPN BJT. The clock-hold signal controlling transistors 310-330 uses a common potential (AVSS) to turn transistors 310-320 on and a clean supply voltage (AVDD) to turn transistors 310-320 off. The clean supply voltage is a voltage supply that is isolated from switching components that can add noise to the clock-hold signal. For example, the clean supply voltage may be a voltage generated by a dedicated voltage source. Advantageously, the clean supply voltage reduces clock coupling of the hold signal, which cannot be trimmed.

[0063] 3, a second switch 230 is shown. Alternatively, the use of transistors 310-330 to implement charge injection cancellation may be applied to the teachings described herein as circuit elements including switches 210 and / or 240 of FIG. 2 to reduce charge injection caused by switching. In some examples, the channel widths of transistors 310 and 330 are a fraction (e.g., approximately half) of the channel width of transistor 320.

[0064] 4 is a schematic diagram of an example input stage 400 of the first reference amplifier 255 of FIG. 2. The input stage 400 includes the first trim circuitry 265 of FIG. 2 and is connected to the large capacitor reference (V REF_C24, input stage 400 includes first trim circuit element 265, first transistor 405, first current source 410, and second transistor 415. Input stage 400 is configured to reduce gain errors caused by DC offsets and / or temperature variations by compensating for the large capacitor reference.

[0065] 4, first trim circuit element 265 includes a third transistor 420, a fourth transistor 425, a second current source 430, an offset compensation circuit element 435, a fifth transistor 440, a sixth transistor 445, a third current source 450, and a temperature compensation circuit element 455. First trim circuit element 265 is configured to trim the large capacitor reference to compensate for DC offsets and / or temperature variations.

[0066] The third transistor 420 is coupled to the transistors 405, 425, and 440, the second current source 430, and the offset compensation circuitry 435. A first offset correction voltage (V CORRP ) is provided to the control terminal of the third transistor 420 by offset circuitry 435 to control the third transistor 420. The offset compensation circuitry 435 generates a first offset correction voltage based on the determined DC offset. The determined DC offset may be determined as part of a calibration of the offset compensation circuitry 435 and / or may be a reference voltage between a large capacitor reference and a first low voltage reference (V REFL1 ) The DC offset that is determined is described in more detail below. When turned on by the first offset correction voltage, the third transistor 420 allows current to flow to the second current source 430. When turned off, the third transistor 420 prevents current from flowing to the second current source 430.

[0067] The fourth transistor 425 is coupled to the transistors 415, 420, and 445, the second current source 430, and the offset compensation circuitry 435. A second offset correction voltage (V CORRM ) is supplied to the control terminal of the fourth transistor 425 by the offset circuitry 435 to control the fourth transistor 425. The offset compensation circuitry 435 generates a second offset correction voltage based on the determined DC offset. The determined DC offset is the difference between the first offset correction voltage and the second offset correction voltage. When the fourth transistor 425 is turned on by the second offset correction voltage, the fourth transistor 425 allows current to flow through the second current source 430. When the fourth transistor 425 is turned off, the fourth transistor 425 prevents current from flowing through the second current source 430.

[0068] Second current source 430 supplies current from transistors 420 and / or 425 to the output of input stage 400 of reference amplifier 255. To reduce noise added by transistors 420 and 425 and provide additional control over DC offset, the magnitude of second current source 430 may be divided by a first scalar value (N1). For example, when the first scalar value of second current source 430 is equal to 10, a DC offset of 10 millivolts (mV) may be corrected by applying a 100 millivolt (mV) difference between the first offset correction voltage and the second offset correction voltage. The magnitude of second current source 430 is approximately (preferably exactly) equal to the magnitude of first current source 410 when the first scalar value is equal to 1. Advantageously, the magnitude of the noise provided by the offset correction voltage is divided by the first scalar value.

[0069] Offset compensation circuitry 435 generates an offset correction voltage that is supplied to transistors 420 and 425. The voltage difference between the offset correction voltages is configured to offset the large capacitor reference by a DC voltage, similar to adding a DC voltage directly to the large capacitor reference. The magnitude of the DC offset can be calibrated or determined. For example, an ADC (and / or other circuitry operable to provide such functionality) can be coupled to the large capacitor reference and the low voltage reference to determine the DC voltage contribution and configure offset compensation circuitry 435 to generate a corresponding DC voltage. In such an example, the ADC can configure the second offset correction voltage to be 3 millivolts (mV) to compensate the large capacitor reference for having a 3 millivolt (mV) offset. An example of offset compensation circuitry 435 is described in further detail below in connection with FIG. 5.

[0070] The fifth transistor 440 is coupled to the transistors 405, 420, and 425, the third current source 450, and the temperature compensation circuitry 455. A first temperature correction voltage (V CORRP_T ) is provided to the control terminal of the fifth transistor 440 by offset circuitry 455 to control the fifth transistor 440. The temperature compensation circuitry 455 generates a first temperature-corrected voltage based on the temperature-dependent circuitry. The temperature compensation circuitry 455 is described in further detail below in connection with FIG. 6 . When the fifth transistor 440 is turned on by the first temperature-corrected voltage, it allows current to flow through the third current source 450. When the fifth transistor 440 is turned off, it prevents current from flowing through the third current source 450.

[0071] The sixth transistor 445 is coupled to the transistors 415, 425, and 440, the third current source 450, and the temperature compensation circuitry 455. A second temperature correction voltage (V CORRM_T) is provided to the control terminal of the sixth transistor 445 by offset circuitry 455 to control the sixth transistor 445. The temperature compensation circuitry 455 generates a second temperature-corrected voltage based on the temperature-dependent circuitry of the compensation circuitry 455. The temperature compensation circuitry 455 is described in further detail below in connection with FIG. 6 . When the sixth transistor 445 is turned on by the second temperature-corrected voltage, it allows current to flow through the third current source 450. When the sixth transistor 445 is turned off, it prevents current from flowing through the third current source 450.

[0072] Third current source 450 supplies current from transistors 440 and / or 445 to a common potential. To reduce noise added by transistors 440 and 445 and provide additional control over temperature variation of the DC offset value, the magnitude of third current source 450 may be divided by a second scalar value (N2). For example, when the second scalar value of third current source 450 is equal to 10, a temperature variation of 10 millivolts (mV) may be corrected with approximately 100 millivolts (mV) of temperature-dependent variation in the difference between the first temperature-corrected voltage and the second temperature-corrected voltage. The magnitude of third current source 450 is approximately (preferably exactly) equal to the magnitude of first current source 410 when the second scalar value is equal to 1. Advantageously, the magnitude of the noise provided by the temperature-corrected voltage is divided by the second scalar value.

[0073] Temperature compensation circuitry 455 generates a temperature-corrected voltage that is supplied to the control terminals of transistors 440 and 445. The voltage difference between the temperature-corrected voltages is configured to offset the large capacitor reference by a voltage that represents variations in the circuitry of reference generation circuitry 150 and first reference amplifier 255 across temperature. The magnitude of the temperature compensation is determined using temperature compensation circuitry 455. An example of temperature compensation circuitry 455 is described in more detail below in connection with FIG. 6.

[0074] 4, a first transistor 405 is coupled to a first current source 410 and transistors 415, 420, and 440. The first transistor 405 is controlled by a large capacitor reference generated across the second capacitor 245 of FIG. 2. When the first transistor 405 is turned on by the second capacitor voltage, it allows current to flow to the first current source 410. When the first transistor 405 is turned off, it prevents current from flowing to the first current source 410.

[0075] A first current source 410 is coupled to transistors 405 and 415. The first current source 410 is configured to provide current from transistors 405 and / or 415 to the output of the input stage 400 of the reference amplifier 255.

[0076] The second transistor 415 is coupled to the transistors 405, 425, and 445. The second transistor 415 is controlled by a feedback input. The feedback input may be coupled to the output of the first reference amplifier 255. When the second transistor 415 is turned on by the feedback input, it allows current to flow to the first current source 410. When the second transistor 415 is turned off, it prevents current from flowing to the first current source 410.

[0077] 4, first trim circuit element 265 is shown. Alternatively, an input stage 400 including circuit elements for compensating for DC offset and / or temperature variations may be applied in the teachings described herein as circuit elements including second trim circuit element 270 of FIG. 2 to reduce gain errors caused by DC offset and / or temperature variations.

[0078] 5 is a schematic diagram of an example implementation for offset compensation circuitry 435 of FIG. 4 configured to generate an offset voltage to compensate the low-voltage reference generated by reference generation circuitry 150 of FIGS. 1 and 2 for DC offsets. In the example of FIG. 5, offset compensation circuitry 435 includes a current source 510, a first resistor 520, an example resistor ladder 530, a second resistor 540, and an example multiplexer 550. Offset compensation circuitry 435 uses multiplexer 550 to select the voltage generated by current source 510 and resistor ladder 530 to generate an offset correction voltage (V CORRP and / or V CORRM )

[0079] 5, a current source 510 is coupled to a first resistor 520 and supplies a current to the first resistor 520. The magnitude of the current supplied by the current source 510 may be determined to generate a potential drop across the first resistor 520, the resistor ladder 530, and / or the second resistor 540.

[0080] First resistor 520 is coupled to current source 510, resistor ladder 530, and multiplexer 550. Resistor ladder 530 is coupled to resistors 520 and 540 and multiplexer 550. Resistor ladder 530 is a resistor circuit configured to divide a potential difference into multiple voltage divisions. For example, resistor ladder 530 may be implemented by multiple coupled resistors. Examples of resistor ladders include those shown in commonly assigned U.S. Patent Nos. 8,618,971, 5,969,658, and 4,467,286 (each of which is incorporated by reference in its entirety). Second resistor 540 is coupled to resistor ladder 530 and multiplexer 550. [Patent Document 1] U.S. Patent No. 8,618,971 [Patent Document 2] U.S. Patent No. 5,969,658 [Patent Document 3] U.S. Patent No. 4,467,286

[0081] Multiplexer 550 couples the voltage generated by resistor ladder 530 to the first offset correction voltage and / or the second offset voltage. Advantageously, multiplexer 550 may be configured to couple a voltage corresponding to the determined DC offset to the offset correction voltage. Multiplexer 550 may be controlled by an ADC (not shown) or by controller 250 of FIG. 2. For example, multiplexer 550 may be configured to be controlled by a digital value resulting from an analog-to-digital conversion of a large capacitor reference. In such an example, multiplexer 550 may include circuitry for converting the digital value to form the offset correction voltage. Alternatively, controller 250 may control multiplexer 550 to correct a DC offset determined as part of a calibration process. For example, a manufacturer may calibrate controller 250 and / or multiplexer 550 to a calibrated value to generate the offset correction voltage.

[0082] 6 is a schematic diagram of an example implementation of the temperature compensation circuitry 455 of FIG. 4 configured to generate a temperature-compensated voltage to compensate the low-voltage reference generated by the reference generation circuitry 150 and first reference amplifier 255 of FIGS. 1 and 2 for variations in temperature. In the example of FIG. 6, the temperature compensation circuitry 455 includes a first variable current source 610, a first resistor 620, a fixed current source 630, a second variable current source 640, a second resistor 650, and a third resistor 660. The temperature compensation circuitry 455 generates a first temperature-compensated voltage (V CORRP_T ) and the second temperature compensation voltage (V CORRM_T )

[0083] 6, a first variable current source 610 is coupled to a first resistor 620. The first variable current source 610 supplies a current to the first resistor 620 to generate a first temperature-corrected voltage. The magnitude of the current supplied by the first variable current source 610 varies with temperature to compensate for temperature variations. The first variable current source 610 may be a current digital-to-analog converter (IDAC) configured to supply a current based on a digital input. In such an example, a temperature sensor may be used to determine the digital input.

[0084] The first resistor 620 is coupled to the first variable current source 610, the fixed current source 630, and the resistors 650 and 660. The first resistor 620 generates a potential difference to set a first temperature-corrected voltage based on the currents supplied by the first variable current source 610 and the third resistor 660.

[0085] A fixed current source 630 is coupled to resistors 620, 650, and 660. The fixed current source 630 supplies a current to a third resistor 660 to generate a fixed potential difference. The magnitude of the current supplied by the fixed current source 630 is determined to set the voltage difference across the third resistor 660.

[0086] A second variable current source 640 is coupled to a second resistor 650. The second variable current source 640 supplies a current to the second resistor 650 to generate a second temperature-corrected voltage. The magnitude of the current supplied by the second variable current source 640 varies with temperature to compensate for temperature variations. The second variable current source 640 may be an IDAC configured to supply a current based on a digital input. In such an example, a temperature sensor may be used to determine the digital input.

[0087] The second resistor 650 is coupled to the fixed current source 630, the second variable current source 640, and resistors 620 and 660. The first resistor 620 generates a voltage difference to set the first temperature-corrected voltage based on the currents supplied by the first variable current source 610 and the third resistor 660. The third resistor 660 is coupled to resistors 630 and 650 and the fixed current source 630. The third resistor 660 is configured to generate a voltage difference to offset both of the temperature-corrected voltages equally.

[0088] 7 is a timing diagram of an example switching operation of the reference generation circuitry 150 of FIGS. 1 and 2 to generate a low-voltage reference. In the example of FIG. 7, the timing diagram shows the remaining amplify / hold phase clock 710, the clock hold signal (CLK HOLD ) 720, non-overlapping clock hold signal (CLK NOV_HOLD ) 730, and high voltage reference signal 740.

[0089] Residual amplify / hold phase clock 710 represents a signal configured to control the operation of amplifier 170 of FIG. 1. For example, amplifier 170 amplifies the difference between the sampled analog input from sample-and-hold circuit element 120 of FIG. 1 and the analog output of M-DAC 140 of FIG. 1 on the rising edge of residue amplify / hold phase clock 710. In such an example, second sub-ADC 180 of FIG. 1 samples the output of amplifier 170 on the falling edge of residue amplify / hold phase clock 710. Residual amplify / hold phase clock 710 can be generated by controller 250 or internal to amplifier 170.

[0090] 3 and 4. Clock hold signal 720 represents the signal generated by controller 250 of FIG. 2 to control second switch 230 of FIG. 3 and 4. Clock hold signal 720 represents second switch 230 being closed as a logic high, such as to turn on second transistor 320 of FIG. 3 and to turn off transistors 310 and 330 of FIG. 3. Clock hold signal 720 represents second switch 230 being open as a logic low, such as to turn off second transistor 320 and to turn on transistors 310 and 330. In the example of FIG. 7, a logic high of clock hold signal 720 corresponds to second switch 230 being closed, although the transistors comprising second switch 230 may be turned on using a common potential (e.g., ground, AVSS, etc.) (e.g., a logic low or "0").

[0091] Non-overlapping clock hold signal 730 represents a signal generated by controller 250 to control third switch 240 of Figure 3. Non-overlapping clock hold signal 730 represents third switch 240 being closed as a logic high, such as to turn second transistor 320 on and transistors 310 and 330 off. Non-overlapping clock hold signal 730 represents third switch 240 being open as a logic low, such as to turn second transistor 320 off and transistors 310 and 330 on. In the example of Figure 7, a logic high of non-overlapping clock hold signal 730 corresponds to third switch 240 being closed, although the transistors comprising third switch 240 may be turned on using a common potential (e.g., ground, AVSS, etc.).

[0092] The high voltage reference signal 740 is a high voltage reference (e.g., V REFH ) represents the high voltage reference signal 740 is provided to the M-DAC 140. The high voltage reference signal 740 settles to a voltage above the average (AVG) of the high voltage reference signal 740. The reference generation circuitry 150 resets the high voltage reference signal 740 at the end of the hold phase (e.g., CLK HOLD2 transitions from logic high to logic low (at time 780). Reference generation circuitry 150 reduces the gain error by using high-voltage reference signal 740 to generate the low-voltage reference. High-voltage reference signal 740 may fluctuate as a result of switching within M-DAC 140, which causes fluctuations in high-voltage reference source 205 of FIG. 2. However, fluctuations in high-voltage reference signal 740 are minimized at the end of switching and / or once high-voltage reference source 205 has settled.

[0093] At a first time 750, the residue amplify / hold phase clock 710 transitions from logic low to logic high, representing the residue amplify / hold phase. For example, the sample-and-hold circuitry 120 of FIG. 1 resamples the analog input and holds the sampled analog input until a subsequent rising edge. The amplifier 170 amplifies the subtracted analog output from the first time 750 until a subsequent falling edge of the residue amplify / hold phase clock 710. At the first time 750, the high-voltage reference signal 740 changes as switching within the M-DAC 140 adds noise and / or requires additional current from the high-voltage reference source 205. These effects from the switching diminish over time as the components of the M-DAC 140 and the reference generation circuitry 150 settle.

[0094] At a second time 760, the non-overlapping clock-hold signal 730 transitions from a logic high to a logic low, indicating that the controller 250 opens the third switch 240 to decouple the capacitors 235 and 245 of FIG. 2 . At the second time 760, the large capacitor reference is approximately equal to the low voltage reference. At the second time 760, the controller 250 ensures that the non-overlapping clock-hold signal 730 is not at a logic high at the same time as the clock-hold signal 720. For example, the falling edge of the non-overlapping clock-hold signal 730 at the second time 760 may be generated to prepare for the rising edge of the clock-hold signal 720. The rising edge of the non-overlapping clock-hold signal 730 is configured to be delayed until the subsequent falling edge of the clock-hold signal 720.

[0095] At a third time 770, the clock hold signal 720 transitions from a logic low to a logic high, indicating that the controller 250 closes the second switch 230, thereby coupling the first capacitor 235 of Figure 2 to the reference voltage generated across the second resistor 225 of Figure 2. At the third time 770, the high voltage reference signal 740 begins to settle, with the large capacitor reference remaining approximately equal to the low voltage reference.

[0096] At a fourth time 780, the clock hold signal 720 transitions from logic high to logic low, indicating that the controller 250 opens the second switch 230. At the fourth time 780, the small capacitor reference is held by the first capacitor 235, and the small capacitor reference is a noisy version of the reference voltage generated by resistors 220 and 225. The noise on the small capacitor reference is responsive to the capacitance of the first capacitor 235 being small enough to retain relatively high frequency variations.

[0097] At a fifth time 790, the non-overlapping clock hold signal 730 transitions from logic low to logic high, indicating that the controller 250 closes the third switch 240, thereby coupling the capacitors 235 and 245 in parallel. The large capacitor reference is configured to filter the relatively higher frequency noise of the small capacitor reference in response to the capacitance of the second capacitor 245 being greater than the capacitance of the first capacitor 235. The noise filtered by the second capacitor 245 may be determined based on the effective bandwidth of the reference generation circuit element 150. The effective bandwidth of the reference generation circuit element 150 may be determined using equation (3) above.

[0098] At a sixth time 795, the residue amplify / hold phase clock 710 transitions from logic high to logic low, causing the amplifier 170 to stop amplifying the subtracted analog output as the sample-and-hold circuit element 120 resamples the analog input. The time between the fourth time 780 and the sixth time 795 is relatively small to ensure that the voltage across the first capacitor 235 is approximately equal to the reference voltage when the high-voltage reference signal 740 settles. Advantageously, opening the second switch 230 near the end of the hold phase at time 795 reduces inter-stage gain error by ensuring that the voltage across the first capacitor 235 is proportional to the high-voltage reference after it has settled. Advantageously, noise on the small capacitor reference is averaged by the second capacitor 245. Advantageously, gain errors resulting from noise are reduced by the second capacitor 245.

[0099] Figure 8 is a timing diagram of an example operation of reference generation circuitry 150 of Figures 1 and 2, including low and high voltage references generated using the switching operation of Figure 7. In the example of Figure 8, the timing diagram includes an example scaled high voltage reference signal 810 and an example low voltage reference signal 820.

[0100] In the example of FIG. 8, scaled high-voltage reference signal 810 is a scaled version of the high-voltage reference provided to M-DAC 140 of FIG. 1. Scaled high-voltage reference signal 810 is scaled to be approximately equal to the low-voltage reference. For example, scaled high-voltage reference signal 810 may be scaled by a factor of two when resistors 220 and 225 of FIG. 2 have equal resistances. Low-voltage reference signal 820 is the low-voltage reference generated by reference generation circuitry 150. In the example operation of FIG. 8, when reference signals 810 and 820 are equal at the time that second sub-ADC 180 of FIG. 1 samples the output of amplifier 170, the inter-stage gain error between the first and second stages of pipelined ADC 100 of FIG. 1 is zero. The inter-stage gain error between the first and second stages is determined by determining the difference between the scaled high voltage reference represented by the scaled high voltage reference signal 810 and the low voltage reference represented by the low voltage reference signal 820 at the end of the residual amplify / hold phase clock 710.

[0101] A first time 830 corresponds approximately to the first time 750 in Figure 7. At a second time 840, the low voltage reference signal 820 follows the scaled high voltage reference signal 810. At a third time 850, the residual amplify / hold phase clock 710 in Figure 7 transitions to a logic low. The third time 850 is approximately equal to the fourth time 780 in Figure 7. The inter-stage gain error of the pipeline ADC 100 contributes to a portion of the difference between the reference signals 810 and 820 at the third time 850. In the example of Figure 8, the error between the reference signals 810 and 820 is approximately equal to 9 microvolts (μV).

[0102] FIG. 9 is a flowchart representing an example method that may be implemented using executable machine-readable instructions and / or hardware configured to implement the reference generation circuitry 150 of FIGS. 1 and 2 and / or, more generally, the pipeline ADC 100 of FIG. 1. The method of FIG. 9 begins at block 910. In block 910, the controller 250 of FIG. 2 determines whether analog-to-digital conversion is required. For example, the controller 250 determines whether the pipeline ADC 100 is required by an example microcontroller (not shown). The method proceeds to completion if the controller 250 determines that the pipeline ADC 100 is not required. The method proceeds to block 920 if the controller 250 determines that the pipeline ADC 100 is required.

[0103] At block 920, the controller 250 enables the reference generation circuitry 150. For example, the controller 250 enables the reference generation circuitry 150 by closing the first switch 210 of FIG. 2 and enabling the current source 215 of FIG. 2. The first switch 210 couples the voltage source 205 of FIG. 2 to the first resistor 220 of FIG. 2 when the first switch 210 is closed. The current source 215 provides a current based on equation (1) above. The method proceeds to block 930.

[0104] At block 930, reference generation circuitry 150 provides a first reference voltage to the first stage of pipeline ADC 100. For example, voltage source 205 of Figure 2 provides a high voltage reference to M-DAC 140. The method proceeds to block 940.

[0105] In block 940, controller 250 closes the first switch to sample the second reference voltage using the first capacitor. For example, controller 250 closes second switch 230 of FIG. 2 to sample the reference voltage generated by resistors 220 and 225 of FIG. 2 by coupling the reference voltage to first capacitor 235. In such an example, controller 250 may turn off transistors 310 and 330 of FIG. 3 and turn on second transistor 320 to close second switch 230. Block 940 corresponds to the third time 770 of FIG. 7. The method proceeds to block 950.

[0106] In block 950, controller 250 opens the first switch to hold the second reference voltage on the first capacitor. For example, controller 250 opens second switch 230 to hold the reference voltage across first capacitor 235. In such an example, controller 250 may turn on transistors 310 and 330 and turn off second transistor 320 to open second switch 230. The method proceeds to block 960.

[0107] At block 960, the controller 250 closes a second switch to sample a second reference voltage using a second capacitor. For example, the controller 250 closes the third switch 240 of Figure 2 to sample the small capacitor reference across the first capacitor 235 using the second capacitor 245. The method proceeds to block 970.

[0108] In block 970, the controller 250 opens the second switch to hold the second reference voltage on the second capacitor. For example, the controller 250 opens the third switch 240 to hold the large capacitor reference across the second capacitor 245. The input of the reference amplifier 255 of FIG. 2 remains settled after block 970. The method proceeds to block 980.

[0109] In block 980, reference amplifiers 255 and / or 260 provide a second reference voltage to a second stage of pipeline ADC 100. For example, reference amplifiers 255 and 260 generate first and second low voltage references based on the large capacitor reference held on second capacitor 245 following block 970. The method proceeds to block 910 to determine whether pipeline ADC 100 is still needed.

[0110] Figure 10 is a block diagram of an example processor platform 1000 configured to execute and / or instantiate the machine-readable instructions and / or operations of Figure 9 to implement the pipeline ADC 100 of Figure 1. The processor platform 1000 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or other wearable device, or any other type of computing device.

[0111] The processor platform 1000 of the illustrated example includes processor circuitry 1012. The processor circuitry 1012 of the illustrated example is hardware. For example, the processor circuitry 1012 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The processor circuitry 1012 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuitry 1012 may implement the controller 250 of FIG. 2 .

[0112] The processor circuitry 1012 of the illustrated example includes local memory 1013 (e.g., cache, resistors, etc.). The processor circuitry 1012 of the illustrated example communicates with main memory, including volatile memory 1014 and non-volatile memory 1016, via a bus 1018. The volatile memory 1014 may be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS® dynamic random access memory (RDRAM®), and / or any other type of RAM device. The non-volatile memory 1016 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 of the illustrated example is controlled by a memory controller 1017. Alternatively, the controller 250 may be implemented using circuitry coupled to the bus 1018.

[0113] The processor platform 1000 of the illustrated example also includes interface circuitry 1020. The interface circuitry 1020 may be implemented by hardware in any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, and / or a Peripheral Component Interconnect Express (PCIe) interface.

[0114] In the illustrated example, one or more input devices 1022 are connected to the interface circuitry 1020. The input devices 1022 allow a user to input data and / or commands into the processor circuitry 1012. The input devices 1022 can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, and / or a voice recognition system.

[0115] One or more output devices 1024 are also connected to the interface circuitry 1020 of the illustrated example. The output device(s) 1024 can be implemented by, for example, a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Thus, the interface circuitry 1020 of the illustrated example can include a graphics driver card, a graphics driver chip, and / or graphics processor circuitry such as a GPU.

[0116] The interface circuitry 1020 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate the exchange of data with external machines (e.g., any type of computing device) over the network 1026. Communication is possible, for example, via an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a cellular phone system, an optical connection, etc.

[0117] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant array of independent disks (RAID) systems, flash memory devices and / or solid-state storage devices such as SSDs, and DVD drives.

[0118] The machine-readable instructions 1032 that may be implemented by the machine-readable instructions of FIG. 9 may be stored in mass storage device 1028, in volatile memory 1014, in non-volatile memory 1016, and / or on a removable non-transitory computer-readable storage medium such as a CD or DVD.

[0119] In this description, the term "and / or" (when used in the form A, B, and / or C, etc.) refers to any combination or subset of A, B, and C, such as (a) A only, (b) B only, (c) C only, (d) A and B, (e) A and C, (f) B and C, and (g) A, B, and C. Also, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an implementation that includes any of (a) at least one A, (b) at least one B, and (c) at least one A and at least one B.

[0120] The term "couple" is used throughout this specification. This term may encompass connection, communication, or a signal path that enables a functional relationship consistent with this description. For example, in a first example, device A is coupled to device B when device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal provided by device A, where intervening component C does not substantially change the functional relationship between device A and device B.

[0121] A device that is "configured" to perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via firmware and / or software programming of the device, via the structure and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0122] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably and, unless otherwise specified, are used generally to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.

[0123] Circuits or devices described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or voltage sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources, e.g., by an end user and / or a third party, to form the described structure either during or after manufacture.

[0124] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead, with slight or no modifications to the remaining circuit elements. For example, metal-oxide-silicon FETs ("MOSFETs") (such as n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, e.g., NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0125] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available before the component replacement. A component depicted as a resistor, unless otherwise noted, generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes, respectively, as a single resistor or capacitor. While some elements of the described examples are included within an integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated within the integrated circuit. Also, some or all of the features depicted as being external to the integrated circuit may be included within the integrated circuit, and / or some features depicted as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) integrated within or on a semiconductor substrate, (2) integrated within a single semiconductor package, (3) integrated within the same module, and / or (4) integrated within or on the same printed circuit board. While some elements of the illustrated examples are included within the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be integrated within the integrated circuit. Also, some or all of the features shown as being external to the integrated circuit may be included within the integrated circuit, and / or some features shown as being internal to the integrated circuit may be integrated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) integrated within or on a semiconductor substrate, (2) integrated within a single semiconductor package, (3) integrated within the same module, and / or (4) integrated within or on the same printed circuit board.

[0126] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the stated value, or, if the value is zero, a reasonable range of values ​​around zero.

[0127] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. 1. An analog-to-digital converter (ADC), comprising: a sample and hold circuit element coupled to the analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summing circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summing circuitry; a second sub-ADC coupled to the amplifier; a reference generation circuit element coupled to the first sub-ADC, the M-DAC, and the second sub-ADC; Including, the reference generation circuitry comprising: a reference voltage circuit element coupled to the M-DAC; a first resistor coupled to the reference voltage circuit element; a second resistor coupled to the first resistor; a capacitor coupled in parallel with the second resistor by a switch; Including, ADC.

2. 2. The ADC of claim 1, wherein the reference voltage circuit element is a first reference voltage circuit element, the first reference voltage circuit element is configured to generate a first voltage, and the first resistor and the second resistor include a second reference voltage circuit element configured to generate a second voltage that is less than the first voltage, and the second reference voltage circuit element is coupled to a first sub-ADC and a second sub-ADC.

3. 2. The ADC of claim 1, wherein the switch is a first switch, the capacitor is a first capacitor, and the reference generating circuitry further includes a second capacitor coupled to the first capacitor and the first switch by a second switch.

4. 4. The ADC of claim 3, wherein the reference generation circuitry further includes a reference amplifier coupled between the second capacitor and the first sub-ADC, the reference amplifier providing a voltage to the first sub-ADC.

5. 4. The ADC of claim 3, further comprising a controller coupled to the first switch and the second switch, the controller comprising: closing the first switch to establish a first voltage across the first capacitor; opening the first switch to hold a first voltage across the first capacitor; closing the second switch to set a second voltage across the second capacitor approximately equal to the first voltage on the first capacitor; It is configured as follows: ADC.

6. 2. The ADC of claim 1, wherein the summing circuitry is configured to provide the output of the sample and hold circuitry minus the output of the M-DAC to the amplifier.

7. 2. The ADC according to claim 1, wherein the first sub-ADC determines the most significant bits of the digital output of the ADC, and the second sub-ADC determines the least significant bits of the digital output of the ADC.

8. 2. The ADC of claim 1, wherein the switch is configured to couple the capacitor to the second resistor after enabling the amplifier and until disabling the amplifier.

9. 2. The ADC of claim 1, wherein a first time interval during which the switch couples the capacitor to the second resistor is a first bandwidth, and a second time interval during which the amplifier is enabled is a second bandwidth, and the first bandwidth is greater than the second bandwidth.

10. A device, a pipelined analog-to-digital converter (ADC); the pipelined analog-to-digital converter (ADC), a first sub-ADC including a first reference input; a second sub-ADC including a second reference input; a multiplying digital-to-analog converter (M-DAC) coupled between the first sub-ADC and the second sub-ADC, the M-DAC including a third reference input; a reference generation circuit element coupled to the first reference input, the second reference input, and the third reference input; Including, the reference generation circuitry comprising: a first resistor; a second resistor coupled to the first resistor at a first node; a first switch configured to couple the first node to a first capacitor; a second switch configured to couple the first capacitor to a second capacitor; a reference amplifier having an input coupled to the second capacitor and having an output coupled to the second reference input; Including, device.

11. 11. The device of claim 10, wherein the first switch: a first transistor coupled to the first resistor and the second resistor; a second transistor coupled to the first resistor, the second resistor, the second switch, the first capacitor, and the first transistor; a third transistor coupled to the second transistor, the second switch, and the first capacitor; Including, the device.

12. 12. The device of claim 11, wherein the first transistor, the second transistor, and the third transistor are p-channel metal oxide semiconductor field effect transistors (pMOSFETs).

13. 11. The device of claim 10, wherein the reference generating circuitry further comprises a controller coupled to the first switch and the second switch, the controller comprising: closing the first switch to set the voltage on the first capacitor equal to a reference voltage; opening the first switch to hold the reference voltage on the first capacitor; closing the second switch to set the voltage on the second capacitor equal to the reference voltage on the first capacitor; It is configured as follows: device.

14. 11. The device of claim 10, wherein the reference generating circuitry comprises: a transistor coupled between a voltage source and the first resistor, the transistor configured to enable the reference generating circuit element; a current source coupled to the transistor and the first resistor, the current source configured to supply a current to set a voltage drop across the first resistor and the second resistor equal to a voltage generated by the voltage source; The device further comprises:

15. 11. The device of claim 10, wherein the second capacitor is configured to include a larger capacitance than the first capacitor.

16. 11. The device of claim 10, wherein the reference amplifier includes trim circuitry configured to compensate the voltage across the second capacitor for direct current (DC) offsets and temperature variations.

17. 11. The device of claim 10, wherein the reference amplifier is a first reference amplifier, the input is a first input, and the output is a second output, and the reference generating circuitry further includes a second reference amplifier, the second reference amplifier having a second input coupled to the second capacitor and a second output coupled to the first reference input.

18. 1. A method of operating an analog-to-digital converter (ADC), said method comprising: providing a first reference voltage to a multiplying digital-to-analog converter of a pipelined analog-to-digital converter (ADC) by reference voltage generation circuitry; closing a first switch by a controller to supply a second reference voltage to a first capacitor, the second reference voltage being generated using the first reference voltage; opening the first switch by the controller to hold the second reference voltage on the first capacitor; closing a second switch by the controller to supply the second reference voltage to a second capacitor; opening the second switch by the controller to hold the second reference voltage on the second capacitor; providing the second reference voltage to a sub-ADC by an amplifier; A method comprising:

19. 20. The method of claim 18, wherein the amplifier is a first amplifier and the sub-ADC is a first sub-ADC, and further comprising supplying the second reference voltage to a second sub-ADC by a second amplifier.

20. 20. The method of claim 18, further comprising averaging the second reference voltage with the second capacitor.

21. 20. The method of claim 18, further comprising: reducing noise on the second reference voltage; and coupling between the second capacitor and the amplifier by increasing the capacitance of the second capacitor.

22. 20. The method of claim 18, further comprising correcting an offset error in the second reference voltage using circuitry to trim an input of the amplifier.

23. 20. The method of claim 18, wherein the second reference voltage is sampled by the first switch before the second switch samples the first capacitor.

24. 20. The method of claim 18, wherein opening the first switch is in response to supplying a potential to a transistor by a dedicated reference source.

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