Memory Device Clock Mapping

Abstract

An exemplary memory device includes a clock circuit. The clock circuit can generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other. The device can include a detection circuit for providing a detection result indicating whether an initial operation of a self-refresh termination operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The device can include a processing circuit for providing odd and even clock signals based on the first and second clock signals and the detection result. The processing circuit can provide odd and even clock signals that are out of phase or in phase with the first and second clock signals depending on the detection result.

Description

[Technical Field]

[0001] Priority application This application claims the benefit of priority to U.S. Patent Application No. 17 / 897,957, filed August 29, 2022, which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to memory devices. More specifically, embodiments relate to clock circuits for memory devices. [Background technology]

[0003] A memory device is a semiconductor circuit that provides electronic storage of data for a host system (e.g., a computer or other electronic device). Memory devices can be volatile or nonvolatile. Volatile memory requires power to retain data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Nonvolatile memory can retain stored data when power is not applied and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM), among others.

[0004] Some memory devices use electrical circuitry to synchronize output data with a system clock. However, this coordination becomes increasingly difficult as the system clock frequency increases. Therefore, there is a general need to improve the operation of memory devices at ever-increasing system clock speeds.

[0005] In the drawings, which are not necessarily drawn to scale, like numerals may refer to like components in different figures. Like numerals with different letter suffixes may represent different instances of like components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. [Brief explanation of the drawings]

[0006] [Figure 1] 1 illustrates an example of a block diagram of a memory device. [Figure 2] 2 illustrates a system clock signal and first and second internal clock signals of a memory device. [Figure 3] 10A and 10B illustrate schematic examples of signal diagrams for a self-refresh exit operation. [Figure 4] 10 illustrates a schematic example of clock signal swapping. [Figure 5] 10 shows a schematic signal diagram including a command lockout signal and a clock swap signal. [Figure 6A] 1 illustrates a schematic diagram of an example clock divider circuit; [Figure 6B] 10 illustrates an example of a clock swap circuit and control logic. [Figure 6C] 1 illustrates a schematic diagram of an example clock swap circuit; [Figure 7A-1] 1 illustrates a schematic diagram of an example of a portion of a command decode circuit. [Figure 7A-2] 1 illustrates a schematic diagram of an example of a portion of a command decode circuit. [Figure 7A-3] 1 illustrates a schematic diagram of an example of a portion of a command decode circuit. [Figure 7B-1] 1 illustrates a schematic diagram of an example of a portion of a command decode circuit. [Figure 7B-2] 1 illustrates a schematic diagram of an example of a portion of a command decode circuit. [Figure 8A] 10 illustrates an example of a command lockout timing circuit; [Figure 8B] 10A and 10B show schematic diagrams of signal diagrams including command lockout windows; [Figure 9] 10A and 10B illustrate schematic signal diagrams including an example of a delay-locked loop (DLL) reset after a self-refresh event. [Figure 10] 10 illustrates an example of a method for using NOP signal detection to determine clock signal timing. [Figure 11] 1 illustrates a block diagram of an example machine with which, within, or adjacent to which any one or more of the techniques described herein may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following description and drawings sufficiently describe particular embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, portions and features of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.

[0008] FIG. 1 generally illustrates a simplified block diagram of various features of memory device 100. Specifically, the block diagram of FIG. 1 is a functional block diagram illustrating certain features of memory device 100. According to one embodiment, memory device 100 may be a random access memory (RAM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device (including double data rate SRAM devices), a holographic RAM (HRAM) flash memory, and / or a phase change memory (PCM) device, and / or other chalcogenide-based memory, such as a self-selection memory (SSM). Additionally, the memory cells of the memory device may each have a corresponding logic storage device (e.g., a capacitor, a resistor, or a chalcogenide device).

[0009] In some examples, the memory device 100 includes a cell or array of cells arranged according to a planar architecture, with individual cells or memory elements located at the intersections of word lines (WL) and bit lines (BL). In some examples, memory elements including chalcogenide materials can be provided at such WL and BL intersections and can function as both selectors and memory elements. In a two-dimensional array, alternating decks of WLs and BLs can be provided, or can be layered to provide a 3D memory array.

[0010] The memory device 100 may include memory partitions 102, each of which may include one or more cell arrays (i.e., memory arrays) including chalcogenide materials or the like. Various configurations, organizations, and sizes of the memory partitions 102 of the memory device 100 may be used depending on the application and design of the overall system. For example, each of the memory partitions 102 may include different dies of a stacked memory device. In such a device, at least one die may be a primary die that interfaces with a host or memory controller 108 using an inter-device bus 110, and one or more other dies may be secondary dies that interface with the primary die using an intra-package bus 124. The array may also be subdivided into multiple separately addressable portions (e.g., multiple channels, banks, ranks, etc.). Alternatively, a memory system may include multiple memory devices, such as the memory device 100 of FIG. 1, where each memory device represents a separately addressable subdivision (e.g., rank, etc.) of the system's memory capacity. Thus, a memory device or memory system with multiple memory devices, ranks, channels, banks, etc. may include multiple terminals (e.g., clock terminals, CMD / ADD terminals, I / O terminals, etc.) dedicated to one or more, but fewer than all, of the multiple separately addressable portions. For example, a multi-channel memory device may include multiple terminals, each corresponding to one of the multiple channels of the memory.

[0011] Memory device 100 may include a command interface 104 and an input / output interface 106. Command interface 104 may receive various signals from an external host device, such as a processor or controller (e.g., memory controller 108) external to memory device 100. In some embodiments, inter-device bus 110 (or signal paths or groups of signal paths), individually or in combination, may enable bidirectional transmission of signals between command interface 104 and the processor or controller (e.g., memory controller 108).

[0012] In an example, memory device 100 may include a second bus 112 (or another group of signal paths) that may, individually or in combination, enable bidirectional transmission of signals, including data signals, between, for example, input / output interface 106 and, for example, a processor or controller (e.g., memory controller 108). Thus, the processor or controller, for example, memory controller 108, may provide various signals to memory device 100 to facilitate sending and receiving data to be written to or read from memory device 100.

[0013] In one example, the command decoder 120 can decode commands such as a read command, a write command, a register set command, an activate command, etc., and provide access to a particular one of the memory partitions 102 corresponding to the command via an intra-package bus 124. The command decoder 120 can send various signals to one or more registers 126 via a bus path (e.g., one or more global interconnects). In one example, the memory device 100 can include various other decoders, such as a row decoder and a column decoder, to facilitate access to the memory partitions 102. In one embodiment, each memory partition 102 can include a respective bank control block 128 that provides decoding (e.g., row decoding and column decoding) and other functions, such as timing control and data control, to facilitate execution of commands to and from the memory partition 102.

[0014] In some examples, command decoder 120 or other components of memory device 100 can provide register commands to one or more of registers 126, which can be used in the operation of each of memory partitions 102, each control block 128, etc. For example, one of registers 126 can define various modes of programmable operation and / or configuration of memory device 100. Registers 126 can be included in a semiconductor device to define operations for various types of memory components, such as DRAM, synchronous DRAM, chalcogenide memory (e.g., PCM), or other types of memory. Registers 126 can receive various signals from command decoder 120 via wiring, which can include a common data path, a common address path, a common write command signal path, or a common read command signal path. Wiring lines can traverse memory device 100 and couple to each register 126.

[0015] Registers 126 may be accessible or otherwise accessible by memory controller 108. Registers 126 may be distributed throughout memory device 100, and registers may represent or contain information such as configuration settings of memory device 100 and / or particular components therein, status information regarding memory device 100 and / or particular components therein, parameters of memory device 100 and / or particular parameters of components of memory device 100, or predetermined patterns that can be written throughout the memory device (e.g., in one or more of memory partitions 102). Thus, while registers 126 are shown in FIG. 1 , it should be appreciated that additional and / or alternative registers can be located elsewhere in the memory device and accessible by memory controller 108 (i.e., during operation, the registers are accessed by memory controller 108). Such access by memory controller 108 may include, for example, reading the registers (e.g., read accesses) and / or writing to the registers (e.g., write accesses).

[0016] In one example, memory device 100 performs operations, such as read commands and write commands, based on command / address signals received from an external device, such as a processor, and / or by memory controller 108. In one example, the command / address signals are clocked to command interface 104 using a clock signal. The command interface may include, for example, command / address input circuitry 116 configured to receive and send commands to provide access to memory partitions 102 via command decoder 120. Command interface 104 may receive memory select signals that enable memory device 100 to process commands in the incoming command / address signals. Access to a particular memory partition 102 within memory device 100 may be encoded in the command.

[0017] The command interface 104 can be configured to receive various other command signals. For example, a reset command can be used to reset the command interface 104, status registers, state machines, etc., e.g., upon power-on or exiting standby. Various signals can be provided to facilitate testing of the memory device 100. For example, a test signal can be used to place the memory device 100 in a test mode for connectivity testing. The command interface 104 can be used to provide alert signals or other alert signals to a system processor or controller for particular errors that may be detected. In some embodiments, the input / output interface 106 can additionally or alternatively send alert signals, e.g., temperature alerts.

[0018] In some examples, command interface 104 may include or use several circuits, such as clock input circuit 114 and command / address input circuit 116, to ensure proper processing of received signals. Command interface 104 may receive one or more clock signals from an external device, such as memory controller 108. Command interface 104 may receive commands (e.g., read commands, write commands, etc.), which may be input, for example, on the positive edge of the clock signal, and may receive data, which may be sent, received, etc., on the positive and / or negative edge of the clock signal. In some examples, commands may have variable clock lengths (e.g., commands may be received using one or more clocks).

[0019] The clock input circuit 114 can receive one or more clock signals and generate an internal clock signal CLK therefrom. In some embodiments, the internal clock signal CLK is provided to an internal clock generator 118, such as a delay-locked loop (DLL) circuit. The DLL circuit 118 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK can be provided to the input / output interface 106, for example, and used as a timing signal to determine the output timing of read data.

[0020] The internal clock signal CLK may also be provided to various other components within the memory device 100 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 120. The command decoder 120 may receive command signals from a command bus 122 and decode the command signals to provide various internal commands. For example, the command decoder 120 may use the internal bus to provide command signals to the internal clock generator 118 to coordinate the generation of the phase-controlled internal clock signal LCLK. In some examples, the phase-controlled internal clock signal LCLK may be used to clock data through the input / output interface 106. In some examples, the frequency of the internal clock signal CLK may be less than the frequency of the clock signal used by the memory controller 108 to communicate via the inter-device bus 110.

[0021] Using the command and clock signals described above, data can be sent to and from memory device 100, for example, by sending and receiving data signals via input / output interface 106. More specifically, data can be sent to and retrieved from memory partition 102 over data path 130, which may include multiple bidirectional data buses. Data I / O signals can be sent and received, for example, on one or more bidirectional data buses to and from input / output interface 106. For certain memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into upper and lower bytes. However, such segmentation is generally not used for other types of memory devices.

[0022] Various other components, such as power supply circuits (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of memory device 100), may be incorporated into memory device 100. It should therefore be understood that the block diagram of Figure 1 is provided to highlight only certain functional features of memory device 100 to aid in the detailed description that follows.

[0023] As previously described herein, memory device 100 can use a variety of internal clock signals. DRAM memory devices, in particular, use an internal clock generator 118 (e.g., a DLL) to synchronize output data with a system clock. In some previous systems and designs, the clock frequency was slow enough that the incoming system clock signal was used to capture commands and addresses and used as an input to internal clock generator 118 to generate output times on the rising or falling edge. However, as clock speeds increased, memory devices could not use a full-frequency clock to capture memory commands and addresses. Therefore, some memory systems can adjust to these faster speeds by generating multiple internal clock signals that toggle at half the frequency of the system clock. Either an “even” clock signal (e.g., CLKE) or an “odd” clock signal (e.g., CLKO) can then be used to capture commands and addresses, depending on whether such commands are synchronized to the rising edge of an even or odd external clock signal. The even and odd clock signals can then be used by internal clock generator 118 to generate output control clock signals. So, in effect, the timing of the output bits can be controlled by two different clocks.

[0024] 2 shows a schematic diagram of a system clock signal and first and second internal clock signals for use in a memory device or the like. The example in FIG. 2 shows the alignment of the rising edges of the first and second internal clock signals with respect to the edges of an external clock.

[0025] In the example of FIG. 2 , an external clock signal is represented by external clock signal 200. A chip select (CS) signal for a command (in that example, no operation, or “NOP”) is represented by signal 202. A first internal clock signal having a rising edge on odd cycles of external clock signal 200 is represented by first clock signal 204. A second internal clock signal having a rising edge on even cycles of external clock signal 200 is represented by second clock signal 206. First clock signal 204 and second clock signal 206 have a frequency that is half the frequency of system clock 200. A rising edge of external clock signal 200 has a rising edge that coincides with either the rising edge of first clock signal 204 or the rising edge of second clock signal 206, and an external user may not be able to detect which rising edge of the internal signals coincides with (e.g., maps to) any given rising edge of external clock signal 200. In some examples, the first clock signal and the second clock signal path may be physically different paths, which in turn may affect edge timing and cause distortion or inconsistency in the output data of the memory device 100.

[0026] To address these and other concerns, embodiments herein allow devices and users of memory device 100 to map external clock signal 200 to a particular internal divided clock signal (e.g., first clock signal 204 or second clock signal 206). In some examples, external users and systems can read the output data, analyze the duty cycle, and adjust the system clock to compensate for duty cycle distortion that may result from having odd and even clock paths.

[0027] FIG. 3 schematically illustrates an example signal diagram for a self-refresh exit operation of a memory device. In the example of FIG. 3, the self-refresh exit operation can be used to determine or define internal clock signals. The self-refresh exit operation and clock signal definition can occur before duty cycle adjuster (DCA) training, which is described later in this specification. In some examples, a self-refresh entry / self-refresh exit (SRE / SRX) operation is performed, and following the operation, the memory device 100 (or, more specifically, the memory controller 108) synchronizes one of the clocks (e.g., the first clock signal 204 (FIG. 2)) with a first NOP issued to the SRX, as described below.

[0028] In the example of FIG. 3 , signal 300 represents an external clock signal (e.g., similar to external clock signal 200 ( FIG. 2 )). Signal 302 is a chip select (CS) signal, and signals 304 and 306 are command signals. A self-refresh operation is provided, which may include a self-refresh entry (SRE, not shown in FIG. 3 ) and a self-refresh exit (SRX) operation 308. In the example of FIG. 3 , the self-refresh exit may include a string of three NOP commands 310, such as may be provided starting at the first odd clock cycle tc+1 of external clock signal 300, which may correspond to a NOP command mapped to the first command pipeline. Following this point, DCA training may be performed. Chip select (CS) signal 302 is shown low for three cycles corresponding to the string of three NOP commands 310. While a string of three NOP commands 310 is illustrated, this is for illustrative purposes only, and embodiments are not limited thereto.

[0029] In one example, the first NOP command of commands 310 can be detected in the DRAM using detection circuitry. When the first NOP command is received, a NOP command arrives from a second (e.g., “even”) command path or pipeline, or arrives from the first (e.g., “odd”) command path or pipeline. The first and second command paths can be identical or substantially identical, but are based on clock signals that are shifted by a half cycle from each other so that the clock signals are out of phase with each other.

[0030] In one example, the detection circuit provides a detection result indicating whether a first NOP command (or other command associated with exiting from a self-refresh operation) arrives in the first command pipeline or the second command pipeline. If the NOP command arrives in the first command pipeline, no clock swap adjustment is indicated because, for example, the first command pipeline can accommodate a NOP command that coincides with an “odd” cycle (e.g., tc+1) of the external clock. The example can then proceed with DCA training.

[0031] Otherwise, if a NOP command arrives in the second command pipeline, a clock swap adjustment may be indicated, and a "clock swap" signal or indicator may be set for use in later processing as described herein. The example may then proceed with DCA training. For any subsequent SRE / SRX sequences, the internal clock may be mapped to what existed during DCA training. However, if any subsequent "soft" reset occurs, a pair of SRE / SRX commands may be issued to ensure that the internal clock is mapped as described above.

[0032] In one example, a clock swap operation may include the following: First, an external clock (e.g., external clock signal 200 (FIG. 2) or clock signal 300 (FIG. 3)) is divided into four phases (e.g., I (0 degrees), IB (90 degree phase shift relative to I)), Q (180 degree phase shift relative to I), and QB (270 degree phase shift relative to I)) using a clock divider. The outputs of the clock divider can be swapped when a "clock swap" signal is set, or "high," such as by inverting the output from the clock divider. When the output is inverted, instead of outputting the I phase, the Q phase is output. Similarly, instead of outputting IB, the QB is output. A multiplexer (mux) can be used for swapping, as provided in the circuit diagrams described later in this specification.

[0033] Referring again to Figure 2, Figure 2 shows that a NOP command occurs (e.g., when CS signal 202 is asserted) in coordination with the rising edge of first clock signal 204. In this example, "clock swapping" is not shown.

[0034] In contrast, Figure 4 illustrates clock swapping according to some embodiments. In that example, an external clock signal 402 is provided. When a NOP command occurs (e.g., when CS signal 404 is asserted), the clock signal with the corresponding rising edge may be a second (e.g., "even") clock signal 406, as shown at point 407. Thus, the clocks can be swapped at 408, for example, by delaying the edges of each of the even and odd clock signals by one complete system (external) clock cycle. In one example, the delay can be achieved by "swapping" the (I, Q) and (IB, QB) phases in pairs.

[0035] FIG. 5 schematically illustrates a signal diagram including a command lockout signal and a clock swap signal. In examples where the clock signals are swapped, a command decode lockout signal 500 can be generated in coordination with the clock swap event. The lockout signal 500 can be used to enforce a lockout window 512, or an interval during which no operations or commands are executed, such as to protect electrical circuitry that may be adversely affected by irregular clock signal pattern(s) during the clock swap event. For example, adjacent flip-flops (not shown in FIG. 5) or other adjacent elements connected to or controlled by the divided clock signal during the "swap" event can be prohibited from performing operations during the lockout window.

[0036] 5, a self-refresh exit (SRX) command is received at signal 501. An external clock is shown at signal 502. Four phase signals of the first and second internal clocks are shown at 504 (I phase, or 0 degrees), 506 (Q phase, or 180 degrees), 508 (IB phase, or 90 degrees), and 510 (QB phase, or 270 degrees). As soon as lockout signal 500 goes high or becomes active, swapping occurs in lockout window 512, during which signals 504 and 506 are swapped and signals 508 and 510 are swapped.

[0037] 6A schematically illustrates an example clock divider circuit 600. In that example, four signals are provided, each separated by a phase or degree, e.g., 90 degrees or a fraction of a clock cycle. Pin 602 provides the I phase or 0 degrees, pin 604 provides the Q phase or 180 degrees, pin 606 provides the IB phase or 90 degrees, and pin 608 provides the QB phase or 270 degrees. The different phase signals are provided based on the system clock signal CLKT.

[0038] 6B schematically illustrates an example of clock swapping circuitry and control logic, including clock swapping circuit 612, which can provide signal swapping when shown with respect to I and Q phase signals, and clock swapping circuit 614, which can provide signal swapping when shown with respect to IB and QB phase signals.

[0039] 6C schematically illustrates an example of a clock swap circuit. In one example, FIG. 6C provides further details regarding the clock swap circuit, according to some embodiments. For example, swap 616, when high, indicates that swapping should not occur, and swap signal 618, when high, indicates that swapping should occur. The circuitry within box 620 includes a multiplexer (mux) for performing the signal swap operation and is configured to provide outputs including a pair of internal clock signals 622 and 624, which can be either the swapped signal or the original, unswapped signal.

[0040] 7A and 7B schematically illustrate an example of a portion of a command decode circuit. The decode circuit can be configured to identify NOP commands (e.g., those that can be associated with self-refresh entry and / or exit operations) in a first command path and a second command path. In that example, block 702 includes an even decoder configured to detect commands arriving via the second (or “even”) pipeline. For example, block 702 can include electrical circuitry configured to identify NOP commands in the second command pipeline and provide an output signal or a NOPE command when one or more NOP commands are identified in the second command pipeline. In that example, block 704 includes an odd decoder configured to detect commands arriving via the first (or “odd”) pipeline. For example, block 704 can include electrical circuitry configured to identify NOP commands in the first command pipeline and provide an output signal or a NOPO command when one or more NOP commands are identified in the first command pipeline. In one example, block 702 and block 704 may include different instances of the same circuitry, but applied to different pipelines.

[0041] 7A , block 706 includes a command decoder circuit configured to monitor or capture NOP command information for the first pipeline and the second pipeline, as well as monitor or capture information regarding a self-refresh exit (SRX) command. For example, receipt of an exit command may have the same or similar effect as a NOP command in triggering a clock swap detection and / or implementation event. In some examples, block 706 includes logic configured to identify whether multiple NOP commands have been received. In some examples, clock swapping may be inhibited unless or until a specified number of individual NOP commands (e.g., three consecutive NOP commands in a particular pipeline) are received.

[0042] 7B, the illustrated portion of the command decode circuitry can be configured to detect whether the NOP command arrives first or earliest in the first or second command pipeline. Based on the detection result regarding the self-refresh end NOP command signal, a signal can be generated indicating whether the clocks need to be swapped, according to various embodiments.

[0043] In one example, the pair of input channels 708 / 710 is coupled to an arbiter circuit that detects a pipeline carrying the first NOP command of the SRX routine. The pair of input channels 708 / 710 can be configured to receive output signals, such as NOPE and NOPO commands, from the portions of the decoder circuitry shown in the example of blocks 702 and 704, respectively. The arbiter circuit can, for example, mask the NOPE command when the NOPO command is captured early, or can mask the NOPO command when the NOPE command is captured early. In the example of FIG. 7B, a clock swap indicator signal 712 can toggle according to the detection result to indicate whether a clock swap is required.

[0044] FIG. 8A schematically illustrates an example of a command lockout timing circuit. At the input of the lockout timing circuit, the circuit can be configured to receive a self-refresh, NOP, and / or power-on reset signal. In response, an electrical circuit can provide a CLKCLKSWAP_START signal to set a flip-flop 804. The output of the flip-flop can be processed or delayed (e.g., using one or more signal delay elements) and fed back to the flip-flop 804 via a feedback path 806, thereby forming a timeout mechanism. The timeout can be configured so that the signal flow settles to a final state within a specified command lockout window, such as corresponding to a specific number of clock cycles. The lockout window can have a duration or interval long enough to allow a clock swap event to complete. In some examples, the power-on reset signal can be introduced at an intermediate portion of the feedback path 806, bypassing some or all of the delay elements.

[0045] FIG. 8B schematically illustrates a signal diagram including a command lockout window. In the example of FIG. 8B, the command lockout window can be triggered at 810, such as in coordination with a self-refresh entry or the start of a self-refresh routine. In that example, a clock swap event can occur during the lockout window 812. Irregular clock signals during the clock swap event can lead to erroneous commands, and therefore, commands arriving during the clock swap event can be intentionally paused or discarded, such as during the lockout window 812. In some examples, the number of cycles used to implement the clock swap can be less than the number of cycles within the lockout window 812. After the self-refresh routine is completed, the internal clock generator 118 (e.g., the DLL shown in FIG. 1) can be reset and then relocked.

[0046] FIG. 9 schematically illustrates a signal diagram including an example of a delay-locked loop (DLL) reset after a self-refresh event. In one example, at time 900 (e.g., SRE), a self-refresh routine can begin, and at time 902 (e.g., SRX), the self-refresh routine can end. In one example, clock synchronization (e.g., with a system clock) may be lost during some portions of the self-refresh routine and can be reestablished later, such as following the self-refresh routine. In the example of FIG. 9, a clock swap event 904 can be initiated upon or in coordination with a self-refresh exit command. A DLL reset command signal 906 can be asserted (e.g., occurring following self-refresh exit), and clock signals can be resynchronized. For example, a DLL reset interval can be initiated in coordination with the self-refresh exit routine. Coarse lock can be established over multiple clock cycles (e.g., a number of clock cycles that generally exceeds the number of cycles used for the self-refresh routine and / or the clock swap event). At time 908, DLL lock can be achieved, and the system can continue normal command processing operations.

[0047] According to various examples, the clock swap event can occur at the earliest possible logic point, such as upon or shortly after receiving a system clock signal (e.g., at a memory chip). Downstream circuitry, such as including internal clock generator 118, can then receive and use the properly aligned clock signal output from the clock swap circuit.

[0048] 10 generally illustrates an example method 1000 for using NOP command signal detection to determine clock signal timing. In method 1000, an internal clock signal can be provided, such as using an internal clock generator 118 (e.g., a DLL) circuit to synchronize output data with a system clock. At operation 1002, method 1000 includes generating a first clock signal and a second clock signal based on the system clock signal. In some examples, the first clock signal and the second clock signal can be out of phase with each other.

[0049] At determining operation 1004, method 1000 may include determining whether an initial operation of the self-refresh termination operation coincides with a rising edge of the first clock signal or the second clock signal. In one example, the initial operation of the self-refresh termination operation may include a no-operation (NOP) command or a series of multiple time-adjacent NOP commands on one or more respective command buses, such as within a memory device. In one example, operation 1004 may be understood with reference to FIG. 3. FIG. 3 illustrates that the command associated with terminating the self-refresh operation may include a NOP command 306, although embodiments are not limited to NOP commands. In one example, various command detection circuits may be used to perform NOP command detection, such as using the electrical circuitry described herein with at least reference to FIGS. 6A and 6B. In one example, the NOP command detection circuit may be configured to provide a detection result, such as a signal with information regarding whether the initial operation of the self-refresh termination operation coincides with a rising edge of the first clock signal or the second clock signal.

[0050] If, at determining operation 1004, the NOP command coincides with a rising edge of a first clock signal (e.g., corresponding to a first command pipeline), method 1000 may continue with operation 1006. If, at determining operation 1004, the NOP command coincides with a rising edge of a second clock signal (e.g., corresponding to a second command pipeline), method 1000 may continue with operation 1008.

[0051] In the example of method 1000, the detection result can be used to toggle the behavior of a clock swap circuit. The clock swap circuit can receive the detection result and the first and second clock signals and, in response, provide odd and even clock signals corresponding to the first and second clock signals, respectively. The timing or phase of the odd and even clock signals can depend on the value of the detection result. For example, in operation 1006, method 1000 can include providing even and odd clock signals that are out of phase with the first and second clock signals, respectively. In operation 1008, method 1000 can include providing even and odd clock signals that are in phase with the first and second clock signals, respectively.

[0052] 11 shows a block diagram of an example machine (e.g., a host system) 1100 that may include one or more memory devices and / or memory systems, such as may include or be capable of using clock swap circuitry as described herein. As described further below, machine 1100 may benefit from improved memory performance from the use of one or more of the described memory devices and / or memory systems, facilitating improved performance of machine 1100 (for many such machines or systems, efficient reading and writing of memory can facilitate improved performance of the processor or other components of the machine).

[0053] In alternative embodiments, machine 1100 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 1100 may operate in the capacity of a server machine, a client machine, or both in a server-client network environment. In one example, machine 1100 may function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1100 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, an IoT device, an automotive system, or any machine capable of executing instructions (sequentially or otherwise) that specify actions to be taken by that machine. Furthermore, while only a single machine is shown, the term “machine” shall be interpreted to include any collection of machines individually or collectively executing a set (or sets) of instructions to perform any one or more of the methodologies described herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations, etc.

[0054] Examples described herein may include or operate with logic, components, devices, packages, or mechanisms. An electrical circuit is a collection (e.g., set) of circuits implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). The components of an electrical circuit may be flexible over time and to variability in the underlying hardware. An electrical circuit includes components that, alone or in combination, can perform a specific task when operated. In some examples, the hardware of an electrical circuit may be invariably designed to perform a specific operation (e.g., hardwired). In some examples, the hardware of an electrical circuit may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include a computer-readable medium that has been physically modified (e.g., modified into a magnetically, electrically movable arrangement of invariable mass particles, etc.) to encode instructions for a specific operation. When connecting the physical components, the underlying electrical properties of the hardware construct are changed, for example, from an insulator to a conductor or vice versa. The instructions cause the associated hardware (e.g., an execution unit or a load mechanism) to create components of the electrical circuit in the hardware via variable connections to perform a portion of a particular task during operation. Thus, the computer-readable medium is communicatively coupled to other components of the electrical circuit when the device is operating. In some examples, any of the physical components may be used in more than one component of two or more electrical circuits. For example, during operation, an execution unit may be used in a first circuit of a first electrical circuit at one time and reused by a second circuit of the first electrical circuit, or reused by a third circuit of the second electrical circuit at a different time.

[0055] The machine (e.g., computer system, host system, etc.) 1100 may include a processing device 1102 (e.g., a hardware processor, a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof, etc.), a main memory 1104 (e.g., read-only memory (ROM), dynamic random access memory (DRAM) such as synchronous dynamic random access memory (SDRAM) or Rambus dynamic random access memory (RDRAM), etc.), a static memory 1106 (e.g., static random access memory (SRAM), etc.), and a storage system 1108, some or all of which may communicate with each other via a communication interface (e.g., bus) 1130. In one example, the main memory 1104 includes one or more memory devices such as those described in the examples above.

[0056] The processing device 1102 may represent one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a multiple instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or a processor implementing a combination of instruction sets. The processing device 1102 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1102 may be configured to execute instructions 1124 to perform the operations and steps described herein. The computer system 1100 may further include a network interface device 1120 for communicating over a network 1126.

[0057] Storage system 1108 may include a machine-readable storage medium (also known as a computer-readable medium) on which one or more sets of instructions 1124 or software that embody any one or more of the methodologies or functions described herein are stored. The instructions 1124 may also reside, completely or at least partially, within main memory 1104 or within processing device 1102 during execution of the instructions by computer system 1100, with main memory 1104 and processing device 1102 also constituting machine-readable storage media.

[0058] The term "machine-readable storage medium" should be interpreted to include a medium or media that stores one or more sets of instructions, or any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies of this disclosure. Accordingly, the term "machine-readable storage medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media. In one example, a high-capacity machine-readable medium includes a machine-readable medium with a plurality of particles having an immutable mass (e.g., rest mass). Thus, a high-capacity machine-readable medium is not a transitory, propagating signal. Specific examples of high-capacity machine-readable media may include semiconductor memory devices (e.g., non-volatile memory such as electrically programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM) and flash memory devices), magnetic disks such as internal hard disks and removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0059] The machine 1100 may further include a display unit 1110, an alphanumeric input device 1112 (e.g., a keyboard), and a user interface (UI) navigation device 1114 (e.g., a mouse). In some examples, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. The machine may include a signal generating device 1118 (e.g., a speaker, etc.), or one or more sensors 1116, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or one or more other sensors. The machine 1100 may include an output controller 1128, such as a serial connection (e.g., a universal serial bus (USB) connection), a parallel connection, or other wired or wireless connection (e.g., infrared (IR), near field communication (NFC), etc.) for communicating with or controlling one or more peripheral devices, etc. (e.g., a printer, a card reader, etc.).

[0060] Instructions 1124 (e.g., software, programs, operating systems (OS), etc.) or other data stored in storage system 1108 can be accessed by main memory 1104 for use by processing device 1102. Main memory 1104 (e.g., DRAM) is a different type of storage than storage system 1108 (e.g., SSD), which is typically fast but volatile and thus suitable for long-term storage, including while in an “off” state. Instructions 1104 or data used by a user or machine 1100 are typically loaded into main memory 1104 for use by processing device 1102. When main memory 1104 fills up, virtual space from storage system 1108 can be allocated to supplement main memory 1104; however, storage system 1108 is typically slower than main memory 1104, with write speeds typically at least twice as slow as read speeds, so using virtual memory (as opposed to main memory 1104, e.g., DRAM) can significantly degrade the user experience due to the latency of the storage system. Additionally, using the storage system 1108 for virtual memory can significantly reduce the usable life of the storage system 1108 .

[0061] The instructions 1124 may further be transmitted or received over a communications network 1126 using a transmission medium via a network interface device 1120 utilizing any one of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Examples of communications networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone service (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 1102.15 family of standards known as Wi-Fi®, the IEEE 802.16 family of standards known as WiMax®), the IEEE 802.15.4 family of standards, a peer-to-peer (P2P) network, among others. In an example, network interface device 1120 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to network 1126. In an example, network interface device 1108 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term “transmission medium” shall be taken to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 1100, and to include digital or analog communication signals or other intangible media for facilitating communication of such software.

[0062] To more fully illustrate the methods and apparatus described herein, a non-limiting set of exemplary embodiments are set forth below as numbered and identified examples.

[0063] Example 1 includes a clock circuit configured to generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other, and a detection circuit configured to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. Example 1 may further include a processing circuit configured to receive the first clock signal and the second clock signal and the detection result, and to responsively provide odd and even clock signals corresponding to the first and second clock signals, respectively, when the detection result coincides with the rising edge of the first clock signal, providing the odd and even clock signals out of phase with the first and second clock signals, and when the detection result coincides with the rising edge of the second clock signal, providing the odd and even clock signals in phase with the first and second clock signals.

[0064] In Example 2, the subject matter of Example 1 may include or use a duty cycle adjustment (DCA) circuit configured to modify a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

[0065] In Example 3, the subject matter of any one or more of Examples 1-2 may include the following, namely, the odd clock signal and the even clock signal each have a frequency that is approximately half the frequency of a system clock signal of the device and are 180 degrees out of phase with each other.

[0066] In Example 4, the subject matter of any one or more of Examples 1 to 3 may include or can use a command processor configured to process commands for the device based on instructions on the command bus, and the command processor may be configured to initiate a command lockout for commands on the command bus in coordination with the self-refresh termination operation.

[0067] In Example 5, the subject matter of any one or more of Examples 1 to 4 may include the following, i.e., providing odd and even clock signals that are out of phase with the first clock signal may include swapping outputs of clock divider pairs.

[0068] In a sixth embodiment, the subject matter of any one or more of the first to fifth embodiments may include a self-refresh exit operation including a self-refresh entry (SRE) command and a self-refresh exit (SRX).

[0069] In Example 7, the subject matter of Example 6 may include an initial operation of the self-refresh exit operation that includes a no-operation (NOP) command or a string of multiple consecutive NOP commands.

[0070] In example 8, the subject matter of any one or more of examples 1-7 includes a memory device including a clock circuit, a detection circuit, and / or a processing circuit.

[0071] In Example 9, the subject matter of Example 8 can include a memory device including a dynamic random access memory (DRAM) device.

[0072] Example 10 is a clock swap circuit for a memory device, the clock swap circuit comprising: a swap signal generator configured to provide a swap signal indicating an earlier arriving instruction (e.g., a NOP instruction or command) on a first command bus or a second command bus; and a multiplexing circuit configured to receive an input clock signal from the clock divider circuit, receive a swap signal from the swap signal generator, and selectively provide odd and even clock signals that are in phase or out of phase with the input clock signal based on the swap signal.

[0073] In Example 11, the subject matter of Example 10 can include or use a clock divider circuit to receive a system clock signal, the input clock signal having a frequency lower than the frequency of the system clock signal.

[0074] In Example 12, the subject matter of any one or more of Examples 10-11 may include or use a first command bus and a second command bus, wherein the first command bus and the second command bus are configured to transmit memory commands for the memory device.

[0075] In Example 13, the subject matter of any one or more of Examples 10 to 12 may include the following, i.e., the command on the first command bus or the second command bus may include an command following the self-refresh exit command.

[0076] Example 14 is a method that includes: generating a first clock signal and a second clock signal based on a system clock signal, where the first clock signal and the second clock signal are out of phase with each other; providing a detection result indicating whether an initial operation of the self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; receiving the first clock signal and the second clock signal and the detection result, and in response thereto, providing odd clock signals and even clock signals corresponding to the first clock signal and the second clock signal, respectively; when the detection result coincides with the rising edge of the first clock signal, providing the odd clock signal and the even clock signal that are out of phase with the first clock signal and the second clock signal, and when the detection result coincides with the rising edge of the second clock signal, providing the odd clock signal and the even clock signal that are in phase with the first clock signal and the second clock signal.

[0077] In Example 15, the subject matter of Example 14 may include initiating a duty cycle adjustment (DCA) routine to modify a duty cycle timing characteristic of at least one of the first clock signal and the second clock signal.

[0078] In Example 16, the subject matter of any one or more of Examples 14 to 15 may include the following, namely, the odd clock signal and the even clock signal each have a frequency that is approximately half the frequency of the system clock and are 180 degrees out of phase with each other.

[0079] In Example 17, the subject matter of any one or more of Examples 14 to 16 may include initiating a command lockout on commands on a command bus of the memory device in coordination with the self-refresh termination operation.

[0080] In Example 18, the subject matter of any one or more of Examples 14 to 17 may include: i.e., providing the odd and even clock signals out of phase with the first and second clock signals includes swapping outputs of clock dividers.

[0081] In Example 19, the subject matter of any one or more of Examples 14-18 includes a self-refresh exit operation including a self-refresh entry (SRE) command and a self-refresh exit (SRX).

[0082] In Example 20, the subject matter of Example 19 may include an initial operation of the SRX command that includes a no-operation (NOP) command or a string of multiple consecutive NOP commands.

[0083] Example 21 is at least one machine-readable medium containing instructions that, when executed by a processing circuit, cause the processing circuit to perform operations that implement any of Examples 1-20.

[0084] Example 22 is an apparatus including means for implementing any one of Examples 1 to 20.

[0085] The twenty-third embodiment is a system that implements any one of the first to twentieth embodiments.

[0086] Example 24 is a method for carrying out any one of Examples 1 to 20.

[0087] Each of these non-limiting examples can stand on its own or can be combined with one or more of the other examples in various permutations or combinations.

[0088] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the inventors also contemplate examples using any combination or permutation of those elements (or one or more aspects thereof) shown or described, either with respect to the particular example (or one or more aspects thereof), or with respect to any other example (or one or more aspects thereof) shown or described herein.

[0089] All publications, patents, and patent documents referenced herein are incorporated by reference in their entirety as if individually incorporated by reference. In the event of inconsistent usage between this document and those documents so incorporated by reference, the usage of the incorporated reference(s) should be considered supplemental to the usage in this document. In the event of an irresolvable inconsistency, the usage in this document will control.

[0090] As used herein, the terms "a" or "an" are used, as is common in patent documents, to include one or more, regardless of any other instance or usage of "at least one" or "one or more." As used herein, the term "or" refers to a non-exclusive or, unless otherwise indicated, "A or B" is used to include "A but not B," "B but not A," and "A and B." In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended; that is, systems, devices, articles, or processes that include elements in addition to elements recited after such terms in a claim are also deemed to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," "third," etc. are used merely as distinguishing terms and are not intended to impose numerical requirements on their objects.

[0091] In various embodiments, a component, controller, processor, unit, engine, or table described herein may include, among other things, physical circuitry or firmware stored on a physical device. As used herein, "processor" means any type of computational circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuitry, including a group of processors or multi-core devices.

[0092] The detailed description herein is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0093] When an element is referred to as being "on," "connected to," or "coupled with" another element, it is understood that the element may be directly on, connected to, or directly coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled with" another element, no intervening elements or layers are present. When two elements are shown in a drawing with a line connecting them, the two elements may either be bonded or directly coupled, unless otherwise indicated.

[0094] The example methods described herein can be implemented, at least in part, on a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples. Implementations of such methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code can be tangibly stored on one or more volatile or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0095] The above description is intended to be illustrative, not limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be utilized, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 CFR §1.72(b) to enable the reader to quickly grasp the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be construed as intending that any unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims

1. a clock circuit configured to generate a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other; a detection circuit configured to provide a detection result indicating whether an initial operation of a self-refresh termination operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; a processing circuit, the processing circuit comprising: receiving the first and second clock signals and the detection result, and in response thereto, providing odd and even clock signals corresponding to the first and second clock signals, respectively; providing the odd and even clock signals out of phase with the first and second clock signals when the detection result coincides with the rising edge of the first clock signal, and providing the odd and even clock signals in phase with the first and second clock signals when the detection result coincides with the rising edge of the second clock signal; An apparatus configured to:

2. 10. The apparatus of claim 1, further comprising a duty cycle adjustment (DCA) circuit configured to modify a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

3. 2. The device of claim 1, wherein the odd clock signal and the even clock signal are each at approximately half the frequency of the system clock signal of the device and are 180 degrees out of phase with each other.

4. 2. The device of claim 1, further comprising: a command processor configured to process commands for the device based on instructions on a command bus, the command processor configured to initiate a command lockout for commands on the command bus in coordination with the self-refresh exit operation.

5. 2. The apparatus of claim 1, wherein the instructions to provide the odd and even clock signals out of phase with the first clock signal include swapping outputs of clock divider pairs.

6. 2. The apparatus of claim 1, wherein the self-refresh exit operation includes a self-refresh entry (SRE) command and a self-refresh exit (SRX) command.

7. 7. The apparatus of claim 6, wherein the initial operation of the self-refresh termination operation comprises a no operation (NOP) command.

8. The apparatus of claim 1 further comprising a memory device containing the clock circuit, the detection circuit, and the processing circuit.

9. 10. The apparatus of claim 8, wherein the memory device comprises a dynamic random access memory (DRAM) device.

10. 1. A clock swap circuit for a memory device, comprising: a swap signal generator configured to provide a swap signal indicative of an earlier arriving instruction on the first command bus or the second command bus; a multiplexing circuit configured to receive an input clock signal from the clock divider circuit, receive the swap signal from the swap signal generator, and selectively provide odd and even clock signals that are in phase or out of phase with the input clock signal based on the swap signal; A clock swap circuit comprising:

11. 11. The clock swap circuit of claim 10, further comprising the clock divider circuit configured to receive a system clock signal, the input clock signal having a frequency that is lower than a frequency of the system clock signal.

12. 11. The clock swap circuit of claim 10, further comprising the first command bus and the second command bus, the first command bus and the second command bus configured to transmit memory commands for the memory device.

13. 11. The clock swap circuit of claim 10, wherein the instructions on the first command bus or the second command bus include an instruction following a self-refresh exit command.

14. generating a first clock signal and a second clock signal based on a system clock signal, the first clock signal and the second clock signal being out of phase with each other; providing a detection result indicating whether an initial operation of a self-refresh termination operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal; receiving the first and second clock signals and the detection result, and in response thereto, providing odd and even clock signals corresponding to the first and second clock signals, respectively; providing the odd and even clock signals out of phase with the first and second clock signals when the detection result coincides with the rising edge of the first clock signal, and providing the odd and even clock signals in phase with the first and second clock signals when the detection result coincides with the rising edge of the second clock signal; A method comprising:

15. 15. The method of claim 14, further comprising initiating a duty cycle adjustment (DCA) to modify a duty cycle characteristic of at least one of the first clock signal and the second clock signal.

16. 15. The method of claim 14, wherein the odd clock signal and the even clock signal are each at approximately half the frequency of a system clock signal and are 180 degrees out of phase with each other.

17. 15. The method of claim 14, further comprising initiating a command lockout for commands on a command bus in coordination with the self-refresh exit operation.

18. 15. The method of claim 14, wherein providing the odd and even clock signals out of phase with the first and second clock signals comprises swapping outputs of clock dividers.

19. 15. The method of claim 14, wherein the self-refresh exit operation includes a self-refresh entry (SRE) command and a self-refresh exit (SRX) command.

20. 20. The method of claim 19, wherein the initial operation of the SRX comprises a no operation (NOP) command.

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