Integration of semiconductor backside transistors with backside power distribution networks

Abstract

The semiconductor structure comprises a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level. The wiring process interconnect level is located on a first side of the substrate process level. A backside power rail is embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. The at least one backside field effect transistor is formed at least in part on a first semiconductor layer disposed above a passive device region. A first side of the passive device region contacts the first semiconductor layer, and a second side of the passive device region opposite the first side contacts the wiring process interconnect level.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to powering active devices. [Background technology]

[0002] Modern integrated circuits (ICs) are made up of transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from one another but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnects, such as metal lines (wires), and vertical interconnects, such as vias and contacts. Power is provided to an integrated circuit through power rails in the metal layers of the integrated circuit. For example, the bottom metal layer (M0 or M1) may include multiple metal lines, such as a VDD power rail and a VSS power rail.

[0003] As IC sizes continue to shrink, backside power rails (BPRs), i.e., power rails formed on the backside of the wafer, typically under the transistor "fins," and backside power distribution ("backside" being under the transistor substrate), have been proposed to alleviate design challenges and enable technology scaling beyond the 5-nm technology node. BPR technology could free up resources for high-density logic connections that limit modern processor performance, enable further scaling of standard logic cells by eliminating overhead in the area occupied by power rails, and enable thicker, low-resistance power rails that enable lower voltage (IR) drops. Existing techniques in semiconductor fabrication are generally adequate for their intended purposes, but are not entirely sufficient in all respects. One particular area of ​​interest involves integrating backside transistors and backside power distribution networks (BSPDNs). Summary of the Invention

[0004] According to an embodiment of the present disclosure, a semiconductor structure includes a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level, the wiring process interconnect level comprising: a substrate process level located on a first side of the substrate process level; a backside power rail embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level, the backside power rail being electrically connected to at least one field effect transistor of the plurality of field effect transistors; and at least one backside field effect transistor on a first semiconductor layer disposed at least partially over a passive device region, the first side of the passive device region contacting the first semiconductor layer and the second side of the passive device region opposite the first side contacting the wiring process interconnect level.

[0005] According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level, the wiring process interconnect level being located on a first side of the substrate process level; forming a backside power rail embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level, the backside power rail being electrically connected to at least one field effect transistor of the plurality of field effect transistors; and forming at least one backside field effect transistor on a first semiconductor layer at least partially disposed above a passive device region, the first side of the passive device region contacting the first semiconductor layer and the second side of the passive device region opposite the first side contacting the wiring process interconnect level. [Brief explanation of the drawings]

[0006] The following detailed description is provided by way of example, and is not intended to be limiting of the invention only, and is best understood in conjunction with the accompanying drawings, in which:

[0007] [Figure 1] 1A-1C are top views of a semiconductor structure at intermediate stages during a semiconductor manufacturing process, illustrating different cross-sectional views used to explain embodiments of the present disclosure.

[0008] [Figure 2] 2 is a cross-sectional view of the semiconductor structure taken along Y1-Y1 shown in FIG. 1 after forming a nanosheet stack according to an embodiment of the present disclosure.

[0009] [Figure 3] FIG. 2 is a cross-sectional view of the semiconductor structure taken along Y1-Y1 shown in FIG. 1 after forming a hard mask layer and patterning the nanosheet stack to form a plurality of nanosheet fins according to an embodiment of the present disclosure.

[0010] [Figure 4] 2 is a cross-sectional view of the semiconductor structure taken along Y1-Y1 shown in FIG. 1 after forming shallow trench isolation regions and removing a hard mask layer according to an embodiment of the present disclosure.

[0011] [Figure 5A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after completing substrate processing steps in accordance with an embodiment of the present disclosure.

[0012] [Figure 5B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0013] [Figure 6A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after a replacement metal gate process according to an embodiment of the present disclosure.

[0014] [Figure 6B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0015] [Figure 7A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after mid-stage contact patterning and metallization according to an embodiment of the present disclosure.

[0016] [Figure 7B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0017] [Figure 7C] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after mid-stage contact patterning and metallization according to an alternative embodiment of the present disclosure.

[0018] [Figure 7D] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an alternative embodiment of the present disclosure.

[0019] [Figure 8A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a wiring process interconnect level and a carrier wafer according to an embodiment of the present disclosure.

[0020] [Figure 8B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0021] [Figure 8C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0022] [Figure 9A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after wafer flipping in accordance with an embodiment of the present disclosure.

[0023] [Figure 9B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0024] [Figure 9C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0025] [Figure 10A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after substrate removal according to an embodiment of the present disclosure.

[0026] [Figure 10B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0027] [Figure 10C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0028] [Figure 11A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a mask layer over the passive device region and removing the first sacrificial layer in accordance with an embodiment of the present disclosure.

[0029] [Figure 11B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0030] [Figure 11C]FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0031] [Figure 12A] FIG. 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after removing the remaining Si-containing areas according to an embodiment of the present disclosure.

[0032] [Figure 12B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0033] [Figure 12C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0034] [Figure 13A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a first backside interlayer dielectric according to an embodiment of the present disclosure.

[0035] [Figure 13B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0036] [Figure 13C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0037] [Figure 14A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a backside transistor device according to an embodiment of the present disclosure.

[0038] [Figure 14B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0039] [Figure 14C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0040] [Figure 15A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a backside power rail and a backside metal contact according to an embodiment of the present disclosure.

[0041] [Figure 15B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0042] [Figure 15C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0043] [Figure 16A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a backside power distribution network and a backside interconnect according to an embodiment of the present disclosure.

[0044] [Figure 16B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an embodiment of the present disclosure.

[0045] [Figure 16C] FIG. 2 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an embodiment of the present disclosure.

[0046] [Figure 17A] 2 is a cross-sectional view of the semiconductor structure taken along Y2-Y2 shown in FIG. 1 after forming a backside power distribution network and a backside interconnect according to an alternative embodiment of the present disclosure.

[0047] [Figure 17B] 2 is a cross-sectional view of a semiconductor structure taken along XX shown in FIG. 1 according to an alternative embodiment of the present disclosure.

[0048] [Figure 17C] FIG. 10 is a cross-sectional view of a semiconductor structure taken along a passive device region according to an alternative embodiment of the present disclosure.

[0049] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements. DETAILED DESCRIPTION OF THE INVENTION

[0050] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0051] For purposes of the remainder of this specification, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and variations thereof, refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above," "over," "top of," "on," "positioned on," or "positioned on top of" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layers at the interface of the two elements.

[0052] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations that are known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations that are known in the art may not be described at all. It should be understood that the following description will instead focus on distinctive features or elements of various embodiments of the present invention.

[0053] Although the disclosed embodiments include a detailed description of an exemplary nanosheet FET architecture having silicon and silicon germanium nanosheets, it should be understood that implementation of the teachings recited herein is not limited to the particular FET architecture described herein. Rather, embodiments of the present invention can be implemented in conjunction with any other type of FET device now known or later developed.

[0054] In current semiconductor fabrication technology, both backside transistors and backside power connections are formed on silicon (Si), which can negatively impact device scaling for logic devices due to the need for additional dielectric spacers to form TSVs that are effectively isolated from the Si layer, as well as forming interconnects for backside power distribution with larger sizes and pitches.

[0055] Accordingly, embodiments of the present disclosure provide a semiconductor structure and method for fabricating the same in which the formation of backside transistors and a backside power distribution network (BPDN) are integrated to improve device scaling. The backside transistors and backside power rail are formed by backside processes performed after BEOL processes and wafer flipping are completed. In proposed embodiments, the remaining silicon layer located above the passive device region on the backside of the wafer allows for the formation of backside transistors at substantially the same level as the backside power rail. According to proposed embodiments, only dielectric material is present below the logic device region (i.e., no Si remains), thereby enabling the formation of a via-to-backside power rail (VBPR) contacting the active region with very small CDs for improved logic scaling. More specifically, the proposed semiconductor structure includes, among other elements or features, at least a via-to-backside power rail contact electrically connecting the FEOL devices to the backside power rail and at least one backside transistor formed on a monocrystalline silicon layer located above the passive device region. However, direct backside contact to the source / drain epi regions (i.e., without VBPR) is also contemplated within the scope of the present invention.

[0056] Embodiments in which a semiconductor structure having a backside transistor integrated with a BSPDN may be formed are described in detail below by reference to the accompanying drawings in FIGS. 1-16C.

[0057] Referring now to FIG. 1 , a top view of a semiconductor structure 100 at an intermediate stage during a semiconductor fabrication process is shown, in accordance with an embodiment of the present disclosure. In particular, FIG. 1 shows different cross-sectional views of the semiconductor structure 100 that will be used to explain embodiments of the present disclosure. The cross-sectional views are taken along lines XX, Y1-Y1, and Y2-Y2. As shown, line XX represents a cut along the nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1 represents a cut through the source / drain regions in the NFET region 12 and PFET region 16 of the semiconductor structure 100, and line Y2-Y2 represents a cut along the gate structure or gate region 24 of the semiconductor structure 100.

[0058] In this embodiment, the cross-sectional view taken along line Y1-Y1 also includes a view of the NFET region 12 and / or the PFET region 16, and the area between the NFET and PFET regions 12, 16 (NP boundary) 14.

[0059] 2, there is shown a cross-sectional view of the semiconductor structure 100 after forming the nanosheet stack 10 according to an embodiment of the present disclosure. In this embodiment, FIG. 2 is a cross-sectional view of the semiconductor structure 100 taken along Y1-Y1 as shown in FIG.

[0060] In the illustrated example, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 located on the substrate 102, and a first semiconductor layer 106 disposed on the first sacrificial layer 104. According to an embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked on top of each other in a direction perpendicular to the substrate 102, as illustrated in the figure.

[0061] The substrate 102 may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide or indium gallium phosphide. Typically, but not by way of limitation, the substrate 102 may be about several hundred microns thick. In other embodiments, the substrate 102 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates the base substrate from an upper semiconductor layer.

[0062] With continued reference to FIG. 2 , according to embodiments, the first sacrificial layer 104 may be formed on the substrate 102 using an epitaxial growth process. For example, in the illustrated embodiment, the first sacrificial layer 104 is formed by epitaxially growing a layer of SiGe with a germanium concentration ranging from about 15 atomic percent to about 35 atomic percent. In some embodiments, the first sacrificial layer 104 may be fabricated by epitaxially growing SiGe with a germanium concentration of about 30 atomic percent. In one or more embodiments, the first sacrificial layer 104 may act as an etch stop layer during subsequent substrate removal. Similarly, the first semiconductor layer 106 is formed by epitaxially growing a Si layer to a thickness ranging from about 30 nm to about 250 nm, although other thicknesses are within the contemplated scope of the invention. In some embodiments, the first sacrificial layer 104 may include SiO 2 . In such an embodiment, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 may be an SOI wafer, and the first sacrificial layer 104 may be a buried oxide (BOX) having a thickness ranging from about 20 nm to about 100 nm, including ranges therebetween.

[0063] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as "epitaxial growth and / or deposition" and "epitaxial formation and / or grown" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the growing semiconductor material has the same or substantially similar crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface and orient themselves to the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystalline surface will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to form on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0064] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to crystalline defects and film cracking.

[0065] Several different precursors may be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas source for deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Combinations of such gas sources may be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, helium, and argon may be used.

[0066] In the illustrated embodiment, an alternating sequence of layers of sacrificial semiconductor material and layers of semiconducting channel material vertically stacked on top of each other in a direction perpendicular to the substrate 102 forms the illustrated nanosheet stack 10. Specifically, the alternating sequence includes a first sacrificial semiconductor layer 110 and a semiconducting channel layer 112 on the first sacrificial semiconductor layer 110. In the illustrated example, the alternating first sacrificial semiconductor layers 110 and semiconducting channel layers 112 are formed in the (nanosheet) stack 10 on the first semiconductor layer 106. As used herein, the term sacrificial refers to a layer or other structure that is removed (or has portions thereof removed) prior to completion of the final device.

[0067] For example, in the illustrated example, a portion of the first sacrificial semiconductor layer 110 is removed from the stack in the channel region of the device, allowing the semiconducting channel layer 112 to be released from the nanosheet stack 10. In this example, the first sacrificial semiconductor layer 110 and the semiconducting channel layer 112 are made of silicon germanium (SiGe) and silicon (Si), respectively, although it should be noted that any combination of sacrificial and channel materials may be utilized in accordance with the present technique. For example, a selective etching technique may instead be utilized that allows Si to be used as the sacrificial material between the SiGe channel layers.

[0068] Generally, the layers (e.g., SiGe and Si layers) in the nanosheet stack 10 can be formed by epitaxial growth by using the first semiconductor layer 106 as a seed layer. For example, the first sacrificial semiconductor layer 110 is formed by epitaxially growing a layer of SiGe. In this embodiment, the germanium concentration of the first sacrificial semiconductor layer 110 can range from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, each of the first sacrificial semiconductor layers 110 includes a layer of SiGe with a germanium concentration of about 30 atomic percent.

[0069] To continue the construction of the nanosheet stack 10, the semiconductor channel layer 112 is formed by epitaxially growing a Si layer. As shown, the first sacrificial semiconductor layer 110 and the semiconductor channel layer 112 have substantially similar or identical thicknesses. The nanosheet stack 10 is grown by alternately forming the (SiGe) sacrificial semiconductor layer 110 and the (Si) semiconductor channel layer 112 on the first semiconductor layer 106. Thus, each of the first sacrificial semiconductor layer 110 and the semiconductor channel layer 112 in the nanosheet stack 10 can be formed in the same manner as described above, e.g., using an epitaxial growth process, to a thickness ranging from about 6 nm to about 12 nm, although other thicknesses are within the contemplated scope of the invention.

[0070] Thus, each of the layers in the nanosheet stack 10 has nanoscale dimensions and may therefore also be referred to as a nanosheet. Furthermore, as emphasized above, the (Si) semiconducting channel layer 112 in the nanosheet stack 10 is used to form the channel layer of the device. As a result, the dimensions of the semiconducting channel layer 112 determine the dimensions of the channel region of the semiconductor structure 100.

[0071] As emphasized above, the goal is to create a stack of alternating (sacrificial and channel) SiGe and Si layers on a wafer. The number of layers in the stack can be adjusted depending on the particular application. Thus, the configurations shown and described herein are merely examples intended to illustrate the present technique. For example, the present nanosheet stack 10 can include more or fewer layers than those shown in the figures.

[0072] The nanosheet stack 10 can be used to create a gate across a device comprising vertically stacked nanosheets of semiconducting channel material for a positive channel field effect transistor (hereinafter "PFET") or negative channel field effect transistor (hereinafter "NFET") device.

[0073] 3 and 4, cross-sectional views of the semiconductor structure 100 are shown after forming a hard mask layer 202, patterning the nanosheet stack 10 to form a plurality of nanosheet fins (hereinafter "nanosheet fins") 302, and forming shallow trench isolation (STI) regions 310, according to embodiments of the present disclosure. In these embodiments, FIGS. 3 and 4 are cross-sectional views of the semiconductor structure 100 taken along Y1-Y1 as shown in FIG.

[0074] In this embodiment, the hard mask layer 202 may be formed on the nanosheet stack 10 by depositing a hard mask material (e.g., silicon nitride) using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 202 may be formed to have a thickness ranging from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm may also be used.

[0075] After depositing the hard mask layer 202, photolithographic patterning is then performed on the deposited hard mask layer 202 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) may be used to etch the nanosheet stack 10 to form the nanosheet fins 302. The etching process may continue until portions of the first semiconductor layer 106 located between adjacent nanosheet fins 302 are removed to form a plurality of trenches (not shown) that may expose the first sacrificial layer 104. The plurality of trenches (not shown) formed during the photolithographic patterning process are then filled with an insulating material to form shallow trench isolation (STI) regions 310 shown in FIG. 4.

[0076] The process for forming the STI regions 310 is standard and well-known in the art and typically involves depositing an insulating material to substantially fill multiple trenches (not shown) formed after removing portions of the first semiconductor layer 106 located between adjacent nano-sheet fins 302. According to an embodiment, the STI regions 310 electrically isolate the nano-sheet fins 302. The STI regions 310 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the STI regions 310 include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. After forming the STI regions 310, the hard mask layer 202 may be removed from the semiconductor structure 100 using any suitable etching technique.

[0077] 5A-5B and 6A-6B simultaneously, cross-sectional views of semiconductor structure 100 are shown after completing substrate end of line (FEOL) processing steps, according to embodiments of the present disclosure. In these embodiments, FIGS. 5A and 6A are cross-sectional views of semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIGS. 5B and 6B are cross-sectional views of semiconductor structure 100 taken along line XX shown in FIG. 1.

[0078] Known semiconductor manufacturing operations were used to form the semiconductor structure 100 shown in Figures 5A-5B and 6A-6B. Accordingly, conventional techniques related to semiconductor device and integrated circuit (IC) manufacturing may or may not be described in detail herein. Furthermore, various tasks and processing steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein. In particular, because the various steps in the manufacturing of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely without providing well-known process details.

[0079] Generally, at this stage of the fabrication process, a replacement gate 910, gate spacers 610, inner spacers 720, first source / drain regions 902, second source / drain regions 904, and an interlayer dielectric (ILD) layer 906 are formed in the semiconductor structure 100. This may be done by first forming a dummy gate 410 as shown in FIG. 5B using conventional deposition, lithography, and etching processes, followed by the formation of the gate spacers 610 and nanosheet stack recesses in the source / drain regions. Then, outer portions of each of the first sacrificial semiconductor layers 110 (FIG. 5B) may be removed using methods known in the art. Inner spacers 720 may be formed within cavities (not shown) in the first sacrificial semiconductor layer 110. As shown in FIG. 5B, the outer vertical surfaces of the inner spacers 720 may be vertically aligned with the semiconductor channel layer 112. The inner spacers 720 may be formed, for example, by conformal deposition of an inner spacer material that forms a recess in the first sacrificial semiconductor layer 110 and pinches off a recessed cavity (not shown) that is formed after a subsequent isotropic etching process. The inner spacers 720 may include any suitable dielectric material, such as silicon dioxide or silicon nitride, and may include a single layer or multiple layers of dielectric material.

[0080] After forming the inner spacers 720, a first source / drain region 902 may be formed in the PFET region of the semiconductor structure 100. Similarly, a second source / drain region 904 may be formed in the NFET region of the semiconductor structure 100, as shown. The first and second source / drain regions 902, 904 may be formed on the exposed ends of the semiconductor channel layer 112 using an epitaxial layer growth process.

[0081] According to an embodiment, first and second source / drain regions 902, 904 may be formed on opposite sides of the nanosheet fin 302 in direct contact with the ends of the semiconducting channel layer 112 and the inner spacer 720. For example, FIG. 5B shows a first source / drain region 902 formed on opposite sides of the nanosheet fin 302 located over the NFET region of the semiconductor structure 100. Typically, after forming the first and second source / drain regions 902, 904, an interlayer dielectric layer 906 may be formed to fill voids in the semiconductor structure 100. The interlayer dielectric layer 906 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the interlayer dielectric layer 906 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0082] As known to those skilled in the art, after deposition of the interlevel dielectric layer 906, a planarization process (e.g., CMP) may be performed on the semiconductor structure 100. This process may expose the top surface of the dummy gate 410 in preparation for a replacement metal gate process. In a gate-last fabrication process, the removed dummy gate 410 is then replaced with a high-k metal gate structure known in the art, i.e., replacement gate 910 (shown in FIG. 6B). According to embodiments, the first sacrificial semiconductor layer 110 (FIGS. 5A-5B) may now be removed from the semiconductor structure 100 using known etching processes, for example, including RIE, wet etching, or dry gas (HCl). Removal of the sacrificial semiconductor layer 110 (FIGS. 5A-5B) forms cavities (not shown) between the inner spacers 720, which are then filled with a corresponding gate dielectric and work function metal to form the high-k metal gate structure or replacement gate 910, as shown in FIG. 6B.

[0083] The replacement gate 910 includes a gate dielectric, such as hafnium oxide (HfO), zirconium dioxide (ZrO), hafnium aluminum oxide (HfAlOx), or hafnium lanthanum oxide (HfLaOx), and one or more work function metals, including, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and conductive metals, such as aluminum (Al), tungsten (W), or cobalt (Co). As can be seen in FIG. 9B , the replacement gate 910 surrounds the (stacked) semiconductor channel layer 112. Additionally, in other embodiments, a gate cap (not shown) can be formed on the replacement gate 910.

[0084] After formation of the replacement gate 910, chemical mechanical polishing (CMP) may be performed to remove excess material and polish the top surface of the semiconductor structure 100.

[0085] 7A-7B, cross-sectional views of a semiconductor structure 100 after mid-line (MOL) contact patterning and metallization are shown, according to an embodiment of the present disclosure. In this embodiment, FIG. 7A is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIG. 7B is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1.

[0086] As illustrated in the figure, a plurality of conductive structures, including metal contacts 1002, are formed in the semiconductor structure 100 to electrically connect the FEOL devices to subsequently formed metal levels. The process for forming the metal contacts is standard and well known in the art. Typically, the process involves forming trenches (not shown) in the interlevel dielectric layer 906 and then filling the trenches with a conductive material or combination of conductive materials to form the metal contacts 1002. In one or more embodiments, the conductive material filling the metal contacts 1002 may include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal adhesion liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0087] The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove any conductive material from the top surface of the semiconductor structure 100. In the example shown, the metal contacts 1002 include source / drain contacts that extend to the top surface of each of the first and second source / drain regions 902, 904, and a gate contact with the replacement gate 910.

[0088] In addition to the metal contacts 1002, a via-backside power rail (VBPR) 1010 may also be formed in the semiconductor structure 100. The VBPR 1010 may electrically connect the semiconductor structure 100 to a subsequently formed backside power rail (BPR), as described in detail below. The VBPR 1010 may be formed using similar conductive materials and similar processing techniques as those used to form the metal contacts 1002. According to an embodiment, the VBPR 1010 may be formed between adjacent first source / drain regions 902 (P2P space) and between adjacent second source / drain regions 904 (N2N space). More specifically, the VBPR 1010 may be formed adjacent to and in electrical contact with at least one metal contact 1002, as shown in FIG. 7A . In the illustrated embodiment, the VBPR 1010 extends widely from the top surface of the at least one metal contact 1002 to the top surface of the first sacrificial layer 104 (or the bottom surface of the STI region 310).

[0089] 7C-7D, only metal contacts 1002 are formed in the semiconductor structure 100 to electrically connect the substrate process devices to a subsequently formed device level (e.g., an interconnect process level). As can be seen, in such embodiments, no VBPR 1010 is formed in the semiconductor structure 100.

[0090] 8A-8C, cross-sectional views of semiconductor structure 100 are shown after forming back-end of line (BEOL) interconnect level 1110 and carrier wafer 1112, according to an embodiment of the present disclosure. In this embodiment, FIG. 8A is a cross-sectional view of semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIG. 8B is a cross-sectional view of semiconductor structure 100 taken along line XX shown in FIG. 1. It should be noted that in this embodiment, FIG. 8C is a cross-sectional view of semiconductor structure 100 taken along passive device region 100B of semiconductor structure 100, while the cross-sectional views shown in FIGS. 8A and 8B are taken along logic (or active) device region 100A.

[0091] In this embodiment, the BEOL interconnect level 1110 is formed above the FEOL device level 30 in the logic device region 100A and above the passive devices 1030 in the passive device region 100B of the semiconductor structure 100. Note that for ease of illustration, and not by way of limitation, the passive devices 1030 are shown simply in FIG. 8C . It will be appreciated that the passive devices 1030 may include multiple electrical components that do not require a backside power supply. Non-limiting examples of the passive devices 1030 in the passive device region 100B may include capacitors, resistors, and the like.

[0092] Although not shown in the figures, the BEOL interconnect levels 1110 typically include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections, as would be known by one of ordinary skill in the art. As mentioned above, the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely, without providing well-known process details.

[0093] According to an embodiment, after forming the BEOL interconnect level 1110, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to a carrier wafer (or support substrate) 1112. The carrier wafer 1112 may act as a stiffening substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 1112 may be accomplished by conventional wafer bonding processes, such as dielectric-dielectric bonding or Cu-Cu bonding.

[0094] Thus, the carrier wafer 1112 may comprise a silicon oxide layer or a SiCN layer, or any other layer applicable in direct bonding techniques applied in prior art packaging techniques. Bonding of the device wafer to the carrier wafer 1112 occurs by such known direct bonding techniques, thus obtaining the assembly shown in Figures 9A-9C after the wafer has been flipped.

[0095] 9A-9C and 10A-10C simultaneously, cross-sectional views of semiconductor structure 100 are shown after wafer flipping and removal of substrate 102, according to embodiments of the present disclosure. In these embodiments, Figures 9A and 10A are cross-sectional views of semiconductor structure 100 taken along line Y2-Y2 shown in Figure 1, while Figures 9B and 10B are cross-sectional views of semiconductor structure 100 taken along line XX shown in Figure 1. Additionally, in this embodiment, Figures 9C and 10C are cross-sectional views of semiconductor structure 100 taken along passive device region 100B of semiconductor structure 100, as described above.

[0096] In the illustrated embodiment, after the wafer is flipped, the substrate 102 is removed using a selective etching process, including conventional grinding, CMP, and wet or dry etching techniques. According to an embodiment, the grinding process is performed until the substrate 102 is substantially removed from the semiconductor structure 100, leaving only a few microns of Si. An optional CMP process may then be further used to reduce thickness variations, and finally, a highly selective Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the illustrated embodiment, the first sacrificial layer 104 acts as an etch stop during the highly selective Si removal process, preventing excessive Si etching that could damage the replacement gate 910 and the first and second source / drain regions 902, 904.

[0097] 11A-11C, 12A-12C, and 13A-13C simultaneously, cross-sectional views of the semiconductor structure 100 after forming a mask layer 1510 over the passive device region 100B, removing the first sacrificial layer 104 and the remaining Si-containing areas, i.e., the first semiconductor layer 106, and forming a first backside interlayer dielectric (BILD) 1402 are shown in accordance with embodiments of the present disclosure. In these embodiments, FIGS. 11A, 12A, and 13A are cross-sectional views of the semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIGS. 11B, 12B, and 13B are cross-sectional views of the semiconductor structure 100 taken along line XX shown in FIG. 1. Furthermore, in the present embodiment, FIGS. 11C, 12C, and 13C are cross-sectional views of the semiconductor structure 100 taken along the passive device region 100B of the semiconductor structure 100, as described above.

[0098] In the illustrated embodiment, prior to removal of the first sacrificial layer 104, a mask layer 1510 (such as an organic planarization layer (OPL)) may be formed on the passive device region 100B of the semiconductor structure 100 by conventional lithography and etching processes, as shown in FIG. 11C . The mask layer 1510 may be made of any organic planarization material that can effectively prevent damage to underlying layers during subsequent etching processes. The mask layer 1510 may include, but is not necessarily limited to, an organic polymer containing C, H, and N. In an embodiment, the organic planarization material may be free of silicon (Si). In another embodiment, the organic planarization material may be free of Si and fluorine (F). As defined herein, a material is free of atoms when the level of atoms in the material is at or below trace levels detectable by analytical methods available in the art. Non-limiting examples of organic planarization materials for forming mask layer 1510 may include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials. Mask layer 1510 may be deposited by, for example, spin coating.

[0099] 11C, the semiconductor structure 100 may be subjected to a lithography process followed by an etching process to etch the mask layer 1510. In some embodiments, the etching of the mask layer 1510 may be performed by, for example, OPL RIE with trace point detection. In one or more embodiments, as shown in FIGS. 12A-12C, the mask layer 1510 may protect the passive device region 100B during subsequent removal of the first sacrificial layer 104 and the first semiconductor layer 106 from selected areas of the logic device region 100A and the passive device region 100B.

[0100] According to an embodiment, any suitable etching technique may be used to remove first sacrificial layer 104 from logic device region 100A. More specifically, any suitable etching technique may be performed on semiconductor structure 100 to remove first sacrificial layer 104 from areas of semiconductor structure 100 that are not covered by mask layer 1510. In embodiments in which first sacrificial layer 104 is made of SiGe, a hot SC1 or dry HCl etch may be used to remove first sacrificial layer 104. In embodiments in which first sacrificial layer 104 is made of SiO2, a DHF wet clean may be used to remove first sacrificial layer 104.

[0101] After removing first sacrificial layer 104, a process similar to that described in Figures 10A-10C for removing substrate 102 may be performed to remove first semiconductor layer 106 from logic device region 100A and from areas of passive device region 100B not covered by mask layer 1510. As shown in Figures 12A-12C, removing first semiconductor layer 106 from logic device region 100A and passive device region 100B forms first opening 1520 in semiconductor structure 100. First opening 1520 may expose top surfaces of first and second source / drain regions 902, 904 in logic device region 100A and outer portions of passive device 1030 in logic device region 100B. Note that first opening 1520 may also expose the top surface and sidewalls of VBPR 1010 opposite STI region 310 (shown in FIG. 12A ) and the top surface of replacement gate 910 (shown in FIG. 12B ). At this point in the fabrication process, any suitable etching technique (e.g., ashing) may be utilized to remove mask layer 1510.

[0102] 13A-13C, a first BILD 1402 may then be formed in the first opening 1520 using standard methods and materials, such as those used to form the interlevel dielectric layer 906. In exemplary embodiments, the thickness of the first BILD 1402 may vary from about 40 nm to about 300 nm and ranges therebetween. In one or more embodiments, after the formation of the first BILD 1402, a planarization process (e.g., CMP) may be performed on the semiconductor structure 100.

[0103] It should be noted that during the planarization process performed on the first BILD 1402, remaining portions of the first sacrificial layer 104 ( FIG. 12C ) are removed from the passive device region 100B of the semiconductor structure 100. It should also be noted that, as shown in FIG. 13C , after removing the mask layer 1510 and the first sacrificial layer 104 from the passive device region 100B, a portion of the first semiconductor layer 106 (previously protected by the mask layer 1510) remains on the back side of the semiconductor structure 100. This remaining portion of the first semiconductor layer 106 (i.e., the Si-containing layer) may enable the formation of one or more field effect transistor devices on the back side of the semiconductor structure 100.

[0104] 14A-14C, cross-sectional views of the semiconductor structure 100 after forming a backside transistor device 1410 are shown in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 14A is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIG. 14B is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. In this embodiment, FIG. 14C is a cross-sectional view of the semiconductor structure 100 taken along the passive device region 100B of the semiconductor structure 100, while the cross-sectional views shown in FIG. 14A and FIG. 14B are taken along the logic device region 100A.

[0105] Known semiconductor fabrication operations were used to form the backside transistor device 1410 as shown in Figure 14C. Accordingly, to avoid unnecessarily obscuring the presented embodiments, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication will not be described in detail herein. As shown in Figure 14C, the backside transistor device 1410 includes backside source / drain regions 1420 adjacent to a backside metal gate 1512. The backside metal gate 1512 is disposed on a gate dielectric 1514, and backside sidewall spacers 1430 are disposed along opposite sidewalls of the backside metal gate 1512 and the gate dielectric 1514.

[0106] In some embodiments, the initial thickness of the first semiconductor layer 106 can be substantially greater than that described above with reference to Figure 2 (i.e., the starting wafer). For example, in such embodiments, the initial thickness of the first semiconductor layer 106 can vary between about 100 nm and about 300 nm. A thicker first semiconductor layer 106 can enable the formation of raised backside source / drain regions 1420 (not shown) for the backside transistor device 1410.

[0107] 15A-15C, cross-sectional views of the semiconductor structure 100 after forming a backside power rail (BPR) 1710 and a backside metal contact 1712 are shown, according to an embodiment of the present disclosure. In this embodiment, FIG. 15A is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIG. 15B is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. In this embodiment, FIG. 15C is a cross-sectional view of the semiconductor structure 100 taken along the passive device region 100B of the semiconductor structure 100, while the cross-sectional views shown in FIGS. 15A and 15B are taken along the logic device region 100A.

[0108] In this embodiment, the BPR 1710 and back metal contact 1712 are formed in a second backside ILD layer that is formed in a similar manner and is composed of similar materials as the first BILD 1402. Therefore, for ease of illustration, this second backside ILD layer will continue to be referred to as the first BILD 1402.

[0109] 15A-15C, the process of forming the VBPR 1710 includes patterning a backside power rail trench (not shown) in the first BILD 1402, for example, by conventional lithography and reactive ion etching. In the example shown, the backside power rail trench (not shown) is etched until it reaches the top surface of the VBPR 1010, as shown in FIG. 15A. In some embodiments, the aspect ratio of the backside power rail trench (not shown) can be about 0.5 to 5.0.

[0110] To form BPR 1710 in logic device region 100A of semiconductor structure 100, backside power rail trenches (not shown) can be filled with a conductive metal. The choice of backside power rail metallization depends on where the rails are formed and metallized in the integration flow. In the illustrated embodiment, BPR 1710 is formed on the backside of semiconductor structure 100. In such a case, BPR 1710 can be formed, for example, by depositing a layer of ruthenium (Ru) or Cu. In other embodiments, the conductive metal forming BPR 1710 can include Co, W, Al, and the like. According to an embodiment, BPR 1710 is electrically connected to one or more (source / drain) metal contacts 1002 through VBPR 1010 to provide power to devices (e.g., field effect transistors) in FEOL level portion 30 (FIGS. 8A-8C).

[0111] More specifically, in a PFET architecture, the BPR 1710 may include a VDD rail integrated into the PFET region of the semiconductor structure 100, while in an NFET architecture, the BPR 1710 may include a VSS rail integrated into the NFET region of the semiconductor structure 100. Thus, in the illustrated embodiment, the BPR 1710 (VSS rail) is electrically connected to the first source / drain region 902 through the VBPR 1010 (located between adjacent first source / drain regions 902) and at least one (source / drain) metal contact 1002. Similarly, the BPR 1710 (VDD rail) is electrically connected to the second source / drain region 904 through the VBPR 1010 (located between adjacent second source / drain regions 904) and at least another (source / drain) metal contact 1002.

[0112] 15A-15C, a back metal contact 1712 may be formed in the passive device region 100B of the semiconductor structure 100 using well-known techniques. For example, the back metal contact 1712 may be formed using processing steps similar to those used to form the metal contact 1002, described above with reference to FIGS. 7A-7B. In some embodiments, the back metal contact 1712 and the BPR 1710 may be metallized simultaneously and may comprise the same metal as that forming the metal contact 1002.

[0113] It should be noted that in the semiconductor structure 100, the backside transistor device 1410 is formed at substantially the same level as the BPR 1710. More specifically, in the proposed embodiment, the top surface of the backside transistor device 1410 is located at the same level as the region located between the bottom surface of the BPR 1710 and the top surface of the BPR 1710.

[0114] 16A-16C, cross-sectional views of the semiconductor structure 100 are shown after forming a backside power delivery network (PDN) 1720 and backside interconnects 1722, according to an embodiment of the present disclosure. In this embodiment, FIG. 16A is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2 shown in FIG. 1, while FIG. 16B is a cross-sectional view of the semiconductor structure 100 taken along line XX shown in FIG. 1. In this embodiment, FIG. 16C is a cross-sectional view of the semiconductor structure 100 taken along the passive device region 100B of the semiconductor structure 100, while the cross-sectional views shown in FIGS. 16A and 16B are taken along the logic device region 100A.

[0115] In this embodiment, PDN 1720 and backside interconnect 1722 are formed in a third backside ILD layer that is formed in a similar manner and is composed of similar materials as first BILD 1402. Accordingly, for ease of illustration, this third backside ILD layer will continue to be referred to as first BILD 1402.

[0116] The structure of the PDN 1720 can be fabricated according to known techniques. Depending on the exact function of the transistor arrangement, multiple first and second source / drain regions 902, 904 can be connected to the backside power supply and ground via the VBPR 1010. As mentioned above, the VBPR 1010 is a metal area located between the first source / drain regions 902 (N2N space) and the second source / drain regions 904 (P2P space), i.e., between source / drain regions of like polarity. As shown in FIG. 16A , the VBPR 1010 contacts the bottom surface of the BPR 1710 and is embedded within the intermediate STI regions 310 (located between regions of the same polarity) and the interlayer dielectric layer 906 (known as a pre-metal dielectric, i.e., a layer known in the art on top of which BEOL layers are built).

[0117] In the passive device region, the remaining Si substrate is maintained to facilitate backside transistor formation on single crystal Si.

[0118] It should be noted that the BEOL interconnect level 1110 in the semiconductor structure 100 fabricated in accordance with the disclosed technology is isolated from the PDN 1720, thereby increasing routing resources in the semiconductor structure 100 for signal wiring at the BEOL level.

[0119] Similar to the PDN 1720, the backside interconnect 1722 may be made according to known techniques. As known by those skilled in the art, depending on the function of the transistor arrangement, substrate vias, or simply vias 1714, may be formed in the first BILD 1402 to electrically connect the PDN 1720 to one or more BPRs 1710 and electrically connect one or more of the backside metal contacts 1712 to the backside interconnect 1722. It should be noted that the process of forming the vias 1714 is standard and well known in the art.

[0120] 7C-7D in which a VBPR 1010 is not formed in the semiconductor structure 100, backside metal contacts 1820 to the first source / drain region 902 and the second source / drain region 904 may be formed in the first BILD 1402 to electrically connect the FEOL device to the BPR 1710, as shown in Figures 17A-17C. Thus, instead of using a VBPR 1010 to connect the first and second source / drain regions 902, 904 to the BPR 1710, in this alternative embodiment, a direct backside contact (BSCA) is used to connect the first and second source / drain regions 902, 904 to the BPR 1710.

[0121] In all cases, all residual Si substrate is removed from the logic device region 100A, eliminating the need to form dielectric spacers to separate the VBPR or BSCA from the remaining Si substrate, thereby facilitating formation of the VBPR or BSCA. The residual Si substrate is retained in the passive device region 100B to facilitate backside transistor formation on single crystal Si.

[0122]

[0010] Accordingly, the previously described embodiments provide a method for forming a semiconductor structure having backside transistors integrated with a backside power distribution network that can improve device scaling, the method comprising: forming a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level, the wiring process interconnect level being located on a first side of the substrate process level, forming a backside power rail embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level, forming a via-backside power rail (or backside metal contact) embedded at least partially in the backside interlayer dielectric, the via-backside power rail adjacent to and electrically connected to at least one source / drain metal contact, extending from the at least one source / drain metal contact to a first surface of the backside power rail, and forming at least one backside field effect transistor on a first semiconductor layer disposed at least partially above a passive device region, the first side of the passive device region contacting the first semiconductor layer and the second side of the passive device region opposite the first side contacting the wiring process interconnect level.

[0123] According to an embodiment, at least one backside field effect transistor is at the same level as the backside power rail, and each of the plurality of field effect transistors includes a source / drain region, a first sidewall of the source / drain region contacting the interlayer dielectric layer, and a second sidewall of the source / drain region opposite the first sidewall contacting the via-backside power rail.

[0124] According to an embodiment, the method further comprises forming a plurality of shallow trench isolation regions located between adjacent field effect transistors, wherein the via-backside power rail is adjacent to at least one shallow trench isolation region located between two field effect transistors of like polarity.

[0125] According to an embodiment, forming at least one backside field effect transistor further includes depositing a mask layer over a portion of the first semiconductor layer located over the passive device region, selectively removing the first semiconductor layer from an active region including a plurality of field effect transistors and from areas of the passive device region not covered by the mask layer, and removing the mask layer to expose a top surface of the first semiconductor layer, wherein the first semiconductor layer comprises a monocrystalline silicon layer. The passive device region of the semiconductor structure includes a plurality of electrical components (e.g., capacitors and resistors) that do not require a backside power supply.

[0126] According to an embodiment, forming the at least one backside field effect transistor further includes forming backside source / drain regions on opposite sides of the metal gate structure disposed on the gate dielectric, and forming backside sidewall spacers disposed along the metal gate structure and the gate dielectric.

[0127] According to an embodiment, the method further comprises forming a power distribution network electrically connected to a backside power rail through substrate vias embedded in the backside interlayer dielectric, and forming a plurality of backside metal contacts electrically connecting the at least one backside field effect transistor to a plurality of interconnect structures through the substrate vias.

[0128] According to an embodiment, the method further comprises forming a carrier wafer in contact with a second surface of the wiring process interconnect level opposite the first surface of the wiring process interconnect level.

[0129] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be provided by the manufacturer in the form of a raw wafer (i.e., as a single wafer having multiple unpackaged chips), a bare die, or in a packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads that are secured to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are subsequently integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-cost applications to sophisticated computer products with displays, keyboards or other input devices, and central processors.

[0130] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprise" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances in which the event occurs as well as instances in which it does not occur.

[0131] Spatially relative terms such as "inside," "outside," "below," "belower," "lower side," "up," "upper," "top," "bottom," etc. may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures, for ease of description. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "below" other elements or features may then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. A device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0132] Approximate language, as used herein throughout the specification and claims, may be applied to modify any quantitative expression that may permissibly vary without resulting in a change in the basic function to which it relates. Thus, values ​​modified by terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some cases, approximation language may correspond to the precision of the instrument measuring the value. Here, and throughout the specification and claims, range limitations may be combined and / or interchanged, and such ranges are specified and include all subranges contained therein, unless the context or language indicates otherwise. "Approximately," as applied to a particular value in a range, applies to both values ​​and may indicate + / - 10% of the stated value, unless otherwise dependent on the precision of the instrument measuring the values.

[0133] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over art found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level, the wiring process interconnect level being located on a first side of the substrate process level; a backside power rail embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level, the backside power rail being electrically connected to at least one field effect transistor of the plurality of field effect transistors; and at least one backside field effect transistor on a first semiconductor layer disposed at least partially over a passive device region, a first side of the passive device region contacting the first semiconductor layer and a second side of the passive device region opposite the first side contacting the wiring process interconnect level; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1 further comprising: a via-backside power rail at least partially embedded in said backside interlayer dielectric, said via-backside power rail adjacent to and electrically connected to at least one source / drain metal contact and extending from said at least one source / drain metal contact to a first surface of said backside power rail.

3. 10. The semiconductor structure of claim 1 wherein said at least one backside field effect transistor is at the same level as said backside power rail.

4. 3. The semiconductor structure of claim 2, wherein each of said plurality of field effect transistors includes a source / drain region, a first sidewall of said source / drain region contacting an interlevel dielectric layer, and a second sidewall of said source / drain region opposite said first sidewall contacting said via-backside power rail.

5. 5. The semiconductor structure of claim 4 wherein said backside power rail is electrically connected to said at least one field effect transistor through a backside metal contact electrically connected to said source / drain regions.

6. 3. The semiconductor structure of claim 2, further comprising a plurality of shallow trench isolation regions located between adjacent field effect transistors, said via-backside power rail adjacent to at least one shallow trench isolation region located between two field effect transistors of like polarity.

7. 10. The semiconductor structure of claim 1 wherein said first semiconductor layer disposed at least partially overlying said passive device region comprises a monocrystalline silicon layer.

8. The at least one backside field effect transistor further comprises: a backside source / drain region opposite the gate structure disposed on the gate dielectric; and Backside sidewall spacers disposed along the gate structure and the gate dielectric 10. The semiconductor structure of claim 1 comprising:

9. 10. The semiconductor structure of claim 1 further comprising a power delivery network electrically connected to said backside power rail through substrate vias embedded in said backside interlayer dielectric.

10. 10. The semiconductor structure of claim 9 further comprising a plurality of backside metal contacts electrically connecting said at least one backside field effect transistor to a plurality of interconnect structures through said substrate vias.

11. 10. The semiconductor structure of claim 1 further comprising a carrier wafer contacting a second surface of said wiring process interconnect level opposite said first surface of said wiring process interconnect level.

12. 10. The semiconductor structure of claim 1, wherein said passive device region comprises a plurality of electrical components that do not require a backside power supply, including at least one of a capacitor and a resistor.

13. forming a substrate process level including a plurality of field effect transistors electrically connected to a wiring process interconnect level, the wiring process interconnect level being located on a first side of the substrate process level; forming a backside power rail embedded in a backside interlayer dielectric located on a second side of the substrate process level opposite the first side of the substrate process level, the backside power rail being electrically connected to at least one field effect transistor of the plurality of field effect transistors; and forming at least one backside field effect transistor on a first semiconductor layer disposed at least partially over a passive device region, a first side of the passive device region contacting the first semiconductor layer and a second side of the passive device region opposite the first side contacting the wiring interconnect level; 1. A method of forming a semiconductor structure comprising:

14. 14. The method of claim 13, further comprising forming a via-backside power rail embedded at least partially in the backside interlayer dielectric, the via-backside power rail adjacent to and electrically connected to at least one source / drain metal contact and extending from the at least one source / drain metal contact to a first surface of the backside power rail.

15. 14. The method of claim 13, wherein the at least one backside field effect transistor is at the same level as the backside power rail.

16. 15. The method of claim 14, wherein each of the plurality of field effect transistors includes a source / drain region, a first sidewall of the source / drain region contacting an interlevel dielectric layer, and a second sidewall of the source / drain region opposite the first sidewall contacting the via-backside power rail.

17. 17. The method of claim 16, wherein the backside power rail is electrically connected to the at least one field effect transistor through a backside metal contact electrically connected to the source / drain regions.

18. 15. The method of claim 14, further comprising forming a plurality of shallow trench isolation regions located between adjacent field effect transistors, wherein the via-backside power rail is adjacent to at least one shallow trench isolation region located between two field effect transistors of like polarity.

19. forming the at least one backside field effect transistor; depositing a mask layer over a portion of the first semiconductor layer located over the passive device region; selectively removing the first semiconductor layer from an active region including the plurality of field effect transistors and from areas of the passive device region not covered by the mask layer; and removing the mask layer to expose a top surface of the first semiconductor layer, wherein the first semiconductor layer comprises a monocrystalline silicon layer; The method of claim 13 further comprising:

20. forming the at least one backside field effect transistor including backside source / drain regions on an opposite side of a gate structure disposed on a gate dielectric; forming a backside sidewall spacer disposed along the gate structure and the gate dielectric; forming a power distribution network electrically connected to the backside power rail through substrate vias embedded in the backside interlayer dielectric; forming a plurality of backside metal contacts through the substrate vias, electrically connecting the at least one backside field effect transistor to a plurality of interconnect structures; and forming a carrier wafer contacting a second surface of the wiring process interconnect level opposite a first surface of the wiring process interconnect level; The method of claim 13 further comprising:

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