Circuit board and semiconductor package including the same

Abstract

A circuit board according to an embodiment includes a first insulating layer and a first circuit pattern layer including a pad disposed on the first insulating layer, the pad including a first metal layer at least partially embedded in the first insulating layer and a second metal layer disposed on the first metal layer and protruding above the first insulating layer, the thickness of the second metal layer being smaller than the thickness of the first metal layer.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] A circuit board includes an insulating layer and a circuit pattern disposed on the insulating layer. The term "circuit board" refers to a board before semiconductor devices are mounted on it. That is, a circuit board refers to a board on which at least one semiconductor device is mounted, with the mounting positions of the semiconductor devices determined and the circuit pattern connected to the semiconductor devices disposed on the insulating layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals via the circuit pattern.

[0003] On the other hand, with the recent trend toward more sophisticated functions in portable electronic devices, signals are being transmitted at higher frequencies to process large amounts of information at high speed, and circuit boards suitable for high-frequency applications are being demanded.

[0004] Such circuit boards minimize signal transmission loss and enable signal transmission in an integrated state, which requires finer circuit patterns included in the circuit boards.

[0005] Meanwhile, technological advances are driving a rapid increase in data processing volume, and to address this, semiconductor packages are required to have high input / output capabilities and small or slim form-factor structures to maintain high performance.

[0006] To meet these requirements, circuit boards are manufactured using the ETS (Embedded Trace Substrate) method, which allows for the realization of fine circuit patterns. The ETS method is a method of manufacturing circuit patterns by embedding them in an insulating layer, which is advantageous for miniaturizing circuit patterns because there is no circuit loss due to etching.

[0007] This allows circuit boards that are combined with logic chips, interposers, etc. to be manufactured using the ETS method.

[0008] However, circuit boards manufactured using the conventional ETS method can suffer from solder runoff during the soldering process used to connect logic chips or interposers, which can lead to electrical reliability issues such as short circuits. Summary of the Invention [Problem to be solved by the invention]

[0009] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0010] Furthermore, the embodiments provide a circuit board with improved electrical reliability and a semiconductor package including the same.

[0011] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same that can solve the problem of short circuits occurring in the arrangement area of ​​the connection members.

[0012] Furthermore, the embodiments provide a circuit board capable of increasing the contact area with a connection member and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board capable of minimizing the height deviation of bumps and a semiconductor package including the same.

[0014] The technical problems to be solved by the proposed embodiments are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the embodiments pertain from the following description. [Means for solving the problem]

[0015] A circuit board according to an embodiment includes a first insulating layer and a pad disposed on the first insulating layer, the pad including a first metal layer at least partially or entirely embedded in an upper surface of the first insulating layer, and a second metal layer disposed on the first metal layer and protruding above the first insulating layer, the thickness of the second metal layer being different from the thickness of the first metal layer.

[0016] The thickness of the second metal layer is smaller than the thickness of the first metal layer.

[0017] The upper surface of the first metal layer has a step.

[0018] In addition, the first metal layer of the pad includes a first portion that vertically overlaps the second metal layer and is in contact with the second metal layer, and a second portion that does not vertically overlap the second metal layer, and the top surface of the first portion is located higher than the top surface of the second portion.

[0019] The top surface of the first portion of the first metal layer is flush with the top surface of the first insulating layer.

[0020] The first metal layer is an electrolytically plated layer, and the second metal layer is a seed layer for electrolytically plating the first metal layer.

[0021] The thickness of the pad satisfies the range of 10 μm to 35 μm.

[0022] The thickness of the first portion of the first metal layer satisfies the range of 8 μm to 25 μm.

[0023] The thickness of the second portion of the first metal layer satisfies the range of 6 μm to 21 μm.

[0024] Furthermore, the difference in thickness between the first portion and the second portion of the first metal layer satisfies the range of 2 μm to 4 μm.

[0025] The thickness of the second metal layer satisfies the range of 2.2 μm to 10 μm.

[0026] The second metal layer also includes a curved side surface along a thickness direction such that the width increases from the upper surface to the lower surface.

[0027] The first metal layer does not contact the first insulating layer or the second metal layer and includes a curved side surface connected to a side surface of the second metal layer.

[0028] The pad further includes a trace disposed on the insulating layer, the trace having a thickness corresponding to a thickness of the second portion of the first metal layer of the pad.

[0029] The circuit board further includes a second circuit pattern layer disposed below the first insulating layer, the second circuit pattern layer having a thickness less than the thickness of the trace.

[0030] The circuit board further includes a surface treatment layer disposed on the pad, the surface treatment layer including a first region in contact with a side surface of the first metal layer of the pad, a second region in contact with a side surface of the second metal layer of the pad, and a third region in contact with a top surface of the second metal layer of the pad.

[0031] Furthermore, the upper surface of the first metal layer is located on the same plane as the upper surface of the first insulating layer, and the second metal layer has a width greater than the width of the first metal layer and is disposed on the first metal layer and the first insulating layer.

[0032] On the other hand, a semiconductor package according to an embodiment includes a first insulating layer, a first circuit pattern layer including a pad arranged on the first insulating layer, a connection member arranged on the pad of the first circuit pattern layer, and an interposer arranged on the connection member, wherein the pad includes a first metal layer at least partially embedded in the first insulating layer and having a first thickness, and a second metal layer protruding above the first insulating layer and having a second thickness smaller than the first thickness, the width of the second metal layer is smaller than the width of the first metal layer, the first metal layer of the pad includes a step portion provided between an area vertically overlapping with the second metal layer and an area not vertically overlapping with the second metal layer, and the connection member is arranged to fill the step portion.

[0033] The interposer includes at least one of an active interposer, a passive interposer, and a bridge substrate. [Effects of the Invention]

[0034] The circuit board of the embodiment may include a first insulating layer and a first circuit pattern layer including a pad disposed on the first insulating layer. The pad may include a first metal layer at least partially embedded in the first insulating layer and a second metal layer disposed on the first metal layer and protruding above the first insulating layer, the second metal layer having a thickness smaller than that of the first metal layer. In this case, the first metal layer of the pad may be an electroplated layer formed by electroplating using the second metal layer of the pad as a seed layer. The second metal layer of the pad may be a seed layer used for electroplating the first metal layer of the pad. That is, the second metal layer of the pad may be an electroless plated layer or a copper foil layer.

[0035] In addition, in an embodiment, a portion of a seed layer used to form a pad of a circuit pattern layer having an ETS structure is not removed. For example, a portion of the seed layer may constitute a second metal layer that functions as a bump of a pad of a first circuit pattern layer. That is, the second metal layer of the pad may function as a bump for disposing a connection member on the pad. As a result, in an embodiment, the second metal layer used to electrolytically plate the first metal layer of the pad can be used as the pad bump. As a result, in an embodiment, the time, material, and cost required for additionally forming a bump can be saved.

[0036] Also, the embodiment can improve the bonding strength between the first metal layer of the pad and the second metal layer that functions as a bump.

[0037] For example, in the comparative example, a separate plating process is performed on the pad to form the bump. As a result, the pad may include a seed layer and an electrolytic plating layer used for plating the bump. As a result, in the comparative example, the adhesive strength between the pad, the seed layer of the bump, and the electrolytic plating layer of the bump is reduced, which in turn reduces the physical and electrical reliability of the circuit board.

[0038] In contrast, in the embodiment, the second metal layer corresponding to the bump can be formed using the copper foil layer, which is the seed layer used for electrolytic plating of the first metal layer of the pad, thereby improving the bonding strength and adhesion between the second metal layer functioning as the bump and the first metal layer of the pad.

[0039] Furthermore, the embodiment may minimize height deviations that occur between a plurality of bumps coupled to a semiconductor device. For example, the second metal layer of the pad may be a copper foil layer provided on the carrier board. As a result, the copper foil layer may have a uniform thickness and height. The copper foil layer is the first metal layer provided in a circuit board manufacturing process, and as a result, height deviations therebetween are nearly zero. In addition, the embodiment may form the second metal layer of the pad, which functions as a bump, by etching away the copper foil layer. In this case, a plurality of pads may be provided on the circuit board. In this case, the second metal layer of each of the plurality of pads may correspond to the copper foil layer. As a result, the embodiment may provide the second metal layer of each of the plurality of pads with a uniform thickness and height. As a result, the embodiment may improve the bonding strength of a semiconductor device or an external substrate disposed on the pad. Furthermore, the embodiment may provide a stable bonding of the semiconductor device or the external substrate to the pad. As a result, the embodiment may improve the electrical reliability and / or physical reliability of the semiconductor device or the external substrate. As a result, the embodiment may improve the product reliability of the semiconductor package.

[0040] In addition, the embodiment may form a second metal layer corresponding to the bump of the pad by etching a seed layer of the first metal layer of the pad, thereby reducing the width of the second metal layer of the pad that functions as a bump.

[0041] This allows the embodiment to further reduce the pitch between the pads. For example, the pad pitch may be determined based on the pitch between the second metal layers of the respective pads. For example, if the pitch between the first metal layers of the pads can be reduced but the pitch between the second metal layers cannot be reduced, the pad pitch must be increased to correspond to the pitch of the second metal layer.

[0042] In contrast, in the embodiment, the width of the bumps can be reduced by etching the second metal layer used as a seed layer. This allows the pitch between the second metal layer of the plurality of pads to be reduced. This also allows the pitch between the first metal layer of the plurality of pads to be reduced. Therefore, the embodiment can reduce the pitch between the plurality of pads. This allows the embodiment to further improve the circuit integration and reduce the volume of the circuit board and the semiconductor package. [Brief explanation of the drawings]

[0043] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor package according to a comparative example. [Figure 2a] FIG. 2a is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 2b] FIG. 2b is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 2c] FIG. 2c is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 2d] FIG. 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 2e] FIG. 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 2f] FIG. 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 2g] FIG. 2g is a cross-sectional view showing a semiconductor package according to the seventh embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a circuit board according to an embodiment. [Figure 4] FIG. 4 is an enlarged plan view of a partial region of the first circuit pattern layer of FIG. [Figure 5] FIG. 5 is an enlarged cross-sectional view of the area where the pads are arranged in FIG. 3 according to the first embodiment. [Figure 6] FIG. 6 is a plan view showing the pad of FIG. [Figure 7]FIG. 7 is a cross-sectional view illustrating the layer structure of the circuit pattern layer according to the embodiment. [Figure 8a-8b] 8a and 8b are enlarged cross-sectional views of the area where the pads are arranged in FIG. 3 according to the second embodiment. [Figure 9] FIG. 9 is an enlarged cross-sectional view of the area where the pads are arranged in FIG. 3 according to the third embodiment. [Figure 10] FIG. 10 is an enlarged cross-sectional view of the area where the pads are arranged in FIG. 3 according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram showing an example of a package substrate according to an embodiment. [Figure 12-23] 12 to 23 are cross-sectional views showing the manufacturing method of the circuit board shown in FIG. 3 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0044] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" used in the following description are used interchangeably to facilitate the preparation of the specification and do not have any distinguishing meaning or function. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related known technology is deemed to interfere with the gist of the embodiments disclosed herein, such a detailed description will be omitted. Furthermore, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be construed as limiting the scope of the present invention, but should be understood to include all modifications, equivalents, and alternatives within the scope of the present invention.

[0045] Although terms including ordinal numbers such as first, second, etc. are used to describe various components, the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0046] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly "coupled" or "connected" to the other component, and that there may be other components between them. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components between them.

[0047] The singular expression includes the plural expression unless the context clearly dictates otherwise.

[0048] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof stated in the specification, but is understood not to preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0049] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0050] <Comparative Example> Before describing the examples, a comparative example to be compared with the circuit board of the examples of the present application will be described.

[0051] FIG. 1 is a cross-sectional view of a semiconductor package according to a comparative example.

[0052] 1, the circuit board according to the comparative example includes an insulating layer 10. A first circuit pattern layer 20 is disposed on the insulating layer 10. A second circuit pattern layer 30 is disposed below the insulating layer 10.

[0053] At this time, the circuit pattern layer of the circuit board is required to be finer. To this end, the circuit board has an ETS (Embedded Trace Substrate) structure, which is advantageous for finer circuit pattern layers. Therefore, the first circuit pattern layer 20 has a structure embedded in the insulating layer 10. The through electrodes 40 penetrate the insulating layer 10. The through electrodes 40 electrically connect the first circuit pattern layer 20 and the second circuit pattern layer 30.

[0054] The first protective layer 50 is disposed on the upper surface of the insulating layer 10. The second protective layer 60 is disposed on the lower surface of the insulating layer 10.

[0055] At this time, the first circuit pattern layer 20 includes pads to be connected to the semiconductor device, and bumps 70 are disposed on the pads.

[0056] The bumps 70 protrude outward from the pads, and a semiconductor element is attached onto the bumps 70 via a connecting member.

[0057] The bumps 70 of the comparative example are formed by performing a plating process on the first circuit pattern layer 20. For example, the bumps 70 are electroplated layers disposed on the first circuit pattern layer 20.

[0058] At this time, the bumps 70 have height deviations due to a decrease in plating uniformity. For example, if a plurality of bumps 70 are provided to be connected to a plurality of terminals of a semiconductor device, deviations in height of the upper surfaces of the bumps 70 occur due to a decrease in plating uniformity in the process of plating each bump 70.

[0059] As a result, the semiconductor device is attached in a tilted state on the bumps 70 due to the height deviation of the bumps 70. This reduces the connection reliability of the semiconductor device, resulting in a problem of degraded electrical characteristics.

[0060] As a result, the embodiment can minimize the height deviation of the plurality of bumps provided on the circuit board, and also eliminate the height deviation of the plurality of bumps provided on the circuit board, so that the plurality of bumps are all positioned on the same plane.

[0061] <Electronic Devices> Before describing the embodiments, a brief description will be given of an electronic device to which the semiconductor package of the embodiments is applied. The electronic device includes a main board (not shown). The main board is physically and / or electrically connected to various components. For example, the main board is connected to the semiconductor package of the embodiments. Various semiconductor elements are mounted in the semiconductor package.

[0062] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, etc. The logic chip may be a central processor (CPU), a graphics processor (GPU), etc. For example, the logic chip may be an application processor (AP) semiconductor chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chipset including a specific combination of the above.

[0063] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and other memory chips.

[0064] On the other hand, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited to these.

[0065] Furthermore, the electronic device may be a smartphone, a PDA (personal digital assistant), a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device is not limited to these, and may of course be any other electronic device that processes data.

[0066] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0067] And, the circuit board in one embodiment may be the first board described below.

[0068] In another embodiment, the circuit board may be the second board described below.

[0069] Figure 2a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 2b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 2c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 2d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 2e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 2f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 2g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0070] Referring to FIG. 2 a, the semiconductor package of the first embodiment may include a first substrate 1100 , a second substrate 1200 and a semiconductor device 1300 .

[0071] The first substrate 1100 may refer to a package substrate.

[0072] For example, the first substrate 1100 may provide a space to which at least one external substrate is coupled. The external substrate may refer to the second substrate 1200 coupled on the first substrate 1100. Alternatively, the external substrate may refer to a main board included in an electronic device coupled to the lower portion of the first substrate 1100.

[0073] Although not shown in the drawings, the first substrate 1100 may provide a space in which at least one semiconductor element is mounted.

[0074] The first substrate 1100 may include at least one insulating layer, an electrode disposed on the at least one insulating layer, and a through electrode that penetrates the at least one insulating layer.

[0075] A second substrate 1200 is disposed on the first substrate 1100 .

[0076] The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space in which at least one semiconductor device is mounted. The second substrate 1200 is connected to at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second substrate 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and electrically connect the first and second semiconductor devices 1310 and 1320 to the first substrate 1100. That is, the second substrate 1200 may function as a horizontal connection between multiple semiconductor devices and a vertical connection between the semiconductor device and a package substrate.

[0077] 2a illustrates two semiconductor elements 1310 and 1320 disposed on the second substrate 1200, but is not limited thereto. For example, one semiconductor element may be disposed on the second substrate 1200, or alternatively, three or more semiconductor elements may be disposed on the second substrate 1200.

[0078] The second substrate 1200 is disposed between at least one semiconductor element 1300 and the first substrate 1100 .

[0079] In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate 1100 and may function as multiple logic chips. Having the functionality of a logic chip may mean having the functionality of both active and passive devices. Unlike passive devices, active devices do not have linear current-voltage characteristics, whereas an active interposer may have the functionality of an active device. Furthermore, the active interposer may function as a logic chip and also transmit signals between the first substrate 1100 and a second logic chip disposed thereon.

[0080] According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may function as a signal relay between the semiconductor device 1300 and the first substrate 1100 and may function as a passive element such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device 1300 is gradually increasing due to factors such as 5G, Internet of Things (IoT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first substrate 1100 is connected to the main board of an electronic device. Therefore, in order for the electrodes provided on the first substrate 1100 to have the width and spacing required to be connected to the semiconductor device 1300 and the main board, respectively, the thickness of the first substrate 1100 increases or the layer structure of the first substrate 1100 becomes complex. Therefore, in the first embodiment, the second substrate 1200 may be disposed on the first substrate 1100 and the semiconductor device 1300. The second substrate 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0081] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0082] On the other hand, the semiconductor package of the first embodiment can include a connecting portion.

[0083] For example, the semiconductor package may include a first connection portion 1410 disposed between the first substrate 1100 and the second substrate 1200. The first connection portion 1410 may couple the first substrate 1100 to the second substrate 1200 and electrically connect them together.

[0084] For example, the semiconductor package may include a second connection part 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection part 1420 may couple the semiconductor device 1300 onto the second substrate 1200 and electrically connect them together.

[0085] The semiconductor package may include a third connection portion 1430 disposed on the lower surface of the first substrate 1100. The third connection portion 1430 may couple the first substrate 1100 to the main board and electrically connect them together.

[0086] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 can electrically connect the multiple components using at least one bonding method of wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package can be understood as the electrically connected part, not the solder or wire.

[0087] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The direct inter-metal bonding method may refer to directly bonding multiple components by applying heat and pressure between the multiple components to cause recrystallization without using a material such as solder, wire, or conductive adhesive. The direct inter-metal bonding method may refer to a bonding method using the second connecting portion 1420. In this case, the second connecting portion 1420 may refer to a metal layer formed between the multiple components by recrystallization.

[0088] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0089] In this case, a protrusion is disposed on the electrode on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are disposed in at least one of the first substrate 1100 and the second substrate 1200. The protrusion may protrude outward from the first substrate 1100 or the second substrate 1200.

[0090] The protrusion may be referred to as a bump, a post, or a pillar. Preferably, the protrusion may refer to an electrode of the second substrate 1200 on which a second connection portion 1420 for coupling to the semiconductor device 1300 is disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection portions 1420, which are respectively connected to the terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion 1420. Accordingly, in an embodiment, the protrusion may be included in the electrode of the second substrate 1200 on which the second connection portion 1420 is disposed to ensure consistency, diffusion strength, and a diffusion prevention force that prevents an intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or substrate.

[0091] Meanwhile, referring to FIG. 2B, the semiconductor package of the second embodiment differs from the semiconductor package of the first embodiment in that a connecting member 1210 is disposed on a second substrate 1200. The connecting member 1210 may be referred to as a bridge substrate. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may function to horizontally electrically connect a plurality of semiconductor devices to each other. Exemplarily, since the area required for a semiconductor device is generally too large, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width of the circuit pattern, etc., a buffering function for the circuit pattern is required for electrical connection. The buffering function may mean that the redistribution layer has an intermediate size between the width of the circuit pattern of the semiconductor package and the width of the circuit pattern of the semiconductor device, and the buffering function may be included.

[0092] In one embodiment, the connecting member 1210 may be a silicon bridge, i.e., the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0093] In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic substrate containing an organic material instead of a silicon substrate.

[0094] The connecting member 1210 may be, but is not limited to, embedded in the second substrate 1200. For example, the connecting member 1210 may be disposed on the second substrate 1200 in a protruding structure.

[0095] Additionally, the second substrate 1200 may include a cavity, and the connecting member 1210 is disposed within the cavity of the second substrate 1200 .

[0096] The connecting members 1210 can horizontally connect the semiconductor elements arranged on the second substrate 1200 together.

[0097] 2c, the semiconductor package of the third embodiment may include a second substrate 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first substrate 1100 is omitted compared to the semiconductor package of the second embodiment.

[0098] That is, the second substrate 1200 of the third embodiment can function as an interposer and also as a package substrate.

[0099] The first connection portion 1410 disposed on the lower surface of the second substrate 1200 can couple the second substrate 1200 to a main board of an electronic device.

[0100] Referring to FIG. 2 d , the semiconductor package of the fourth embodiment may include a first substrate 1100 and a semiconductor device 1300 .

[0101] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second substrate 1200 is omitted compared to the semiconductor package of the second embodiment.

[0102] That is, the first substrate 1100 of the fourth embodiment can function as a package substrate and also as a connection between the semiconductor device 1300 and the main board. To this end, the first substrate 1100 can include a connection member 1110 for connecting between the plurality of semiconductor devices. The connection member 1110 can be a silicon bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0103] Referring to FIG. 2e, the semiconductor package of the fifth embodiment may further include a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

[0104] For this purpose, a fourth connection part 1440 is disposed on the lower surface of the first substrate 1100.

[0105] The third semiconductor element 1330 is disposed on the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0106] In this case, the third semiconductor device 1330 may have a structure in which it is disposed on the lower surface of the second substrate 1200 in the semiconductor package of FIG. 2c.

[0107] 2f, the semiconductor package of the sixth embodiment may include a first substrate 1100. A first semiconductor device 1310 is disposed on the first substrate 1100. To this end, a first connection part 1410 is disposed between the first substrate 1100 and the first semiconductor device 1310.

[0108] The first substrate 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump or alternatively as a post. The conductive coupling part 1450 may be disposed in a protruding structure on an electrode disposed on the top side of the first substrate 1100.

[0109] The second semiconductor element 1320 is disposed on the conductive coupling part 1450. At this time, the second semiconductor element 1320 is connected to the first substrate 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 is disposed on the first semiconductor element 1310 and the second semiconductor element 1320.

[0110] As a result, the second semiconductor element 1320 is electrically connected to the first semiconductor element 1310 via the second connection portion 1420 .

[0111] That is, the second semiconductor device 1320 is connected to the first substrate 1100 through the conductive coupling part 1450 and also connected to the first semiconductor device 1310 through the second connection part 1420 .

[0112] At this time, the second semiconductor device 1320 is supplied with a power signal and / or power through the conductive coupling part 1450. In addition, the second semiconductor device 1320 can exchange communication signals with the first semiconductor device 1310 through the second connection part 1420.

[0113] The semiconductor package of the sixth embodiment supplies a power signal and / or power to the second semiconductor element 1320 via the conductive coupling part 1450, thereby providing sufficient power to drive the second semiconductor element 1320 and enabling smooth control of the power supply operation.

[0114] As a result, the embodiment may improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment may solve the problem of insufficient power provided to the second semiconductor device 1320. Furthermore, the embodiment may provide at least one of the power signal, power, and communication signal of the second semiconductor device 1320 via different paths via the conductive coupling part 1450 and the second connection part 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0115] Meanwhile, in the sixth embodiment, the second semiconductor device 1320 may be disposed on the first substrate 1100 in a package-on-package (POP) structure in which a plurality of package substrates are stacked. For example, the second semiconductor device 1320 may be a memory package including a memory chip. The memory package is coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0116] Meanwhile, the semiconductor package according to the sixth embodiment may include a molding member 1460. The molding member 1460 is disposed between the first substrate 1100 and the second semiconductor element 1320. For example, the molding member 1460 may mold the first connecting member 1410, the second connecting member 1420, the first semiconductor element 1310, and the conductive coupling member 1450.

[0117] Referring to FIG. 2 g , the semiconductor package of the seventh embodiment may include a first substrate 1100 , a first connecting portion 1410 , a semiconductor device 1300 , and a third connecting portion 1430 .

[0118] The semiconductor package of the seventh embodiment differs from the semiconductor package of the fourth embodiment in that the connecting member 1110 is omitted and the first substrate 1100 includes a plurality of substrate layers.

[0119] The first substrate 1100 may include multiple substrate layers, for example, a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a connecting member.

[0120] That is, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B in which the first substrate (package substrate) 1100 and the second substrate (interposer) 1200 shown in FIG. 2A are integrally formed. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photo-curable material. For example, the second substrate layer 1100B may be a photo-imageable dielectric (PID). The second substrate layer 1100B may include a photo-curable material, which allows for miniaturization of electrodes. Therefore, in the seventh embodiment, the second substrate layer 1100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first substrate layer 1100A and then forming miniaturized electrodes on the insulating layers of the photo-curable material. Therefore, the second substrate 1100B may have a redistribution layer function including miniaturized electrodes, and may have a function of connecting the plurality of semiconductor elements 1310 and 1320 horizontally.

[0121] <Circuit board> The circuit board of the embodiment will be described below.

[0122] Before describing the circuit board of the embodiment, the circuit board described below may refer to any one of a plurality of boards included in the previous semiconductor package.

[0123] For example, in one embodiment, the circuit board described below may refer to any one of the first substrate 1100, the second substrate 1200, and the connecting members (or bridge substrates) 1110, 1210 shown in any one of Figures 2a to 2g.

[0124] For example, the "pads" of the circuit board described below may be pads to which the second substrate 1200 is bonded, or may alternatively be electrodes on which semiconductor elements are mounted.

[0125] Figure 3 is a cross-sectional view of a circuit board according to an embodiment, Figure 4 is a plan view of an enlarged portion of the first circuit pattern layer of Figure 3, Figure 5 is a cross-sectional view of an enlarged portion of the area where the pads of Figure 3 according to the first embodiment are arranged, Figure 6 is a plan view showing the pads of Figure 5, Figure 7 is a cross-sectional view for explaining the layer structure of the circuit pattern layer according to an embodiment, Figures 8a and 8b are cross-sectional views of an enlarged portion of the area where the pads of Figure 3 according to the second embodiment are arranged, Figure 9 is a cross-sectional view of an enlarged portion of the area where the pads of Figure 3 according to the third embodiment are arranged, and Figure 10 is a cross-sectional view of an enlarged portion of the area where the pads of Figure 3 according to the fourth embodiment are arranged.

[0126] The circuit boards according to the respective embodiments will be specifically described below with reference to FIGS.

[0127] The circuit board includes an insulating layer 110. The insulating layer 110 may have at least one layer or more.

[0128] 3 illustrates the circuit board including three insulating layers, but is not limited thereto. For example, the circuit board may include two or fewer insulating layers, or alternatively, may include four or more insulating layers.

[0129] However, for the sake of convenience, the following description will be given assuming that the circuit board includes three insulating layers.

[0130] The insulating layer 110 may include a first insulating layer 111 , a second insulating layer 112 and a third insulating layer 113 .

[0131] At least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be rigid or flexible. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include glass or plastic. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include sapphire. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include an optically isotropic film. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be made of a material including an inorganic filler and an insulating resin. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a structure in which inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 can be made of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imagable Dielectric resin (PID), BT, etc. For example, at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 can include Resin coated copper (RCC).

[0132] The first insulating layer 111 may be a first outer insulating layer of the circuit board. For example, the first insulating layer 111 may be an insulating layer arranged on the uppermost side of a plurality of insulating layers. The second insulating layer 112 may be an inner insulating layer of the circuit board. For example, the second insulating layer 112 may be an intermediate insulating layer arranged between the first outer insulating layer and the second outer insulating layer. For example, the third insulating layer 113 may be a second outer insulating layer. For example, the third insulating layer 113 may be an insulating layer arranged on the lowermost side of a plurality of insulating layers.

[0133] In this case, when the circuit board of the embodiment includes one insulating layer, the insulating layer 110 can include only the first insulating layer 111. For example, when the circuit board of the embodiment includes two insulating layers, the insulating layer 110 can include the first insulating layer 111 and the third insulating layer 113. For example, when the circuit board of the embodiment includes four or more insulating layers, the second insulating layer 112 can include multiple insulating layers.

[0134] The first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a thickness in the range of 10 μm to 40 μm. Preferably, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may satisfy a thickness in the range of 15 μm to 35 μm. More preferably, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may satisfy a thickness in the range of 18 μm to 32 μm. If the thickness of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 is less than 10 μm, the warpage characteristics of the substrate will be reduced. Furthermore, if the thickness of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 is less than 10 μm, the circuit pattern layer will not be stably protected, thereby reducing electrical reliability. Furthermore, if the thickness of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 exceeds 40 μm, the overall thickness of the substrate increases, which in turn increases the thickness of the semiconductor package. Furthermore, if the thickness of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 exceeds 40 μm, it becomes difficult to miniaturize the circuit pattern layer of the substrate 100.

[0135] The thickness may correspond to the distance in the vertical direction of the substrate between circuit pattern layers arranged on different layers. That is, the thickness may refer to the length from the top surface of the substrate to the bottom surface or from the bottom surface to the top surface, and may refer to the vertical length of the substrate. Here, the top surface may refer to the highest position in the vertical direction of each component, and the bottom surface may refer to the lowest position in the vertical direction of each component. These positions may be referred to as opposite positions.

[0136] For example, the thickness of the first insulating layer 111 may refer to the vertical distance between the lower surface of the first circuit pattern layer 121 and the upper surface of the second circuit pattern layer 122. For example, the thickness of the second insulating layer 112 may refer to the vertical distance between the lower surface of the second circuit pattern layer 122 and the third circuit pattern layer 123. For example, the thickness of the third insulating layer 113 may refer to the vertical distance between the lower surface of the third circuit pattern layer 123 and the fourth circuit pattern layer 124.

[0137] A circuit pattern layer 120 is disposed on the surface of the insulating layer 110 .

[0138] For example, a first circuit pattern layer 121 is disposed on the upper surface of the first insulating layer 111. For example, a second circuit pattern layer 122 is disposed on the lower surface of the first insulating layer 111 or the upper surface of the second insulating layer 112. For example, a third circuit pattern layer 123 is disposed on the lower surface of the second insulating layer 112 or the upper surface of the third insulating layer 113. For example, a fourth circuit pattern layer 124 is disposed on the lower surface of the third insulating layer 113.

[0139] In an embodiment, the circuit board may be manufactured using an ETS (Embedded Trace Substrate) method. Therefore, at least one of the circuit patterns included in the circuit board may have an ETS structure. For example, one of the circuit patterns arranged on the outermost layer of the circuit board may be embedded in an insulating layer.

[0140] For example, the first circuit pattern layer 121 disposed on the upper surface of the first insulating layer 111 may have an ETS structure. For example, the first circuit pattern layer 121 may be a circuit pattern layer disposed on the first outermost side of the circuit board. This allows the upper surface of the first circuit pattern layer 121 to be exposed to the first outermost side of the circuit board. The lower surface of the first circuit pattern layer 121 is covered by the first insulating layer 111. At least a portion of the side surface of the first circuit pattern layer 121 is covered by the first insulating layer 111.

[0141] Meanwhile, the second circuit pattern layer 122 may protrude downward from the lower surface of the first insulating layer 111. For example, the second circuit pattern layer 122 may have a structure in which it is embedded in the upper surface of the second insulating layer 112. The side and lower surfaces of the second circuit pattern layer 122 are covered with the second insulating layer 112.

[0142] In addition, the third circuit pattern layer 123 may protrude downward from the lower surface of the second insulating layer 112. For example, the third circuit pattern layer 123 may have a structure in which it is embedded in the upper surface of the third insulating layer 113. The side and lower surfaces of the third circuit pattern layer 123 are covered with the third insulating layer 113.

[0143] For example, the fourth circuit pattern layer 124 may have a structure that protrudes downward from the lower surface of the third insulating layer 113. For example, the fourth circuit pattern layer 124 may be a circuit pattern layer disposed on the second outermost side of the circuit board, so that the side and lower surfaces of the fourth circuit pattern layer 124 can be exposed to the second outermost side of the circuit board.

[0144] Meanwhile, the circuit pattern layer 120 of the embodiment may include traces and pads. For example, the first circuit pattern layer 121 and the fourth circuit pattern layer 124, which are disposed on the first and second outermost sides of the circuit board, may include pads connected to a chip or an external board. Also, the first circuit pattern layer 121 and the fourth circuit pattern layer 124 may include traces connected to the pads.

[0145] The circuit pattern layer 120 may be made of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The circuit pattern layer 120 may also be made of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the circuit pattern layer 120 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0146] At least one of the first circuit pattern layer 121, the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may have a thickness different from at least one of the others. For example, the thickness of the first circuit pattern layer 121 may have a thickness different from that of at least one of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124. Preferably, the thickness of the first circuit pattern layer 121 may be greater than the thicknesses of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124.

[0147] That is, the first circuit pattern layer 121 may be disposed as the outermost layer of a plurality of insulating layers and may have a structure embedded within the outermost insulating layer. The first circuit pattern layer 121 may include pads on which a semiconductor device or an external substrate is disposed. Therefore, if the first circuit pattern layer 121 has a relatively small thickness, bonding with the semiconductor device or the external substrate may be reduced, resulting in reduced electrical and / or physical reliability. Furthermore, if the first circuit pattern layer 121 has a relatively small thickness, the pads of the first circuit pattern layer 121 may collapse during the bonding process with the semiconductor device or the external substrate.

[0148] Therefore, the first circuit pattern layer 121 may have a thickness greater than the other circuit pattern layers, but the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may have a thickness smaller than the first circuit pattern layer 121 in order to allow for finer circuit patterns.

[0149] The first circuit pattern layer 121 may have a thickness of 10 μm to 35 μm. Preferably, the first circuit pattern layer 121 may have a thickness of 12 μm to 33 μm. More preferably, the first circuit pattern layer 121 may have a thickness of 14 μm to 30 μm. If the thickness of the first circuit pattern layer 121 is less than 10 μm, the bonding strength with the semiconductor device or external substrate decreases. If the thickness of the first circuit pattern layer 121 exceeds 35 μm, it becomes difficult to miniaturize the first circuit pattern layer 121. In other words, the thickness of the first circuit pattern layer 121 may refer to "T1" in FIG. 5.

[0150] In this case, the thickness of the first circuit pattern layer 121 may refer to the thickness of the pads of the first circuit pattern layer 121. Specifically, it may refer to the thickness of the pads of the first circuit pattern layer 121. Preferably, the first circuit pattern layer 121 may include pads and traces. The thickness of the pads of the first circuit pattern layer 121 may be different from the thickness of the traces of the first circuit pattern layer 121. The traces of the first circuit pattern layer 121 may have a different layer structure from the pads of the first circuit pattern layer 121. This will be described in more detail below.

[0151] The second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may each have a thickness T2 (see FIG. 5) in the range of 8 μm to 28 μm. For example, the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may each have a thickness T2 in the range of 10 μm to 25 μm. The second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may each have a thickness T2 in the range of 12 μm to 21 μm. If the thickness T2 of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 is less than 8 μm, resistance increases, resulting in a decrease in signal transmission efficiency. For example, if the thickness T2 of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 is less than 8 μm, signal transmission loss increases. For example, if the thickness T2 of each of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 exceeds 28 μm, the line width of the circuit pattern increases, thereby increasing the overall volume of the circuit board.

[0152] That is, the thickness T1 of the pads of the first circuit pattern layer 121 may be greater than the thickness T2 of the second circuit pattern layer 122. That is, the pads of the first circuit pattern layer 121 and the second circuit pattern layer 122 may each have a structure including a seed layer. In this case, the thickness of the seed layer included in the pads of the first circuit pattern layer 121 may be greater than the thickness of the seed layer included in the second circuit pattern layer 122. Therefore, the thickness T1 of the pads of the first circuit pattern layer 121 may be greater than the thickness T2 of the second circuit pattern layer 122 by the difference in the thickness of the seed layer.

[0153] Meanwhile, referring to FIGS. 4 and 5, the first circuit pattern layer 121 may include pads 121-1 and traces 121-2.

[0154] The pads 121-1 may refer to electrodes to which a semiconductor element or an interposer is coupled in the first circuit pattern layer 121. The traces 121-2 may be signal lines connecting between multiple pads on the first circuit pattern layer 121.

[0155] The pad 121-1 may have a first width W1. For example, if the planar shape of the pad 121-1 is circular, the first width W1 may refer to the diameter of the pad 121-1. Also, if the planar shape of the pad 121-1 is elliptical, the first width W1 may refer to the diameter of the pad 121-1 in the major axis direction.

[0156] The first width W1 of the pad 121-1 may range from 40 μm to 70 μm. Preferably, the first width W1 of the pad 121-1 may range from 42 μm to 68 μm. More preferably, the first width W1 of the pad 121-1 may range from 45 μm to 65 μm. If the first width W1 of the pad 121-1 is less than 40 μm, the electrical connection with the chip mounted on the circuit board is reduced. If the first width W1 of the pad 121-1 is less than 40 μm, the allowable current of the signal transmitted through the pad is reduced. Furthermore, if the allowable current is reduced, the signal transmission characteristics are degraded. If the first width W1 of the pad 121-1 exceeds 70 μm, it is difficult to arrange all the pads connected to the chip within a limited space. If the first width W1 of the pad 121-1 exceeds 70 μm, the volume of the circuit board and the volume of the semiconductor package are increased. Meanwhile, the first width W1 of the pad 121-1 may refer to the width of the bottom surface of the pad 121-1. For example, the first width W1 of the pad 121-1 may refer to the width of the first metal layer 121-1a of the pad 121-1.

[0157] The line width W2 of the trace 121-2 can have a width of 15 μm or less. For example, the line width W2 of the trace 121-2 can have a width of 12 μm or less. For example, the line width W2 of the trace 121-2 can have a width of 10 μm or less. For example, the line width W2 of the trace 121-2 can have a width of 8 μm or less.

[0158] For example, the line width W2 of the trace 121-2 may be in the range of 2 μm to 15 μm. Preferably, the line width W2 of the trace 121-2 may be in the range of 2.2 μm to 12 μm. More preferably, the line width W2 of the trace 121-2 may be in the range of 2.5 μm to 10 μm.

[0159] If the line width W2 of the trace 121-2 is less than 2 μm, the signal resistance of the trace 121-2 increases, making it difficult to properly communicate with a chip mounted on the circuit board. Furthermore, if the line width W2 of the trace 121-2 is less than 2 μm, not only is it difficult to implement, but the trace 121-2 may easily break during the manufacturing process, resulting in reliability issues. Furthermore, if the line width W2 of the trace 121-2 exceeds 15 μm, it becomes difficult to arrange all of the traces 121-2 connected to the pads 121-1 within the limited space. If the line width W2 of the trace 121-2 exceeds 12 μm, the volume of the circuit board and the semiconductor package increases.

[0160] Furthermore, the spacing W3 between the pads 121-1, between the traces 121-2, or between the pads 121-1 and the traces 121-2 may range from 2 μm to 15 μm. For example, the spacing W3 may range from 2.2 μm to 12 μm. For example, the spacing W3 may range from 2.5 μm to 10 μm.

[0161] If the spacing W3 is less than 2 μm, adjacent circuit patterns may be connected to each other, resulting in an electrical short. If the spacing W3 is less than 2 μm, interference may occur between signals transmitted from adjacent circuit patterns. Furthermore, if the spacing W3 exceeds 15 μm, it becomes difficult to arrange all of the pads 121-1 and traces 121-2 within the limited space. If the spacing W3 exceeds 15 μm, the volume of the circuit board and semiconductor package increases.

[0162] The first circuit pattern layer 121 will be described in detail below.

[0163] The first circuit pattern layer 121 may include pads 121-1 and traces 121-1.

[0164] The pad 121-1 may include multiple metal layers. Alternatively, the trace 121-1 may include a single metal layer. For example, the pad 121-1 may include a first metal layer 121-1a and a second metal layer 121-1b. The trace 121-1 may include only a layer corresponding to the first metal layer 121-1a of the pad 121-1. The second metal layer 121-1b may function as a bump for the pad 121-1. Therefore, the second metal layer 121-1b may also be referred to as a "bump." That is, the "bump" described below may refer to the second metal layer 121-1b of the pad 121-1.

[0165] The first metal layer 121-1a of the pad 121-1 is disposed in the first insulating layer 111. The first metal layer 121-1a of the pad 121-1 may be embedded in the first insulating layer 111. The first metal layer 121-1a of the pad 121-1 may have a step. For example, the top surface of the first metal layer 121-1a of the pad 121-1 may include portions having different heights. For example, the first metal layer 121-1a of the pad 121-1 may include a step portion 121SP.

[0166] Specifically, the first metal layer 121-1a of the pad 121-1 may include a first portion that vertically overlaps the second metal layer 121-1b and a second portion that does not vertically overlap the second metal layer 121-1b. The top surfaces of the first and second portions of the first metal layer 121-1a may have different heights. For example, the top surface of the first portion of the first metal layer 121-1a may be higher than the top surface of the second portion of the first metal layer 121-1a.

[0167] The second metal layer 121-1b of the pad 121-1 is disposed at a certain height above the first metal layer 121-1a of the pad 121-1. The second metal layer 121-1b of the pad 121-1 can also be called a bump.

[0168] The width of the second metal layer 121-1b of the pad 121-1 may be smaller than the width of the first metal layer 121-1a of the pad 121-1. For example, the second metal layer 121-1b of the pad 121-1 may have a width smaller than the second portion of the first metal layer 121-1a of the pad 121-1 and may have the same width as the first portion of the first metal layer 121-1a of the pad 121-1.

[0169] The second metal layer 121-1b of the pad 121-1 is provided for stable attachment of a semiconductor device or an interposer onto the pad 121-1.

[0170] The first metal layer 121-1a and the second metal layer 121-1b of the pad 121-1 may include the same metal material, for example, but not limited to, copper.

[0171] The first metal layer 121-1a of the pad 121-1 may be an electrolytic plated layer that is electrolytically plated using the second metal layer 121-1b of the pad 121-1 as a seed layer.

[0172] And the second metal layer 121-1b of the pad 121-1 may be a seed layer used to electrolytically plate the first metal layer 121-1a of the pad 121-1 and the trace 121-1.

[0173] In one embodiment, the second metal layer 121-1b of the pad 121-1 may be an electroless plating layer, for example, a chemical copper plating layer.

[0174] In another embodiment, the second metal layer 121-1b of the pad 121-1 may be a copper foil layer of a carrier board used to manufacture the circuit board of the embodiment.

[0175] That is, in the circuit board of the embodiment, the first circuit pattern layer 121 can be formed by electrolytic plating using a copper foil layer (Cu foil) that constitutes a carrier board (described later) as a seed layer.

[0176] In this embodiment, the portion of the copper foil layer used as the seed layer is not removed. For example, the portion of the copper foil layer used as the seed layer may constitute the second metal layer 121-1b of the pad 121-1 of the first circuit pattern layer 121.

[0177] Therefore, the pad 121-1 of the first circuit pattern layer 121 can include the first metal layer 121-1a and the second metal layer 121-1b. In contrast, the trace 121-1 of the first circuit pattern layer 121 can include only the first metal layer 121-1a. That is, the second metal layer 121-1b is not removed only on the first metal layer 121-1a corresponding to the pad 121-1.

[0178] The second metal layer 121-1b of the pad 121-1 can function as a bump for placing a connection member on the pad 121-1.

[0179] In this case, the second metal layer 121-1b used for electroplating the first metal layer 121-1a of the pad 121-1 can be used as a bump for the pad 121-1, thereby reducing the time, materials, and costs required to form an additional bump.

[0180] Furthermore, the embodiment can improve the bonding strength between the first metal layer 121-1a and the second metal layer 121-1b of the pad 121-1.

[0181] For example, in the comparative example, a bump is formed by performing a separate plating process on the pad. Therefore, the pad may include a seed layer and an electroplated layer used for plating the bump. As a result, the comparative example reduces the adhesive strength between the pad, the bump seed layer, and the bump electroplated layer, thereby reducing the physical and electrical reliability of the circuit board. In contrast, in the example, the second metal layer 121-1b corresponding to the bump may be formed using the copper foil layer, which is the seed layer used for electroplating the first metal layer 121-1a of the pad 121-1. As a result, the example may improve the adhesive strength and adhesion between the second metal layer 121-1b functioning as the bump and the first metal layer 121-1a of the pad 121-1.

[0182] In addition, the embodiment may minimize height deviation of the bumps. For example, the second metal layer 121-1b of the pad 121-1 may be a copper foil layer provided on the carrier board. As a result, the copper foil layer may have a uniform thickness and height. In addition, in the embodiment, the second metal layer 121-1b of the pad 121-1, which functions as a bump, may be formed by etching away the copper foil layer. In this case, a plurality of pads may be provided on the circuit board. In this case, the second metal layer of each of the plurality of pads may correspond to the copper foil layer. As a result, in the embodiment, the second metal layer of each of the plurality of pads may have a uniform thickness and height. As a result, the embodiment may improve the bonding strength of a semiconductor device or an external substrate disposed on the pad 121-1. In addition, the embodiment may allow the semiconductor device or the external substrate to be stably bonded to the pad 121-1. As a result, the embodiment may improve the electrical reliability and / or physical reliability of the semiconductor device or the external substrate. As a result, the embodiment may improve the product reliability of the semiconductor package.

[0183] In addition, in the embodiment, the bump of the pad 121-1 can be formed by etching the second metal layer 121-1b used as a seed layer for the first metal layer 121-1a of the pad 121-1, thereby reducing the width of the second metal layer 121-1b of the pad 121-1 that functions as a bump.

[0184] This allows the embodiment to further reduce the pitch between the multiple pads 121-1. For example, the pitch between the pads 121-1 may be determined based on the pitch between the second metal layers of each pad. For example, if the pitch between the first metal layers of the pads 121-1 can be reduced but the pitch between the second metal layers cannot be reduced, the pitch between the pads 121-1 must be increased corresponding to the pitch of the second metal layers.

[0185] In contrast, in the embodiment, the width of the bumps can be reduced by etching the second metal layer used as a seed layer. This allows the pitch between the second metal layer of the plurality of pads to be reduced. This also allows the pitch between the first metal layer of the plurality of pads to be reduced. Therefore, the embodiment can reduce the pitch between the plurality of pads. This allows the embodiment to further improve the circuit integration and reduce the volume of the circuit board and the semiconductor package.

[0186] On the other hand, the thickness T1 of the pad 121-1 can have a thickness of 10 μm to 35 μm, 12 μm to 33 μm, or 14 μm to 30 μm as described.

[0187] The first metal layer 121-1a of the pad 121-1 may be divided into a plurality of regions in the horizontal direction. For example, the first metal layer 121-1a of the pad 121-1 may include a first region that vertically overlaps the second metal layer 121-1b and a second region that does not vertically overlap the second metal layer 121-1b.

[0188] The thickness (T1-1)+(T1-2) of the first region of the first metal layer 121-1a of the pad 121-1 can be in the range of 8 μm to 25 μm. For example, the thickness (T1-1)+(T1-2) of the first region of the first metal layer 121-1a of the pad 121-1 can be in the range of 9 μm to 23 μm. For example, the thickness (T1-1)+(T1-2) of the first region of the first metal layer 121-1a of the pad 121-1 can be in the range of 10 μm to 20 μm.

[0189] The thickness T1-1 of the second region of the first metal layer 121-1a may be in the range of 6 μm to 21 μm. The thickness T1-1 of the second region of the first metal layer 121-1a may be in the range of 7 μm to 19 μm. The thickness T1-1 of the second region of the first metal layer 121-1a may be in the range of 8 μm to 16 μm. The thickness T1-1 of the second region of the first metal layer 121-1a of the pad 121-1 may correspond to the thickness of the trace 121-1 of the first circuit pattern layer 121.

[0190] As a result, the thickness T1-2 of the step portion 121SP of the pad 121-1 can satisfy the range of 2 μm to 4 μm. If the thickness T1-2 of the step portion 121SP is less than 2 μm, a problem may occur in which part of the second metal layer 121-1b remains on the upper surface of the first insulating layer 111. This may result in a short circuit problem in which multiple pads are electrically connected to each other. Furthermore, if the thickness T1-2 of the step portion 121SP of the pad 121-1 is less than 2 μm, the connecting material may diffuse horizontally from the pad 121-1. If the connecting material diffuses, the diffusing connecting material may electrically connect multiple adjacent pads to each other, resulting in a short circuit problem. If the thickness T1-2 of the step portion 121SP of the pad 121-1 exceeds 4 μm, the amount of connecting material applied increases, thereby reducing the rigidity of the connecting material. If the thickness T1-2 of the stepped portion 121SP of the pad 121-1 exceeds 4 μm, deviations in height or thickness of the connecting members disposed on each of the pads may occur, and such deviations may reduce the bonding strength with the semiconductor device or the external substrate.

[0191] Meanwhile, the thickness T1-2 of the step portion 121SP of the pad 121-1 may refer to the vertical distance from the upper surface of the first insulating layer 111 to the lowermost end of the upper surface of the pad 121-1.

[0192] Furthermore, the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 may be in the range of 2.2 μm to 10 μm. For example, the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 may be in the range of 3 μm to 8 μm. For example, the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 may be in the range of 4 μm to 6 μm. In this case, the thickness T1-3 of the second metal layer 121-1b may be smaller than the thickness T2 of at least one of the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 described above.

[0193] Specifically, the second circuit pattern layer 122 may include a seed layer 122-1 and an electroplated layer 122-2. The thickness T1-3 of the second metal layer 121-1b may be greater than the thickness of the seed layer 122-1 of the second circuit pattern layer 122, but less than the thickness of the electroplated layer 122-2 of the second circuit pattern layer 122.

[0194] The third circuit pattern layer 123 may include a seed layer 123-1 and an electroplated layer 123-2. The thickness T1-3 of the second metal layer 121-1b may be greater than the thickness of the seed layer 123-1 of the third circuit pattern layer 123, but less than the thickness of the electroplated layer 123-2 of the third circuit pattern layer 123.

[0195] The fourth circuit pattern layer 124 may include a seed layer 124-1 and an electroplated layer 124-2. The thickness T1-3 of the second metal layer 121-1b may be greater than the thickness of the seed layer 124-1 of the fourth circuit pattern layer 124, but less than the thickness of the electroplated layer 124-2 of the fourth circuit pattern layer 124.

[0196] If the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 is less than 2.2 μm, the first metal layer 121-1a cannot function as a seed layer for electrolytic plating of the first metal layer 121-1a of the pad 121-1. If the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 is less than 2.2 μm, the second metal layer 121-1b cannot function as a bump for securing a connecting member.

[0197] If the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 exceeds 10 μm, it becomes difficult to miniaturize the first metal layer 121-1a electroplated using the second metal layer 121-1b. If the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 exceeds 5.0 μm, the etching time of the second metal layer 121-1b functioning as a bump increases. Furthermore, if the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 exceeds 10.0 μm, the etching rate of the etching solution used to etch the second metal layer 121-1b functioning as a bump may cause the side of the pad to become curved, which may cause the upper part of the pad 121-1 to collapse. Also, referring to Figure 8a or 8b, if the thickness T1-3 of the second metal layer 121-1b of the pad 121-1 exceeds 10.0 μm, the etching rate may cause the upper surface of the second metal layer 121-1b to become pointed, or the width of the interface between the second metal layer 121-1b and the first metal layer 121-1a may be too narrow, resulting in a stripping problem.

[0198] 6(a), the first metal layer 121-1a of the pad 121-1 may have an elliptical planar shape, and the second metal layer 121-1b of the pad 121-1 is disposed on the first metal layer 121-1a with an elliptical shape corresponding to the first metal layer 121-1a.

[0199] In this case, the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction may be in the range of 40 μm to 70 μm. Preferably, the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction may be in the range of 42 μm to 68 μm. More preferably, the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction may be in the range of 45 μm to 65 μm. If the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction is less than 40 μm, the electrical connectivity with the chip mounted on the circuit board will be reduced. If the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction is less than 40 μm, the allowable current of the signal transmitted through the pad will be reduced. Furthermore, if the allowable current is reduced, the signal transmission characteristics will be degraded. If the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction exceeds 70 μm, it becomes difficult to arrange all the pads connected to the chip within the limited space, and if the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the longitudinal direction exceeds 70 μm, the volume of the circuit board and the volume of the semiconductor package increase.

[0200] On the other hand, the width W1-2 in the minor axis direction of the first metal layer 121-1a of the pad 121-1 can be in the range of 30% to 60% of the width W1-1 in the major axis direction of the first metal layer 121-1a of the pad 121-1. For example, the width W1-2 in the minor axis direction of the first metal layer 121-1a of the pad 121-1 can be in the range of 35% to 55% of the width W1-1 in the major axis direction of the first metal layer 121-1a of the pad 121-1. For example, the width W1-2 in the minor axis direction of the first metal layer 121-1a of the pad 121-1 can be in the range of 35% to 52% of the width W1-1 in the major axis direction of the first metal layer 121-1a of the pad 121-1. If the width W1-2 of the first metal layer 121-1a of the pad 121-1 in the minor axis direction is less than 30% of the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the major axis direction, the second metal layer 121-1b will not be stably disposed on the first metal layer 121-1a of the pad 121-1. Also, if the width W1-2 of the first metal layer 121-1a of the pad 121-1 in the minor axis direction exceeds 55% of the width W1-1 of the first metal layer 121-1a of the pad 121-1 in the major axis direction, the area occupied by the pad 121-1 will increase, thereby reducing the circuit integration density.

[0201] On the other hand, the width W4-1 of the second metal layer 121-1b of the pad 121-1 in the longitudinal direction may be in the range of 25 μm to 60 μm. Preferably, the width W4-1 of the second metal layer 121-1b of the pad 121-1 in the longitudinal direction may be in the range of 28 μm to 58 μm. More preferably, the width W4-1 of the second metal layer 121-1b of the pad 121-1 in the longitudinal direction may be in the range of 30 μm to 55 μm. If the width W4-1 of the second metal layer 121-1b of the pad 121-1 in the longitudinal direction is less than 25 μm, the second metal layer 121-1b will not function as a bump, and therefore the connecting member will not be stably disposed on the second metal layer 121-1b. If the width W4-1 of the second metal layer 121-1b of the pad 121-1 in the longitudinal direction is less than 25 μm, the synergy of the contact area with the connecting member will be small. If the width W4-1 in the major axis direction of the second metal layer 121-1b of the pad 121-1 exceeds 60 μm, the circuit integration density decreases.

[0202] On the other hand, the width W4-2 in the minor axis direction of the second metal layer 121-1b of the pad 121-1 can be in the range of 30% to 60% of the width W4-1 in the major axis direction of the second metal layer 121-1b of the pad 121-1. For example, the width W4-2 in the minor axis direction of the second metal layer 121-1b of the pad 121-1 can be in the range of 35% to 55% of the width W4-1 in the major axis direction of the second metal layer 121-1b of the pad 121-1. For example, the width W4-2 in the minor axis direction of the second metal layer 121-1b of the pad 121-1 can be in the range of 38% to 52% of the width W4-1 in the major axis direction of the second metal layer 121-1b of the pad 121-1.

[0203] As a result, in the plane of the pad 121-1, the horizontal distance W5 from the outermost edge of the first metal layer 121-1a to the outermost edge of the second metal layer 121-1b can satisfy the range of 10 μm to 45 μm. For example, in the plane of the pad 121-1, the horizontal distance W5 from the outermost edge of the first metal layer 121-1a to the outermost edge of the second metal layer 121-1b can satisfy the range of 12 μm to 43 μm. For example, in the plane of the pad 121-1, the horizontal distance W5 from the outermost edge of the first metal layer 121-1a to the outermost edge of the second metal layer 121-1b can satisfy the range of 15 μm to 40 μm.

[0204] On the other hand, as shown in Figure 6(b), when the planar shape of the pad 121-1 is circular, the first metal layer 121-1a of the pad 121-1 may have a width W1 in a range corresponding to the width W1-1 in the long axis direction in Figure 6(a), and the second metal layer 121-1b of the pad 121-1 may have a width W4 corresponding to the width W4-1 in the long axis direction in Figure 6(a).

[0205] Meanwhile, the circuit board of the embodiment may include a through electrode 130 .

[0206] The through electrode 130 may penetrate the insulating layer 110 included in the circuit board of the embodiment. The through electrode 130 may electrically connect between circuit pattern layers arranged on different layers. In this case, the through electrode 130 may penetrate only one insulating layer, or may penetrate at least two insulating layers in common.

[0207] For example, the circuit board may include a first through electrode 131. The first through electrode 131 may penetrate the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit pattern layer 121 and the second circuit pattern layer 122. For example, an upper surface of the first through electrode 131 may be directly connected to a lower surface of the first circuit pattern layer 121. For example, a lower surface of the first through electrode 131 may be directly connected to an upper surface of the second circuit pattern layer 122. The first circuit pattern layer 121 and the second circuit pattern layer 122 may be electrically connected to each other through the first through electrode 131 to transmit signals.

[0208] For example, the circuit board may include a second through electrode 132. The second through electrode 132 may penetrate the second insulating layer 112. The second through electrode 132 may electrically connect the second circuit pattern layer 122 and the third circuit pattern layer 123. For example, the upper surface of the second through electrode 132 may be directly connected to the lower surface of the second circuit pattern layer 122. For example, the lower surface of the second through electrode 132 may be directly connected to the upper surface of the third circuit pattern layer 123. As a result, the second circuit pattern layer 122 and the third circuit pattern layer 123 may be directly electrically connected to each other via the second through electrode 132, thereby transmitting signals.

[0209] For example, the circuit board may include a third through electrode 133. The third through electrode 133 is formed to penetrate the third insulating layer 113. The third through electrode 133 may electrically connect the third circuit pattern layer 123 and the fourth circuit pattern layer 124. For example, an upper surface of the third through electrode 133 may be directly connected to a lower surface of the third circuit pattern layer 123. For example, a lower surface of the third through electrode 133 may be directly connected to an upper surface of the fourth circuit pattern layer 124. As a result, the third circuit pattern layer 123 and the fourth circuit pattern layer 124 may be electrically connected to each other and transmit signals.

[0210] The first through electrode 131, the second through electrode 132, and the third through electrode 133 are formed by filling through holes that penetrate the insulating layer 110 with a conductive material.

[0211] The through-holes can be formed by any one of mechanical, laser, and chemical processing methods, for example, milling, drilling, routing, UV laser, CO2 laser, aminosilane chemicals, and ketone chemicals.

[0212] The metal material forming the through electrode may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).The conductive material may be filled into the through hole by any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing.

[0213] Meanwhile, the first through-hole electrode 131, the second through-hole electrode 132, and the third through-hole electrode 133 may have widths corresponding to each other.

[0214] For example, the first through electrode 131 may have a slope in which its width increases from a region adjacent to the first circuit pattern layer 121 toward the second circuit pattern layer 122. For example, the first through electrode 131 may have a slope in which its width increases from an upper surface adjacent to the first circuit pattern layer 121 toward a lower surface adjacent to the second circuit pattern layer 122.

[0215] The width W6 of the upper surface of the first through electrode 131 can be in the range of 30 μm to 50 μm. For example, the width W6 of the upper surface of the first through electrode 131 can be in the range of 30 μm to 45 μm. For example, the width W6 of the upper surface of the first through electrode 131 can be in the range of 30 μm to 40 μm. Furthermore, the width W7 of the lower surface of the first through electrode 131 can be in the range of 40 μm to 65 μm. For example, the width W7 of the lower surface of the first through electrode 131 can be in the range of 40 μm to 60 μm. For example, the width W7 of the lower surface of the first through electrode 131 can be in the range of 40 μm to 55 μm. If the widths W6 and W7 of the upper and lower surfaces of the first through electrode 131 are out of the above ranges, the first through electrode 131 will not be able to penetrate the first insulating layer 111. If the widths W6 and W7 of the upper and lower surfaces of the first through-hole electrodes 131 are out of the above ranges, the signal transmission characteristics will be degraded. If the widths W6 and W7 of the upper and lower surfaces of the first through-hole electrodes 131 are out of the above ranges, the pitch between the plurality of first through-hole electrodes will be increased, thereby reducing the circuit integration density.

[0216] On the other hand, the circuit board of the embodiment may include a protective layer.

[0217] The protective layer may include a first protective layer 150 disposed on the insulating layer 110. The protective layer may also include a second protective layer 160 disposed below the insulating layer 110.

[0218] For example, the first protective layer 150 is disposed on the first insulating layer 111, and the second protective layer 160 is disposed below the third insulating layer 113.

[0219] The first protective layer 150 and the second protective layer 160 may be, but are not limited to, a solder resist.

[0220] The first protective layer 150 may include at least one first opening 150a. The first opening 150a of the first protective layer 150 may vertically overlap the pad 121-1. Furthermore, the width W5 of the first opening 150a of the first protective layer 150 may be greater than the width W4 of the second metal layer 121-1b of the pad 121-1. At least a portion of the side surface of the second metal layer 121-1b of the pad 121-1 may not contact the first protective layer 150.

[0221] Meanwhile, the second protective layer 160 may include at least one second opening 160a.

[0222] The first protective layer 150 and the second protective layer 160 may include an epoxy acrylate resin. More specifically, the first protective layer 150 and the second protective layer 160 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 150 and the second protective layer 160 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0223] The first protective layer 150 and the second protective layer 160 may each have a thickness of 1 μm to 20 μm. The first protective layer 150 and the second protective layer 160 may each have a thickness of 1 μm to 15 μm. For example, the first protective layer 150 and the second protective layer 160 may each have a thickness of 5 μm to 20 μm.

[0224] If the thickness of each of the first protective layer 150 and the second protective layer 160 exceeds 20 μm, the thickness of the semiconductor package increases, making it difficult to make it thinner, or greater stress is applied to the insulating layer disposed between the first protective layer 150 and the second protective layer 160. If the thickness of the first protective layer 150 and the second protective layer 160 is less than 1 μm, the circuit pattern layer included in the substrate is not stably protected, resulting in reduced electrical or physical reliability.

[0225] Meanwhile, in an embodiment, the circuit pattern layer and the through-electrode may have a multi-layer structure, however, in an embodiment, the pad 121-1 of the first circuit pattern layer 121 may have a multi-layer structure, and the trace 121-1 of the circuit pattern layer 121 may have a single-layer structure.

[0226] Referring to FIG. 7, the first circuit pattern layer 121 may have a different layer structure from the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer .

[0227] The pad 121-1 of the first circuit pattern layer 121 may include a first metal layer 121-1a and a second metal layer 121-1b, and the trace 121-1 of the first circuit pattern layer 121 may include only a layer corresponding to a portion of the first metal layer 121-1a of the pad 121-1.

[0228] Alternatively, the second circuit pattern layer 122, the third circuit pattern layer 123, and the fourth circuit pattern layer 124 may each include a seed layer and an electroplating layer.

[0229] For example, the second circuit pattern layer 122 may include a seed layer 122-1 and an electrolytic plating layer 122-2. For example, the third circuit pattern layer 123 may include a seed layer 123-1 and an electrolytic plating layer 123-2. For example, the fourth circuit pattern layer 124 may include a seed layer 124-1 and an electrolytic plating layer 124. Correspondingly, the vias included in the circuit board may include a seed layer and an electrolytic plating layer. For example, the first through electrode 131 may include a seed layer 131-1 and an electrolytic plating layer 131-2. For example, the second through electrode 132 may include a seed layer 132-1 and an electrolytic plating layer 132-2. For example, the third through electrode 133 may include a seed layer 133-1 and an electrolytic plating layer 133-2.

[0230] Meanwhile, when the circuit board of the embodiment is manufactured by the MSAP method, at least one of the second circuit pattern layer, the third circuit pattern layer, and the fourth circuit pattern layer may further include a metal layer corresponding to the copper foil layer.

[0231] 8A, in the previous embodiment, the vertical cross-sectional shapes of the pad 121-1 and the trace 121-1 of the first circuit pattern layer 121 were each rectangular. In this case, a portion of the first metal layer 121-1a and the second metal layer 121-1b of the pad 121-1 of the first circuit pattern layer 121 of the embodiment are removed by etching.

[0232] Therefore, a portion of the first metal layer 121-1a and the second metal layer 121-1b of the pad 121-1 of the first circuit pattern layer 121 may include curved side surfaces that are removed by etching.

[0233] For example, a portion of the side surface of the first metal layer 121-1a of the pad 121-1 may be removed by etching, so that the side surface 121-1aS has a curved surface with a curvature in the thickness direction.

[0234] In addition, the second metal layer 121-1b of the pad 121-1 can be removed by etching to include a curved side surface 121-1bS having a curvature in the thickness direction.

[0235] In this case, at least a portion of the first protective layer 150 may contact a side surface 121-1aS of the first metal layer 121-1a of the pad 121-1. For example, at least a portion of the side surface 121-1aS of the first metal layer 121-1a of the pad 121-1 is covered with the first protective layer 150. In this case, the inner wall of the opening of the first protective layer 150 may be inclined at a right angle to the top surface of the first insulating layer 111. Alternatively, the inner wall of the opening of the first protective layer 150 may be inclined in a specific direction rather than at a right angle. This will be described below.

[0236] In addition, the lower surface of the first protective layer 150 may have a step. That is, the first metal layer 121-1a of the pad 121-1 may include a step portion 121SP. As a result, a step is also provided between the upper surface of the first insulating layer 111 and the first metal layer 121-1a of the pad 121-1. Therefore, the first protective layer 150 may include a first portion disposed on the upper surface of the first insulating layer 111 and a second portion disposed on the step portion 121SP. The first and second portions of the first protective layer 150 may have a step.

[0237] In addition, the first insulating layer 111 may include an inner surface that horizontally overlaps the stepped portion 121SP. The inner surface of the first insulating layer 111 may refer to a portion to which the top surface of the first insulating layer 111 is connected and that does not contact the first metal layer 121-1a of the pad 121-1. The first protective layer 150 may be in contact with the inner surface of the first insulating layer 111. For example, the inner surface of the first insulating layer 111 is covered with the first protective layer 150.

[0238] Therefore, in this embodiment, at least a portion of the first protective layer 150 is disposed to cover the inner surface of the first insulating layer 111, thereby increasing the bonding area between the first insulating layer 111 and the first protective layer 150 and improving adhesion. Also, a connecting member such as solder disposed on the pad 121-1 can be prevented from penetrating into the interface between the first protective layer 150 and the first insulating layer 111. This can further improve the physical reliability and / or electrical reliability of the circuit board.

[0239] 8b, the inner wall 150S of the opening in the first protective layer 150 may have a slope. For example, the widths of the openings in the first protective layer 150 may be different from each other in the vertical direction. In this regard, although the drawing shows the inner wall 150S of the opening in the first protective layer 150 having a curved slope in the vertical direction, this is not limited thereto. For example, the inner wall 150S of the opening in the first protective layer 150 may have a linear slope inclined in a specific direction.

[0240] Meanwhile, the opening of the first protective layer 150 may include a region whose width varies. For example, the width of the opening of the first protective layer 150 may vary from the upper surface of the first protective layer 150 to the lower surface of the first protective layer 150. Preferably, the width of the opening of the first protective layer 150 decreases from the upper surface of the first protective layer 150 to the lower surface of the first protective layer 150.

[0241] For example, the upper width W8 and the lower width W9 of the opening of the first protective layer 150 may be different. The upper width W8 of the opening of the first protective layer 150 may be larger than the lower width W9 of the opening of the first protective layer 150.

[0242] For example, the upper width W8 of the opening in the first protective layer 150 may be larger than the width W1 of the first metal layer 121-1a of the pad 121-1. For example, the lower width W9 of the opening in the first protective layer 150 may be smaller than the width W1 of the first metal layer 121-1a of the pad 121-1. Therefore, at least a portion of the side surface 121-1aS of the first metal layer 121-1a of the pad 121-1 is covered with the first protective layer 150.

[0243] As described above, the embodiment allows a larger amount of solder to be placed within the limited opening area by adjusting the upper width W8 and the lower width W9 of the opening in the first protective layer 150. This allows the embodiment to improve the bonding strength between the solder and the pad 121-1, and ultimately improve the bonding strength between the solder and the semiconductor element.

[0244] Meanwhile, referring to FIG. 9, a surface treatment layer 170 is disposed on the pads 121-1 of the first circuit pattern layer 121.

[0245] The surface treatment layer 170 is disposed on the first metal layer 121-1a and the second metal layer 121-1b of the pad 121-1.

[0246] The surface treatment layer 170 may be divided into a plurality of portions. For example, the surface treatment layer 170 may include a first portion provided on the stepped portion 121SP of the first metal layer 121-1a of the pad 121-1, a second portion provided on the side surface of the second metal layer 121-1b of the pad 121-1, and a third portion provided on the top surface of the second metal layer 121-1b of the pad 121-1.

[0247] The surface treatment layer 170 may be an organic solderability preservative (OSP) layer. For example, the surface treatment layer 170 may be an organic coating layer coated with an organic substance such as benzimidazole. However, the embodiment is not limited thereto. For example, the surface treatment layer 170 may be a plating layer. For example, the surface treatment layer 170 may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0248] On the other hand, the thickness of the surface processing layer 170 may be smaller than the thickness T1-2 of the stepped portion 121SP, and may also be smaller than the thickness T1-3 of the second metal layer 121-1b of the pad 121-1.

[0249] For example, the surface treatment layer 170 may include a portion disposed on the stepped portion 121SP of the first metal layer 121-1a of the pad 121-1. In this case, the thickness of the surface treatment layer 170 disposed on the stepped portion 121SP may be smaller than the thickness T1-2 of the stepped portion 121SP. Therefore, the upper surface of the surface treatment layer 170 may be positioned lower than the upper surface of the first insulating layer 111 within the stepped portion 121SP. As a result, the embodiment may prevent at least a portion of the surface treatment layer 170 from extending onto the upper surface of the first insulating layer 111 beyond the stepped portion 121SP. That is, the width of the portion of the surface treatment layer 170 disposed on the stepped portion 121SP may be the same as the width of the stepped portion 121SP. That is, the surface treatment layer 170 does not extend onto the area beyond the stepped portion 121SP. As a result, the embodiment may solve the problem of short circuits, which may occur when adjacent pads are electrically connected to each other by the surface treatment layer 170, thereby improving electrical reliability. Furthermore, in this embodiment, since the numerical value due to the expansion of the surface treatment layer 170 does not need to be considered, the pitch between the pads can be further reduced.

[0250] Referring to FIG. 10, the width of the second metal layer 121-1b of the pad 121-1 in the previous embodiment is smaller than the width of the first metal layer 121-1a.

[0251] Unlike the first embodiment, the circuit board of the second embodiment may include a first circuit pattern layer 221 disposed on a first insulating layer 211. The first circuit pattern layer 221 may include a pad 221-1 including a first metal layer 221-1a and a second metal layer 221-1b. The circuit board may also include a second insulating layer 212 disposed below the first insulating layer 211, a second circuit pattern layer 222 disposed between the first insulating layer and the second insulating layer, and a first through electrode 231 that penetrates the first insulating layer 211. The circuit board may also include a surface treatment layer 270 disposed on the pad 221-1.

[0252] In this case, the first metal layer 221-1a of the pad 221-1 may not have a step. For example, the top surface of the first metal layer 221-1a of the pad 221-1 may be flat. For example, the top surface of the first metal layer 221-1a of the pad 221-1 may be located on the same plane as the top surface of the first insulating layer 211. This is because the second metal layer 221-1b is disposed on the first metal layer 221-1a of the pad 221-1 with a width greater than that of the first metal layer 221-1a. As a result, the first metal layer 221-1a is not removed during the etching process of the second metal layer 221-1b, and therefore the top surface of the first metal layer 221-1a may not have a step.

[0253] A second metal layer 221-1b is disposed on the first metal layer 221-1a of the pad 221-1. For example, the second metal layer 221-1b may include a first region that vertically overlaps the first metal layer 221-1a and a second region that extends horizontally from the first region and does not vertically overlap the first metal layer 221-1a. This allows the surface treatment layer 270 to be out of contact with the first metal layer 221-1a of the pad 221-1.

[0254] In addition, the circuit board of the embodiment may have a structure that combines the embodiments of Figures 9 and 10. For example, in a section requiring a fine pitch, it may have the structure shown in Figure 9, and in a section requiring a wide pitch, it may have the structure shown in Figure 10. In addition, when etching to form pads (preferably, when performing a process of forming a second metal layer of the pad), the width of the photoresist for etching can be adjusted to realize pad shapes of different embodiments on the same surface, thereby increasing the degree of freedom in circuit design.

[0255] The circuit board of the embodiment may include a first insulating layer and a first circuit pattern layer including a pad disposed on the first insulating layer. The pad may include a first metal layer at least partially embedded in the first insulating layer and a second metal layer disposed on the first metal layer and protruding above the first insulating layer, the second metal layer having a thickness smaller than that of the first metal layer. In this case, the first metal layer of the pad may be an electroplated layer formed by electroplating using the second metal layer of the pad as a seed layer. The second metal layer of the pad may be a seed layer used for electroplating the first metal layer of the pad. That is, the second metal layer of the pad may be an electroless plated layer or a copper foil layer.

[0256] In addition, in an embodiment, a portion of a seed layer used to form a pad of a circuit pattern layer having an ETS structure is not removed. For example, a portion of the seed layer may constitute a second metal layer that functions as a bump of a pad of a first circuit pattern layer. That is, the second metal layer of the pad may function as a bump for disposing a connection member on the pad. As a result, in an embodiment, the second metal layer used to electrolytically plate the first metal layer of the pad can be used as the pad bump. As a result, in an embodiment, the time, material, and cost required for additionally forming a bump can be saved.

[0257] Also, the embodiment can improve the bonding strength between the first metal layer of the pad and the second metal layer that functions as a bump.

[0258] For example, in the comparative example, a separate plating process is performed on the pad to form the bump. As a result, the pad may include a seed layer and an electrolytic plating layer used for plating the bump. As a result, in the comparative example, the adhesive strength between the pad, the seed layer of the bump, and the electrolytic plating layer of the bump is reduced, which in turn reduces the physical and electrical reliability of the circuit board.

[0259] In contrast, in the embodiment, the second metal layer corresponding to the bump can be formed using the copper foil layer, which is the seed layer used for electrolytic plating of the first metal layer of the pad, thereby improving the bonding strength and adhesion between the second metal layer functioning as the bump and the first metal layer of the pad.

[0260] In addition, the embodiment may minimize height deviation of the bumps. For example, the second metal layer of the pad may be a copper foil layer provided on the carrier board. As a result, the copper foil layer may have a uniform thickness and height. In addition, the embodiment may form the second metal layer of the pad, which functions as a bump, by etching away the copper foil layer. In this case, a plurality of pads may be provided on the circuit board. In this case, the second metal layer of each of the plurality of pads may correspond to the copper foil layer. As a result, in the embodiment, the second metal layer of each of the plurality of pads may have a uniform thickness and height. As a result, the embodiment may improve the bonding strength of a semiconductor device or an external substrate disposed on the pad. Furthermore, the embodiment may allow the semiconductor device or the external substrate to be stably bonded to the pad. As a result, the embodiment may improve the electrical reliability and / or physical reliability of the semiconductor device or the external substrate. As a result, the embodiment may improve the product reliability of the semiconductor package.

[0261] In addition, the embodiment may form a second metal layer corresponding to the bump of the pad by etching a seed layer of the first metal layer of the pad, thereby reducing the width of the second metal layer of the pad that functions as a bump.

[0262] This allows the embodiment to further reduce the pitch between the pads. For example, the pad pitch may be determined based on the pitch between the second metal layers of the respective pads. For example, if the pitch between the first metal layers of the pads can be reduced but the pitch between the second metal layers cannot be reduced, the pad pitch must be increased to correspond to the pitch of the second metal layer.

[0263] In contrast, in the embodiment, the width of the bumps can be reduced by etching the second metal layer used as a seed layer. This allows the pitch between the second metal layer of the plurality of pads to be reduced. This also allows the pitch between the first metal layer of the plurality of pads to be reduced. Therefore, the embodiment can reduce the pitch between the plurality of pads. This allows the embodiment to further improve the circuit integration and reduce the volume of the circuit board and the semiconductor package.

[0264] <Package substrate> 11 is a diagram illustrating an example of a package substrate according to an embodiment. Here, the package substrate may have a structure in which a semiconductor device is disposed on a first substrate or a second substrate as illustrated in any one of FIGS. 2a to 2g.

[0265] Referring to FIG. 11, an example package substrate can include the circuit board of FIG.

[0266] The package substrate may include a first connection member 310. The first connection member 310 is disposed on the second metal layer 121-1b of the pad 121-1 of the circuit board. Preferably, the first connection member 310 is disposed in the first opening 150a of the first protective layer 150.

[0267] As a result, the first connection member 310 is provided to surround at least a portion of the side surface of the second metal layer 121-1b of the pad 121-1. The first connection member 310 is also disposed on the step portion 121SP of the first metal layer 121-1a of the pad 121-1. The step portion 121SP of the first metal layer 121-1a can function to block the flow of the first connection member 310.

[0268] A first semiconductor element 320 is disposed on the first connection member 310. The first semiconductor element 320 may be a logic chip. A terminal 325 of the first semiconductor element 320 is electrically connected to a pad 121-1 of the circuit board via the first connection member 310.

[0269] Although the drawings illustrate one semiconductor device disposed on a circuit board, this is not limiting. For example, at least two semiconductor devices spaced apart from each other in the horizontal direction may be disposed on the circuit board. In this case, the circuit board may include a connecting member (e.g., a bridge board).

[0270] Meanwhile, a second connection member 340 is disposed in the opening of the second protective layer 160. The second connection member 340 may be for connecting to a main board (or mother board) of an external device.

[0271] In addition, a molding member 330 is disposed on the circuit board. The molding member 330 is disposed to cover the first semiconductor element 320 and the first connecting member 310.

[0272] In this case, the molding member 330 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding member 330 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding member 330 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding member 330 may be 0.8 to 5. Thus, in this embodiment, the molding member 330 has a low dielectric constant, thereby enhancing the heat dissipation characteristics of the semiconductor device.

[0273] <Manufacturing method> A method for manufacturing a circuit board according to an embodiment will be described below. Specifically, the method for manufacturing a circuit board shown in FIG. 3 will be described in order of steps.

[0274] 12 to 23 are cross-sectional views showing the manufacturing method of the circuit board shown in FIG. 3 in the order of steps.

[0275] Referring to FIG. 12, in an embodiment, basic materials for manufacturing a circuit board can be prepared using the ETS method.

[0276] For example, in an embodiment, a carrier board 410 may be prepared, including a carrier insulating layer 411 and a metal layer 412 disposed on at least one surface of the carrier insulating layer 411. In this case, the metal layer 412 may be disposed on only one of the first and second surfaces of the carrier insulating layer 411, or may be disposed on both surfaces. For example, the metal layer 412 may be disposed on only one surface of the carrier insulating layer 411, thereby allowing an ETS process for manufacturing a circuit board to be performed on only one surface. Alternatively, the metal layer 412 may be disposed on both surfaces of the carrier insulating layer 411, thereby allowing an ETS process for manufacturing a circuit board to be performed simultaneously on both surfaces of the carrier board 410. In this case, two circuit boards may be manufactured at one time.

[0277] The metal layer 412 may be formed by electroless plating on the carrier insulating layer 411. Alternatively, the carrier insulating layer 411 and the metal layer 412 may be CCL (Copper Clad Laminate). That is, the metal layer 412 may be a copper foil layer. For example, the metal layer 412 may be copper foil. For example, the metal layer 412 may be an electroless plating layer formed on the carrier insulating layer 411. That is, the metal layer 412 is the first metal layer formed in the circuit board manufacturing process. The metal layer 412 can be used as a seed layer for the first metal layer 121-1a of the first circuit pattern layer 121 formed in a subsequent process. The metal layer 412 may ultimately constitute the second metal layer 121-1b of the pad 121-1 of the first circuit pattern layer 121.

[0278] 13, in this embodiment, a first circuit pattern layer 121 is formed under the metal layer 412. The process of forming the first circuit pattern layer 121 can be performed by electrolytic plating using the metal layer 412 as a seed layer under the metal layer 412. For this purpose, a mask (not shown) including an open region corresponding to the region where the first circuit pattern layer 121 will be disposed is disposed under the metal layer 412.

[0279] In this embodiment, a curing process of heat-treating the mask may be additionally performed before the electrolytic plating process of the first circuit pattern layer 121. For example, in this embodiment, a mask curing process may be performed after the mask exposure and development processes. The mask curing process may include curing using ultraviolet light and curing using infrared light. For example, in this embodiment, the mask may be cured using ultraviolet light in a range of 5 mV to 100 mV. Alternatively, in this embodiment, the mask may be cured by infrared thermal curing. As described above, in this embodiment, the mask curing process may be additionally performed to improve the adhesive strength between the metal layer 412 and the mask. As a result, in this embodiment, the first circuit pattern layer 121 can be miniaturized due to the improved adhesive strength between the mask and the metal layer 412. In this embodiment, the process of forming the first circuit pattern layer 121 may be a process of essentially forming the first metal layer 121-1a and the trace 121-1 of the pad 121-1 of the first circuit pattern layer 121.

[0280] Next, referring to FIG. 14 , in an embodiment, once the first circuit pattern layer 121 is formed, the mask may be removed. Thereafter, in an embodiment, a process of pre-treating the first circuit pattern layer 121 may be performed. For example, in an embodiment, a process of imparting a certain level of surface roughness to the surface of the first circuit pattern layer 121 may be performed. For example, in an embodiment, the first circuit pattern layer 121 may be surface-treated so that the surface of the first circuit pattern layer 121 has a 10-point average surface roughness (Rz) ranging from 0.01 μm to 0.5 μm. Thereafter, in an embodiment, a first insulating layer 111 may be formed under the metal layer 412 to cover the first circuit pattern layer 121.

[0281] 15, in this embodiment, a process of forming through holes VH in the first insulating layer 111 can be performed. The through holes VH can be formed by laser processing, but the method is not limited to this.

[0282] Next, referring to FIG. 16, in the embodiment, a process of forming the first through electrode 131 and the second circuit pattern layer 122 may be performed.

[0283] Specifically, in this embodiment, a seed layer is formed on the lower surface of the first insulating layer 111 and the inner wall of the through hole VH. Thereafter, in this embodiment, a process of forming the second circuit pattern layer 122 and the first through electrode 131 by electrolytic plating using the seed layer may be performed.

[0284] Next, referring to FIG. 17, an embodiment may perform a step of forming a second insulating layer 112 under the first insulating layer 111.

[0285] Referring now to Figure 18, in this embodiment, the steps of Figures 15 and 16 can be repeated to form a second through electrode 132 that penetrates the second insulating layer 112 and a third circuit pattern layer 123 that protrudes from the underside of the second insulating layer 112.

[0286] Referring now to FIG. 19, an embodiment may perform additional lamination steps by repeating the steps illustrated in FIGS.

[0287] Specifically, in this embodiment, a process of forming a third insulating layer 113 covering the third circuit pattern layer 123 on the lower surface of the second insulating layer 112 may be performed. Next, in this embodiment, a process of forming a third through electrode 133 penetrating the third insulating layer 113 and a fourth circuit pattern layer 124 protruding from the lower surface of the third insulating layer 113 may be performed.

[0288] 20 , in an embodiment, a step of removing the carrier board from the circuit board manufactured as described above can be performed. For example, in an embodiment, a step of separating the carrier insulating layer 411 and the metal layer 412 from the carrier board 410 can be performed. As a result, the metal layer 412 included in the carrier board remains on the outermost side of the circuit board of the embodiment.

[0289] 21, in this embodiment, a process of forming a mask 420 on the upper surface of the metal layer 412 may be performed. At this time, the mask 420 is formed to a certain thickness on the metal layer 412. At this time, the mask 420 may cover a region of the upper surface of the metal layer 412 corresponding to the second metal layer 121-1b of the pad 121-1.

[0290] 22, in an embodiment, a process may be performed in which a portion of the metal layer 412 not covered by the mask 420 is etched away to form the second metal layer 121-1b of the pad 121-1 of the first circuit pattern layer 121. As a result, in an embodiment, the second metal layer 121-1b of the pad 121-1, which functions as a bump, may be formed using the seed layer used in forming the first circuit pattern layer 121.

[0291] 23, an embodiment may perform a process of forming a first protective layer 150 including a first opening 150a on the first insulating layer 111. Also, an embodiment may perform a process of forming a second protective layer 160 including a second opening 160a under the third insulating layer 113.

[0292] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stabilize functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, or electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functions in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0293] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0294] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in another embodiment by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

[0295] The above description has focused on the embodiments, but these are merely illustrative and do not limit the present invention. A person skilled in the art to which the present invention pertains may make various modifications and applications not exemplified above within the scope of the essential characteristics of the present embodiments. For example, each component specifically presented in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the present invention as defined by the appended claims.

Claims

1. a first insulating layer; a pad disposed on the first insulating layer; the pad includes a first metal layer at least partially or entirely embedded in an upper surface of a first insulating layer, and a second metal layer disposed on the first metal layer and protruding above the first insulating layer; The thickness of the second metal layer is different from the thickness of the first metal layer.

2. The circuit board of claim 1 , wherein the thickness of the second metal layer is less than the thickness of the first metal layer.

3. The circuit board according to claim 1 , wherein the top surface of the first metal layer has a step.

4. the first metal layer of the pad includes a first portion that vertically overlaps the second metal layer and contacts the second metal layer, and a second portion that does not vertically overlap the second metal layer; The circuit board according to claim 3 , wherein an upper surface of the first portion is located higher than an upper surface of the second portion.

5. 5. The circuit board of claim 4, wherein a top surface of the first portion of the first metal layer is coplanar with a top surface of the first insulating layer.

6. the first metal layer is an electroplated layer, The circuit board according to claim 1 , wherein the second metal layer is a seed layer for electrolytic plating of the first metal layer.

7. 5. The circuit board according to claim 4, wherein the thickness of the pad satisfies the range of 10 μm to 35 μm.

8. 8. The circuit board according to claim 7, wherein the thickness of the first portion of the first metal layer satisfies the range of 8 μm to 25 μm.

9. 8. The circuit board according to claim 7, wherein the thickness of the second portion of the first metal layer satisfies the range of 6 μm to 21 μm.

10. 9. The circuit board according to claim 7, wherein the difference in thickness between the first portion and the second portion of the first metal layer is in the range of 2 μm to 4 μm.

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