Backside contacts for signal routing

Abstract

A cell layout that can be implemented in FinFET devices or other FET devices is disclosed. The cell layout utilizes an insulated gate structure to provide routing between a signal input of an active gate and a backside metal layer. The insulated gate structure includes a metal fill surrounded by a gate spacer. The metal fill connects between an upper layer within the device and a backside layer within the device. The metal fill can be connected to the signal input of the active gate via routing in either the upper metal layer or a metal wire disposed within the upper insulating layer. The insulated gate structure can be part of any standard cell located at the cell boundary or inside the cell to provide access to backside signal routing. Additionally, filler cells with insulated gate structures can provide backside routing connections for adjacent functional cells.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate to signal routing in semiconductor devices. More particularly, the embodiments described herein relate to signal routing through backside layers of integrated circuits. [Background technology]

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell methodology is to reduce the size of the standard cell while increasing the complexity (e.g., circuit density and number of components) within the standard cell. However, as standard cell designs become smaller, it becomes more difficult to provide access (e.g., connections) to the components within the standard cell. Summary of the Invention

[0003] Furthermore, the performance of a standard cell can become more affected by characteristics within the cell as the size of the standard cell decreases. For example, resistance within a standard cell, such as a metal trace or an interface between a diffusion region and a metal trace within the cell, can reduce the performance of the cell, and as cells become smaller, the impact on performance becomes more of an issue. Therefore, reducing the trace resistance within a standard cell can improve the performance of the cell.

[0004] The features and advantages of the method and apparatus of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred, but nevertheless exemplary, embodiments in accordance with the embodiments described in this disclosure, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates a diagram of an embodiment of a standard cell with backside layer power connections, according to some embodiments.

[0006] [Figure 2] 2 illustrates a cross-sectional view of a standard cell taken along section line 2-2 shown in FIG. 1, according to some embodiments.

[0007] [Figure 3] 1 illustrates a diagram of an embodiment of a cell having routing between an active gate and a backside metal layer through an insulated gate structure, according to some embodiments.

[0008] [Figure 4] 4 illustrates a cross-sectional view of a cell taken along section line 4-4 shown in FIG. 3, according to some embodiments.

[0009] [Figure 5] 1 illustrates a diagram of an embodiment of a cell having alternative routing between an active gate and an insulated gate structure, according to some embodiments.

[0010] [Figure 6] 6 illustrates a cross-sectional view of a cell taken along section line 6-6 shown in FIG. 5, according to some embodiments.

[0011] [Figure 7] 1 illustrates a cross-sectional view of a cell with a gate contact connecting to a signal input and source / drain of an active gate according to some embodiments.

[0012] [Figure 8] 1 illustrates a diagram of an embodiment of an integrated circuit layout having an insulated gate with signal routing on both the top and bottom layers, according to some embodiments.

[0013] [Figure 9] 1 illustrates a diagram of top-side signal tracks in an integrated circuit layout having top-side-only signal routing, according to some embodiments.

[0014] [Figure 10]1 illustrates a diagram of topside and backside signal tracks in an integrated circuit layout having topside and backside signal routing, according to some embodiments.

[0015] [Figure 11] 1 illustrates a cross-sectional view of an integrated circuit device having both types of routing connections between a signal input on an active gate and a metal fill in an insulated gate, according to some embodiments.

[0016] [Figure 12] 1 illustrates a top view of an integrated circuit layout having functional cells and filler cells according to some embodiments.

[0017] [Figure 13] 1 illustrates a cross-sectional view of a filler cell having an insulated gate structure to provide backside access, according to some embodiments.

[0018] [Figure 14] FIG. 1 is a block diagram of one embodiment of an exemplary system. DETAILED DESCRIPTION OF THE INVENTION

[0019] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, the present application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure, as defined by the appended claims.

[0020] The present disclosure is directed to the use of backside metal layers to provide control signal connections to transistors within integrated circuit cells (such as standard cells). As used herein, the term "standard cell" refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. Embodiments of the circuit design cells described herein may be implemented in various implementations of logic or memory integrated circuits.

[0021] Many current designs of cells provide connections and routing for power or signals to transistors or other structures in regions above the transistors. For example, connections and routing for power or signals may be provided in an upper layer of the device (e.g., a layer above the active layer of the transistors in the device when viewed in a typical cross-sectional view). As used herein, the term "upper side" refers to a region in the device that is vertically above the active layer of the device (e.g., above the transistor region of the device). For example, the upper side may refer to components such as contacts or layers that are above the transistor region in the vertical dimension, as shown in the figures and described herein. In some cases, the term "front side" may be used interchangeably with the term "upper side."

[0022] Some recent advances for standard cell design move connections and routing for power connections to metal layers below the transistors. For example, connections and routing for power may be provided in the backside layer of the device (e.g., a layer below the active layer of the transistor in the device when viewed in a typical cross-sectional view). As used herein, the term "backside" refers to a region within a device that is vertically below the active layer of the device (e.g., below the transistor region of the device). For example, backside may refer to components such as contacts or layers that are below the transistor region in the vertical dimension, as shown in the figures and described herein. Note that, as used herein, backside elements disposed below the active layer may be located on, within, or below the silicon substrate on which the active layer is fabricated. That is, as used herein, "backside" refers to the active layer rather than the silicon substrate.

[0023] FIG. 1 shows a diagram of one embodiment of a standard cell with backside layer power connections, according to some embodiments. For simplicity of illustration, the representation of the cell disclosed herein shows only components relevant to the present disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein. For example, in FIG. 1, a gate extending vertically in the drawing is visible in some depictions. In FIG. 1, (A) is a top view of an embodiment of a standard cell 100, and (B) is a bottom view of an embodiment of the standard cell. FIG. 2 shows a cross-sectional view of the standard cell 100 along section line 2-2 shown in FIG. 1, according to some embodiments. Section line 2-2 is located across the power rail of the backside metal layer 126, as shown in FIG. 1B. FIG. 1B shows a diagram of a backside via 128, which will be further described below.

[0024] In the illustrated embodiment of FIG. 2 , standard cell 100 includes substrate 102. In particular embodiments, substrate 102 is a silicon substrate. In various embodiments, substrate 102 may include additional components or features for implementation in cell 100. For example, substrate 102 may include an insulating layer 104 (e.g., an oxide layer), a diffusion (e.g., oxide diffusion) region, or a doped region for implementation in cell 100. For simplicity of illustration, substrate 102 and insulating layer 104 are shown as single layers. In some embodiments, insulating layer 104 may include multiple insulating layers. For example, insulating layer 104 may include multiple oxide layers, multiple nitride layers, or a combination of various insulating layers.

[0025] In various embodiments, standard cell 100 includes a device 106 formed on a substrate 102. Device 106 may be a transistor, such as, for example, a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("gate-all-around" FET) device. Other embodiments of transistor devices may also be contemplated. In various embodiments, device 106 includes a gate 108, gate spacers 110, source / drain regions 112, and source / drain contacts 114 formed on substrate 102.

[0026] In certain embodiments, the gate 108 (e.g., gates 108A, 108B) is the active gate of the device 106. The gate 108 may be, for example, a polyline (e.g., a polysilicon layer or a metal layer). Gate spacers 110 may be disposed between the gate 108 and the source / drain regions 112. In various embodiments, the gate spacers 110 are formed as part of the gate 108 (e.g., the gate and the spacers are formed in the same process flow). The source / drain regions 112 (e.g., source / drain regions 112A, 112B, 112C) are disposed on the sides of the gate 108 and the spacers 110. The source / drain regions 112 may be, for example, epitaxial layers grown on a fin or nanosheet stack or any 2D (two-dimensional) channel material. Various embodiments are also contemplated in which the source / drain regions 112 are at least partially disposed within the substrate 102.

[0027] In particular embodiments, an insulated gate 116 is disposed on each side of the device 106. The insulated gate 116 may include a metal fill 118 and a spacer 120. In some embodiments, the insulated gate 116 may include only an insulating material (e.g., the fill 118 is an insulating material). As shown in the illustrated embodiment of FIG. 2, the insulated gate 116 (e.g., gates 116A, 116B) provides insulation on each side of the device 106, and the metal fills 118A, 118B and spacers 120A, 120B extend into the substrate 102 beneath the active area of ​​the device (e.g., beneath the transistors of the device 106). Additionally, the spacer 120 extends into the insulating layer 104 such that the insulated gate 116 defines isolation for the device 106 and provides electrical signal isolation between the device 106 and adjacent devices.

[0028] In particular embodiments, insulating layer 122 and upper metal layer 124 are formed over (e.g., above) device 106 and insulated gate 116. Insulating layer 122 may include one or more insulating layers formed over device 106. For example, insulating layer 122 may include one or more oxide layers. In various embodiments, insulating layer 122 at least partially surrounds or encapsulates regions of device 106 (e.g., gate 108, spacers 110, source / drain regions 112, and contacts 114) and insulated gate 116.

[0029] In the illustrated embodiment, the upper metal layer 124 includes one or more metal layers that provide routing for the device 106 and / or other devices in the cell 100. In various embodiments, the upper metal layer 124 provides routing for connections to control signals to / from the device 106. For example, the gate 108 may be connected to various metal routings in the upper metal layer 124 by vias or other connections through the insulating layer 122. As used herein, the term “metal routing” refers to any combination of metal vias, metal wires, metal traces, etc. that provide a path / route between two structures. Additional embodiments may be contemplated in which the metal in the “metal routing” is replaced with an alternative conductive material. For example, the metal in the “metal routing” may be replaced with a superconductor material, a semiconductor material, or a non-metallic conductor.

[0030] In various embodiments of cell 100, a backside metal layer 126 is formed below (e.g., on the backside of) device 106. In particular embodiments, backside metal layer 126 includes one or more metal layers that provide power connections for device 106 (e.g., the backside metal layer is a power rail for device 106). For example, backside metal layer 126 may include one or more metal layers that provide power routing from device 106 to Vdd (e.g., a supply voltage) and Vss (e.g., ground).

[0031] In the illustrated embodiment, power connections to the source / drain regions 112A of the device 106 are made from the backside metal layer 126 by backside vias 128. The backside vias 128 provide connections between the source / drain regions 112A and the backside metal layer 126 through the substrate 102 and the insulating layer 104. In some embodiments, the backside vias 128 are buried vias that extend through the substrate 102 and the insulating layer 104.

[0032] 2, the backside metal layer 126 is formed at or near the bottom surface of the substrate 102. In particular embodiments, the backside metal layer 126 comprises one or more backside layers of the active layers of the device 106 (e.g., the backside metal layer is vertically below the transistor region of the device 106). In some embodiments, the backside metal layer 126 comprises one or more buried layers within the substrate 102 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 126 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments can be envisioned in which the backside metal layer 126 is not disposed within the substrate 102.

[0033] 1 and 2 can improve area utilization within a cell layout. While providing backside power routing provides improved area utilization, further improvements in area utilization can be achieved by routing signal connections (e.g., connections for control signals, data signals, or other signals not related to power) through the backside of the device in addition to the topside of the device. Providing additional signal connections or routing through the cell can reduce RC delays that typically result from resistance in via connections in the upper layers of the cell.

[0034] However, a challenge in routing signals through backside layers is providing a reasonable and implementable approach for routing signals from above the active gate to the backside metal layer. For example, routing signal connections from the gate to the backside layer can place signal and power connections closely together, thereby creating parasitic problems that reduce device reliability. Additionally, forming signal connections from the backside layer to the gate can require highly controlled processes to allow for close placement of signal and power connections, thereby increasing costs and reducing device yield. The present disclosure contemplates utilizing signal paths through isolated regions of the device (e.g., insulated gates) to provide low-resistance routing paths that can be implemented in both logic cell and memory cell designs. The insulated gates may be part of any standard cell located at the cell boundary, as described herein, or may be located inside the cell to provide access for backside signal routing. Providing the signal routing paths described herein can provide better cell performance, power utilization, and area utilization.

[0035] Certain embodiments disclosed herein have three broad elements: 1) a metal layer (e.g., a backside metal layer) disposed below a transistor region of an integrated circuit device; 2) a gate structure formed in the transistor region on the side of an active gate of the transistor, the gate structure including a metal fill disposed between gate spacers, the metal fill connected to the metal layer; and 3) a metal wire disposed over the transistor region, connecting the metal fill to a signal input of the active gate. In certain embodiments, the gate structure is an insulated gate structure disposed on a side of the active region of the integrated circuit device (e.g., on a side of an active gate in the device), and the metal layer is a backside metal layer having wiring for carrying signals (e.g., control signals). In some embodiments, the metal fill is connected to the backside metal layer by a gate contact or other connecting structure.

[0036] In various embodiments, metal wires are disposed in an upper metal layer above the transistor region. Gate contacts or other connecting structures can connect metal fill in the gate structure to the metal wires in the upper metal layer. Thus, the metal fill in the gate structure connects the upper metal layer to the back metal layer via the gate contact. In such embodiments, the gate structure provides a connection path between the signal input of the active gate and the back metal layer, enabling routing of signals from the active gate to signal wiring in the back metal layer.

[0037] In some embodiments, a metal wire is disposed within the insulating layer between the transistor region and the upper metal layer. For example, the metal wire may be a jumper or cross coupler connecting the signal input of the active gate to a metal fill within the gate structure. The metal wire may include a gate contact through the insulating layer to the signal input of the active gate and to the top of the metal fill. The metal wire connecting the signal input of the active gate to the metal fill provides a connection path between the signal input of the active gate and the backside metal layer through the metal fill, allowing routing of a signal from the active gate to a signal wiring within the backside metal layer.

[0038] In short, the inventors have recognized that an insulated gate structure can be utilized to provide a connection path between a signal input of an active gate and a backside metal layer. Utilizing an insulated gate structure has little or no impact on the area cost in an integrated circuit device and does not require significant changes to the process for fabricating the integrated circuit device. The ability to route control signals from the active gate through a backside metal layer within the device structure can improve performance, power utilization, and area scaling in integrated circuit devices, as described herein.

[0039] FIG. 3 shows a diagram of an embodiment of a cell having routing between an active gate and a backside metal layer via an insulated gate structure, according to some embodiments. In FIG. 3, (A) is a top view of an embodiment of cell 200, and (B) is a bottom view of the embodiment of the cell. FIG. 4 shows a cross-sectional view of cell 200 along section line 4-4 shown in FIG. 3, according to some embodiments. Section line 4-4 is located across signal portions of top metal layer 224 and backside metal layer 226, as shown in FIG. 3B. FIG. 3A shows a diagram of gate contacts 227A, 227B, which are described further below, and FIG. 3B shows a diagram of gate contact 228, which is also described further below.

[0040] In the illustrated embodiment of FIG. 4 , cell 200 includes a substrate 202. In certain embodiments, substrate 202 is a silicon substrate. In various embodiments, substrate 202 may include additional components or features for implementation in cell 200. For example, substrate 202 may include an insulating layer 204, a diffusion region, or a doped region for implementation in cell 200. In certain embodiments, insulating layer 204 includes one or more oxide layers. For simplicity of illustration, substrate 202 and insulating layer 204 are shown as single layers. In some embodiments, insulating layer 204 may include multiple insulating layers (e.g., multiple oxide layers).

[0041] In the illustrated embodiment, cell 200 includes a device 206 formed on a substrate 202. Device 206 may be a transistor, such as a FinFET device, a nanosheet FET (NSH) device, or a GAAFET ("gate-all-around" FET) device, similar to device 106 described above. In a particular embodiment, device 206 includes gates 208A, 208B, a gate spacer 210, source / drain regions 212A-C, and source / drain contacts 214A-C formed in a transistor region 215 of device 206 in cell 100.

[0042] In particular embodiments, insulated gates 216A, 216B are disposed on either side of device 206. Insulated gates 216A, 216B can include metal fills 218A, 218B, respectively, and spacers 220A, 220B, respectively. In various embodiments, as shown in FIG. 4 , spacers 220A, 220B extend into insulating layer 204. Thus, insulated gates 216A, 216B provide insulation on each side of device 206, and metal fills 218A, 218B and spacers 220A, 220B extend into substrate 202 beneath the active area of ​​the device (e.g., beneath the transistor). Thus, insulated gate 216 defines an isolation region for device 206 and provides electrical signal isolation between device 206 and adjacent devices.

[0043] In certain embodiments, gates 108A, 108B are active gates for device 206. Gates 108A, 108B may include, for example, poly lines (e.g., polysilicon or metal layers) that form the active portion of the gate. Gate spacers 210 may be disposed between gate 208 and source / drain regions 212 to define the active gate. In various embodiments, gate spacers 210 are formed as part of gate 208 (e.g., the gate and spacers are formed in the same process flow). Source / drain regions 212A, 212B, 212C are disposed on the sides of gates 208A, 208B, 208C. Source / drain regions 212A, 212B, 212C may be, for example, fins or nanosheet stacks in a FinFET or NSH device. Various embodiments are also contemplated in which source / drain regions 212A, 212B, 212C are at least partially disposed within substrate 202.

[0044] In particular embodiments, insulating layer 222 and upper metal layer 224 are formed over device 206 and insulated gate 216 (e.g., above the device over transistor region 215). Insulating layer 222 may include one or more insulating layers formed over transistor region 215. For example, insulating layer 222 may include one or more oxide or nitride layers. In various embodiments, insulating layer 222 at least partially surrounds or encapsulates transistor region 215 of device 106 (e.g., gate 208, spacers 210, source / drain regions 212, contacts 214, and insulated gate 216).

[0045] In various embodiments, the upper metal layer 224 includes one or more metal layers above the insulating layer 222. The upper metal layer 224 can provide signal routing (e.g., control signal routing) for the device 206. For example, metal routing within the upper metal layer 224 can provide signal routing for the device 206. In the illustrated embodiment of the cell 200, the backside metal layer 226 is formed below the insulating layer 204 of the device 206 (e.g., on the backside of the device below the transistor region 215).

[0046] 4, the backside metal layer 226 is formed at or near the bottom surface of the substrate 202. In some embodiments, the backside metal layer 226 comprises one or more backside layers of the active layers of the device 206 (e.g., the backside metal layer is vertically below the transistor region 215 of the device 206). In some embodiments, the backside metal layer 226 comprises one or more buried layers within the substrate 202 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 226 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments can be envisioned in which the backside metal layer 226 is not disposed within the substrate 202.

[0047] In particular embodiments, backside metal layer 226 provides signal routing (e.g., control signal routing) between device 206 and / or other devices within cell 200. For example, backside metal layer 226 may include metal routing that routes control signals from device 206 to another device within cell 200 (or to a device in another cell).

[0048] As described herein, metal routing in backside metal layer 226 may be implemented in combination with metal routing above transistor region 215 (e.g., metal routing in upper metal layer 224) and metal routing through insulated gate structures (e.g., routing through metal fill 218 in insulated gate 216) to provide a signal routing path between a signal input of an active gate in device 206 and another device. In the illustrated embodiment of FIG. 4 , the signal input of gate 208A is connected to upper metal layer 224 by gate contact 227A. Additionally, the top of metal fill 218B in insulated gate 216B is connected to upper metal layer 224 by gate contact 227B. Gate contacts 227A, 227B may be metal vias or other connections formed between transistor region 215 and upper metal layer 224 through insulating layer 222.

[0049] In a particular embodiment, gate contact 227A connects the signal input of gate 208A to metal routing in upper metal layer 224, which further connects to gate contact 227B. Gate contact 227B then connects the metal routing in upper metal layer 224 to metal fill 218B in insulated gate 216B. The bottom of metal fill 218B then connects through insulating layer 204 to metal routing in backside metal layer 226 using gate contact 228 (e.g., a gate contact via through the insulating layer). Thus, metal fill 218B provides a connection between the metal routing in upper metal layer 224 and the metal routing in backside metal layer 226. Thus, metal fill 218B in insulated gate 216B provides a path for routing control signals from the top side of device 206 to the backside of the device. Because insulated gate 216B is typically included in a standard cell layout, the implementation of metal fill 218B to provide a connection between metal routing in top metal layer 224 and metal routing in back metal layer 226 has little or no impact on area utilization within cell 200.

[0050] Additionally, in the embodiment of cell 200 shown in FIG. 4 , the metal wire in upper metal layer 224 that provides the connection between gate contact 227A and gate contact 227B has a relatively short length that provides low electrical resistance. Therefore, the connection between the signal input of gate 208A and metal fill 218B can provide a low RC delay for transmitting the signal. Furthermore, in cell 200, metal fill 218B can have low electrical resistance due to the volume of metal that forms the metal fill. The low electrical resistance of metal fill 218B can reduce the impact of routing a signal through insulated gate 216B on the RC delay of the signal.

[0051] An alternative to using metal routing in the upper metal layer 224 to connect the signal input of gate 208A to the metal fill 218B in the insulated gate 216B can be the addition of a metal wire (or other metal structure) in the insulating layer 222 that connects the signal input of the gate to the metal fill in the insulated gate.

[0052] FIG. 5 shows a diagram of an embodiment of a cell having alternative routing between the active gate and the insulated gate structure, according to some embodiments. In FIG. 5, (A) is a top view of an embodiment of cell 200, and (B) is a bottom view of the embodiment of the cell. FIG. 6 shows a cross-sectional view of cell 200 along section line 6-6 shown in FIG. 5, according to some embodiments. Section line 5-5 is located across the signal portions of top metal layer 224 and backside metal layer 226, as shown in FIG. 5B. A view of gate contact 230, described further below, is shown in FIG. 5A, along with a view of gate contact 228, described herein, shown in FIG. 5B.

[0053] In the illustrated embodiment of FIG. 6 , the connection between the signal input of gate 208A and the top of metal fill 218B is made by gate contact 230 disposed within insulating layer 222. In particular embodiments, gate contact 230 includes a gate contact via formed within insulating layer 222 from the signal input of gate 208A and the top of metal fill 218B. The gate contact via then connects to a metal wire (or other metal routing) formed within insulating layer 222. In various embodiments, the metal wire portion of gate contact 230 is formed within a single layer of insulating layer 222 when the insulating layer includes multiple insulating layers. In some embodiments, insulating layer 222 may have an increased thickness (e.g., compared to insulating layer 122 shown in FIG. 1 ) to provide space for disposing the metal wire portion of gate contact 230 within an insulating layer with electrical insulation both above and below the metal wire.

[0054] Using gate contact 230 to provide a connection between the signal input of gate 208A and the top of metal fill 218B provides this connection without requiring the utilization of resources in upper metal layer 224. For example, gate contact 230 is a local jumper or shunt between the signal input of gate 208A and the top of metal fill 218B.

[0055] In some embodiments, gate contact 230 may be implemented to further pick up signals from source / drain regions in device 206. FIG. 7 shows a cross-sectional view of a cell having a gate contact connecting to the signal input and source / drain of the active gate, according to some embodiments. In the illustrated embodiment, gate contact 230′ disposed in insulating layer 222 connects to contact 214C for source / drain region 212C, in addition to connecting to the signal input of gate 208A and the top of metal fill 218B. Connecting gate 208A to both the signal input and source / drain region 212C in device 206 may enable additional implementations of cell 200.

[0056] Embodiments described herein provide for routing of signal paths (e.g., control signal paths) through the backside of an integrated circuit device by utilizing metal fill within insulated gates in the layout of the integrated circuit device to provide connections between active gates and backside layers. FIG. 8 shows a diagram of an embodiment of an integrated circuit layout having insulated gates with signal routing on both the top and backside layers, according to some embodiments. In FIG. 8, (A) is a top view of an embodiment of the integrated circuit layout 800, and (B) is a bottom view of the embodiment of the integrated circuit layout. To better understand the present disclosure, a dashed box representing cell 200 (shown in FIGS. 3 and 4) is shown in layout 800.

[0057] In layout 800, regions 810A and 810B are active regions of an integrated circuit device. Layout 800 includes multiple instances of active gates 208 and insulated gates 216 laid out along regions 810A and 810B between top metal layer 224 at (A) and bottom metal layer 226 at (B). In the illustrated embodiment, layout 800 includes top signal tracks 820A and 820B shown in (A) and bottom signal tracks 830A and 830B shown in (B). Top signal track 820A and bottom signal track 830A correspond to region 810A, and top signal track 820B and bottom signal track 830B correspond to region 810B.

[0058] As shown in FIG. 8 , signal routing through the active area can be implemented on both the top and backside of the device using routing connections between the top metal layer 224 and the backside metal layer 226 provided on the insulated gate 216. For example, for active area 810A, top signal track 820A provides a signal path, shown from left to right in (A), until it reaches insulated gate 216′, where the signal path is routed to backside signal track 830A and propagates through the layout to the right, as shown in (B). For active area 810B, top signal track 820B provides a signal path, shown from left to right in (A), until it reaches insulated gate 216″, where the signal path is routed to backside signal track 830B and propagates through the layout to the right, as shown in (B). Layout 800 of FIG. 8 illustrates an embodiment that utilizes upper metal layer 224 for upper signal routing (as described in the embodiment of FIGS. 3 and 4), it should be understood that a layout similar to layout 800 can be used in embodiments that implement metal wires within an insulating layer for upper signal routing (e.g., the embodiment of FIGS. 5-7).

[0059] 8, adding the ability to route signals through the backside of a device in integrated circuit layout 800 at insulated gate 216 allows backside signal routing to be combined with topside signal routing. Combining signal routing on the backside of an integrated circuit device with signal routing on the topside of the integrated circuit device (e.g., signal routing on both the topside and backside) can provide benefits such as, but not limited to, reduced RC delays for signal transmission within the integrated circuit while enabling improved power routing characteristics with little or no impact on area scaling within the integrated circuit device.

[0060] Furthermore, utilizing backside signal routing in addition to topside routing can reduce the number of topside signal tracks required in an integrated circuit layout. With topside-only signal routing, multiple signal tracks are typically required to route signals for parallel active areas. For example, three topside signal tracks are typically required, along with two active areas, to provide spacing for making contacts to each of the active areas. FIG. 9 shows a diagram of topside signal tracks in an integrated circuit layout with topside-only signal routing, according to some embodiments. In the illustrated embodiment, three signal tracks 910A, 910B, 910C are required to provide sufficient spacing (e.g., x-y spacing in the figure) for the various gate contacts 920 to make connections to the underlying gates.

[0061] 10 shows a diagram of topside and backside signal tracks in an integrated circuit layout with topside and backside signal routing, according to some embodiments. In the illustrated embodiment of FIG. 10, the addition of backside signal routing allows the integrated circuit layout to have only a single topside signal track 1010 and a single backside signal track 1020. Only a single track is needed because the topside gate contact 1015 and backside gate contact 1025 can be placed at closer xy spacing in the illustration due to variations in depth (z direction in the illustration).

[0062] Various additional embodiments of integrated circuit devices can be contemplated, including connections between signal inputs of active gates and metal fills in insulated gates that utilize a combination of routing through an upper metal layer (as shown in the embodiment of FIG. 4 ) and routing through metal wires in an upper insulating layer (as shown in the embodiment of FIG. 6 ). FIG. 11 illustrates a cross-sectional view of an integrated circuit device having both types of routing connections between signal inputs of active gates and metal fills in insulated gates, according to some embodiments. In various embodiments, an integrated circuit device 1100 includes two insulated gates 216′, 216″, with multiple active gates 208 between the insulated gates (and the two active gates to the right of insulated gate 216″ in the figure) in a transistor region above substrate 202 and insulating layer 204. Active gates 208 have source / drain regions 212, contacts 214 are disposed between the gates, and insulated gates 216′, 216″ have metal fills 218′, 218″ surrounded by gate spacers 220′, 220″.

[0063] In the illustrated embodiment, metal fill 218' in insulated gate 216' is connected to signal routing in top metal layer 224 by gate contact 227'. Metal fill 218' is also connected to signal routing in backside metal layer 226 by gate contact 228'. The signal routing in top metal layer 224 is then connected to the signal input of active gate 208A by gate contact 227A, completing the routing between the signal input of active gate 208A and the signal routing in backside metal layer 226.

[0064] The metal fill 218'' in the insulated gate 216'' is connected to the signal input of the active gate 208A' by a gate contact 230 located in the insulating layer 222. The metal fill 218'' is also connected to the signal routing in the backside metal layer 226 by a gate contact 228''. Thus, signal routing between the signal input of the active gate 208A' and the signal routing in the backside metal layer 226 is completed via the metal fill 218'' in the insulated gate 216'', the gate contact 228'', and the gate contact 230. Additionally, the device 1100 may include one or more source / drain contacts 1110 that provide signal connection between the source / drain regions 212 and routing in the upper metal layer 224.

[0065] Various embodiments of device 1100 may also include power routing to the backside metal layer 226. For example, as shown in FIG. 11 , device 1100 includes backside vias 128 connecting source / drain regions 212 to the backside metal layer 226. The backside vias 128 can be connected to power routing within the backside metal layer 226. The power routing within the backside metal layer 226 may be separate from the signal routing within the backside metal layer. Thus, the backside metal layer 226 provides both power and signal routing within device 1100 with electrical isolation between the different routing paths. Additional implementations utilizing a connection between the signal input of the active gate and the metal fill within the insulated gate by a combination of routing through an upper metal layer and routing through a metal wire within an upper insulating layer can be contemplated without departing from the scope of the present disclosure.

[0066] In various embodiments, the structure of insulated gate 216 in cell 200 described herein (shown in FIGS. 3-7 ) can be implemented in filler cells in an integrated circuit layout. Implementing insulated gate 216 in filler cells can provide backside access for functional cells located adjacent to the filler cells. FIG. 12 shows a top view of an integrated circuit layout having functional and filler cells, according to some embodiments. In the illustrated embodiment, layout 1200 includes functional cell 1210 and filler cell 1220.

[0067] FIG. 13 shows a cross-sectional view of a filler cell having an insulated gate structure for providing backside access, according to some embodiments. In the illustrated embodiment, the filler cell 1220 includes three insulated gate structures 1310. It should be understood that the filler cell 1220 may include any number of insulated gate structures 1310. For example, the number of insulated gate structures 1310 may be determined by the size of the filler cell 1220, with larger filler cells having a greater number of insulated gate structures. Increasing the number of insulated gate structures 1310 in the filler cell 1220 can reduce the resistance of the connection between the top metal layer 224 and the backside metal layer 226, and reducing the number of insulated gate structures can reduce material or processing costs. Additionally, the width of the insulated gate structures 1310 may be varied to determine the resistance and material costs associated with the filler cell 1220.

[0068] The insulated gate structure 1310 has a structure similar to the insulated gate 216 described herein. In the illustrated embodiment, the insulated gate structure 1310 includes a metal fill 218 between spacers 220, with source / drain regions 212 with contacts 214 disposed between the insulated gate structures. The source / drain regions 212 and contacts 214 may be inactive in the filler cells 1220 (e.g., the transistor regions of the filler cells 1220 are inactive). Embodiments are contemplated in which the source / drain regions 212 and contacts 214 are not formed in the filler cells 1220.

[0069] Gate contact 227 connects the top of metal fill 218 in insulated gate structure 1310 to upper metal layer 224, and gate contact 228 connects the bottom of the metal fill to backside metal layer 226. Thus, metal fill 218 connects upper metal layer 224 to backside metal layer 226. If the connection between upper metal layer 224 and backside metal layer 226 is made within filler cell 1220, routing within upper metal layer 224 or backside metal layer 226 can be made between functional cell 1210 and filler cell 1220 shown in FIG. 12 . Thus, filler cell 1220 provides an access point to backside metal layer 226 for functional cell 1210 in layout 1200. Exemplary Computer System

[0070] 14 , a block diagram of one embodiment of a system 1400 that may incorporate and / or otherwise utilize the methods and mechanisms described herein is shown. In the illustrated embodiment, the system 1400 includes at least one instance of a system on chip (SoC) 1406, which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or other types of processing units, a communications fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 1406 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 1406 is coupled to an external memory 1402, peripheral devices 1404, and a power supply 1408.

[0071] A power supply 1408 is also provided to provide a supply voltage to the SoC 1406 and to provide one or more supply voltages to the memory 1402 and / or peripherals 1404. In various embodiments, the power supply 1408 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, or tablet computer, or other device). In some embodiments, more than one instance of the SoC 1406 is included (and more than one external memory 1402 is also included).

[0072] The memory 1402 may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled to a circuit board to form a memory module, such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices may be mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0073] Peripherals 1404 may include any desired circuitry depending on the type of system 1400. For example, in one embodiment, peripherals 1404 may include devices for various wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripherals 1404 may also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripherals 1404 may include user interface devices, such as a display screen, including a touch or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0074] As shown, system 1400 is shown to have a wide range of applications. For example, system 1400 may be utilized as part of a chip, circuit, component, etc. in a desktop computer 1410, a laptop computer 1420, a tablet computer 1430, a cellular or mobile phone 1440, or a television 1450 (or a set-top box coupled to a television). Also illustrated is a smartwatch and a health monitoring device 1460. In some embodiments, a smartwatch may include various general-purpose computing-related functions. For example, a smartwatch may provide access to email, cellular telephone service, a user calendar, etc. In various embodiments, a health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any health monitoring-related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, and glasses designed to provide an augmented and / or virtual reality experience.

[0075] System 1400 can further be used as part of cloud-based service(s) 1470. For example, the aforementioned devices and / or other devices may access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Furthermore, system 1400 can be utilized in one or more devices in a home 1480 other than those described above. For example, appliances in the home can monitor and detect noteworthy conditions. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the device status and alert the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat can monitor the home's temperature and automate adjustments to the heating / cooling system based on the homeowner's historical responses to various conditions. FIG. 14 also illustrates the application of system 1400 to various transportation modes 1490. For example, system 1400 can be used in control and / or entertainment systems for airplanes, trains, buses, rental vehicles, private cars, watercraft ranging from private boats to cruise ships, scooters (rented or owned), etc. In various cases, system 1400 can be used to provide automated guidance (e.g., for autonomous vehicles), general system control, and other methods. Many other embodiments of any of these are possible and contemplated. Note that the devices and applications illustrated in Figure 14 are illustrative only and are not intended to be limiting. Other devices are possible and contemplated. ***

[0076] The present disclosure includes references to "one embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different implementations or examples of the disclosed concepts. References to "one embodiment," "one embodiment," "particular embodiment," etc. do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, as well as modifications or alternatives that are within the spirit or scope of the present disclosure, are contemplated.

[0077] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of any disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, suboptimal design practices of a particular implementation (e.g., implementation techniques or tools) may also negate or reduce a disclosed advantage. Even assuming skilled practice, realization of advantages may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, resulting in the benefits of that solution not being realized. Given the existence of factors external to the present disclosure that may arise, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met in order to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the type(s) of improvement available to a designer having the benefit of the present disclosure. The fact that such advantages are permissibly described (e.g., a statement that a particular advantage "may result") is not intended to convey any doubt as to whether such advantage can actually be realized, but rather to recognize the technological reality that realization of such advantages often depends on additional factors.

[0078] Unless otherwise specified, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, not limiting, unless a statement to the contrary is present in the present disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments, but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0079] For example, features of the present application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) for any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims as appropriate, including claims that are dependent on other independent claims. Similarly, features from each independent claim may be combined as appropriate.

[0080] Thus, the accompanying dependent claims may each be drafted to depend on a single other claim, although additional dependencies are also contemplated. Any combination of features in the dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically recited in the accompanying claims.

[0081] Where appropriate, it is contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is also intended to support a corresponding claim in another format or statutory type (e.g., method). ***

[0082] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The public is hereby notified that the definitions provided in the following paragraphs, as well as throughout this disclosure, will be used in interpreting the claims made based on this disclosure.

[0083] Reference to a singular item (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more" unless the context clearly indicates otherwise. Thus, a reference to an "item" in a claim does not exclude additional instances of the item without context. A "plurality" of an item refers to a set of two or more items.

[0084] The word "may" is used herein in a permissive sense (i.e., having the possibility, being able to do), not in an obligatory sense (i.e., not required).

[0085] The terms "comprising" and "including" and their forms are open-ended and mean "including, but not limited to."

[0086] When the term "or" is used in this disclosure in reference to a list of alternatives, it will generally be understood to be used in an inclusive sense unless the context clearly indicates otherwise. Thus, a list of "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes clear that "or" is used in an exclusive sense.

[0087] The enumeration of "w, x, y, z, or any combination thereof," or "...at least one of w, x, y, and z" is intended to encompass all possibilities, including single elements, up to the total number of elements in the set. For example, for the set [w, x, y, z], these expressions encompass any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase should not be interpreted as requiring that there be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0088] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context clearly indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, when applied to features, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0089] As used herein, the phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based solely on the specified factors, or on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0090] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the particular factor or independently of the specified factor. That is, the effect may depend only on these factors, or on the specified factor as well as other unspecified factors. Consider the phrase "performing A in response to B." By this phrase, B is a factor that triggers the execution of A or triggers a particular result for A. This phrase does not exclude that the execution of A may also be in response to other factors, such as C. This phrase also does not exclude that performing A may be in response to both B and C. This phrase is intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to." ***

[0091] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase "entity" configured to perform one or more tasks is used herein to refer to a structure (i.e., a physical thing). More specifically, this phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently operating. In this manner, an entity described or explained as being "configured" to perform a task refers to a physical thing, such as a device, a circuit, a system having a processor unit and a memory storing executable program instructions to perform the task. This phrase is not used herein to refer to an intangible thing.

[0092] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations, and even if not specifically described, it will be understood that those entities are "configured to" perform those tasks / operations.

[0093] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0094] For purposes of U.S. patent applications based on this disclosure, reciting in a claim that a structure is "configured to" perform one or more tasks is expressly intended to invoke 35 U.S.C. §112(f) for that claim element. not present If an applicant, based on this disclosure, wishes to invoke Section 112(f) during prosecution of a U.S. patent application, it would use "means for" to recite claim elements.

[0095] Various "circuits" may be described in this disclosure. These circuits or "circuitry" comprise hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Particular types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0096] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform this function. This specification of this function is sufficient to suggest a set of possible configurations of the circuit to one skilled in the computer arts.

[0097] In various embodiments, as described in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the way they interact form a microarchitecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with a microarchitecture definition provided in accordance with this disclosure can, without undue experimentation, implement the structure by coding the circuit / unit / component description into a hardware description language (HDL), such as Verilog or VHDL, using ordinary skill. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions may take the form of behavioral-level code (which is typically not synthesizable), register transfer language (RTL) code (which is typically synthesizable, as opposed to behavioral-level code), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit. An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and the circuit elements.Some embodiments may implement multiple integrated circuits connected together to realize the hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into and implemented in a programmable logic array, such as a field programmable gate array (FPGA). This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits generally results in a scenario where the circuit or logic designer does not specify any particular set of structures for the low-level implementation other than a description of how the circuit is organized, since this process is performed at a different stage in the circuit implementation process.

[0098] The fact that many different low-level combinations of circuit elements can be used to implement the same specification for a circuit results in numerous equivalent structures for that circuit. As noted above, these low-level circuit implementations may vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methods to generate these different implementations may be arbitrary.

[0099] Furthermore, for a given embodiment, it is common for a single implementation of a circuit's particular functional specifications to include a large number of devices (e.g., millions of transistors). Thus, this absolute amount of information makes it impractical to exhaustively enumerate the low-level structures used to implement a single embodiment, let alone the vast number of equivalent possible implementations. For this reason, this disclosure describes the structure of a circuit using functional abbreviations used in the industry.

Claims

1. a transistor formed in a transistor region of the integrated circuit, the transistor having an active gate with a signal input; a metal layer disposed below the transistor region in a vertical dimension perpendicular to the transistor region; a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill disposed between gate spacers in the transistor region, the gate structure disposed on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, the metal fill connected to the metal layer; a metal wire disposed above the transistor region in the vertical dimension, the metal wire connecting the metal fill to the signal input of the active gate; An apparatus comprising:

2. 2. The device of claim 1, further comprising an upper metal layer disposed above said transistor region in said vertical dimension, said metal wires being disposed within said upper metal layer.

3. an upper metal layer disposed above the transistor region in the vertical dimension; an insulating layer disposed between the transistor region and the upper metal layer; and the metal wire is disposed within the insulating layer.

10. The apparatus of claim 1.

4. 2. The device of claim 1, wherein the metal fill and the gate spacers in the gate structure extend below the transistor in the vertical dimension, and the metal fill in the gate structure is separated from the first side of the transistor by at least one of the gate spacers to provide electrical isolation between the metal fill and the active gate.

5. 2. The device of claim 1, further comprising: a second gate structure formed in the transistor region of the integrated circuit, the second gate structure including a second metal fill disposed between second gate spacers in the transistor region, the second gate structure disposed on a second side of the transistor in the horizontal dimension, the second side being opposite the first side of the transistor in the horizontal dimension.

6. 2. The apparatus of claim 1, further comprising a control signal routed to the signal input of the active gate, the control signal being routed from the metal layer to the signal input via the metal fill and the metal wire.

7. 2. The device of claim 1, further comprising a metal signal wire in the metal layer, the metal fill connecting the signal input of the active gate to the metal signal wire.

8. 8. The apparatus of claim 7, wherein the metal signal wire is connected to at least one additional transistor formed in the transistor region of the integrated circuit.

9. an insulating layer disposed between the transistor region and the metal layer; a gate contact via in the insulating layer, the gate contact via providing a connection between the metal fill and the metal layer; The apparatus of claim 1 further comprising:

10. a transistor formed in a transistor region of the integrated circuit; a first metal layer disposed over the transistor region in a vertical dimension perpendicular to the transistor region; a second metal layer disposed below the transistor region in the vertical dimension; a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill disposed between gate spacers in the transistor region, the gate structure being disposed on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension, the metal fill connecting the first metal layer and the second metal layer; An apparatus comprising:

11. an active gate within the transistor, the active gate having a signal input, the signal input connected to the metal fill through the first metal layer; The apparatus of claim 10 further comprising:

12. an active gate within the transistor, the active gate having a signal input; a first metal wire disposed in a first metal layer, the first metal wire connecting the signal input to the metal fill; The apparatus of claim 10 further comprising:

13. further comprising a second metal wire disposed within the second metal layer; the second metal wire is connected to the signal input via the metal fill and the first metal wire; 13. The apparatus of claim 12.

14. the transistor and the gate structure are disposed within a filler cell, the transistor in the transistor region of the filler cell being inactive, and the device comprises: a functional cell disposed adjacent to the filler cell, the functional cell including an active transistor having an active gate with a signal input, the signal input of the active transistor coupled to the first metal layer, and the second metal layer providing routing for a control signal between the signal input and a backside metal layer of the functional cell; 11. The apparatus of claim 10.

15. an insulating layer disposed between the transistor region and the first metal layer; a first gate contact via in the insulating layer, the first gate contact via connecting the metal fill and the first metal layer; a second gate contact via in the insulating layer connecting a signal input of an active gate in the transistor to the first metal layer; and The apparatus of claim 10 further comprising:

16. a transistor formed in a transistor region of the integrated circuit; a first insulating layer disposed over the transistor region in a vertical dimension perpendicular to the transistor region; a metal layer disposed below the transistor region in the vertical dimension; a second insulating layer disposed between the transistor region and the metal layer in the vertical dimension; a gate structure formed in the transistor region of the integrated circuit, the gate structure including a metal fill disposed between gate spacers in the transistor region, the gate structure disposed on a first side of the transistor in a horizontal dimension perpendicular to the vertical dimension; a metal wire disposed within the first insulating layer, the metal wire being connected to the metal fill; a gate contact via disposed in the second insulating layer, the gate contact via connecting the metal fill to the metal layer; An apparatus comprising:

17. 17. The apparatus of claim 16, further comprising an active gate in the transistor, a signal input of the active gate connected to the metal layer by the metal wire, the metal fill, and the gate contact via.

18. 18. The device of claim 17, wherein the source / drain regions of the active gate are connected to the metal wire.

19. a first gate contact via in the first insulating layer, the first gate contact via connecting the metal fill and the metal wire; a second gate contact via in the first insulating layer, the second gate contact via connecting the signal input of the active gate and the metal wire; 20. The apparatus of claim 17, further comprising:

20. 17. The device of claim 16, further comprising a top metal layer disposed over the transistor region, the top metal layer being electrically insulated from the metal wires.

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