Nanowire device with mask layer

Abstract

1. A structure comprising a doped substrate and a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; A structure wherein a plurality of nanowires or nanopyramids are grown from the substrate within the openings, the nanowires or nanopyramids comprising at least one III-V semiconductor compound.

Description

[Technical Field]

[0001] The present invention relates to structures comprising nanowires or nanopyramids grown on a doped substrate through a mask layer. The structures formed can be used in electronic devices such as LEDs, solar cells, transistors, lasers, or photodetectors. The present invention also relates to structures / devices comprising nanowires or nanopyramids grown on a metal substrate through a mask layer. [Background technology]

[0002] [background] In recent years, as nanotechnology has emerged as an important engineering field, there has been growing interest in semiconductor nanowires, also called nanowhiskers, nanorods, nanopillars, or nanocolumns by some authors, which have found important applications in a variety of electrical devices, including sensors, solar cells, transistors, and LEDs.

[0003] Traditionally, semiconductor nanowires have been grown on the same substrate as the nanowire itself (homoepitaxial growth). Thus, GaAs nanowires are grown on GaAs substrates, and GaN nanowires on GaN substrates. This, of course, ensures a lattice match between the crystalline structure of the substrate and that of the growing nanowire. In the case of heteroepitaxial growth, GaN nanowires are grown on substrates such as sapphire or silicon. Both the substrate and the nanowire may have the same crystalline structure.

[0004] It is known to use a mask with a hole array pattern to position the nanowires, with the nanowires growing only / predominantly in the hole pattern areas. The mask can also promote nanowire growth in a direction perpendicular to the substrate. Typically, a silica layer is applied to the substrate and etched to form holes in the desired pattern. Nanowires then grow only / predominantly at the hole locations.

[0005] The growth of nanowires (NWs) on graphene is known, with the graphene acting as an electrode. WO 2012 / 080252 describes the growth of semiconductor nanowires on graphene substrates. WO 2013 / 104723 improves on the disclosure of WO 2012 / 080252 by employing a graphene top contact for nanowires grown on graphene. However, in this case, the growth of the nanowires occurs on the graphene layer and not on the underlying substrate. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2012 / 080252 [Patent Document 2] International Publication No. 2013 / 104723 Summary of the Invention [Problem to be solved by the invention]

[0007] Graphene has been suggested as a potential mask layer and electrode (WO2021 / 009325), but achieving good electrical contact with graphene is difficult. [Means for solving the problem]

[0008] We propose using a thin mask layer on a doped substrate. Nanowires / nanopyramids are grown through openings (e.g., patterned holes or defects) in the mask layer. The doped substrate is the active substrate that can participate in the device's function. The mask layer acts as a tunnel barrier that improves the vertical conduction of the device, thus improving its efficiency. Similar advantages are seen when using a metallic (conductive) substrate.

[0009] [Summary of the Invention] Thus, the present invention in one aspect provides a method for producing a composition comprising: doped substrate; a structure comprising a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; and a plurality of nanowires or nanopyramids are grown from the substrate in the holes, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; Provides structure.

[0010] In a further aspect, doped substrate; a mask layer having a thickness of 2 nm or less on top of the substrate, a mask layer having a plurality of openings therethrough; and a corrugated continuous III-V film on top of the mask layer and extending from the hole, For example, the nanowires or nanopyramids may be formed from a plurality of coalesced nanowires or nanopyramids grown in the pores, the nanowires or nanopyramids being corrugated continuous III-V film comprising at least one III-V semiconductor compound. A structure is provided that includes:

[0011] In a further aspect, there is provided a device, such as an optoelectronic device, comprising a structure as defined herein, e.g., a solar cell, a photodetector, a transistor, a laser, or an LED, preferably an LED, more preferably a UV LED, more preferably a UV-C LED.

[0012] In a further aspect, (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (II) growing a plurality of nanowires or nanopyramids from the substrate in a plurality of openings in the mask layer, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; There is provided a method of manufacturing a structure as defined herein, comprising:

[0013] In a further aspect, (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (II) growing a plurality of nanowires or nanopyramids from the substrate in a plurality of openings in the mask layer until the nanowires or nanopyramids coalesce, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; There is provided a method of manufacturing a structure as defined herein, comprising:

[0014] In a further aspect, Metal substrate; a structure comprising a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; and A structure is provided in which a plurality of nanowires or nanopyramids are present on the substrate in the openings, the nanowires or nanopyramids comprising at least one III-V semiconductor compound.

[0015] In a further aspect, Metal substrate; a mask layer having a thickness of 2 nm or less over the substrate, the mask layer having a plurality of openings therethrough; and a corrugated continuous III-V film on top of the mask layer and extending from the opening, the corrugated continuous III-V film being formed, for example, from a plurality of coalesced nanowires or nanopyramids grown in the opening, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; A structure is provided that includes:

[0016] In a further aspect, (I) removing the nanowire or nanopyramid from the substrate in the structure defined herein; and (II) transferring the removed nanowires or nanopyramids to a different substrate, said second substrate being doped / conductive or undoped / insulating; A method for manufacturing a device, for example an optoelectronic device, is provided, comprising:

[0017] In a further aspect, (I) removing said continuous III-V film from said substrate in said structure defined herein; and (II) transferring the removed III-V film to a different substrate, said second substrate being doped / conductive or undoped / insulating; A method for manufacturing a device, for example an optoelectronic device, is provided, comprising:

[0018] The features of the aspects and / or embodiments presented herein can be used individually and in any combination in all technically feasible aspects and embodiments of the invention, unless otherwise specified. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 shows aligned flat-tip nanowires epitaxially grown on a doped crystalline substrate with a mask layer in which holes have been etched. [Figure 2] FIG. 2 is similar to FIG. 1, the only difference being that the nanowires have pyramidal tips. [Figure 3] Figure 3 is similar to Figure 2, the only difference being that the nanowires are fully coalesced, either directly onto the doped nanowire core or as a result of the growth of an additional doped nanowire shell layer. [Figure 4] FIG. 4 is similar to FIG. 3, but uses coalesced nanopyramids instead of coalesced nanowires. [Figure 5]FIG. 5 shows a top-emitter nanowire GaN / AlGaN UV LED device grown on a hole-etch mask layer formed on a p-doped Si substrate according to the present invention. [Figure 6a-d] Figures 6(a) and (b) show top-view and 30° tilted scanning electron microscope (SEM) images, respectively, of n-GaN nanowires grown on the graphene-covered portion of a doped Si wafer. Figures 6(c) and (d) show top-view and 30° tilted scanning electron microscope (SEM) images, respectively, of n-GaN nanowires grown on the graphene-free adjacent region of a doped Si wafer. [Figure 6e] Figure 6e shows the current density-voltage characteristics of n-GaN nanowires grown on the graphene-covered part of the n++-Si wafer (filled circles) and on the graphene-uncovered part of the n++-Si wafer (filled squares), respectively. DETAILED DESCRIPTION OF THE INVENTION

[0020] [Definition] III-V compound semiconductors refer to those containing at least one element from group III and at least one element from group V. Multiple elements from each group may be present, such as InGaAs, AlGaN (i.e., ternary compounds), AlInGaN (i.e., quaternary compounds), etc. The term semiconductor nanowires or nanopyramids refers to nanowires or nanopyramids formed from semiconductor materials of group III-V elements.

[0021] As used herein, the term nanowire refers to a solid, wire-like structure of nanometer dimensions. Nanowires preferably have a uniform diameter over the majority of the nanowire, e.g., at least 75% of its length. The term nanowire is intended to encompass the use of nanorods, nanopillars, nanocolumns, or nanowhiskers, some of which may have tapered end structures. Nanowires are essentially one-dimensional structures whose width or diameter is nanometer-sized and whose length is typically in the range of hundreds of nanometers to several micrometers. Ideally, nanowires have a diameter (width) of 500 nm or less. Ideally, nanowires have a diameter (width) of 50 to 500 nm, although diameters may exceed several micrometers (referred to as microwires).

[0022] Ideally, the diameters of the base of the nanowire and the top of the nanowire are approximately the same (eg, within 20% of each other).

[0023] The term nanopyramid refers to a solid pyramidal structure. The term pyramidal is used herein to define a structure having a base with sides tapering to a point generally above the center of the base. It is understood that a single apex may appear chamfered, e.g., such that the pyramid has a flat top. Typically, the chamfered portion represents less than 50%, e.g., less than 40%, e.g., less than 30%, e.g., less than 20%, e.g., less than 10%, e.g., less than 5% of the total length of the nanopyramid's edge. Nanopyramids can have multiple faces, e.g., 3-8 faces, or 4-7 faces. Thus, the base of a nanopyramid may be square, pentagonal, hexagonal, heptagonal, octagonal, etc. Pyramids are formed such that the faces taper from the base to a central point (thus forming triangular faces). The triangular faces typically terminate in (1-101) or (1-102) faces. The sides of the (1-101) triangle may converge at the apex or form a new plane (the (1-102) plane) before converging at the apex. In some cases, the nanopyramid is truncated, terminating at the {0001} plane at its apex. The base itself may have a uniform cross-section before tapering to form the pyramidal structure. Thus, the thickness of the base may be up to 500 nm, e.g., up to 200 nm, e.g., 50 nm.

[0024] The base of the nanopyramid may have a diameter (width) at its widest point of 50 nm to 500 nm. In another embodiment, the base of the nanopyramid may have a diameter (width) at its widest point of 200 nm to 1 micrometer. The height of the nanopyramid may be 200 nm to several micrometers, for example, 400 nm to 1 micrometer.

[0025] The substrate will be understood to include a plurality of nanowires or nanopyramids, sometimes referred to as an array of nanowires or nanopyramids.

[0026] A graphene layer is a film consisting of a single or multiple layers of graphene or its derivatives. The term graphene refers to the honeycomb crystalline structure of sp 2 It refers to a planar sheet of bonded carbon atoms. Graphene is preferred, but derivatives of graphene, such as those with surface modifications, can also be used. For example, hydrogen atoms can be attached to the graphene surface to form graphane. Graphene with oxygen atoms attached to the surface along with carbon and hydrogen atoms is called graphene oxide. Surface modification can also be achieved by chemical doping or oxygen / hydrogen or nitrogen plasma treatment.

[0027] The term epitaxy comes from the Greek words epi, meaning "on," and taxi, meaning "ordered." The atomic arrangement of the nanowires or nanopyramids is based on the crystalline structure of the substrate. There is usually no epitaxial relationship between the nanowires / nanopyramids and the mask layer. Epitaxial growth is a term commonly used in the art. Epitaxial growth, as used herein, refers to the growth of nanowires or nanopyramids on the substrate that mimics the orientation of the substrate.

[0028] Selective area growth (SAG) is the most promising method for growing well-positioned nanowires and nanopyramids. This method differs from the self-assembled metal catalyst-assisted vapor-liquid-solid (VLS) method in that a metal catalyst acts as a nucleation site at random locations for nanowire or nanopyramid growth. Another self-assembled method for growing nanowires or nanopyramids is the catalyst-free method, which nucleates nanowires or nanopyramids at random locations. These methods result in large variations in the length and diameter of the nanowires and the height and width of the nanopyramids. Well-positioned nanowires or nanopyramids can also be grown by catalyst-assisted methods.

[0029] The SAG or catalyst-assisted positioned growth method typically requires a mask with a nanopore pattern on the substrate. The nanowires or nanopyramids nucleate primarily within the holes of the patterned mask on the substrate, resulting in uniform size and predetermined positions of the nanowires or nanopyramids. Nanowires / nanopyramids can also nucleate at defects in the mask layer that expose the underlying substrate.

[0030] Molecular beam epitaxy (MBE) is a method for depositing films on crystalline substrates. The MBE process involves heating a crystalline substrate in a vacuum to activate the substrate's lattice structure. An atomic or molecular beam is then irradiated onto the substrate surface. The term element, as used above, is intended to cover atoms, molecules, and ions of that element. When the irradiated atoms or molecules reach the substrate surface, they encounter the substrate's current-carrying lattice structure or catalytic droplets, as described in more detail below. Over time, the opposing atoms form nanowires.

[0031] Metalorganic vapor phase epitaxy (MOVPE), also known as metalorganic chemical vapor deposition (MOCVD), is an alternative to MBE for depositing films on crystalline substrates. In MOVPE, the deposition material is provided in the form of metalorganic precursors, which decompose upon reaching the hot substrate, leaving atoms on the surface. This method also requires a carrier gas (usually H2 and / or N2) to transport the deposition material (atoms / molecules) across the substrate surface. These atoms react with other atoms to form an epitaxial layer on the substrate surface. Careful selection of deposition parameters results in the formation of nanowires.

[0032] The term supported directly means that the layers in question are adjacent.

[0033] [Mask Layer] The mask layer serves several purposes: the openings in the mask allow the NW / NP material to be epitaxial with the substrate (NW = nanowire, NP = nanopyramid). The mask layer also surprisingly serves as a tunnel junction for conduction from the substrate to the NW / NP (or vice versa) for the portion of the NW / NP that extends laterally (i.e., outside the openings) of the mask layer. The openings in the mask layer can be purposefully patterned to allow for nanowire / nanopyramid positioning (i.e., SAG).

[0034] The mask layer can include or consist of a two-dimensional (2D) material. By 2D material, we mean a material having a layered structure, e.g., a structure formed by stacking sheets on top of each other, preferably held together by van der Waals forces. Examples of such 2D materials include graphene, hexagonal-BN (h-BN), MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. While graphene is preferred, other "graphene-like" materials having a two-dimensional structure, such as hexagonal-BN, MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2 layers, are suitable for this application. Therefore, the mask layer may be a graphene, hexagonal-BN, MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 or NiTe2 mask layer. Preferably, the mask layer is a graphene mask layer or a h-BN mask layer, and most preferably a graphene mask layer.

[0035] As used herein, the term graphene refers to a group of nanomaterials densely packed sp 2 It refers to a planar sheet of bonded carbon atoms. The term "graphene" also refers to structures with a small number of graphene sheets. The lattice spacing of graphene is 0.335 nm.

[0036] The mask layer should ideally contain 10 or fewer sheets of two-dimensional material (i.e., graphene or graphene-like material), preferably 5 or fewer sheets, more preferably 4 or fewer sheets, preferably 3 or fewer sheets, more preferably 2 or fewer sheets of two-dimensional material. Preferably, the mask layer should contain 1 to 5 sheets, preferably 1 to 4 sheets, preferably 1 to 3 sheets, preferably 1 to 2 sheets of two-dimensional material, most preferably 1 sheet of two-dimensional material (i.e., a monolayer of graphene or graphene-like material). Particularly preferred are planar sheets of graphene one atom thick.

[0037] In terms of metric thickness, the mask layer generally has a thickness of 2 nm or less. The mask layer preferably contains only a few layers of two-dimensional material (i.e., graphene or graphene-like material) and is ideally less than 1.5 nm thick. More preferably, the mask layer may have a thickness of 1 nm or less, more preferably 0.9 nm or less, more preferably 0.8 nm or less, more preferably 0.7 nm or less, more preferably 0.6 nm or less, and more preferably 0.5 nm or less. Preferred thickness ranges include 0.3-2 nm, preferably 0.3-1.5 nm, e.g., 0.3-1 nm, 0.3-0.9 nm, 0.3-0.8 nm, 0.3-0.7 nm, e.g., 0.3-0.5 nm.

[0038] The mask layer can function as (or be) a tunneling barrier, e.g., for carrier tunneling injection from the doped substrate into the III-V nanowire or nanopyramid. The carrier tunneling injection typically occurs where the nanowire / nanopyramid extends laterally beyond the mask layer. Making the mask layer thin is important for electronic properties. The thinner the mask layer, the better the tunneling between the substrate and the nanowire / nanopyramid. Particularly efficient tunneling is achieved for mask layers with a thickness of 1-2 atomic layers, preferably a single layer of graphene. Mask layers much thicker than the above typically do not exhibit the required beneficial tunneling, resulting in poor tunneling efficiency.

[0039] The portion of the nanowire or nanopyramid that extends beyond the mask layer is in contact with the mask layer. Typically, there is a conductive path from the substrate through the mask layer to the nanowire or nanopyramid. The conductive path penetrates the region of the nanowire / nanopyramid that extends beyond the mask layer. Thus, the mask layer may act as a tunnel barrier between the substrate and the portion of the nanowire / nanopyramid that extends beyond the mask layer (i.e., outside the opening).

[0040] The area of ​​the mask layer is generally not limited. The area of ​​the mask layer is 0.5 mm 2 or more, e.g. 5mm 2 or more, e.g. 10cm 2 Thus, the area of ​​the mask layer is limited only by practicality. The graphene wafer may be, for example, 1.0 to 100 square inches, e.g., 2 square inches, or 50 square inches.

[0041] In a highly preferred embodiment, the mask layer is a single-layer or multi-layer graphene (preferably a single layer) grown on a metal catalyst using chemical vapor deposition (CVD). The metal catalyst is a metal film or foil, such as Cu, Ni, or Pt. The graphene layer grown on these metal catalysts can be transferred to another substrate using the techniques detailed below. The graphene layer can also be grown directly on the doped substrate (such as a doped Si, Ge, or III-V substrate). In this case, a transfer step is not required. The graphene layer can also be grown on a SiC substrate using a thermal sublimation process and transferred to a target substrate as needed.

[0042] The graphene layer is preferably used without surface modification.

[0043] The mask layer (e.g., graphene) may be doped to improve conductivity. This is useful when the mask layer functions as an electrode (e.g., as the gate of a vertical transistor). The mask layer may be washed with isopropanol, acetone, or n-methyl-2-pyrrolidone to remove surface impurities. The washed graphene surface can be further modified by doping. The doping step can use a solution of FeCl3, AuCl3, or GaCl3.

[0044] The graphene layer is well known for its excellent optical, electrical, thermal, and mechanical properties. Although it is very thin, it is very strong, light, flexible, and impermeable. Most importantly, it acts as a thin tunnel barrier and hole mask for the nanowire / nanopyramid SAG.

[0045] If the nanowire or nanopyramid extends laterally beyond the mask outside the opening, there is good electrical contact between the nanowire / nanopyramid and the substrate vertically downward through the tunnel barrier layer. The nanowire or nanopyramid typically nucleates in an opening (whether a patterned hole or defect) in the mask on the substrate and then grows laterally, i.e., radially, on the upper surface (top) of the mask layer (i.e., "mushroom"-like) from the opening. Typically, the core of the nanowire or nanopyramid extends laterally (i.e., radially) beyond the mask layer outside the mask opening. The portion that extends beyond the mask layer is in direct and / or electrical contact with the mask layer. As used herein, "lateral" or "lateral" means coplanar with the substrate and / or mask layer.

[0046] It is preferred herein that the mask layer is not an electrode or does not function as an electrode. Preferably, there is no electrical contact with the graphene layer. In certain applications, for example, in transistors, it may be beneficial for the mask layer to function as an electrode. Thus, in certain embodiments, the mask layer functions (or is) an electrode. Thus, the structure can have electrical contact (directly, i.e., physically as well as electrically) with the mask layer. This can reduce the tunneling barrier and thereby enhance the vertical tunneling current.

[0047] The mask layer is typically disposed directly on the substrate (or an intermediate native silicon oxide layer that typically covers a silicon substrate, if a silicon substrate is used). The mask layer is planar.

[0048] The openings in the mask layer can be of any type. They can be patterned holes (i.e., "intentionally" placed holes) or pre-existing defects in the mask layer. They can also be defects formed during the growth of the nanowires / nanopyramids. They can be the openings of positioned holes or defects in the mask layer. The openings can be of any size, ranging from atomic vacancy defects in the mask layer to patterned holes, e.g., up to 500 nm in diameter. The openings can be of any shape, e.g., circular holes or elongated openings such as grain boundaries or cracks. In this specification, openings refer to openings in the mask layer that expose the substrate surface. The openings in the mask layer are openings that allow nucleation (typically epitaxial nucleation) of the nanowires / nanopyramids from the substrate. Preferably, one nanowire or nanopyramid is grown per opening.

[0049] [Patterning] The nanowires or nanopyramids are first grown or nucleated from the substrate. This occurs in / from the openings present in the mask layer. These openings can be in the form of holes (intentionally) patterned in the mask layer. The formation of these holes is a well-known process and can be performed using electron beam lithography, etching, or other known techniques. The hole pattern in the mask can be easily created using conventional lithography techniques such as photo / electron beam lithography, nanoimprinting, etc. Focused ion beam techniques can also be used to create a regular array of nucleation sites on the substrate surface for the growth of the nanowires or nanopyramids. The holes formed in the masking and seed layers can be arranged in any desired pattern.

[0050] The diameter of the pores is preferably up to 500 nm, e.g., up to 100 nm, ideally up to 20-200 nm. The diameter of the pore set sets the maximum diameter for the size of the nanowire or nanopyramid during initial growth. However, by modifying the growth parameters or by adopting a core-shell nanowire or nanopyramid geometry, nanowire or nanopyramid diameters larger than the size of the pores can be achieved. Preferably, the nanowire or nanopyramid extends laterally (i.e., radially) beyond the mask outside the pores.

[0051] The number of holes is a function of the area of ​​the mask and the desired density of nanowires or nanopyramids.

[0052] The shape of the holes is not limited. The holes may be circular, but may also be other shapes such as triangular, rectangular, or elliptical. As used herein, a "hole" is typically defined as one whose smallest lateral dimension is within 75% of its longest lateral dimension. The mask layer may be in electrical contact with the base of the nanowire or nanopyramid, which is useful when the mask layer functions as an electrode.

[0053] As the nanowires or nanopyramids begin to grow within the pores, the initial growth of the nanowires or nanopyramids tends to be epitaxial and substantially perpendicular to the substrate, which is a further preferred feature of the invention.

[0054] [Defect opening] The openings in the mask layer may be defects in the mask layer. The defects may be formed during the growth / preparation of the mask or during the growth of the nanowires / nanopyramids. The openings may be any type of defect in the mask layer, such as point defects, grain boundary defects, planar defects, or crack defects (see Qin et al., Journal of Applied Mechanics 2020, Vol. 87, pp. 030802-1 to 030802-11). The defect openings are typically randomly positioned and are typically smaller than positioned / patterned holes. The defect openings in this embodiment may be of any size and shape. The defect openings expose the surface of the substrate, allowing for nucleation (typically epitaxial nucleation) of the nanowires / nanopyramids from the substrate.

[0055] As mentioned above, the defects may be pre-existing defects in the mask layer, or they may be defects formed during growth of the nanowires / nanopyramids (e.g., due to annealing, ex-situ plasma, in-situ plasma, etc.).

[0056] Point defects include vacancies, dislocations, and SW defects (Stone-Wales defects). A vacancy is the absence of one or more atoms in the crystalline structure of the mask layer. A single vacancy is the absence of one atom, and a double vacancy is the absence of two atoms. Dislocations in graphene are typically pentagon-heptagon (5|7) pairs. SW defects are topological defects that form without the addition or removal of atoms. In graphene, SW defects transform four adjacent hexagons into two pentagons and two heptagons (5|7|7|5). The heptagons act as openings through which the nanowires / nanopyramids can nucleate.

[0057] Grain boundary defects are the interfaces between two adjacent crystal grains in the mask layer, and are typically arrays of linearly aligned dislocations.

[0058] Planar defects typically refer to holes formed by the coalescence of multiple voids.

[0059] Crack defects are cracks in the mask layer, typically elongated.

[0060] [substrate] The substrate is preferably a crystalline substrate, since nanowires and nanopyramids are typically grown from the substrate first.

[0061] The substrate can have a crystal orientation normal to the surface of

[0111] ,

[0110] ,

[0100] , or

[0001] . For cubic semiconductors such as Si and GaAs,

[0100] and

[0111] are preferred. Commercially,

[0100] is preferred, while

[0111] is preferred for NW / NP growth.

[0001] is also preferred, typically for SiC or III-N substrates. Thus, the substrate can be either

[0100] or

[0111] silicon.

[0062] The substrate can be selected from silicon, Ge, SiC, Ga2O3, or a III-V substrate. The III-V materials described for the nanowires / nanopyramids are also suitable for III-V substrates, and therefore the definition of III-V materials for the nanowires / nanopyramids also applies to III-V substrates. Silicon is preferred as the substrate. Silicon is an inexpensive, versatile substrate and easy to handle. It is also suitable for mask protection, preventing oxidation (e.g., graphene oxidation, if graphene is used). It is particularly more readily available than, for example, III-V semiconductor substrates. The combination of a silicon substrate and a graphene mask layer is advantageous because it provides excellent SAG for III-V materials, particularly Ga-V materials such as GaAs, GaN, GaSb, and GaP. Furthermore, silicon substrates are nonpolar, which effectively suppresses nucleation on the graphene mask during SAG of the nanowires / nanopyramids. The substrate in the present invention can be doped, i.e., n-doped or p-doped, and is typically p-doped. Preferably, the substrate is heavily doped (hence, designated "n++" or "p++"). The doped substrate typically functions as a current injector. The doped substrate can be an electron injector (in the case of n-doping, such as an "n++" Si substrate) or a hole injector (in the case of p-doping, such as a "p++" Si substrate). Heavy doping is beneficial because it lowers the barrier height and facilitates (increases) vertical tunneling current between the substrate and the nanowire / nanopyramid. Furthermore, substrates such as silicon can accommodate high doping levels, thereby increasing current injection and improving device efficiency. One advantage of the present invention is that when using a heavily doped substrate (e.g., p++ Si), hole injection is much greater than expected (as long as tunneling through the mask layer is efficient) because the substrate doping density is much higher compared to the doping density in the NW / NP core. A p++ silicon substrate can be doped to a much higher level than, for example, a p-GaN NW / NP.

[0063] The doping of the substrate typically involves the introduction of impurity ions. The doping level is ~10 15 / cm 3 ~10 22 / cm 3 , e.g. 10 18 / cm 3 ~10 21 / cm 3 (These figures are in 1cm increments.) 3 In certain embodiments, the substrate is highly doped, e.g., at least 10 15 / cm 3 , preferably at least 10 16 / cm 3 , preferably at least 10 17 / cm 3 , preferably at least 10 18 / cm 3 , preferably at least 10 19 / cm 3 The substrate may be p-type doped or n-type doped. For applications such as UVC LEDs, the substrate is preferably p-type doped, while for other applications such as UVA / visible LEDs and photodetector devices, the substrate is preferably n-type doped.

[0064] Suitable acceptors for the substrate may include boron, aluminum, gallium, and indium if the substrate is p-doped. Therefore, the substrate may be doped with at least one of boron, aluminum, gallium, or indium, preferably boron. For n-type substrates, suitable donors are phosphorus, arsenic, or antimony, preferably phosphorus. Therefore, the substrate may be doped with at least one of phosphorus, arsenic, or antimony. The dopant may be introduced during the growth process or by ion implantation after the substrate is formed.

[0065] In the case of silicon substrates, a native SiO2 layer typically exists on the silicon substrate. Therefore, in the present invention, the term "silicon substrate" does not exclude the presence of a very thin SiO2 layer on top of the substrate (i.e., at the interface with the graphene mask in the structure / device of the present invention). Thus, in certain embodiments, the silicon substrate includes this native SiO2 layer. The thickness of the top native SiO2 layer is typically less than 20 nm, preferably less than 10 nm, preferably less than 5 nm, preferably less than 3 nm, preferably less than 2 nm, preferably less than 1.9 nm, preferably less than 1 nm, e.g., 1-5 nm, 1-2 nm, or 2-3 nm. Because the SiO2 layer is insulating, vertical current from the Si substrate occurs only via tunneling current, and the vertical tunneling current increases as the thickness of the native SiO2 layer decreases. Therefore, the inventors surprisingly discovered that this insulating layer, together with the mask layer, can create a conduction path. Furthermore, we surprisingly found that when nanowires (e.g., GaN nanowires) are grown on Si substrates with a graphene mask layer (the structures depicted in Figures 6a and 6b), the oxide at the nanowire / silicon interface is much thinner (i.e., 1.0–1.5 mm) compared with nanowires grown on Si substrates without a graphene mask layer (i.e., 2.0–2.5 mm) (the structures depicted in Figures 6c and 6d). Furthermore, the presence of the graphene mask layer results in a more efficient conduction path between the n-doped nanowires and the n++-doped Si substrate compared with the absence of the graphene mask (Figure 6e).

[0066] The substrate may also function as a current injector. For example, it is much easier to make electrical contacts on the substrate than on graphene. One need only etch away a portion of the substrate and apply a metal as an electrical contact. Making electrical contacts on graphene and other graphene-like materials is difficult. In certain embodiments, the substrate is provided with an electrical contact (typically a metal), preferably on the top surface of the substrate (i.e., the same surface as the NWs / NPs). For example, a portion of the top surface of the substrate can be etched to connect the electrical contact. This electrical contact allows for vertical hole tunneling injection and vertical electron tunneling injection. Thus, the substrate can function as an electrode.

[0067] In further embodiments, the nanowires or nanopyramids can be grown on a substrate and then removed (e.g., peeled) from the substrate and transferred to another substrate. Removal can proceed by etching, peeling, spalling, or electrochemical removal / peeling. The mask layer can be removed from the substrate in combination with the nanowires or nanopyramids, or the nanowires or nanopyramids can be removed from both the substrate and the mask layer. The nanowires or nanopyramids removed from the original substrate can be transferred to a new substrate (optionally with the removed mask layer). The new substrate can include any of the features of the substrates mentioned herein. Alternatively, the new substrate can be composed of a doped or conductive substrate, such as a metal (Co, Ti, Mo, stainless steel, etc.), that functions as an electrical contact. The new substrate can be rigid or a thin film, enabling flexible devices. The electrical contact allows for vertical charge carrier tunneling injection into or from the doped / conductive substrate. Thus, the doped / conductive substrate can function as, or be, an electrode.

[0068] For example, with a metal substrate, the same advantage of high electrical conductivity from the substrate applies in terms of tunneling through the mask layer.

[0069] Therefore, the present invention provides Metal substrate; a structure comprising a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; and a plurality of nanowires or nanopyramids are present on the substrate within the opening, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; Provides structure.

[0070] The metal substrate, in this example, is a conductive metal, distinct from a semiconductor. The nanowires or nanopyramids reside on the substrate and are typically in direct electrical contact with the substrate. The considerations regarding their location on the metal substrate (e.g., perpendicular to the substrate) are the same as for the doped substrate.

[0071] In such embodiments, the same characteristics as for the doped substrate embodiment apply with respect to the mask layer, the nanowires / nanopyramids, the device, etc., and will not be repeated here for the sake of brevity.

[0072] The same considerations apply to coalesced structures, i.e., nanostructures or non-planar films formed from the coalescence of III-V continua.

[0073] [Nanowires / Nanopyramids] Discussion of nanowires (NWs) herein applies equally to nanopyramids (NPs) where technically possible. Discussion of nanowires / nanopyramids can refer to the core of said nanowire / nanopyramid or the core in combination with additional layers positioned thereon.

[0074] To produce commercially important nanowires or nanopyramids, they are preferably grown epitaxially on a substrate, ideally perpendicular to the substrate, ideally in the 0111 (cubic) or 0001 (hexagonal) direction. The phrase "grown from the substrate at the opening" means that the nanowire / nanopyramid is located above the opening, with a portion of the nanowire / nanopyramid extending down to the substrate at the opening, preferably forming an epitaxial relationship with the substrate. Alternatively, the nanowire / nanopyramid is present in the opening of the mask layer. Alternatively, the nanowire / nanopyramid is nucleated or extends from the opening in the mask layer.

[0075] In growing nanopyramids, the triangular faces typically terminate in (1-101) or (1-102) planes. The sides of the (1-101) faceted triangles may converge at the apex, or they may form new faceted (1-102) planes before converging at the apex. In some cases, nanopyramids are truncated, terminating at their apex in a {0001} plane.

[0076] Preferably, said nanowires and / or nanopyramids have pyramidal tips.

[0077] Ideally, there would be no lattice mismatch between the growing nanowires or nanopyramids and the substrate layer, but nanowires or nanopyramids can accommodate much more lattice mismatch than, for example, thin films.

[0078] The growth of nanowires / nanopyramids can be controlled by the flux ratio, for example, a high group V flux promotes the growth of nanopyramids.

[0079] The grown nanowires can be described as essentially one-dimensional, with widths or diameters on the nanometer scale and lengths typically ranging from a few hundred nanometers to a few micrometers. Ideally, the nanowires have a diameter of 500 nm or less. Ideally, the nanowires have a diameter of 50-500 nm, although they can also have diameters greater than a few micrometers (called microwires).

[0080] Thus, the nanowires grown in the present invention can have lengths from 250 nm to several micrometers, e.g., 5 micrometers. Preferably, the nanowires have a length of at least 1 micrometer. If multiple nanowires are grown, it is preferred that they all meet these dimensional requirements. Ideally, at least 90% of the nanowires grown on the substrate have a length of at least 1 micrometer. Preferably, substantially all of the nanowires have a length of at least 1 micrometer.

[0081] The height of the nanopyramids may be between 250 nm and 1 micrometer, for example between 400 and 800 nm, for example about 500 nm.

[0082] Furthermore, it is preferred that the grown nanowires or nanopyramids have the same dimensions, e.g., within 10% of each other. Thus, at least 90% (preferably substantially all) of the nanowires or nanopyramids on a substrate preferably have the same diameter and / or the same length (i.e., within 10% of each other's diameter / length). Thus, those skilled in the art essentially seek homogeneity and nanowires or nanopyramids that are substantially the same in dimensions.

[0083] The length of the nanowires or nanopyramids is often controlled by the length of time the growth process is carried out: the longer the process, the (much) longer the nanowires will generally be.

[0084] The nanowires or nanopyramids typically have a hexagonal (hexagonal) cross-sectional shape. The nanowires can have a cross-sectional diameter (i.e., their thickness) ranging from 25 nm to several microns. As noted above, the diameter is ideally constant throughout the majority of the nanowire. Nanowire diameter can be controlled by manipulating growth parameters such as the substrate temperature and / or the ratio of atoms used to create the nanowire, as further described below.

[0085] Additionally, the length and diameter of the nanowires or nanopyramids can be affected by the temperature at which they are formed: higher temperatures result in higher aspect ratios (i.e., longer and / or thinner nanowires). One skilled in the art can manipulate the growth process to design nanowires or nanopyramids of desired dimensions.

[0086] The nanowires or nanopyramids of the present invention are formed from at least one III-V compound, preferably a III-N compound. The III options are B, Al, Ga, In, and Tl. The preferred options here are Ga, Al, and In.

[0087] The options for Group V are N, P, As, and Sb. All are preferred. N is especially preferred.

[0088] Of course, at least one element from group III and / or at least one element from group V can be used. The compound can be binary, ternary, quaternary, quinary, etc. Preferred compounds for the fabrication of nanowires or nanopyramids include AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaN, InGaAs, InSb, InAs, or AlGaAs. Compounds based on Al, Ga, and In in combination with N are also an option. The use of GaN, AlGaN, AlInGaN, or AlN is highly preferred. The above and below applies not only to the nanowire / nanopyramid core, but also to any intrinsic or doped layers on / around the core. Typically, at least one of the intrinsic or doped layers on / around the core is a ternary or quaternary compound layer, such as AlGaN.

[0089] The additional layers on / around the nanowire / nanopyramidal core have individual thicknesses in the range of 10-1000 nm.

[0090] Most preferably, the nanowires or nanopyramids are composed of Ga, Al, In, and N (including doping atoms as described below).

[0091] The ternary compound may be represented by the formula XYZ, where X is a Group III element, Y is a Group III element different from X, and Z is a Group V element. The molar ratio of X to Y in XYZ is preferably 0.1 to 0.9, i.e., the formula is preferably X x Y 1-x Z, and the subscript x is 0.1 to 0.9.

[0092] Quaternary systems are also sometimes used, for example, x B 1-x C Y D 1-y (wherein A and B are group III elements and C and D are group V elements) or formula A x B y C 1-x-yD, where A, B, and C are Group III elements and D is Group V. Again, the subscripts x and y are typically between 0.1 and 0.9. Other options will be apparent to those skilled in the art.

[0093] Although ternary / quaternary nanowires or nanopyramids can also be used, it is preferable to use binary materials such as GaN for the nanowire core. Thus, the nanowire / nanopyramid may comprise GaN, e.g., n-GaN or p-GaN, preferably p-GaN. This is particularly preferred for UVC / UVB devices. The nanowire or nanopyramid core may comprise or consist of GaN, e.g., n-GaN or p-GaN, preferably p-GaN. GaN has been shown to grow particularly well by SAG on graphene hole masks and to form a good interface with graphene (outside the graphene openings). The presence of Al in the core generally results in poorer growth due to reduced growth selectivity. Therefore, it is preferable to avoid Al in the nanowire / nanopyramid core. Nanoislands of Al-containing materials (e.g., Al(Ga)N nanoislands) can be used to promote NW / NP nucleation.

[0094] When GaN, eg, n-GaN or p-GaN, is used for the nanowires / nanopyramids, good conduction is observed from the substrate through the graphene mask and through the nanowires.

[0095] As previously mentioned, the nanowires / nanopyramids of the present invention typically extend above the surface of the mask layer. They grow / extend laterally (i.e., coplanar with the substrate / mask) such that only the inner portion of the NW / NP core is formed above the opening in the mask layer. The NW / NP can grow from the opening in the mask and grow laterally (i.e., radially) to cover at least a portion of the top surface of the mask layer.

[0096] [doping] The nanowires or nanopyramids of the present invention can include pn, np, nip, or pn junctions, enabling their use in, for example, LEDs. The nanowire or nanopyramid core typically has the same doping type as the substrate (e.g., if the substrate is n-doped, the nanowire or nanopyramid core will be n-type, and vice versa). These may also be in the form of additional layers formed on or around the NW / NP core. Thus, the NWs or nanopyramids of the present invention optionally comprise an undoped intrinsic semiconductor region between the p-type and n-type semiconductor regions. This intrinsic region may consist of a single layer of material or a heterostructure consisting of multiple quantum wells and barriers.

[0097] Therefore, it is preferred that the nanowire or nanopyramid is doped. Preferably, not only the core but also at least one additional layer on / around the core is doped. Doping typically involves introducing impurity ions into the nanowire, such as during MBE or MOVPE growth. Doping levels are in the range of ∼10 15 / cm 3 ~10 20 / cm 3 The nanowires or nanopyramids can be p-type doped or n-type doped as desired. As mentioned above, the core of the nanowire / nanopyramid can be p-type doped, e.g., p-GaN. This is particularly preferred for UVC / UVB devices.

[0098] n-type (p-type) semiconductors are formed by doping an intrinsic semiconductor with donor (acceptor) impurities, resulting in a higher electron (hole) concentration than the hole (electron) concentration. Suitable donors (acceptors) for III-V compounds include Te, Sn, and Si (Be, Mg, Zn). Si is amphoteric and can act as either a donor or an acceptor depending on the site to which it is directed, depending on the orientation of the growth surface and the growth conditions. Dopants can be introduced during the growth process or by ion implantation after the formation of the nanowires or nanopyramids.

[0099] To obtain a high external quantum efficiency (EQE) of an LED, a high carrier injection efficiency is required.

[0100] The nanowire / nanopyramid may include an additional n-layer, in-layer, p-layer, ip-layer, nip-layer, or pin-layer, preferably an additional pin-layer or additional nip-layer, disposed, for example, on or around the NW / NP. The nanowire / nanopyramid can further include, for example, a p-AlGaN layer, an i-AlGaN layer, and an n-AlGaN layer (e.g., in that order, with the p-AlGaN adjacent to the core, e.g., the p-GaN core). Thus, in certain embodiments, the nanowire or nanopyramid includes or consists of a p-GaN core, with p-AlGaN, i-AlGaN, and n-AlGaN layers thereon. At least one of these layers, e.g., the top n-AlGaN layer, can extend continuously over multiple underlying layers and the NW / NP core.

[0101] The top layer (e.g., an n-type layer, preferably n-AlGaN) can function as a top-emitting transparent electrode. Transparent means transparent to the light emitted by the nanowires / nanopyramids, e.g., in the case of a UV-C LED, the layer is transparent to at least UV-C light. In the case of a photodetector, transparent means transparent to all incident light. For example, if the structure / device is a solar cell, transparent means transparent to at least sunlight.

[0102] The nanowires / nanopyramids usually have an Al-containing layer. Because the ionization energy of Mg acceptors increases with increasing Al content in AlGaN alloys, it is difficult to obtain higher hole concentrations in AlGaN alloys with high Al content. To obtain higher hole injection efficiency (especially in cladding / barrier layers with high Al content), we have devised several strategies that can be used individually or together.

[0103] Therefore, there are problems to be overcome in the doping process. It is preferable that the nanowires or nanopyramids of the present invention contain Al, for example, in at least one layer. The use of Al is advantageous because a high Al content results in a high bandgap, enabling UV-C LED emission from the active layer of the nanowire or nanopyramid and / or avoiding absorption of the emitted light in the doped cladding / barrier layer. With a high bandgap, UV light is less likely to be absorbed in this part of the nanowire or nanopyramid. Therefore, it is preferable to use AlN or AlGaN for the nanowire or nanopyramid.

[0104] However, p-type doping of AlGaN or AlN to achieve high electrical conductivity (high hole concentration) is difficult because the ionization energy of the Mg or Be acceptors increases as the Al content in the AlGaN alloy increases. The inventors have proposed various solutions to maximize electrical conductivity (i.e., maximize hole concentration) in AlGaN alloys with high average Al content.

[0105] When one of the layers / regions of the nanowire or nanopyramid comprises AlN or AlGaN, achieving high electrical conductivity by introducing p-type dopants becomes a challenge.

[0106] One solution relies on short-period superlattices (SPSLs). In this method, instead of a uniform AlGaN layer with a high Al content, a superlattice structure is grown with alternating layers of different Al content. For example, a cladding layer with 35% Al content is grown with an AlGaN layer with x=0.30 / y=0.40. x Ga 1-x N:Mg / Al y Ga 1-yIt can be replaced with an SPSL having a thickness of 1.8 to 2.0 nm and consisting of an alternating stack of N:Mg. Since the ionization energy of acceptors in the layer with a low Al composition is low, the hole injection efficiency is improved without sacrificing the barrier height of the cladding layer. This effect is further enhanced by the polarization field at the interface. The SPSL can be followed by a highly p-doped GaN:Mg layer for better hole injection.

[0107] More generally, the inventors have found that for a p-type doped Al z Ga 1-z N alloy where x < z < y, instead of the p-type doped Al x Ga 1-x N / Al y Ga 1-y N short-period superlattice (i.e., an alternating thin layer of Al x Ga 1-x N and Al y Ga 1-y N) is proposed to be introduced into (or onto) the nanowire or nanopyramid structure (where the molar fraction x of Al is less than y). It is understood that x is 0 (e.g., GaN) and y is 1 (e.g., AlN). The superlattice period is preferably 5 nm or less, for example 2 nm. In this case, the superlattice functions as a single Al z Ga 1-z N alloy (z is the layer thickness weighted average of x and y), but has a higher conductivity than the Al z Ga 1-z N alloy. This is because the p-type doping efficiency of the low Al content Al x Ga 1-x N layer is high.

[0108] In a nanowire or nanopyramid including a p-type doped superlattice, the p-type dopant is preferably an alkaline earth metal such as Mg or Be.

[0109] A further option for solving the problem of doping nanowires / nanopyramids with Al follows a similar principle. Instead of a superlattice containing a thin AlGaN layer with low or no Al content, one can design a nanostructure that contains a gradient of Al content (mole fraction) along the growth direction of the AlGaN within the nanowire or nanopyramid. Thus, as the nanowire or nanopyramid grows, the Al content decreases / increases, then increases / decreases again, creating an Al content gradient within the nanowire or nanopyramid.

[0110] This is sometimes called polarization doping. In one method, the layers are graded from GaN to AlN or AlN to GaN. The GaN to AlN and AlN to GaN graded regions can induce n-type and p-type conduction, respectively. This occurs because of the presence of dipoles with different magnitudes than their neighbors. The GaN to AlN and AlN to GaN graded regions can be additionally doped with n-type and p-type dopants, respectively.

[0111] In a preferred embodiment, p-type doping is used in the AlGaN nanowires using Be as the dopant.

[0112] Therefore, one option would be to start with GaN nanowires / nanopyramids and gradually increase the Al and decrease the Ga content, perhaps growing AlN at a growth thickness of 100 nm. This gradient region could function as a p-type or n-type region, depending on the crystal plane, polarity, and whether the Al content decreases or increases in the gradient region. Next, the reverse process would be used to grow GaN again, creating n-type or p-type regions (opposite to the previously created region). These gradient regions could be further doped with n-type dopants such as Si and p-type dopants such as Mg or Be, respectively, to obtain n-type or p-type regions with higher charge carrier densities. The crystal plane and polarity are governed by the type of nanowire / nanopyramid, as is known in the art.

[0113] Thus, viewed from another aspect, the nanowires or nanopyramids of the present invention comprise Al, Ga and N atoms, and the concentration of Al is varied during growth of the nanowire or nanopyramid to form an Al concentration gradient within the nanowire or nanopyramid.

[0114] In a third embodiment, the doping issue in Al-containing nanowires or nanopyramids is addressed using a tunnel junction. A tunnel junction is a barrier, such as a thin layer, between two conductive materials. In the context of the present invention, the barrier acts as an ohmic electrical contact in the middle of a semiconductor device.

[0115] In one approach, a thin electron-blocking layer is inserted immediately after the active region, followed by a p-doped AlGaN cladding layer with a higher Al content than that used in the active layer. The p-doped cladding layer is followed by a highly p-doped cladding layer and a very thin tunnel junction layer, followed by an n-doped AlGaN layer. The tunnel junction layer is chosen so that electrons tunnel from the valence band of the p-AlGaN to the conduction band of the n-AlGaN, generating holes that are injected into the p-AlGaN layer.

[0116] In certain embodiments, the nanowire or nanopyramid comprises two regions of doped GaN (one p-doped and one n-doped) separated by a very thin Al layer, such as a few nanometers thick, such as 1-10 nm. It is understood that any other material that functions as a tunnel junction may be used, including a heavily doped InGaN layer.

[0117] In particular, it is surprising that a doped GaN layer can be grown on an Al layer.

[0118] Thus, in one embodiment, the present invention provides a nanowire or nanopyramid having a p-type doped (Al)GaN region and an n-type doped (Al)GaN region separated by an Al layer.

[0119] The nanowires or nanopyramids of the present invention can be grown to have radial or axial heterostructures. For example, in the case of nanowires or nanopyramids with axial heterostructures, a p-n junction can be formed axially by first growing a p-type doped core and then an n-type doped core (or vice versa). In the case of radial heterostructure nanowires or nanopyramids, the p-n junction can be formed radially by first growing a p-type doped nanowire or nanopyramid core and then growing an n-type doped semiconductor shell (or vice versa) (core-shell nanowire). The core can also be axially heterostructured and the shell can be radially heterostructured. The intrinsic shell can be located between the doped regions of a pin nanowire. For axial or radial growth, the NW or nanopyramid is formed from a first section and a second section. The two sections are differently doped to create a p-n junction or a pin junction. The first or second section of the NW or nanopyramid can be p-type doped or n-type doped. The nanowires or nanopyramids may further comprise doped core or shell layers that combine axial and radial heterostructures, forming ppin junctions, etc. (see Figures 3 and 4).

[0120] However, it is particularly preferred if the NW / NP core has a pyramidal tip and the additional p / i / n layers mirror the topography (i.e., shape) of the underlying core. The additional layers (which can be considered to form part of the nanowire / nanopyramid) can be limited to the width of the NW / NP or can be in the form of a layer continuously covering at least a portion of the nanowires / nanopyramids. In certain embodiments, at least one of the layers continuously covers at least a portion of the nanowire / nanopyramid (i.e., a potential intermediate layer of the NW / NP core between the NW / NP core and the top continuous layer). A layer continuously covering at least a portion of the NW / NP can be continuous in its upper region but void in its lower region. The top layer (e.g., top n layer) can be continuous, covering, for example, at least 50% of the nanowire or nanopyramid, e.g., at least 75%, at least 90%, or at least 99% of the nanowire. This is beneficial because the doped top layer (e.g., n-layer) can function as a transparent current spreader with acceptable sheet resistance without being too thick. Preferably, the top layer has a thickness of 100-2000 nm, e.g., 500 nm. The layers below the top layer (e.g., i-layer and below) can be continuous or discontinuous (i.e., limited to the width of the NWs / NPs).

[0121] [Epitaxy] The nanowires or nanopyramids of the present invention preferably grow epitaxially on the substrate through the openings in the mask layer. The nanowires or nanopyramids are attached to the underlying substrate by covalent bonds. Thus, at the junction of the substrate and the basal plane of the nanowire, crystal planes grow epitaxially with the nanowire. They stack on top of each other in the same crystallographic direction, enabling epitaxial growth of the nanowire. Preferably, the nanowires or nanopyramids grow vertically. Vertical here means that the nanowires or nanopyramids grow perpendicular to the substrate. In experimental science, the growth angle may not be exactly 90°, but the term vertical is understood to mean that the nanowires or nanopyramids are within about 10°, e.g., 5°, of perpendicular. Due to epitaxial growth via covalent bonds, intimate contact between the nanowires or nanopyramids and the substrate is expected.

[0122] As previously mentioned, the nanowires / nanopyramids of the present invention typically extend above the mask surface. The epitaxial relationship between the NW / NP core and the substrate is maintained despite the presence of an intermediate mask layer. Thus, in certain embodiments, the crystal structure of the NW / NP core matches the crystal structure of the substrate (i.e., there is an epitaxial relationship between the two). In certain embodiments, there is no epitaxial relationship between the NW / NP core and the mask layer. Nucleated NWs / NPs maintain their crystal orientation (epitaxy with the substrate) even as they extend laterally beyond the mask layer. The interaction between the NW / NP and the mask layer is typically through van der Waals forces (very weak bonding).

[0123] Thus, the nanowires / nanopyramids can be grown such that the crystallographic and facet orientation of the nanowires or nanopyramids is dictated by the crystalline substrate, and thus the crystallographic and facet orientations are the same for all nanowires / nanopyramids.

[0124] Surprisingly, it has been found that conduction from the substrate through the mask is superior to conduction through the openings in the mask. Graphene and other graphene-like materials (when appropriately thin) act as very efficient tunneling barriers. Therefore, extending the nanowires / nanopyramids radially onto the top surface of the mask layer improves the electrical efficiency of the device.

[0125] It will be appreciated that the substrate comprises a plurality of nanowires or nanopyramids. Preferably, the nanowires or nanopyramids grow substantially parallel to one another. Thus, it is preferred that at least 90%, such as at least 95%, and preferably substantially all, of the nanowires or nanopyramids grow from the same plane of the substrate in the same direction.

[0126] It will be appreciated that within a substrate there are many planes in which epitaxial growth can occur. Preferably, substantially all of the nanowires or nanopyramids grow from the same plane. Preferably, that plane is parallel to the substrate surface. Ideally, the grown nanowires or nanopyramids are substantially parallel. Preferably, the nanowires or nanopyramids grow substantially perpendicular to the substrate.

[0127] The nanowires of the present invention are preferably grown in the

[0111] direction for nanowires or nanopyramids with a cubic crystal structure, and in the

[0001] direction for nanowires or nanopyramids with a hexagonal crystal structure. If the crystal structure of the growing nanowire or nanopyramid is cubic, the (111) interface between the nanowire or nanopyramid and the substrate represents the plane in which axial growth occurs. If the nanowire or nanopyramid has a hexagonal crystal structure, the (0001) interface between the nanowire or nanopyramid and the substrate represents the plane in which axial growth occurs. Both the (111) and (0001) planes represent the same (hexagonal) plane of the nanowire; the nomenclature of the plane differs depending on the crystal structure of the growing nanowire.

[0128] The nanowires or nanopyramids are preferably grown by MBE or MOVPE. In MBE, molecular beams of each reactant, e.g., group III and group V elements, are preferably supplied to the substrate simultaneously. For example, MBE techniques using migration-enhanced epitaxy (MEE) or atomic layer MBE (ALMBE), which can supply group III and group V elements alternately, allow for greater control over the nucleation and growth of the nanowires or nanopyramids on the substrate.

[0129] The preferred technique is solid-source MBE, in which very pure elements such as gallium and arsenic are heated in separate effusion cells until they slowly begin to evaporate (e.g., gallium) or sublime (e.g., arsenic). The gaseous elements then condense onto the substrate, where they can react with each other. In the case of gallium and arsenic, single-crystalline GaAs is formed. The use of the term "beam" means that the evaporated atoms (e.g., gallium) or molecules (e.g., As4 and As2) do not interact with each other or with the gases in the vacuum chamber until they reach the substrate.

[0130] MBE is performed in ultra-high vacuum, with a background pressure typically around 10 -10 ~10 -9 Torr. Nanostructures are typically grown slowly, at rates up to a few microns per hour (e.g., about 10 microns), which allows for epitaxial growth of nanowires and nanopyramids, maximizing structural performance.

[0131] In MOVPE, the substrate is held in a reactor to which a carrier gas and metalorganic gases of the reactants, such as a group III-containing metalorganic precursor and a group V-containing metalorganic precursor, are preferably supplied simultaneously. Typical carrier gases are hydrogen, nitrogen, or a mixture thereof. For example, by using a pulsed layer growth technique that can alternately supply group III and group V elements, a high degree of control over the nucleation and growth of the nanowires or nanopyramids on the substrate can be achieved with MOVPE.

[0132] Epitaxial growth of nanowires or nanopyramids can provide homogeneity to the formed material, potentially improving various final properties, including structural, mechanical, optical, and electrical properties.

[0133] Epitaxial nanowires or nanopyramids can be grown from gas, liquid, or solid precursors. Because the substrate acts as a seed crystal, the deposited nanowires or nanopyramids can adopt the same lattice structure and orientation as the substrate. Epitaxy differs from other thin film deposition methods, which deposit polycrystalline or amorphous films even on single-crystalline substrates.

[0134] [Selective Area Growth of Nanowires or Nanopyramids] The nanowires or nanopyramids of the present invention can be grown, for example, by selective area growth (SAG) in the case of III-nitride nanowires. The substrate temperature can be set in a growth chamber in the case of MBE or in a reactor in the case of MOVPE, at a temperature suitable for the growth of the nanowires or nanopyramids. In the case of MBE, the growth temperature can be in the range of 300-1000°C. However, the temperature employed is specific to the nature of the nanowire material. In the case of GaN, a preferred temperature is 700-950°C, e.g., 800-900°C, e.g., 810°C. In the case of AlGaN, the range is somewhat higher, e.g., 800-980°C, e.g., 830-950°C, e.g., 850°C.

[0135] It will therefore be appreciated that the nanowire or nanopyramid may include different III-V semiconductors within the nanowire, for example starting with a GaN stem followed by an AlGaN component or an AlGaInN component, etc.

[0136] Nanowire growth can be initiated by simultaneously opening the shutters of the Ga effusion cell, nitrogen plasma cell, and dopant cell to initiate the growth of doped GaN nanowires or nanopyramids (referred to here as stems). The length of the GaN stem can be maintained between 10 nm and several hundred nanometers. The substrate temperature can then be increased as needed, and the Al shutter can be opened to initiate AlGaN nanowire or nanopyramid growth. While AlGaN nanowire or nanopyramid growth can be initiated on the substrate without growing a GaN stem, GaN stems are preferred. During nanowire or nanopyramid growth, n-doped and p-doped nanowires or nanopyramids can be obtained by opening the shutters of the n-dopant cell and p-dopant cell, respectively. For example, a Si dopant cell can be used for n-doping the nanowire or nanopyramid, and a Mg dopant cell can be used for p-doping the nanowire or nanopyramid.

[0137] The temperature of the effusion cell can be used to control the growth rate. Convenient growth rates measured for conventional planar (layer-by-layer) growth are 0.05-2 μm per hour, e.g., 0.1 μm per hour. The Al / Ga ratio can be varied by changing the temperature of the effusion cell.

[0138] The pressure of the molecular beam can also be adjusted depending on the nature of the nanowires or nanopyramids being grown. A suitable level of equivalent beam pressure is 1x10 -7 From 1x10 -4 Between Torr.

[0139] The beam flux ratio between reactants (e.g., group III atoms and group V molecules) can be varied, and the preferred flux ratio depends on the other growth parameters and the nature of the nanowires or nanopyramids being grown. In the case of nitrides, nanowires or nanopyramids are always grown under nitrogen-rich conditions.

[0140] For example, it is an embodiment of the present invention to employ a multi-step, such as two-step, growth procedure to separately optimize the nucleation of the nanowires or nanopyramids and the growth of the nanowires or nanopyramids.

[0141] MOVPE offers the significant advantage of faster growth rates for the nanowires and nanopyramids. This method is advantageous for growing radial heterostructure nanowires or nanopyramids and microwires, such as n-doped GaN cores with intrinsic AlN / Al(In)GaN multiple quantum wells (MQWs), AlGaN electron blocking layers (EBLs), and p-doped (Al)GaN shells. Furthermore, this method can be used to grow axially heterostructure nanowires and nanopyramids by varying growth parameters, such as lowering the V / III molar ratio and increasing the substrate temperature, using techniques such as pulsed growth and continuous growth modes.

[0142] More specifically, after the sample is placed in the reactor, it is necessary to evacuate the reactor and purge it with N2 to remove oxygen and moisture from the reactor. This is to avoid damage to the mask layer (e.g., graphene) at the growth temperature and to avoid unwanted reactions between oxygen and water and the precursors. The total pressure is set to 50-400 Torr. After purging the reactor with N2, the substrate is thermally cleaned in a H2 atmosphere at a substrate temperature of approximately 1200°C. The substrate temperature can then be set to a temperature suitable for the growth of the nanowires or nanopyramids. The growth temperature can range from 700-1200°C. However, the temperature employed depends on the nature of the nanowire material. For GaN, the preferred temperature is 800-1150°C, e.g., 900-1100°C, e.g., 1100°C or 1000°C. For AlGaN, the range is slightly higher, for example 900-1250°C, for example 1050-1250°C, for example 1250°C or 1150°C.

[0143] Metalorganic precursors for the growth of the nanowires or nanopyramids include trimethylgallium (TMGa) or triethylgallium (TEGa) for Ga, trimethylaluminum (TMAl) or triethylaluminum (TEAl) for Al, and trimethylindium (TMIn) or triethylindium (TEIn) for In. Dopant precursors include SiH4 for silicon and bis(cyclopentadienyl)magnesium (CpMg) or bis(methylcyclopentadienyl)magnesium ((MeCp)Mg) for Mg. The flow rates of TMGa, TMAl, and TMIn can be maintained between 5 and 100 sccm. The flow rate of NH3 can be varied between 5 and 150 sccm.

[0144] In particular, the simple use of vapor-solid deposition may allow the growth of nanowires or nanopyramids. Thus, in the context of MBE, nanowires can be formed by simply applying reactants, such as In and N, to the substrate without the use of a catalyst. This forms a further aspect of the invention, whereby semiconductor nanowires or nanopyramids formed from the elements mentioned above can be grown directly on a substrate. The term "directly" therefore refers to the absence of a catalyst film that allows the growth.

[0145] [Catalyst-assisted growth of nanowires or nanopyramids] The nanowires or nanopyramids of the present invention can also be grown in the presence of a catalyst, which can be introduced into their openings to provide nucleation sites for the growth of the nanowires or nanopyramids. The catalyst can be one of the elements that make up the nanowires or nanopyramids, so-called autocatalytic, or it can be different from any of the elements that make up the nanowires.

[0146] In catalyst-assisted growth, the catalyst can be Au or Ag, or a metal from the group used to grow the nanowire or nanopyramid (e.g., a group III metal), particularly one of the metallic elements that make up the actual nanowire or nanopyramid (self-catalysis). Therefore, it is possible to use another element from group III as a catalyst for growing III-V nanowires or nanopyramids. For example, Ga can be used as a catalyst for Ga-V nanowires or nanopyramids. Preferably, the catalyst is Au, or the growth is self-catalytic (i.e., Ga for Ga-V nanowires or nanopyramids). The catalyst can be deposited on the substrate in the holes patterned through the mask and, optionally, a masking layer, to serve as nucleation sites for the growth of the nanowire or nanopyramid. Ideally, this can be achieved by providing a thin film of catalytic material on the masking layer after holes have been etched into the layer. When the temperature is raised to the NW or nanopyramid growth temperature, the catalyst film melts and the catalyst forms nanometer-sized particle-like droplets on the substrate, and these droplets form the growth points of the nanowires or nanopyramids.

[0147] This is called vapor-liquid-solid growth (VLS) because the catalyst is a liquid, the molecular beam is a vapor, and the nanowire or nanopyramid is a solid component. In some cases, the catalyst particles become solid during the growth of the nanowire or nanopyramid, via a so-called vapor-solid-solid growth (VSS) mechanism. As the nanowire or nanopyramid grows (via the VLS method), a droplet of liquid (e.g., gold) remains on top of the nanowire. Because this droplet remains on top of the nanowire or nanopyramid after growth, it may play a major role in contacting the top electrode.

[0148] As mentioned above, it is also possible to prepare self-catalytic nanowires or nanopyramids, meaning that one of the components of the nanowire or nanopyramid acts as a catalyst for its growth.

[0149] For example, a layer of Ga can be applied to a masking layer and melted to form droplets that act as nucleation sites for the growth of Ga-containing nanowires or nanopyramids, with the Ga metal portion again located at the top of the nanowire.

[0150] More specifically, for MBE-grown nanowires, a Ga / In flux can be applied to the substrate surface for a period of time to initiate the formation of Ga / In droplets on the surface as the substrate is heated. The substrate temperature can then be set to a temperature suitable for the growth of the nanowire or nanopyramid. Growth temperatures can range from 300 to 700°C. However, the temperature employed is specific to the nature of the materials in the nanowire, the catalyst material, and the substrate material. For GaAs, a preferred temperature is 540 to 630°C, e.g., 590 to 630°C, e.g., 610°C. For InAs, the range is lower, e.g., 420 to 540°C, e.g., 430 to 540°C, e.g., 450°C.

[0151] Nanowire growth can be initiated after the catalyst film has been deposited and melted by simultaneously opening the shutters of the Ga / In emission cell and the counterion emission cell.

[0152] The temperature of the emission cell can be used to control the growth rate. Convenient growth rates measured for conventional planar (layer-by-layer) growth are between 0.05 and 2 μm per hour, e.g., 0.1 μm per hour.

[0153] The pressure of the molecular beam can also be adjusted depending on the nature of the nanowire or nanopyramid being grown. A suitable level of beam equivalent pressure is 1×10 -7 From 1×10 -5 Between Torr.

[0154] The beam flux ratio between the reactants (eg, group III atoms and group V molecules) can be varied, and the preferred flux ratio depends on the other growth parameters and the nature of the nanowires or nanopyramids being grown.

[0155] The beam flux ratio between reactants has been shown to affect the crystalline structure of the nanowires. For example, when Au is used as a catalyst, a growth temperature of 540 °C, a Ga flux corresponding to a planar (layer-by-layer) growth rate of 0.6 μm per hour, and a beam equivalent pressure (BEP) of 9×10 for As4 are used. -6 In contrast, GaAs nanowires or nanopyramids grown at Torr yield a wurtzite crystal structure. At the same growth temperature, but with a planar growth rate of 0.9 μm / h for As and 4 × 10 for BEP, -6 When GaAs nanowires or nanopyramids are grown using a Ga flux equivalent to Torr, a zinc blende crystal structure is obtained.

[0156] The nanowire diameter can sometimes be varied by changing the growth parameters. For example, if a self-catalytic GaAs nanowire or nanopyramid is grown under conditions where the axial nanowire or nanopyramid growth rate is determined by the As flux, the diameter of the nanowire or nanopyramid can be increased or decreased by increasing or decreasing the Ga:As flux ratio. Thus, one skilled in the art can manipulate the nanowire or nanopyramid in various ways. Furthermore, the diameter can also be varied by growing a shell around the nanowire or nanopyramid core, creating a core-shell geometry.

[0157] Thus, it is an embodiment of the present invention to employ a multi-step, eg, two-step, growth procedure to separately optimize nanowire or nanopyramid nucleation and nanowire or nanopyramid growth.

[0158] Furthermore, the size of the holes can be controlled so that only one nanowire or nanopyramid can grow in each hole. Thus, preferably, only one nanowire or nanopyramid grows per hole in the mask. Finally, the holes can be made large enough that the catalyst droplets formed within the holes allow for the growth of nanowires or nanopyramids. In this way, regular arrays of nanowires or nanopyramids can be grown, even with Au catalysts.

[0159] [Combined structure] As multiple nanowires or nanopyramids grow from the substrate, the nanowires / nanopyramids may coalesce at a distance from the substrate or directly on top of the mask layer. It can be beneficial to form large-area structures by coalescing aligned nanowires / nanopyramids or by coalescing one of the top layers (e.g., n-AlGaN). The coalesced nanowire structure may appear almost film-like (e.g., like a corrugated film, as described below, when the NWs / NPs have pyramidal tips). However, in certain embodiments, the cores of the nanowires / nanopyramids are separate. In certain embodiments, there is at least one layer (e.g., a top n-layer, e.g., n-AlGaN) that covers at least a portion of the multiple nanowires / nanopyramids, e.g., by the coalesced structure of the layer. In such a scenario, this layer can be considered as a layer that continuously covers the multiple nanowires / nanopyramids, or at least some / most of them.

[0160] Coalescence refers to the lateral joining of two or more nanostructures during growth. In the case of coalesced nanowires / nanopyramids, the "island" nanostructures grown between them are typically inevitably coalesced, resulting in the formation of 2D or 3D structures. For coalescence to occur, the nanostructures preferably have the same crystal lattice orientation, i.e., the coalesced nanowires / nanopyramids or their doping layers preferably have nearly identical epitaxial relationships to the substrate, so that the formation of gaps and dislocations is largely eliminated.

[0161] In certain embodiments, the nanowire or nanopyramid cores do not coalesce. Preferably, the nanowire / nanopyramid coalescence is induced at least by a top doped layer (e.g., n-AlGaN) continuously covering at least a portion, preferably all, of the nanowires / nanopyramids (or at least 50%, at least 75%, or at least 90%, or at least 99% of the nanowires / nanopyramids).

[0162] [Waveform / non-planar structure] The nanowires and / or nanopyramids preferably have pyramidal tips. When a layer (e.g., an n-AlGaN top layer) continuously covers at least a portion of the NWs / NPs, the top surface of the structure is preferably nonplanar and / or corrugated, with pyramidal tips on the surface. Thus, the nonplanar / corrugated layer / film is preferably a nonplanar layer / film comprising multiple protrusions, with the protrusions (e.g., pyramidal protrusions) positioned on the nanopyramid / nanowire tips. The nonplanar / corrugated structure is also nanometer-scale, e.g., 10-1000 nm thick. The top layer mimics the topography of the underlying nanostructure. In certain embodiments, the multiple NWs / NPs (optionally coated with a layer continuously covering at least a portion of them) have a corrugated structure and / or are not planar. Therefore, this structure is typically ridged. Therefore, it is typically different from a planar thin film (i.e., a flat thin film) grown on a substrate.

[0163] The corrugated structure is beneficial as it allows for good light extraction for both transverse electric (TE) and transverse magnetic (TM) polarizations (see Figure 5). Oftentimes, manufacturers of nanostructured devices etch a corrugated / ridged design to improve light extraction. In this case, by using pyramidal-tipped NW / NPs, the corrugation can be achieved without a subsequent etching step. Using the pyramidal-tipped NW / NP geometry offers advantages in terms of ease of fabrication and light extraction.

[0164] At least the NW / NP cores can be separate (i.e., non-coalesced), or alternatively, the entire NW / NP structure can be coalesced, i.e., ridged, such that multiple nanowires / nanopyramids resemble (or are) a corrugated film. The corrugated layer / film in this example is preferably a non-planar layer containing multiple protrusions, where the protrusions (e.g., pyramid tips) are the tips of the nanopyramids / nanowires. A coalesced structure is beneficial because the top continuous layer acts as a transparent electrode, onto which top finger electrodes can be placed.

[0165] Thus, the structure of the present invention can include a corrugated continuous III-V film overlying the mask layer and extending from the opening in the mask layer. The film typically extends beyond the mask layer. For NWs / NPs, the film typically has an epitaxial relationship with the substrate. The non-planar continuous III-V structure is typically formed from multiple coalesced nanowires or nanopyramids grown in the opening, the nanowires or nanopyramids comprising at least one semiconducting III-V compound. The film can have different layers corresponding to different layers of the nanowires / nanopyramids described above.

[0166] Accordingly, the present invention provides a structure, wherein said structure comprises: doped substrate; a mask layer on top of the substrate, the mask layer having a plurality of openings therethrough; and a corrugated continuous III-V film overlying the layer and extending from the opening, the corrugated continuous III-V film being formed, for example, from a plurality of coalesced nanowires or nanopyramids grown in the opening, the nanowires or nanopyramids comprising at least one semiconductor III-V compound; Includes.

[0167] The NW / NP cores may be coalesced, and additional intrinsic and / or doped layers (e.g., p-, i-, and / or n-layers) may continuously cover at least a portion, preferably all, of the coalesced nanowires / nanopyramids. The corrugated film (typically grown by the coalescence of multiple nanowires or nanopyramids) typically grows from the substrate at the openings. Thus, the corrugated film can be viewed as multiple coalesced nanowires or nanopyramids grown from the substrate at the openings.

[0168] It will be understood that discussions of nanowires / nanopyramids, or additional intrinsic or doped layers for separate NWs / NPs, also apply to structures incorporating NWs / NPs or additional layers. For example, the length of a nanowire discussed above also applies to the length of an incorporated nanowire. Definitions of structures including nanowires or nanopyramids (e.g., related to the nature of the materials including the substrate, mask layer, NWs / NPs, etc.) are also applicable here, where technically possible. The nanowire / nanopyramid material is also applicable to corrugated films. The corrugated film can be composed of the same layers as the nanowires / nanopyramids.

[0169] [Device / Application] Semiconductor nanowires or nanopyramids have a wide range of applications. Because they are semiconductors, they have potential applications in all areas where semiconductor technology is useful. They are primarily used in integrated nanoelectronics and nano-optoelectronics applications.

[0170] Devices ideal for these configurations include solar cells, transistors, laser LEDs, and photodetectors.

[0171] The semiconductor nanowires or nanopyramids have utility in LEDs, particularly UV LEDs, especially UV-A, UV-B, or UV-C LEDs, more preferably UV-C LEDs. Accordingly, the present invention provides devices, such as optoelectronic devices, that include a structure as defined herein, e.g., a solar cell, a photodetector, or an LED, preferably an LED, more preferably a UV LED, more preferably a UV-C LED. Preferably, the device (whether LED or otherwise) emits or absorbs light in the UV region, preferably the UV-C region. In the present disclosure, any discussion regarding light emission in the context of a light emitter, such as a UV LED, also applies to light absorption in the case of a light absorber.

[0172] In the structures / devices of the present invention, individual NWs / NPs can be considered as individual LED nanostructures (or individual photodetectors / solar cells). The nanowires or nanopyramids comprise the light-generating (or light-absorbing) region.

[0173] It will be understood that the device of the present invention includes electrodes for conducting charge through the device. To create an optoelectronic device, the top of the nanowire or nanopyramid preferably includes a top contact. In one embodiment, a conventional top contact is disposed on the top layer of the nanowire / nanopyramid, e.g., a top-layer n-type layer (e.g., n-AlGaN) disposed on the nanowire / nanopyramid core (which may extend continuously over the underlying layers and the NW / NP core). This top contact has a finger design to reduce the amount of contact blocking light from entering or exiting the device. The top contact may be a strip-like sheet of metal, e.g., a ribbon-like strip, with one dimension substantially larger than the other. Therefore, it is preferred that the metal contact or metal stack contact layer does not cover the entire nanowire / nanopyramid. Therefore, the area covered by the n-contact is typically 50% or less, preferably 20% or less, of the top surface area of ​​the nanowire or nanopyramid. A single finger contact can be used per LED device, made of metal, which provides good ohmic contact to the top doped NW / NP layer. Alternatively, multiple finger contacts can be used. The finger opening (the distance between adjacent fingers) is typically larger than the width of the NW / NP, so most NW / NPs do not have metal fingers on them (which would allow light to escape). The thick n-AlGaN top layer has a low enough sheet resistance to spread the current laterally from the fingers before it is injected into the active (intrinsic) region.

[0174] In one embodiment, a conventional top contact metal layer stack can be used. The contacts described herein are typically metallic and are selected, for example, to exhibit ohmic behavior with the top layer.

[0175] In certain embodiments, it is preferred that light is emitted (or absorbed in the case of a photodetector) from the top of the device, i.e., substantially away from the substrate. Therefore, it is preferred that the device is not a flip-chip device or configuration. Preferably, there is no (continuous) reflective layer on top of the NW / NP structure that would direct light back towards the substrate. In certain embodiments, the NW / NP does not include a (continuous) reflective layer covering the top of the NW / NP structure.

[0176] The contacts / contact pads may be electrically connected to appropriate power leads of the device package.

[0177] As mentioned above, the doped substrate can act as an active injector of current. In certain embodiments, a conductive path exists from the substrate through the mask layer to the nanowire or nanopyramid. If the nanowire / nanopyramid extends laterally across the top surface of the mask, the conductive path is elevated through the region of the nanowire / nanopyramid that extends beyond the mask layer. The conductive path is vertical, i.e., oriented in the same axis as the nanowire / nanopyramid (see Figures 1-4). If the substrate is p-doped, the conduction path for holes (same as the current flow direction) is from bottom to top. For n-doped substrates, the conduction path for electrons is from bottom to top (note: the current flow direction is defined as opposite to the electron flow direction). Surprisingly, it has been found that conduction from the substrate through the mask is higher than conduction through the openings in the mask. Conduction through the opening in the mask layer can be poor due to the formation of an insulating or defect layer at the interface between the NW / NP and the substrate, and therefore it is important to laterally overgrow the NW / NP outside the opening in the mask layer. From this perspective, a small opening is beneficial to maximize vertical conduction by tunneling.

[0178] Unless otherwise specified, the term "bottom" refers to the substrate side of the substrate nanowire / nanopyramid, and the term "top" refers to the side of the substrate nanowire / nanopyramid opposite the substrate.

[0179] The invention will now be further described in connection with the following non-limiting examples and figures.

[0180] [Brief description of the drawing] Figure 1 shows aligned flat-tip nanowires epitaxially grown on a doped crystalline substrate with a mask layer etched with holes. The nanowires first nucleate epitaxially on the substrate through the holes in the mask layer. The nanowires continue to grow both axially and radially, growing above the mask layer while maintaining an epitaxial relationship with the substrate. The nanowires are grown as axial heterostructures to create either an axial p-i-n nanowire device structure on a p-doped substrate (as shown) or an n-i-p junction nanowire device structure on an n-doped substrate (not shown). The vertical dashed arrows in the p-i-n nanowire device indicate hole current injected from the p-doped substrate into the p-doped nanowire by tunneling through the mask layer.

[0181] Figure 2 is similar to Figure 1, except that the nanowires have pyramidal tips. The nanowires are grown as axial heterostructures to create either axial p-i-n nanowire device structures on p-doped substrates (as shown) or n-i-p junction nanowire device structures on n-doped substrates (not shown).

[0182] Figure 3 is similar to Figure 2, with the only difference being that the nanowires are fully coalesced, either directly onto a doped nanowire core or as a result of the growth of an additional doped nanowire shell layer. The nanowires are grown as axial heterostructures to create axial p-i-n and p-i-n nanowire device structures on p-doped substrates (as shown), or n-i-p and n-i-n junction nanowire device structures on n-doped substrates (not shown), respectively.

[0183] Figure 4 is similar to Figure 3, but uses coalesced nanopyramids instead of coalesced nanowires. The nanopyramids are grown as axial heterostructures to create axial p-i-n and p-i-n nanopyramid device structures (as shown) on p-doped substrates, or n-i-p and n-i-n junction nanopyramid device structures (not shown) on n-doped substrates, respectively.

[0184] Figure 5 shows a top-emitter nanowire GaN / AlGaN UV LED device grown on a hole-etch mask layer formed on a p-doped Si substrate according to the present invention. The dashed arrows indicate idealized TM-polarized and TE-polarized light generated in the active multiple quantum well region from one exemplary nanowire and how they are directed toward the pyramidal top surfaces of several neighboring nanowires. The LED device has a metal bottom contact to the Si substrate and metal finger contacts covering the top surfaces of several of the nanowires.

[0185] Figure 6(a) and (b) are top-view and 30° tilted scanning electron microscope (SEM) images, respectively, of n-GaN nanowires grown on the graphene-covered portion of a doped Si wafer.

[0186] Figure 6(c) and (d) are top-view and 30° tilted scanning electron microscope (SEM) images, respectively, of n-GaN nanowires grown in nearby graphene-free regions on a doped Si wafer.

[0187] Figure 6e shows the ++ -Graphene-covered area of ​​Si wafer (filled circle) and n ++ Figure 1 shows the current density-voltage characteristics of n-GaN nanowires grown on the non-graphene-covered portion (filled squares) of a Si wafer, respectively.

[0188] [Example] Figure 6 shows the area of ​​approximately 1 cm 2 The central part is covered with a single layer of polycrystalline CVD graphene (i.e., one atomic layer of carbon atoms in a hexagonal crystal pattern), and the 19 / cm 3 2-inch diameter n ++ This figure shows experimental results of self-assembled n-GaN nanowires grown by plasma-assisted molecular beam epitaxy (MBE) on a Si wafer (resistivity <0.005 Ohm.cm). Radio-frequency etching was performed immediately before graphene transfer to reduce the thickness of the native SiO2 present on the Si substrate. After graphene transfer, the sample was loaded into the MBE chamber. Silicon-doped n-GaN nanowires were then grown under nitrogen-rich conditions in an MBE system equipped with a Knudsen Si cell, a SUMO Ga cell, and a Riber S63 RF nitrogen plasma source. A two-step procedure was used for n-GaN nanowire growth. The first step was at a growth temperature of 720 °C for 30 min with a Ga flux of 0.6 × 10 -7 Torr, followed by an 11-minute ramp-up, followed by a growth temperature of 750 °C for 60 minutes with a Ga flux of 1.8 × 10 -7 The second growth stage was performed at Torr. The Si cell was kept at 1200 °C for the first growth stage and 1255 °C for the second growth stage, the N plasma was constantly maintained at a nitrogen flow rate of 0.8 sccm, and the RF power was 450 W.

[0189] Figures 6(a) and (b) show top-view and 30° tilted scanning electron microscope (SEM) images of n-GaN nanowires grown on a graphene-covered Si wafer. The top-view image (a) reveals that the GaN nanowire facets are aligned in the same direction and epitaxially coalesce over a large area. This indicates that the GaN nanowires are epitaxial with the Si(111) substrate and that nucleation of the GaN nanowires begins at the openings in the graphene.

[0190] n ++ To measure the conduction between the -Si wafer and the n-GaN nanowire, we used the n-GaN nanowire as shown in the inset of Figure 6(e). ++ -Ohmic metal contacts were made on the bottom of the Si wafer (negative potential) and on the top of the n-GaN nanowires (positive potential) for 1 mm. 2 As a result, n ++ -Graphene-covered area of ​​Si wafer (filled circle) and n ++ Figure 6(e) shows the current density-voltage characteristics of n-GaN nanowires grown on the non-graphene-covered portions (filled squares) of the Si wafer. The device fabricated on the graphene-covered portion of the Si wafer exhibits very high electrical conductance in both the positive and negative bias directions, exhibiting near-ohmic behavior, whereas the non-graphene-covered portion exhibits onset voltages of approximately 1 V and -2 V in the forward and reverse directions, respectively. Measurements on the graphene-covered portion of the Si substrate show high conductivity and near-ohmic behavior, indicating tunneling.

Claims

1. doped substrate; a structure comprising a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; and A structure wherein a plurality of nanowires or nanopyramids are grown from the substrate within the openings, the nanowires or nanopyramids comprising at least one III-V semiconductor compound.

2. 10. A structure according to any preceding claim, wherein the substrate is p-doped or n-doped, preferably p-doped.

3. The substrate is 10 15 / cm 3 ~10 22 / cm 3 , e.g., 10 18 / cm 3 ~10 21 / cm 3 10. The structure of any preceding claim, wherein the structure is doped to a level of

4. The substrate is silicon, Ge, SiC, Ga 2 O 3 Or a structure according to any of the preceding claims, which is a III-V substrate, preferably a silicon substrate.

5. 10. A structure according to any preceding claim, wherein the doped substrate acts as a current injector.

6. 10. The structure of any preceding claim, wherein the structure includes electrical contacts on the doped substrate.

7. The mask layer is made of a two-dimensional material, such as graphene, hexagonal-BN, MoS 2 , W.S. 2 , MoSe 2 , NbSe 2 , TaSe 2 , Bi 2 Te 3 , Bi 2 Se 3 or NiTe 2 10. A structure according to any of the preceding claims, which is a mask layer, preferably a graphene mask layer, preferably an atomically thick graphene mask layer.

8. 10. A structure according to any preceding claim, wherein the nanowire or nanopyramid comprises GaN, preferably a GaN core, preferably a doped GaN core, preferably a p-GaN core.

9. 10. A structure according to any preceding claim, wherein the nanowires or nanopyramids extend laterally (i.e. radially) beyond the mask layer outside the opening.

10. the mask layer is a tunnel barrier, e.g., a tunnel barrier for current conduction from the substrate to the nanowire / nanopyramid or from the nanowire / nanopyramid to the substrate; For example, a tunnel barrier for vertical hole or electron tunnel injection from the doped substrate into the nanowire or nanopyramid.

10. A structure according to any preceding claim, acting as

11. 10. The structure of any preceding claim, wherein the masking layer has a thickness of 1.5 nm or less, more preferably 1 nm or less, more preferably 0.9 nm or less, more preferably 0.8 nm or less, more preferably 0.7 nm or less, more preferably 0.6 nm or less, more preferably 0.5 nm or less.

12. 10. A structure according to any of the preceding claims, wherein said mask layer is a two-dimensional material, said mask layer being 1 to 5 atomic sheets thick, preferably 1 to 4 atomic sheets thick, preferably 1 to 3 atomic sheets thick, preferably 1 to 2 atomic sheets thick, preferably 1 atomic sheet thick.

13. 10. A structure according to any preceding claim, wherein the substrate is a silicon substrate, and wherein the substrate comprises a layer of native silicon dioxide at the interface of the mask layer, preferably the layer of silicon dioxide having a thickness of less than 10 nm, preferably less than 5 nm, preferably less than 3 nm, preferably less than 2 nm, for example 1-5 nm, 1-2 nm or 2-3 nm.

14. the nanowire or nanopyramid comprises a pn junction or a pin junction; 10. A structure according to any preceding claim, wherein preferably the pn junction or pin junction comprises p-AlGaN and n-AlGaN, and preferably the nanowire or nanopyramid comprises a pin junction comprising p-AlGaN, i-AlGaN and n-AlGaN.

15. 15. The structure of claim 14, wherein the intrinsic layer (i-layer) is a multiple quantum well.

16. - if the nanowire / nanopyramid core is p-doped, additional intrinsic and n-type layers are present on the nanowire / nanopyramid core, preferably additional p-type, intrinsic and n-type layers are present on the nanowire / nanopyramid core; or - a structure according to any of the preceding claims, wherein if the nanowire / nanopyramid core is n-doped, additional intrinsic and p-type layers are present on the nanowire / nanopyramid core, preferably additional n-type, intrinsic and p-type layers are present on the nanowire / nanopyramid core.

17. 10. A structure according to any of the preceding claims, wherein the structure is an electronic or optoelectronic device, preferably a transistor, a solar cell, a laser, a photodetector or an LED, preferably an LED, preferably a UV LED, preferably a UVC LED.

18. 10. A structure according to any preceding claim, wherein the structure is not in a flip-chip configuration or does not include a light-reflecting layer covering (e.g. continuously covering) the top of the nanowire or nanopyramid.

19. A structure according to any of the preceding claims, wherein the top layer of the pn or pin junction, preferably the top n-layer, acts as a transparent current spreader.

20. 10. The structure of any preceding claim, wherein the tip of the nanowire / nanopyramid core is pyramidal.

21. 10. The structure of any preceding claim, comprising a layer continuously covering at least a portion of a plurality of nanowires / nanopyramids, e.g., at least 50%, at least 75%, at least 90%, or at least 99% of said nanowires / nanopyramids.

22. 22. The structure of claim 21, wherein the top layer of the nanowires / nanopyramids has a non-planar, e.g., corrugated, structure.

23. A structure according to claims 21-22, wherein said continuous layer is a top-doped layer, preferably an n-type top-doped layer, for example n-AlGaN.

24. 10. The structure of any preceding claim, wherein the nanowires or nanopyramids are doped.

25. 10. A structure according to any of the preceding claims, wherein the nanowire or nanopyramid is a core-shell structure or a radial heterostructure, preferably an axial heterostructure.

26. 10. A structure according to any of the preceding claims, wherein a metal contact layer or a metal stack contact layer is present on top of the nanowire or nanopyramid, preferably said metal contact layer or metal stack contact layer having a finger design, e.g. strips.

27. 10. A structure according to any preceding claim, wherein the nanowires or nanopyramids are epitaxially grown from the substrate through the openings in the mask, i.e. the nanowires or nanopyramids are epitaxial with the substrate.

28. 10. The structure of any preceding claim, wherein an electrical contact is in contact with the mask layer.

29. 10. A structure according to any preceding claim, wherein the openings in the mask layer are defects or patterned holes.

30. doped substrate; a mask layer having a thickness of 2 nm or less over the substrate, the mask layer having a plurality of openings therethrough; and a corrugated continuous III-V film overlying the mask layer and extending from the opening, the corrugated continuous III-V film being formed, for example, from a plurality of coalesced nanowires or nanopyramids grown in the opening, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; A structure containing:

31. A device, for example an optoelectronic device, such as a solar cell, a photodetector, a transistor, a laser, or an LED, preferably an LED, more preferably a UV LED, more preferably a UV-C LED, comprising a structure according to any of claims 1 to 30.

32. A method for producing a structure according to any one of claims 1 to 29, comprising the steps of: The method comprises: (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (II) growing a plurality of nanowires or nanopyramids from the substrate in a plurality of openings in the mask layer, the nanowires or nanopyramids comprising at least one III-V semiconductor compound. A method comprising:

33. 31. A method for manufacturing the structure of claim 30, comprising: (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (II) growing a plurality of nanowires or nanopyramids from the substrate in a plurality of openings in the mask layer until the nanowires or nanopyramids coalesce, the nanowires or nanopyramids comprising at least one III-V semiconductor compound. A method comprising:

34. The method according to claims 32 to 33, (III) growing an additional layer in which a pn junction or pin junction is provided in said nanowire or nanopyramid; The method further comprises:

35. (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (I') etching a plurality of holes through the mask layer; and (II) growing a plurality of nanowires or nanopyramids from the substrate in the holes, the nanowires or nanopyramids comprising at least one III-V semiconductor compound.

33. The method of claim 32, comprising:

36. (I) providing a mask layer having a thickness of 2 nm or less carried on a doped substrate; (I') etching a plurality of holes through the mask layer; and (II) growing a plurality of nanowires or nanopyramids from the substrate in the holes until the nanowires or nanopyramids coalesce, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; 34. A method for manufacturing the structure of claim 33, comprising:

37. Metal substrate; a structure comprising a mask layer having a thickness of 2 nm or less on top of the substrate, a plurality of openings are present through the mask layer; and a plurality of nanowires or nanopyramids are present on the substrate in the opening, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; structure.

38. Metal substrate; a mask layer having a thickness of 2 nm or less over the substrate, the mask layer having a plurality of openings therethrough; and a corrugated continuous III-V film overlying the mask layer and extending from the opening, the corrugated continuous III-V film being formed, for example, from a plurality of coalesced nanowires or nanopyramids grown in the opening, the nanowires or nanopyramids comprising at least one III-V semiconductor compound; A structure containing:

39. 1. A method for manufacturing a device, e.g., an optoelectronic device, comprising: The method comprises: (I) removing the nanowires or nanopyramids from the substrate in the structure of any one of claims 1 to 29; and (II) transferring the removed nanowires or nanopyramids to a different substrate, the second substrate being doped or undoped; A method comprising:

40. the mask layer is removed from the substrate in combination with the nanowires or nanopyramids, or the nanowires or nanopyramids are removed from both the substrate and the mask layer; 40. The method of claim 39.

41. The different substrates are: a metal substrate (e.g. Cu, Ti, Mo, stainless steel), preferably a substrate where a different substrate provides the electrical contact (e.g. bottom contact); or - an insulating substrate, 41. The method of claim 39 or 40.

42. 1. A method for manufacturing a device, such as an optoelectronic device, the method comprising: (I) removing the continuous III-V film from the substrate in the structure of claim 30; and (II) transferring the removed III-V film to a different substrate, the second substrate being doped / conducting or undoped / insulating; A method comprising:

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