Stacked FET SRAM cell with bottom pFET

Abstract

A semiconductor structure is presented that includes a bottom field effect transistor (FET) including multiple bottom source / drain (S / D) epi regions, a top FET including multiple top S / D epi regions, a junction dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from one of the multiple bottom S / D epi regions of the bottom FET through the junction dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET is electrically connected to back-end-of-line (BEOL) components, and the bottom FET is electrically connected to a backside power distribution network (BSPDN).

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor devices, and more particularly to the construction of stacked field effect transistor (FET) static random access memory (SRAM) cells with a bottom p-type FET (pFET).

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric, conductive, and semiconducting layers of materials above a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry has experienced rapid growth due to increasing integration densities of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In large part, this increased integration density has been achieved by shrinking semiconductor process nodes. With increasing demands for smaller size, higher speed, greater bandwidth, lower power consumption, and lower latency, chip layouts have become more complex and difficult to achieve in the manufacture of semiconductor dies.

[0004] Fin-based active devices, primarily transistors, are widely applied to the formation of standard cells and other active device configurations processed in the substrate (Front-End-Of-Line) portion of the integrated circuit manufacturing process, including FinFETs as well as more recent devices based on nanowires or nanosheets. An example technique involves the use of buried interconnect rails in the FEOL. Buried power rails (BPRs) allow transistors in the FEOL to be directly connected to a power delivery network located entirely on the backside of the integrated circuit chip. Specifically, the source or drain regions of multiple transistors are directly connected to the buried rail. The current method for achieving this configuration is to create interconnect vias to the buried rail and connect the interconnect vias to the source or drain regions through local interconnects that are part of the chip's source / drain contact level, also known as the "middle-end of line," which is the transition between active devices in the FEOL and interconnect levels (M1, M2, etc.) in the back-end of line (BEOL).

[0005] Some implementations of this approach have several drawbacks. Because the rail is buried under the active device, the size of the buried power rail (BPR) is limited by the inter-cell space between two nearby active areas. As the cell height scales down, the inter-cell space also becomes smaller, reducing the buried power rail size and increasing its resistance, which degrades circuit performance.

[0006] To achieve better performance, optimization of contacts on source / drain (S / D) epitaxy is necessary. In particular, FinFET technology and other technologies beyond FinFET, such as nanosheet technology, where S / D epitaxy can be expensive, require wraparound contacts that contact not only the top surface of the S / D epi but also the sidewall surface to maximize contact area and reduce contact resistance. As transistor device scaling progresses beyond (e.g., below) the 10-nanometer (nm) technology node, contact resistance becomes a contributing factor to the total resistance of a transistor. The term "contact resistance" is a measure of the ease with which current can flow across a metal-semiconductor interface. Reducing contact resistivity (RhoC) alone is insufficient to reduce external resistance to the target of the 10-nm technology node and beyond, and new contact structures are needed to increase the contact area. Backside contacts may be considered an ideal contact structure. However, conventional backside contacts are known to cause problems in certain semiconductor manufacturing processes. Summary of the Invention

[0007] According to one embodiment, a semiconductor structure is provided that includes a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions, a top FET including a plurality of top S / D epi regions, a junction dielectric layer disposed directly between the bottom FET and the top FET, and a node contact extending from one of the plurality of bottom S / D epi regions of the bottom FET through the junction dielectric layer and into the top FET.

[0008] According to another embodiment, a semiconductor structure is provided that includes a junction dielectric layer disposed directly between a bottom field effect transistor (FET) and a top FET, and a node contact extending from the bottom FET through the junction dielectric layer and into the top FET to electrically connect to an inverter gate.

[0009] According to yet another embodiment, a method for forming a semiconductor structure is provided, the method including forming a bottom nanosheet stack between a plurality of bottom source / drain (S / D) epi regions disposed on a sacrificial placeholder, performing a p-type field effect transistor (pFET) cut, depositing a sacrificial material in the pFET cut, forming a gate cap on the sacrificial material to form a bottom FET, forming a junction dielectric layer on the bottom FET, forming a top nanosheet stack on the junction dielectric layer and between the plurality of top S / D epi regions, removing the sacrificial layer from the top and bottom nanosheet stacks to define a first opening, depositing a replacement metal gate in the first opening, forming a gate cut and a node contact, selectively removing the sacrificial placeholder and the sacrificial material to define a second opening, wherein the node contact extends from the bottom FET through the junction dielectric layer and into the top FET, and filling the second opening with a cross-couple.

[0010] In one preferred embodiment, the bottom FET comprises an inverter gate.

[0011] In another preferred embodiment, the gate cap is placed on top of the bottom pFET gate metal.

[0012] In yet another preferred embodiment, the inverter gate directly contacts some of the bottom S / D epi regions.

[0013] In one preferred embodiment, the node contact is vertically aligned with a portion of the inverter gate.

[0014] In another preferred embodiment, the top FET is electrically connected to a back-end-of-line (BEOL) component and the bottom FET is electrically connected to a backside power delivery network (BSPDN).

[0015] In another preferred embodiment, the bit line (BL) directly contacts one of the top S / D epi regions.

[0016] In another preferred embodiment, the word line (WL) directly contacts the metal gate located in the top FET.

[0017] In yet another preferred embodiment, the gate cap directly contacts the cross-couple in the bottom FET.

[0018] In yet another preferred embodiment, a gate cap is placed on top of the bottom pFET gate metal.

[0019] Advantages of the present invention include producing transistors that consume less power, have better performance, occupy less wafer real estate, and reduce semiconductor manufacturing costs. Advantages of the present invention further include providing a method and device for constructing stacked FET SRAM with bottom pFETs by advantageously electrically connecting the node contact and inverter gate (cross-coupled) by replacing the pFET under the pass gate with a conductor, thereby improving backside contact and backside power distribution network technology for the backside power rail.

[0020] It should be noted that exemplary embodiments are described with reference to different subject matters. In particular, some embodiments are described with reference to method claims, while other embodiments are described with reference to apparatus claims. However, those skilled in the art will understand from the above and following description that, unless otherwise indicated, any combination of features belonging to one of the subject matters, as well as any combination between features relating to different subject matters, in particular between features of method claims and features of apparatus claims, is also considered to be described herein.

[0021] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0022] The present invention is provided in more detail in the following description of preferred embodiments with reference to the following drawings.

[0023] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor structure including a bottom nanosheet stack formed on a substrate, in which an internal spacer, a bottom sacrificial placeholder, a source / drain (S / D) epi region, and an interlayer dielectric (ILD) are also formed adjacent to the bottom nanosheet stack, according to one embodiment of the present invention.

[0024] [Figure 2] 2 is a cross-sectional view of the semiconductor structure of FIG. 1 after a mask layer (such as an Organic Planarization Layer (OPL)) has been deposited and patterned to perform a p-type field effect transistor (pFET) cut, in accordance with one embodiment of the present invention.

[0025] [Figure 3] 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a lateral etch is performed, according to one embodiment of the present invention.

[0026] [Figure 4] 4 is a cross-sectional view of the semiconductor structure of FIG. 3 after the OPL has been selectively removed and a sacrificial material has been deposited, according to one embodiment of the present invention.

[0027] [Figure 5] 5 is a cross-sectional view of the semiconductor structure of FIG. 4 with a dielectric capping layer formed and a nanosheet layer for a top device bonded to a bottom device by a dielectric-dielectric bonding process, according to one embodiment of the present invention.

[0028] [Figure 6]A cross-sectional view of the semiconductor structure of Figure 5 in which a top nanosheet stack has been formed, and internal spacers, source / drain (S / D) epi regions, and an interlayer dielectric (ILD) have also been formed adjacent to the top nanosheet stack, according to one embodiment of the present invention.

[0029] [Figure 7] 7 is a cross-sectional view of the semiconductor structure of FIG. 6 with a replacement metal gate (RMG) opening formed therein, according to one embodiment of the present invention.

[0030] [Figure 8] 8 is a cross-sectional view of the semiconductor structure of FIG. 7 with the dummy gate and alternating sacrificial layers of the top and bottom nanosheet stacks selectively removed, according to one embodiment of the present invention.

[0031] [Figure 9] 9 is a cross-sectional view of the semiconductor structure of FIG. 8 with a high-k metal gate (HKMG) deposited and a gate cut performed, according to one embodiment of the present invention.

[0032] [Figure 10] 10 is a cross-sectional view of the semiconductor structure of FIG. 9 in which a middle-of-line (MOL) contact is inverted, a back-end-of-line (BEOL) component is formed, and a carrier wafer is bonded to the BEOL, according to one embodiment of the present invention.

[0033] [Figure 11] 11 is a cross-sectional view of the semiconductor structure of FIG. 10 with the wafer flipped and the substrate removed, according to one embodiment of the present invention.

[0034] [Figure 12] 12 is a cross-sectional view of the semiconductor structure of FIG. 11 after the etch stop layer and remaining silicon (Si) layer have been removed and a backside ILD has been deposited, according to one embodiment of the present invention.

[0035] [Figure 13] 13 is a cross-sectional view of the semiconductor structure of FIG. 12 with the sacrificial placeholder selectively removed and back contact metallization applied, according to one embodiment of the present invention.

[0036] [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor structure of FIG. 13 with a backside power distribution network (BSPDN) connected to a metal contact, according to one embodiment of the present invention.

[0037] Throughout the drawings, the same or similar reference numbers represent the same or similar elements. DETAILED DESCRIPTION OF THE INVENTION

[0038] Embodiments in accordance with the present invention provide methods and devices for advantageously constructing stacked field-effect transistor (FET) static random access memories (SRAMs) with a bottom p-type FET (pFET) by electrically connecting the node contact and inverter gate (cross-coupled) by replacing the pFET below the pass gate with a conductor. The stacked FET architecture advantageously includes a top FET joined to the bottom FET by a junction dielectric layer. The bottom FET advantageously includes the node contact and inverter gate, and all transistor physical parameters, such as gate length, spacer thickness, and contact size, can be advantageously optimized for better transistor speed and / or lower power. Beneficially, unlike lateral transistors, much of this structural tuning does not affect the transistor pitch (the distance between transistors). In the exemplary stacked FETs with nanosheets described herein, integrated circuit (IC) vendors can advantageously vary the width of the nanosheets within a transistor. For example, nanosheets with wider sheets provide more drive current and performance. Narrower nanosheets provide less drive current but occupy less area.

[0039] Examples of semiconductor materials that can be used to form such nanosheet structures include silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors, and / or II-VI compound semiconductors. III-V compound semiconductors are materials that contain at least one element from Group III of the periodic table of elements and at least one element from Group V of the periodic table of elements. II-VI compound semiconductors are materials that contain at least one element from Group II of the periodic table of elements and at least one element from Group VI of the periodic table of elements.

[0040] However, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention. Note that for clarity, some features may not be shown in all drawings. This is not intended to be construed as a limitation of any particular embodiment, or of the scope of the illustrations, or claims.

[0041] FIG. 1 is a cross-sectional view of a semiconductor structure including a bottom nanosheet stack formed on a substrate according to one embodiment of the present invention, with an internal spacer, a bottom sacrificial placeholder, a source / drain (S / D) epitaxial region, and an interlayer dielectric (ILD) also formed adjacent to the bottom nanosheet stack.

[0042] In various exemplary embodiments, structure 5A includes a bottom nanosheet stack 25 formed on a substrate 10. An etch stop layer 12 and a silicon (Si) layer 14 are formed between the substrate 10 and the bottom nanosheet stack 25. The bottom nanosheet stack 25 includes alternating layers of a first semiconductor material (or layer) 22 and a second semiconductor material (or layer) 24. The first semiconductor material 22 can be, for example, silicon (Si), and the second semiconductor material 24 can be, for example, silicon germanium (SiGe).

[0043] In the structure 5B, in the Y-cut direction, a bottom nanosheet stack 25 is formed on a bottom dielectric isolation (BDI) layer 30. A shallow trench isolation (STI) region 15 is formed between the fins formed in the Si layer 14. A dummy gate 34 is also formed on the nanosheet stack 25.

[0044] In structure 5A, in the X-cut direction, dummy gates 34 are formed between spacers 32. Si layer 14 houses bottom sacrificial placeholders 16. Bottom source / drain (S / D) epi regions 18 are formed on the bottom sacrificial placeholders 16. ILD is deposited and planarized (e.g., by chemical mechanical polishing (CMP)) to form interlayer dielectric (ILD) regions 20 on the bottom S / D epi regions 18. For bottom nanosheet stack 25, inner spacers 26 are formed between first semiconductor materials (or layers) 22. Bottom nanosheet stack 25 rests on BDI layer 30.

[0045] The sidewalls of the BDI layer 30 are in direct contact with the sidewalls of the bottom sacrificial placeholder 16. The top surface of the BDI layer 30 is in direct contact with the bottom inner spacer 26. The bottom sacrificial placeholder 16 is vertically aligned with the bottom S / D epi region 18 and the ILD region 20. The bottom nanosheet stack 25 is vertically offset from the bottom sacrificial placeholder 16.

[0046] The top view 7 shows the bottom sheet (pFET) and the top sheet (nFET). The top view 7 shows a stacked FET with two adjacent parallel diffusion regions. Two active gates are formed perpendicular to the diffusion regions.

[0047] In one or more embodiments, substrate 10 can be a semiconductor or an insulator having an active surface semiconductor layer. Substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. Substrate 10 can be essentially (e.g., excluding impurities) a single element (e.g., silicon), can be predominantly (e.g., with doping) a single element, such as silicon (Si) or germanium (Ge), or can include a compound, such as Al2O3, SiO2, GaAs, SiC, or SiGe. Substrate 10 may also have multiple material layers, such as a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GeOI), or a silicon-germanium-on-insulator substrate (SGOI). Substrate 10 may also have other layers forming substrate 10, including high-k oxides and / or nitrides. In one or more embodiments, substrate 10 may be a silicon wafer. In one embodiment, substrate 10 is a single crystal silicon wafer.

[0048] For example, with reference to nanosheet stack 25, first semiconductor material 22 can be a first layer in a stack of sheets of alternating materials. Thus, nanosheet stack 25 includes first semiconductor material (or layer) 22 and second semiconductor material (or layer) 24. While it is specifically contemplated that first semiconductor material 22 can be formed from Si and second semiconductor material 24 can be formed from silicon germanium, it should be understood that any suitable materials can be used instead, so long as the two semiconductor materials have etch selectivity with respect to one another. As used herein, the term "selective" in reference to a material removal process indicates that the rate of material removal for the first material is greater than the rate of removal for at least another material in the structure to which the material removal process is being applied. Alternating semiconductor materials 22 / 24 can be deposited by any suitable mechanism. In particular, it is contemplated that the first and second semiconductor materials 22 / 24 may be alternately grown epitaxially, although alternative deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition are also contemplated.

[0049] The inner spacer 26 may include any one or more of the following films: SiN, SiBN, SiCN, and / or SiBCN.

[0050] ILD regions 20 can be any suitable material, such as, for example, porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric material. Any known method for forming ILD regions 20 can be utilized. ILD regions 20 can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD.

[0051] BDI layer 30 may include, for example, SiC, SiOC, etc. BDI layer 30 may be deposited, for example, by ALD with anisotropic etchback.

[0052] The bottom S / D epi regions 18 can be formed of the same or different materials for pFET and nFET devices and can be doped in-situ or by ion implantation with the appropriate polarity dopant (B for pFET devices and P for nFET devices).

[0053] The terms "epitaxial growth" and "epitaxial deposition" refer to the growth of a semiconductor material on a semiconductor material deposition surface, where the growing semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the deposited atoms have enough energy to move around the surface and orient themselves to the crystalline arrangement of the atoms on the deposition surface. Thus, in some instances, an epitaxial film deposited on a {100} crystalline surface will have a {100} orientation.

[0054] With respect to the various dielectrics or dielectric layers discussed herein (such as bottom sacrificial placeholder 16), the dielectric may include, but is not limited to, SiN, SiOCN, SiOC, SiBCN, SO2, or Ultra Low-k (ULK) materials such as, for example, porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous variants, silsesquioxanes, siloxanes, or other dielectric materials having a dielectric constant, for example, in the range of about 2 to about 10.

[0055] In some embodiments, the dielectric may be conformally deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Variations of CVD processes suitable for forming the dielectric include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), metal-organic CVD (MOCVD), and combinations thereof.

[0056] FIG. 2 is a cross-sectional view of the semiconductor structure of FIG. 1 after a mask layer (such as an organic planarization layer (OPL)) has been deposited and patterned to perform a p-type field effect transistor (pFET) cut, according to one embodiment of the present invention.

[0057] In various exemplary embodiments, a mask layer 40 is deposited and patterned to make a p-type field effect transistor (pFET) cut 42. The pFET cut 42 extends well into the fin formed by the Si layer 14. A BDI section 30' of the BDI layer 30 remains, along with the interior spacer 26 and spacer 32 adjacent to the dummy gate 34.

[0058] Mask layer 40 can be an OPL that includes an organic material, such as a polymer. The thickness of OPL 40 can range from about 10 nm to about 300 nm. In one example, the thickness of OPL 40 is about 100 nm to 150 nm.

[0059] Etching may include, for example, dry etching processes such as wet etching, reactive ion etching, plasma etching, ion etching, or laser ablation. Etching may also include wet chemical etching processes in which one or more chemical etchants are used to remove portions of the blanket layer not protected by the patterned photoresist.

[0060] Dry and wet etching processes may have adjustable etching parameters, such as the etchant used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes may include biased plasma etching processes using chlorine-based chemicals. Other dry etchant gases may include tetrafluoromethane (CF), nitrogen trifluoride (NF), sulfur hexafluoride (SF), and helium (He), and chlorine trifluoride (ClF). Dry etching may also be performed anisotropically using mechanisms such as deep reactive ion etching (DRIE). Chemical vapor etching may be used as a selective etching method, and the etching gas may include a gas mixture of hydrogen chloride (HCl), tetrafluoromethane (CF), and hydrogen (H). Chemical vapor etching may be performed by CVD with suitable pressure and temperature.

[0061] FIG. 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a lateral etch is performed, according to one embodiment of the present invention.

[0062] In various exemplary embodiments, a lateral etch 44 is performed to selectively remove the Si portions between the inner spacers 26 and the Si portions under the BDI sections 30′ of the BDI layer 30. The sidewalls 17 of the bottom sacrificial placeholder 16 are also exposed. The regions between the inner spacers 26 are shown as 46 in the X-cut direction. In the Y-cut direction, there is an additional recess 48 in the Si layer 14.

[0063] FIG. 4 is a cross-sectional view of the semiconductor structure of FIG. 3 after the OPL has been selectively removed and a sacrificial material has been deposited, according to one embodiment of the present invention.

[0064] In various exemplary embodiments, mask layer 40 is selectively removed and sacrificial material 50 is deposited. Sacrificial material 50 is recessed to form openings 52 above sacrificial material 50 in both the X-cut and Y-cut directions. Removal of mask layer 40 exposes top surfaces 35 of dummy gates 34, as well as top surfaces of spacers 32 and ILD regions 20.

[0065] The sacrificial material 50 may be composed of the same materials as the bottom sacrificial placeholder 16, and may include various dielectrics or dielectric layers, as discussed above.

[0066] FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 with a dielectric capping layer formed and a nanosheet layer for a top device bonded to a bottom device by a dielectric-dielectric bonding process, according to one embodiment of the present invention.

[0067] In various exemplary embodiments, a dielectric cap 54 is formed on the recessed sacrificial material 50, and then a nanosheet layer 60 is bonded to the bottom device layer using a dielectric-dielectric bonding process. Layer 56 represents a bonding oxide. The dielectric cap 54 is planarized (e.g., by CMP) so that it is flush with the top surface 35 of the dummy gate 34 and the top surface of the spacer 32. The bottom stacked FET can be a pFET. The bonding dielectric layer 56 separates the bottom stacked FET from a subsequently constructed top stacked FET. The top stacked FET starts with a top nanosheet stack 60 including alternating layers of a first semiconductor material 62 and a second semiconductor material 64. The top stacked FET can be an nFET.

[0068] Figure 6 is a cross-sectional view of the semiconductor structure of Figure 5 in which a top nanosheet stack has been formed, and internal spacers, source / drain (S / D) epi regions, and an interlayer dielectric (ILD) have also been formed adjacent to the top nanosheet stack, according to one embodiment of the present invention.

[0069] In various exemplary embodiments, a top nanosheet stack 60' is formed on the bonding dielectric layer 56 in an X-cut structure. The top nanosheet stack 60' includes alternating layers of a first semiconductor material (or layers) 62' and a second semiconductor material (or layers) 64'. The first semiconductor material 62' can be, for example, silicon (Si), and the second semiconductor material 64' can be, for example, silicon germanium (SiGe).

[0070] In the X-cut direction, dummy gates 78 are formed between spacers 76. Top source / drain (S / D) epi regions 70 are formed on the junction dielectric layer 56. ILD is deposited and planarized (e.g., by chemical mechanical polishing (CMP)) such that ILD regions 72 are formed on the top S / D epi regions 70. For the top nanosheet stack 60′, inner spacers 74 are formed between the first semiconductor material (or layers) 62′.

[0071] In the Y-cut direction, a dummy gate 78 is also formed on the nanosheet stack 60'.

[0072] FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 with a replacement metal gate (RMG) opening formed therein, according to one embodiment of the present invention.

[0073] In various exemplary embodiments, a replacement metal gate (RMG) opening 79 is shown formed in the Y-cut orientation, extending through the bonding dielectric layer 56 and down to the top surface of the dummy gate 34 of the bottom stacked FET.

[0074] FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 with the dummy gate and alternating sacrificial layers of the top and bottom nanosheet stacks selectively removed, according to one embodiment of the present invention.

[0075] In various exemplary embodiments, the dummy gates 78, 34 and alternating sacrificial layers 64′, 24 of the top nanosheet stack 60′ and bottom nanosheet stack 25 are selectively removed to create openings 80. The openings 80 are formed at opposing ends of the Si layers 62′, 22 of the top and bottom stacked FETs.

[0076] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 with a high-k metal gate (HKMG) deposited and a gate cut made, according to one embodiment of the present invention.

[0077] In various exemplary embodiments, a high-k metal gate (HKMG) 82 is deposited and a gate cut 84 is made. The gate cut 84 is shown in a Y-cut orientation. The gate cut 84 extends into the junction dielectric layer 56. The gate cut 84 is made through the HKMG 82. The gate cut 84 is vertically offset from the top nanosheet stack 60′ and the bottom nanosheet stack 25.

[0078] The HKMG material of HKMG82 can be deposited by any suitable technique, such as ALD, CVD, metal organic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or other suitable technique. The gate dielectric material of HKMG82 can include, for example, HfO2, LaO, AlO, ZrO, TiO, Ta2O5, YO3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), or other suitable materials. HKMG82 further includes a work function metal such as TiN, TiAl, TiC, TiAlC, etc., and a conductive metal filler such as W, Al, Ru, etc.

[0079] 10 is a cross-sectional view of the semiconductor structure of FIG. 9 in which middle-of-line (MOL) contacts have been formed, back-end-of-line (BEOL) components have been formed, and a carrier wafer has been bonded to the BEOL, in accordance with one embodiment of the present invention.

[0080] In various exemplary embodiments, an ILD 86 is deposited and MOL contacts are formed. The MOL contacts may include, for example, a node contact 90, a VSS pin 92, and a bit line (BL) 94 in an X-cut orientation. The MOL contacts may include, for example, a word line (WL) 96 in a Y-cut orientation.

[0081] The node contact 90 advantageously extends through the bonding dielectric layer 56 and into the bottom S / D epi region 18. The VSS pin 92 extends to the top S / D epi region 70, and the BL extends to the top S / D epi region 70. The WL 96 is shown extending in the Y-cut direction to the top surface of the HKMG 82.

[0082] After the formation of the MOL contacts, back end of line (BEOL) components are formed and a carrier wafer 102 is bonded to the BEOL 100 .

[0083] Non-limiting examples of suitable conductive materials for the node contact 90, VSS pin 92, BL 94, and WL 96 include silicide liners such as Ti, Ni, NiPt, etc., adhesion metal liners such as TiN, TaN, etc., and conductive metal fillers such as Al, W, Co, Ru, etc. The conductive material may further include dopants incorporated during or after deposition. The conductive metal may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, coating, thermal or electron beam evaporation, and sputtering.

[0084] FIG. 11 is a cross-sectional view of the semiconductor structure of FIG. 10 with the wafer flipped and the substrate removed (the view is not flipped), according to one embodiment of the present invention.

[0085] In various exemplary embodiments, the wafer is flipped over and the substrate 10 is removed to expose the etch stop layer 12 .

[0086] FIG. 12 is a cross-sectional view of the semiconductor structure of FIG. 11 after the etch stop layer and remaining silicon (Si) layer have been removed and a backside ILD has been deposited, according to one embodiment of the present invention.

[0087] In various exemplary embodiments, the etch stop layer 12 and remaining silicon (Si) layer 14 are removed, and a backside ILD 110 is deposited. The backside ILD 110 directly contacts the BDI layer 30. The backside ILD 110 can be planarized, for example, by CMP.

[0088] The backside ILD 110 can be any suitable material, such as, for example, porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric material. Any known method for forming the backside ILD 110 can be utilized. The backside ILD 110 can be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD.

[0089] FIG. 13 is a cross-sectional view of the semiconductor structure of FIG. 12 with the sacrificial placeholder selectively removed and back contact metallization applied, according to one embodiment of the present invention.

[0090] In various exemplary embodiments, the bottom sacrificial placeholder 16 and sacrificial material 50 are selectively removed and backside contact metallization is applied. In other words, the pFET channel under the pass gate is selectively removed. The removed pFET channel region and the bottom of the pFET are replaced with a conductor or inverter gate 114. Specifically, the metallization includes a VDD pin 112 and an inverter gate 114. The VDD pin 112 and the inverter gate 114 directly contact the bottom S / D epi region 18 and the gate cap 54 in the X-cut direction. In the Y-cut direction, the inverter gate 114 directly contacts the gate cap 54. The inverter gate 114 may also be referred to as a cross-couple. The inverter gate 114 is a conductor.

[0091] FIG. 14 is a cross-sectional view of the semiconductor structure of FIG. 13 with a backside power distribution network (BSPDN) connected to a metal contact, according to one embodiment of the present invention.

[0092] In various exemplary embodiments, a backside power distribution network (BSPDN) 124 is connected to the metal contacts. First, the ILD 120 is deposited, then vias 122 are formed through the ILD 120 to the top surface of the VDD pin 112, and then the BSPDN 124 is formed.

[0093] Structure 125A illustrates a stacked FET SRAM cell in an X-cut orientation, and structure 125B illustrates a stacked FET SRAM cell in a Y-cut orientation. The stacked FET cell advantageously includes a top FET portion 130A and a bottom FET portion 130B, which advantageously includes a node contact 90 and an inverter gate 114. Thus, the exemplary embodiment presents a stacked FET SRAM with a bottom pFET by electrically connecting the node contact 90 and the inverter gate 114 (cross-coupled) by replacing the pFET under the pass gate with a conductor.

[0094] 14, structures 125A, 125B show bottom FET 130B including a plurality of bottom source / drain (S / D) epi regions 18, top FET 130A including a plurality of top S / D epi regions 70, junction dielectric layer 56 disposed directly between bottom FET 130B and top FET 130A, and node contact 90 advantageously extending from the bottom S / D epi regions 18 of the plurality of bottom S / D epi regions of bottom FET 130B through junction dielectric layer 56 and into top FET 130A. In other words, junction dielectric layer 56 is disposed directly between bottom FET 130B and top FET 130A, and node contact 90 advantageously extending from bottom FET 130B through junction dielectric layer 56 and into top FET 130A, where it is advantageously electrically connected to inverter gate 114.

[0095] The bottom FET 130B includes an inverter gate 114. The inverter gate 114 directly contacts the gate cap 54 of the bottom FET 130B. The inverter gate 114 directly contacts some of the bottom S / D epi regions 18. A node contact 90 is advantageously vertically aligned with a portion of the inverter gate 114. The top FET 130A is electrically connected to the BEOL components, and the bottom FET 130B is electrically connected to the backside power distribution network (BSPDN) 124. A bit line (BL) 94 advantageously directly contacts one of the top S / D epi regions 70, and a word line (WL) 96 advantageously directly contacts a high-k metal gate (HKMG) 82 disposed within the top FET 130A. Furthermore, the node contact 90 is vertically offset from the BL 94 and the WL 96.

[0096] Consequently, exemplary embodiments of the present invention present a stacked FET architecture including a top FET bonded to a bottom FET by a bonding dielectric layer. The bottom FET advantageously includes a node contact and inverter gate, allowing all transistor physical parameters, such as gate length, spacer thickness, and contact size, to be advantageously optimized for better transistor speed and / or lower power. Beneficially, unlike lateral transistors, much of this structural tuning does not affect the transistor pitch (the distance between transistors). In exemplary stacked FETs with nanosheets according to Figures 1-14, integrated circuit (IC) vendors advantageously have the ability to vary the width of the nanosheets within a transistor. For example, nanosheets with wider sheets provide more drive current and performance. Narrower nanosheets provide less drive current but occupy less area.

[0097] 1-14, deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. As used herein, "depositing" may include any technique now known or later developed that is appropriate for the material to be deposited, including, but not limited to, for example, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), and ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), coating, evaporation.

[0098] As used herein, the term "processing" includes depositing, patterning, exposing, developing, etching, cleaning, stripping, implanting, doping, stressing, laminating, and / or removing material or photoresist as needed to form the described structures.

[0099] Removal is any process that removes material from the wafer, examples of which include etching processes (either wet or dry), chemical-mechanical planarization (CMP), and the like.

[0100] Patterning, the shaping or modification of deposited material, is commonly referred to as lithography. For example, in traditional lithography, a wafer is first coated with a chemical called photoresist; then a machine called a stepper focuses, aligns, and moves a mask to expose selected portions of the wafer underneath to short-wavelength light; the exposed areas are washed away with a developer solution. After etching or other processing, the remaining photoresist is removed. Patterning also includes electron-beam lithography.

[0101] The present invention is described in terms of given example architectures; however, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention.

[0102] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0103] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical mechanism (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., over the Internet). The stored design is then converted into a format (e.g., GDSII) suitable for the manufacture of photolithography masks, which typically contain multiple copies of the chip design in question, to be formed on a wafer. The photolithography masks are utilized to define the areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0104] Methods such as those described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0105] It should also be understood that material compounds are described in terms of the elements listed, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe may contain Si x Ge 1-x where x is less than or equal to 1, etc. Additionally, other elements may be included within the compound and still function in accordance with the present embodiments. Compounds with additional elements are referred to herein as alloys.

[0106] References herein to "one embodiment" or "an embodiment" of the present invention, and other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," and any other variations, in various places throughout this specification are not necessarily all referring to the same embodiment.

[0107] It should be understood that the use of any of the following terms " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of both options (A and B), for example, "A / B," "A and / or B," and "at least one of A and B." As a further example, "A, B, and / or C" and "at least one of A, B, and C" are intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of only the third listed option (C), or the selection of only the first and second listed options (A and B), or the selection of only the first and third listed options (A and C), or the selection of only the second and third listed options (B and C), or the selection of all three options (A, B, and C). This can be extended to many of the items listed, as would be readily apparent to one skilled in this and related arts.

[0108] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0109] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like are used herein for ease of description and may describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" such other elements or features. Thus, the term "below" can encompass both an orientation of above and below. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, when a layer is referred to as being "between" two layers, it will also be understood that it may be the only layer between the two layers, or that one or more intervening layers may also be present.

[0110] Terms such as "first," "second," and the like may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0111] While preferred embodiments of methods and structures providing for the construction of stacked field effect transistor (FET) static random access memory (SRAM) cells with a bottom pFET have been described (for purposes of illustration and not limitation), it is noted that modifications and variations may occur to those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described and are within the scope of the invention as outlined by the appended claims. Thus, having described aspects of the invention with the detail and specificity required by the Patent Laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. a bottom field effect transistor (FET) including a plurality of bottom source / drain (S / D) epi regions; a top FET including multiple top S / D epi regions; a junction dielectric layer disposed directly between the bottom FET and the top FET; and a node contact extending from one of the bottom S / D epi regions of the bottom FET through the junction dielectric layer into the top FET; 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1 wherein said bottom FET comprises an inverter gate.

3. 3. The semiconductor structure of claim 2 wherein a gate cap is disposed on top of the bottom pFET gate metal.

4. 3. The semiconductor structure of claim 2 wherein said inverter gate directly contacts some of said plurality of bottom S / D epi regions.

5. 3. The semiconductor structure of claim 2 wherein said node contact is vertically aligned with a portion of said inverter gate.

6. 10. The semiconductor structure of claim 1, wherein said top FET is electrically connected to a back end of line (BEOL) component and said bottom FET is electrically connected to a backside power delivery network (BSPDN).

7. 2. The semiconductor structure of claim 1, wherein a bit line (BL) directly contacts one of said top S / D epi regions.

8. 8. The semiconductor structure of claim 7, wherein a word line (WL) directly contacts a metal gate disposed in said top FET.

9. 9. The semiconductor structure of claim 8 wherein a gate cap directly contacts a cross couple in said bottom FET.

10. a junction dielectric layer disposed directly between the bottom field effect transistor (FET) and the top FET; and a node contact extending from the bottom FET through the junction dielectric layer into the top FET and electrically connecting to an inverter gate; 1. A semiconductor structure comprising:

11. 11. The semiconductor structure of claim 10 wherein a gate cap is disposed on top of the bottom pFET gate metal.

12. 11. The semiconductor structure of claim 10 wherein said inverter gate directly contacts some of said bottom S / D epi regions of said bottom FET.

13. 11. The semiconductor structure of claim 10 wherein a gate cap directly contacts a cross couple in said bottom FET.

14. 11. The semiconductor structure of claim 10, wherein said top FET is electrically connected to a back end of line (BEOL) component and said bottom FET is electrically connected to a backside power delivery network (BSPDN).

15. 11. The semiconductor structure of claim 10 wherein a bit line (BL) directly contacts the top S / D epi region of said top FET.

16. 11. The semiconductor structure of claim 10, wherein a word line (WL) directly contacts a metal gate disposed in said top FET.

17. forming a bottom nanosheet stack between a plurality of bottom source / drain (S / D) epi regions disposed on a sacrificial placeholder; performing a p-type field effect transistor (pFET) cut; depositing a sacrificial material within the pFET cut; forming a gate cap on the sacrificial material to form a bottom FET; forming a junction dielectric layer on the bottom FET; forming a top nanosheet stack on the bonding dielectric layer and between the plurality of top S / D epi regions; removing a sacrificial layer from the top and bottom nanosheet stacks to define a first opening; depositing a replacement metal gate in the first opening; forming a gate cut and a node contact, the node contact extending from the bottom FET through the junction dielectric layer and into the top FET; Selectively removing the sacrificial placeholder and the sacrificial material to define a second opening; and filling the second opening with a cross couple. A method comprising:

18. 20. The method of claim 17, wherein a bit line (BL) directly contacts one of the top S / D epi regions.

19. 20. The method of claim 18, wherein a word line (WL) directly contacts the replacement metal gate disposed in the top FET.

20. 20. The method of claim 17, wherein the top FET is electrically connected to a back end of line (BEOL) component and the bottom FET is electrically connected to a backside power delivery network (BSPDN).

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