Substrate containing nanowires

Abstract

A microstructure substrate comprising a main body and a plurality of elongated basic microstructures extending from the main body, the microstructure substrate including a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the basic microstructures extending from the main body over the area.

Description

[Technical Field]

[0001] The present invention relates to the field of micro-energy storage devices, and more particularly, but not exclusively, to planar and / or microstructured substrates integrating onto their surface substructures with dimensions measurable on the nanometer scale. The present invention also relates to methods for manufacturing such substructures.

[0002] The following in-text bibliographic references are written in the text of the specification in this way: [ ] and are listed in the table of references. [Background technology]

[0003] For example, substrates used in the manufacture of energy storage devices may be made from a base made of semiconductor or dielectric material and may be in the form of a thin disk, also referred to as a "wafer." By nature, such a base has a planar surface corresponding to a two-dimensional (2D) topology. However, depending on the intended use of the substrate, it may be advantageous to hollow out the surface of the substrate on the micro- or nano-scale so that it has a three-dimensional (3D) topology, thus defining a microstructured or nanostructured substrate.

[0004] Such microstructured substrates have a larger usable or developed surface area than planar (or smooth) substrates; for example, the microstructured substrates allow for the deposition of a larger amount of material on their surfaces, and more particularly on the outer surfaces of the microstructures, which can, for example, improve the performance of electrical energy storage devices, increase the number of components that can be integrated onto the substrate, etc.

[0005] Microstructured silicon substrates with increased surface area associated with their roughened structure have been described, for example, in patent application [1]. Generally, the construction of such microstructures is achieved using surface treatments such as chemical or physical etching, microstructure growth, or electrochemical deposition of microscale or even nanoscale material inside a mold followed by dissolution of the mold.

[0006] In particular, as it becomes established that increasing the usable surface area improves the performance of solid-state microbatteries, microcapacitors, or microsupercapacitors, there is an ongoing need to develop solutions that allow energy storage devices to increase the usable surface area outside the visible substrate while preserving the dimensions of the original base from which the substrate is made, without deviating from the continuing need to miniaturize electrical components. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] WO 15 / 052412 [Patent Document 2] WO 22 / 069842 [Patent Document 3] WO 20 / 114379 Summary of the Invention [Problem to be solved by the invention]

[0008] To meet this need, a first object of the present invention consists in modifying the surface of a microstructured or nanostructured substrate in order to increase its usable surface area.

[0009] Furthermore, it is known to use methods for forming thin layers of materials on substrates, for example, for producing layers of lithium-containing materials. In particular, these laminated substrates are used in batteries, for example, for forming electrodes or field barriers, or in any other electrical storage device. These layers can be deposited using precursor-based atomic layer deposition (commonly known by the acronym ALD), chemical vapor layer deposition (commonly known by the acronym ALCVD), or atomic layer epitaxy (commonly known by the acronym ALE). In particular, the ALD technique is a thin film deposition technique based on gas-surface reactions to expose the desired surface on which to deposit a layer of material using different successive chemical precursors.

[0010] Patent application [2] describes a method for carrying out atomic layer deposition of a precursor of a first metal, which may be, for example, an organometallic complex containing a transition metal (such as nickel) or another type of metal, such as aluminum, and which allows the preparation of a compound containing a thin layer of a lithium-containing material. Such a layer, consisting of a complex, an electrochemically active material, and which is particularly homogeneous and adapted to follow the more or less complex surface relief of a microstructured substrate, has a thickness of 1 nm to 1 μm.

[0011] A second object of the present invention consists in modifying the surface of a substrate in order to increase its usable surface area by implementing such a layer deposition method compatible with microstructured substrates, whose surfaces are complex and difficult to apply any of the surface treatment methods according to the prior art.

[0012] Patent application [3] describes a hybrid substrate consisting of a glass layer coated with a metal layer, typically molybdenum (Mo), indium (In) micropillars perpendicular to the surface of the substrate and having convex apexes, a copper (Cu) layer covering the convex apexes of these In-containing micropillars, and copper (I) sulfide (CuS) nanowires starting only from the apexes of the micropillars. [Means for solving the problem]

[0013] The present invention relates to a microstructural substrate comprising a body and a plurality of elongated elementary microstructures extending from the body, characterized in that the microstructural substrate comprises a plurality of nanowires located on at least one area of ​​the surface of the body and on the surfaces of the elementary microstructures extending from the body in said area. Such a geometry of the substrate integrating the nanowires allows a further increase in the exploitable surface area by at least a factor of 10, thus improving the storage capacity of a storage device integrating said substrate.

[0014] Within the scope of the present invention, the terms "microstructured" or "microstructure" are applied independently to surfaces having relief, the shapes of which have dimensions that are measurable on both the microscale and the nanoscale.

[0015] Preferably, the elementary microstructures of elongated shape are micropillars or microtubes (which are micropillars hollowed out at their centres).

[0016] Advantageously, the main body and the basic microstructure extending along said main body of the substrate of the microstructure according to the invention are made from the same material, preferably chosen from materials comprising or consisting only of silicon Si, silicon dioxide SiO2, gallium arsenide GaAs, silicon nitride Si3N4 and indium phosphide InP.

[0017] Preferably, the basic microstructure comprises a cross section selected from circular, oval, rectangular, square and triangular cross sections.

[0018] Preferably, the nanowires comprise an oxide, preferably a material selected from SiO2, ZnO, and TiO2, and preferably the nanowires consist solely of SiO2.

[0019] Preferably, the nanowires have a cross-section with a diameter of 20 nm to 250 nm and a length of 100 nm to 10 μm. Advantageously, the nanowires have a cross-section with a diameter of 50 nm to 250 nm and a length of 0.5 μm to 2 μm. The structure of these nanowires is characterized by electron microscopy techniques, and more particularly by scanning electron microscopy (SEM), and evaluation of the dimensions and structure of the nanowires is carried out using images collected by this technique.

[0020] Preferably, the nanowire-containing area has a developed surface area that is 2 to 50 times, and advantageously 10 to 40 times, or even 15 to 35 times, the developed surface area of ​​said area without nanowires. The increase in surface area associated with the presence of nanowires is measured indirectly using electrochemical methods via the use of capacitive, inductive, or pseudocapacitive materials, whose electrochemical properties are specific to the developed surface area. The developed surface area is representative of the total surface area introduced via the creation of porosity and by inversion through the addition of micro- and nano-objects relative to the initial object, and is generally represented by an increase in surface area greater than 1 (1 being representative of the increase in surface area of ​​the initial object).

[0021] The present invention provides a method for producing a method for manufacturing a semiconductor device, comprising the steps of: a- covering a planar or microstructured substrate with a thin layer of SiO2; b- depositing a layer of non-oxidizing metal using atomic layer deposition techniques; c- carrying out a photolithography process on at least one area of ​​the surface of the planar or microstructured base that has undergone steps a- and b-; d- performing an etching treatment; e- carrying out thermal annealing, preferably by carrying out at least one temperature step; The present invention also relates to a method for manufacturing a planar substrate or a microstructured substrate as described herein above, within the scope of the present invention, comprising:

[0022] Advantageously, step a- comprises the deposition of a nanometric thin film of SiO2 by low pressure chemical vapor deposition, also known by the acronym "LP CVD".

[0023] Step b- involves atomic layer deposition, also known by the acronym "ALD". Layers deposited by such atomic layer deposition techniques are deposited using precursors by atomic layer chemical vapor deposition techniques (commonly known by the acronym "ALCVD") or atomic layer epitaxy deposition techniques (commonly known by the acronym "ALE"), as described in reference [2]. In particular, the ALD technique is a thin film deposition technique based on gas-surface reactions to expose the desired surface on which to deposit a layer of material using different successive chemical precursors.

[0024] Step c- is photolithography to restrict the growth of SiO2 nanowires only on the areas of the substrate where the presence of nanowires is desired. Such a step protects these areas of interest of the substrate where the presence of nanowires is desired, and allows the growth of nanowires over a range of several mm 2 This allows for the formation of a resin mask in the area of ​​interest, and leaves the material from the precursor (catalyst) "bare" on the rest of the surface of the substrate.

[0025] Advantageously, step d-, dry etching of the catalyst to keep it only on the areas of interest, is carried out using reactive thermal etching, also known by the acronym "RIE", preferably RIE etching carried out in an RIE-ICP device sold as a reactor by Sentech®, such as the device known under the reference Sentech Si500 (ICP-RIE). Such dry etching is based on the generation of a reactive plasma based on a gaseous mixture of Cl2 / Ar (10 sccm, 30 sccm) in a reactor at a pressure of 5 mTorr and preferably at 10°C.

[0026] Advantageously, step e- is an annealing that implements a vapor-liquid-solid synthesis technique, also known by the acronym "VLS", which has the advantage that it does not require the use of gas-phase silane precursors as previously known in the literature. The growth is directly correlated, on the one hand, with the transformation into gas phase of the thin layer of SiO2 generated in step a-, and, on the other hand, with the presence of a catalyst generated in step b-. Advantageously, step e- comprises at least two stages: a first stage that allows the formation of metal clusters to control the diameter of the future nanowires, and a second stage that allows the nanowire growth phenomenon to occur.

[0027] Preferably, the non-oxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh, and Pd, and preferably it consists of Pt. It should be noted that the precursor of the first metal can be in liquid or powder form. For example, the precursor of the first metal can be selected from the following precursors: MeCpPtMe3, FeCl2, FeCp2, Fe(thd)3, La(thd)3, CoCp2, MnCp2, Mn(thd)3, NiCp2, TiCl4, NbOEt5, Cr(OCl)2, and preferably it consists of MeCpPtMe3.

[0028] Preferably, step e- comprises two temperature stages: a first stage of 200°C to 1200°C applied for less than 5 minutes and a second stage of 300°C to 1400°C applied for less than 15 minutes.

[0029] The present invention also relates to the use of a microstructured substrate as described above within the scope of the present invention for the manufacture of micro energy storage devices, preferably selected from batteries, supercapacitors, and dielectric and electrolytic capacitors of micrometric or nanometric size, energy regenerating components or sensor-type devices where the use of a large specific surface area is required.

[0030] The present invention is also described in the following detailed description of the invention using an experimental section, which details some embodiments using examples given for illustrative purposes only and should not be considered as limiting, and the drawings are briefly described in the following section. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 shows XRR (X-ray reflectometry) measurements on a thin layer of NiO deposited on a silicon substrate using ALD. [Figure 2] FIG. 2 shows SEM (scanning electron microscope) images following nanowire synthesis using the VLS (vapor-liquid-solid) technique. [Figure 3] Figure 3 shows the rapid thermal annealing (RTA) profile used for growing SiO2 nanowires. [Figure 4] Figure 4 shows XRR measurements of thin layers of Pt with thicknesses of 5, 10, 15 and 20 nm. [Figure 5A] FIG. 5A shows an image obtained using SEM for a layer thickness of 15 nm SiO 2 and 10 nm Pt. [Figure 5B] FIG. 5B shows an image obtained using SEM for a layer thickness of 15 nm SiO 2 and 10 nm Pt. [Figure 5C] FIG. 5C shows an image obtained using SEM for a layer thickness of 15 nm SiO 2 and 10 nm Pt. [Figure 5D] FIG. 5D shows an image obtained using SEM for a layer thickness of 15 nm SiO 2 and 10 nm Pt. [Figure 6] FIG. 6 shows a magnified SEM image on the surface of the substrate after annealing at 900° C. for 1 minute. [Figure 7] FIG. 7 shows a magnified SEM image on the surface of the substrate after annealing at 950° C. for 1 minute. [Figure 8] FIG. 8 shows a magnified SEM image on the surface of a substrate that has undergone annealing at 900° C. for 1 minute followed by annealing at 1050° C. for 3 minutes. [Figure 9]FIG. 9 shows a magnified SEM image on the surface of a substrate that has undergone annealing at 950° C. for 1 minute followed by annealing at 1100° C. for 3 minutes. [Figure 10] FIG. 10 shows the normalized surface area capacitance as a function of scan rate for thin films of RuO 2 deposited on different types of substrates, allowing one to estimate the effective electrochemical enhancement. DETAILED DESCRIPTION OF THE INVENTION

[0032] [Experimental Department] Materials and Methods The reagents used were sold by STREM® Chemistry and were used without further purification.

[0033] [Surface area measurement] The surface area enhancement (area expansion factor, AEF) is measured indirectly using three-electrode cell cyclic voltammetry. The electrolyte used is sulfuric acid (H2SO4) diluted to 0.5 M, the reference electrode is an Ag / AgCl electrode, the counter electrode is made of platinum, and the working electrode corresponds to the fabricated sample covered with a thin layer (30 nm) of platinum deposited using ALD (microstructured substrate, hierarchical backbone). The scan rate is 50 mV / s.

[0034] [Measurement of the thickness of deposited thin films] The layer thickness is measured by X-ray reflectometry (XRR), an interferometric technique that allows obtaining quantitative information on the interface roughness, density, and thickness of amorphous or non-amorphous thin layers. After a process of sample height and surface alignment, the measurement is performed. Such a measurement consists of irradiating an X-ray beam onto the sample surface at a low angle of incidence theta and collecting the reflected intensity. Measurements are obtained that allow studying the reflected intensity as a function of the angle of incidence (2θ), as shown in Figure 1. The curve generally follows the range 2θ<θ c For θ, we draw a plateau followed by a decay containing one or more oscillations, where θ c corresponds to the critical angle, the period of which is given by the following relation:

number

[0035] The gradient of the vibration makes it possible to study the surface roughness, and the change in gradient after the vibration makes it possible to study the layer density. X-ray reflectivity is a technique that makes it possible to accurately measure the thickness of thin layers (approximately 5 nm to 100 nm) using Equation 1 provided that the layer has low roughness, making it the technique of choice for the ALD depositions performed within this work. X-ray reflectivity measurements were made on a SMARTLAB® rotating copper anode system from Rigaku®.

[0036] Observation of the surface topography of the samples was performed using top view, cross section, and grazing incidence scanning electron microscopy (SEM) using an FEI Magellan 400™.

[0037] Nanowire size distribution was performed using SEM and nanowire size measurements were made using ImageJ™ software.

[0038] Within the scope of the present invention, percentages by weight expressed in % w / w define the percentage by weight of the component considered with respect to the total weight of the object considered: mixture, material (composite, etc.), membrane, etc., used in the preparation. [Example]

[0039] [Part 1: Synthesis of silicon oxide SiO2 by dry oxidation (LP CVD, low-pressure chemical vapor deposition)] - Wafer cleaning: Piranha solution (mixture of sulfuric acid H2SO4 and hydrogen peroxide H2O2) 1:1 (20 min), deionized water rinse, N2 dry, HF 1% (2 min), EDI rinse, N2 dry, - introduction of silicon wafers into a furnace at 500 ° C, 2 slm (standard liters per minute, T = 0 ° C and P = 1 bar) of N2, - Heating to 675°C for 30 minutes (10°C / min), - 1 hour temperature increase to 900°C (10°C / min), - Pre-oxidation at 900°C for 30 minutes with 2 slm N2 and 0.2 slm O2, - oxidation at 900 °C with 2 slm O2 for 42 min (15 nm SiO2 - deposition rate 0.357 nm / min), - Ramping down to 500°C with 2 slm N2 for 1 hour.

[0040] [Part 2: Atomic Layer Deposition (ALD) of Pt Catalysts]

[0041] The platinum layer is deposited using ALD, where the reagents are "Pt" and molecular oxygen.

[0042] The sample obtained in part 1 was placed in an ALD chamber (Beneq model TFS200), the pressure was reduced to 2 mbar, and the temperature was adjusted to 300 °C.

[0043] To form an atomic monolayer, several distinct steps (corresponding to cycles) are required: Nitrogen is injected for 500 ms into a source containing the first reagent (1), MeCpPtMe3, or (trimethyl)methylcyclopentadienylplatinum(IV), declared 99% pure by STREM® chemistry; its temperature is maintained at 54°C; a 100 ms wait time is observed to increase the pressure in the precursor chamber; then the source is opened for a 500 ms (pulse time). A 2-second purge is then performed to expel excess species and products. The second reagent (2), in the form of gaseous O2, is then injected for a 500 ms interval, followed by a 1-second purge. The deposition rate is 0.83 Å / cy (angstroms per cycle), allowing precise control of deposition thickness from 5 nm to 60 nm.

[0044] [Part 3: Optical lithography to select areas of interest]

[0045] 1-Wafer cleaning and deoxidation:

[0046] The wafers from Part 2 are placed in a beaker of acetone for 5 minutes and then in isopropanol for 5 minutes to allow the wafers to be degreased. The wafers are then dried at 110°C for 10 minutes.

[0047] 2-Resin coating and exposure:

[0048] Coating with HMDS adhesion promoter (speed = 2000 revolutions per minute (rpm); acceleration = 1000 revolutions per minute per second (rpm / s); time = 20 s).

[0049] Coating with AZ1505 resin (speed = 3000 revolutions per minute; acceleration = 1000 revolutions per minute per second; time = 20 s).

[0050] Annealing at 110°C for 1 min, no relaxation time.

[0051] 3 seconds exposure in hard contact mode, no relaxation time.

[0052] Development in MIF726 for 50 seconds followed by 30 seconds of deionized water.

[0053] This optical lithography is performed on a scale of a few mm 2 This allows for the formation of a resin mask that protects the areas of interest and leaves the platinum "bare" over the entire substrate.

[0054] [Part 4: Dry etching of the catalyst to keep it only on the area of ​​interest]

[0055] Platinum etching is performed by RIE-ICP (Sentech®), a physical-chemical dry etching enabled by physical Cl / Ar plasma etching (10 sccm, 30 sccm) in a reactor at a pressure of 5 mTorr and a temperature of 10°C. The ICP source generates a high-density plasma by inductive coupling between an RF antenna and the plasma. The RF antenna generates an alternating RF magnetic field, which induces an RF electric field that accelerates electrons involved in the gas molecule ionization process. To perform the plasma etching, the source power is set to 600 W, and that of the RF generator is set to 200 W. The etching rate is 2.8 Å / s (Angstroms per second, i.e., 10 -10 Meters per second: this is the speed at which the platinum is etched to become structured).

[0056] [Part 5: Rapid Thermal Annealing (RTA)]

[0057] The annealing is carried out in a flash annealing furnace sold by Jipelec®, by observing two stages in a nitrogen atmosphere.

[0058] The synthesis technique employed is described as vapor-liquid-solid (VLS). Small clusters of Pt, droplets of a few tens of nanometers in diameter, are formed on the surface of SiO2. A first step at 1000 °C (10 °C / sec) to form SiO2 in the gas phase is maintained for 1 minute to dewet the Pt catalyst. SiO2 diffuses in the droplets and precipitates at the metal / substrate interface during a second supersaturation / precipitation step. This triggers the growth of SiO2 nanowires. Their growth is directly correlated with the transition of the SiO2 layer previously synthesized on the substrate in Part 1 to the gas phase and the presence of the catalyst (here, platinum).

[0059] The second stage at 1100 °C is maintained for 5 min to promote the growth of SiO2 nanowires. The diameter, length, and density (number of nanowires / mm) of the SiO2 nanowires are measured. 2The growth rate is controlled by the properties of the initial SiO2 and Pt films, and also by the annealing parameters (holding temperature and time of the high-temperature step, the first step allowing the formation of Pt clusters to control the diameter of the future nanowires, and the second step to induce the growth phenomenon by controlling the length of the nanowires). Images obtained by SEM magnification are shown in Figure 2 with a reduced scale to observe the dimensions of the nanowires. Figure 3 shows the temperature profile of the steps as a function of time.

[0060] [Analysis and Results] Different silicon samples were processed after thermal annealing by identifying different thickness parameters of the SiO2 thin layer and the Pt layer (5, 10, 15, 20 nm). The Pt thin layer was measured using XRR, the diagram of which is shown in Figure 4.

[0061] The samples were observed using SEM microscopy.

[0062] By varying the SiO2 thickness from 10 to 15 nm, the inventors observed the presence of very dense matchstick-shaped nanowires, strictly perpendicular to the surface, with an average length of more than 1 μm and a diameter that could be more than 80 nm.

[0063] Statistical study of SEM images makes it possible to determine the average nanowire diameter and length parameters. A common method consists of analyzing the image through a process that makes it possible to delineate the boundaries of the structures. Analysis of the image then makes it possible to count, pixel by pixel, the space occupied by each object (length, diameter, intersections with other objects, surface area, etc.).

[0064] For a 15 nm thick Pt layer, the results are shown in Table 2.

[0065] [Table 1]

[0066] Further results are shown in Table 3 and the resulting images are shown in Figures 5A-5D for layer thicknesses of 15 nm SiO2 and 10 nm Pt.

[0067] [Table 2]

[0068] [Study of phenomena related to temperature stages]

[0069] The role of the two annealing steps was determined by SEM imaging: the first allows platinum dewetting via the formation of Pt droplets on the surface, which condenses the evaporated SiO2 during the second temperature step; - Figure 6 corresponds to a substrate that has undergone annealing at 900°C for 1 minute, - Figure 7 corresponds to a substrate that has undergone annealing at 950°C for 1 minute, - Figure 8 corresponds to a substrate that has undergone annealing at 900°C for 1 minute and then at 1050°C for 3 minutes; - Figure 9 corresponds to a substrate that has undergone annealing at 950°C for 1 minute and then at 1100°C for 3 minutes.

[0070] Figures 6 to 8 show the importance of the first stage to promote catalyst (Pt) dewetting for nanowire growth. In particular, Figure 8 shows that a first stage at 900 °C is insufficient to promote growth during the second stage. Figure 9 shows that a first stage at 950 °C followed by a second step at 1100 °C makes it possible to obtain initial growth. This Figure 9 also shows the importance of the second stage interval on nanowire length, where a 3-minute interval is applied (while for other results described in the experimental section, the second stage is applied for 5 minutes).

[0071] [Measuring the increased surface area provided by nanowires]

[0072] The inventors have demonstrated that the high surface area capacity of the components integrating the substrate of the present invention is strictly linked to their structure, even when the aforementioned structures contain infinite composite structural elements in terms of material architecture, or are essentially intertwined with one another. The high surface area capacity is due to the large surface area, expressed in terms of projected surface area, provided by the presence of nanowire-covered micropillars (microstructured substrates). The methodology adopted to determine the surface area enhancement consists of using a parameter called "area enhancement factor," also known as "AEF," and comparing the AEF and contribution of various structures, measured independently first on a planar surface in 2D, then in 3D, and in 2D with nanowires and in 3D with nanowires.

[0073] To calculate the surface area enhancement (AEF) measured using three-electrode cell cyclic voltammetry, various measurements were performed under identical conditions. The electrolyte used was sulfuric acid (H2SO4) diluted to 0.5 M, the reference electrode was an Ag / AgCl electrode, the counter electrode was made of platinum, and the working electrode was platinum (30 nm) deposited by ALD on the sample to be measured (the "spine" of the microstructure). The scan rate was 50 mV / s. The estimated surface area observed during the measurement was 0.407 cm 2 The results are shown in Table 4 below.

[0074] [Table 3]

[0075] Table 4 then shows that the measurement method allows examining the calculated 3D enhancements (listed in columns 3 and 4) from microtube-type 3D structures. This method demonstrates that nanowires provide enhancements in surface area of ​​2 to 19 in the examples cited in the remainder of Table 2, listed in columns 5 to 8, respectively.

[0076] The same measurements were performed using a supercapacitor electrode material (RuO2) that exhibits an increase of 10 on a microstructure with an increase of 50 (i.e., a total surface area increase of 50 × 10 = 500). Thus, the increase in surface area of ​​the microstructure was demonstrated to be between 50 and 70, and that of the nanowire between 4 and 10. Figure 10 shows the capacitance as a function of scan speed for a thin layer of RuO2 on different types of substrates, allowing us to demonstrate, completely unexpectedly, that the cumulative increases are multiplicative rather than additive, achieving increases of between 200 and 700. In this Figure 10, we find the capacitance of a thin layer of RuO2 that allows us to investigate a surface area increase of 500 (circle) on a hierarchical substrate compared to 50 (square) and planar surfaces (triangle) for microtube-type structures.

[0077] [reference] The following table lists the references mentioned above in the text.

[0078] [Table 4]

Claims

1. a main body; a plurality of elongated basic microstructures extending from the main body; A microstructure substrate comprising: A microstructure substrate, characterized in that the microstructure substrate includes a plurality of nanowires positioned on at least one area of ​​the surface of the main body portion and on a surface of the basic microstructure extending from the main body portion over said area.

2. The body and the basic microstructure extending along the body are made of the same material, preferably silicon, silicon dioxide (SiO ２ , gallium arsenide GaAs, silicon nitride Si ３ N ４ 10. The microstructure substrate of claim 1, comprising a material selected from the group consisting of: and indium phosphide InP.

3. 3. The microstructure substrate of claim 1, wherein the basic microstructure comprises a cross section selected from a circular, oval, rectangular, square, and triangular cross section.

4. The nanowires are selected from oxides, preferably SiO ２ , ZnO, and TiO ２ Preferably, the nanowires comprise a material selected from SiO ２ The microstructure substrate according to any one of claims 1 to 3, which consists solely of

5. 5. The microstructure substrate according to claim 1, wherein the nanowires have a cross section with a diameter of 20 nm to 250 nm and a length of 100 nm to 10 μm.

6. 6. A microstructured substrate according to claim 1, wherein the area containing the nanowires has an developed surface area that is between 2 and 50 times the developed surface area of ​​the area without the nanowires.

7. The following steps: a-SiO ２ covering a planar or microstructured substrate with a thin layer of b- depositing a layer of non-oxidizing metal using atomic layer deposition techniques; c- carrying out optical lithography on at least one area of ​​the surface of said planar or microstructured base that has undergone steps a- and b-; d- performing an etching treatment; e- carrying out thermal annealing, preferably by carrying out at least one temperature step; A method for manufacturing a device according to any one of claims 1 to 6, comprising:

8. 8. The method for producing a microstructured substrate according to claim 7, wherein the non-oxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh and Pd, preferably it consists of Pt.

9. Step e- consists of two temperature stages: a first stage of 200°C to 1200°C applied for less than 5 minutes; a second stage of 300°C to 1400°C applied for less than 15 minutes; The method for manufacturing a microstructured substrate of claim 8, comprising:

10. Use of a microstructured substrate according to one of claims 1 to 6 for the manufacture of micro energy storage devices, preferably selected from batteries, supercapacitors, and dielectric and electrolytic capacitors of micrometer or even nanometer size, energy regenerating components or sensor type devices requiring the use of a large specific surface area.

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