Thin film transistor, transistor array substrate, and method for manufacturing the transistor array substrate

Abstract

A thin film transistor, a transistor array substrate including the same, and a method for manufacturing the transistor array substrate are provided. The thin film transistor includes a substrate, an active layer disposed on the substrate and including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region, a gate insulating layer disposed on a portion of the active layer, a gate electrode comprising an electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer, a source electrode comprising the electrode conductive layer, extending to the source region of the active layer and contacting a portion of the source region, and a drain electrode comprising the electrode conductive layer, extending to the drain region of the active layer and contacting a portion of the drain region. The active layer is made of an oxide semiconductor in a state including crystals due to heat treatment, and is arranged in a completely planar shape.

Description

[Technical Field]

[0001] The present invention relates to a thin film transistor, a transistor array substrate, and a method for manufacturing a transistor array substrate. [Background technology]

[0002] With the development of an information society, the demands on display devices for displaying images are becoming increasingly diverse. For example, display devices are being applied to a variety of electronic devices such as smartphones, digital cameras, notebook computers, navigation systems, and smart televisions.

[0003] The display device may include a display panel that emits light for displaying an image, and a driver that supplies a signal or power source for driving the display panel.

[0004] The display panel includes a display area from which light for displaying an image is emitted, and may include a polarizing member or a light-emitting member disposed in the display area.

[0005] The display area may be arranged with sub-pixels that emit light with different brightness and colors.

[0006] The display panel may also include a transistor array substrate having a substrate and a circuit layer disposed on the substrate and including pixel drivers corresponding to the sub-pixels, such that the sub-pixels in the display area can emit light with respective luminances and colors.

[0007] Each of the pixel driving units of the transistor array substrate may include at least one thin film transistor.

[0008] A thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer, and can function as a switching element in which current flows through a channel region of the active layer when a potential difference between the gate electrode and the source electrode exceeds a threshold value due to a driving signal transmitted to the gate electrode. Summary of the Invention [Problem to be solved by the invention]

[0009] When manufacturing a transistor array substrate including thin film transistors, an increase in the number of mask processes may increase manufacturing costs and reduce yields.

[0010] However, when the number of mask processes is reduced, the components of the thin film transistor are not formed using mask processes appropriate for their respective characteristics, which increases the possibility that the components of the thin film transistor will not be formed as designed, resulting in a problem of reduced reliability and uniformity of the current characteristics of the thin film transistor.

[0011] Therefore, an object of the present invention is to provide a thin film transistor that can be formed with a relatively small number of mask processes while maintaining reliability and uniformity of current characteristics, a transistor array substrate including the same, and a method for manufacturing the transistor array substrate.

[0012] The problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned here will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0013] According to one embodiment of the present invention, a thin film transistor includes a substrate, an active layer disposed on the substrate and including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region, a gate insulating layer disposed on a portion of the active layer, a gate electrode comprising an electrode conductive layer on the gate insulating layer and overlapping with the channel region of the active layer, a source electrode comprising the electrode conductive layer and extending to the source region of the active layer and in contact with a portion of the source region, and a drain electrode comprising the electrode conductive layer and extending to the drain region of the active layer and in contact with a portion of the drain region. The active layer is made of an oxide semiconductor in a state including crystals by heat treatment, and is arranged in a complete island shape without any holes in a plan view.

[0014] In the active layer, the separation regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode may be disposed in a continuous form alongside the channel region.

[0015] The active layer may be disposed on a buffer layer covering the substrate. The gate electrode, the source electrode, and the drain electrode may be covered with an interlayer insulating layer. Separated regions of the active layer between the gate electrode and each of the source electrode and the drain electrode may contact the interlayer insulating layer and be disposed between the interlayer insulating layer and the buffer layer.

[0016] At least a portion of the active layer excluding the channel region may be made conductive.

[0017] The active layer may have conductive regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode.

[0018] The electrode conductive layer may include a first metal layer disposed on the gate insulating layer and made of titanium (Ti), a second metal layer disposed on the first metal layer and made of a metal material having a lower resistance than titanium (Ti), and a third metal layer disposed on the second metal layer and made of ITO (Indium Tin Oxide).

[0019] According to one embodiment of the present invention, a transistor array substrate includes a substrate including a display region where subpixels are arranged and a non-display region disposed around the display region, and a circuit layer disposed on the substrate and including pixel drivers corresponding to the subpixels. Each of the pixel drivers includes at least one thin film transistor. One thin film transistor of the circuit layer includes: an active layer disposed on the substrate and including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region; a gate insulating layer disposed on a portion of the active layer; a gate electrode formed of an electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer; a source electrode formed of the electrode conductive layer and extending to the source region of the active layer and contacting a portion of the source region; and a drain electrode formed of the electrode conductive layer and extending to the drain region of the active layer and contacting a portion of the drain region. The circuit layer further includes a buffer layer disposed on the substrate and covering the light-shielding conductive layer; and an interlayer insulating layer disposed on the buffer layer and covering the thin film transistor. The active layer is made of an oxide semiconductor in a crystalline state due to heat treatment. In the active layer, the isolation regions between the source electrode and the gate electrode, and the isolation regions between the drain electrode and the gate electrode are in direct contact with the interlayer insulating layer and are disposed between the interlayer insulating layer and the buffer layer.

[0020] In the active layer, the separation regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode may be disposed in a continuous form alongside the channel region.

[0021] The circuit layer may further include a light-shielding electrode made of a light-shielding conductive layer on the substrate, overlapping at least the channel region of the active layer and covered with the buffer layer, and a planarization layer disposed on the interlayer insulating layer.

[0022] At least a portion of the active layer excluding the channel region may be made conductive.

[0023] The active layer may have conductive regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode.

[0024] The electrode conductive layer may include a first metal layer disposed on the gate insulating layer and made of titanium (Ti), a second metal layer disposed on the first metal layer and made of a metal material having a lower resistance than titanium (Ti), and a third metal layer disposed on the second metal layer and made of ITO (Indium Tin Oxide).

[0025] The circuit layer may further include signal pads disposed in a portion of the non-display area, and one of the signal pads may include a first pad layer formed in the same layer as the light-blocking conductive layer, and a second pad layer formed in the same layer as the electrode conductive layer and electrically connected to the first pad layer.

[0026] The transistor array substrate may further include a light emitting device layer disposed on the circuit layer and including light emitting devices electrically connected to each of the pixel drivers. The circuit layer may further include a scan gate line transmitting a scan signal to the pixel driver, a data line transmitting a data signal to the pixel driver, and an initialization voltage line transmitting an initialization voltage to the pixel driver. One of the pixel drivers may include, between a first power line and a second power line transmitting a first power source and a second power source, respectively, for driving the light emitting device, a first thin film transistor connected in series with one of the light emitting devices, a second thin film transistor electrically connected between the data line and a gate electrode of the first thin film transistor and turned on in response to the scan signal of the scan gate line, a pixel capacitor electrically connected to a first node between the gate electrode of the first thin film transistor and the second thin film transistor and a second node between the first thin film transistor and the one light emitting device, and a third thin film transistor electrically connected between the initialization voltage line and the second node and turned on in response to an initialization control signal of the initialization gate line.

[0027] The first power wiring is made of the light-shielding conductive layer. One of the source electrode and the drain electrode of the first thin film transistor may be electrically connected to the first power wiring through a first electrode connection hole that penetrates the gate insulating layer and the buffer layer. The other of the source electrode and the drain electrode of the first thin film transistor may be electrically connected to the light-shielding electrode through a second electrode connection hole that penetrates the gate insulating layer and the buffer layer.

[0028] The one light emitting device may include an anode electrode disposed on the planarization layer and electrically connected to the first thin film transistor through an anode contact hole that penetrates the planarization layer and the interlayer insulating layer.

[0029] The circuit layer may be formed in the same layer as the active layer and may further include a capacitor electrode electrically connected to the gate electrode of the first thin film transistor, and the pixel capacitor may be provided as an overlapping region between the capacitor electrode and the light-shielding electrode.

[0030] A method for manufacturing a transistor array substrate according to one embodiment for solving the above problems includes the steps of: disposing a first semiconductor material layer made of an oxide semiconductor in an amorphous state on a substrate; performing a heat treatment on the first semiconductor material layer to provide a second semiconductor material layer in a state including crystals due to the heat treatment; disposing a gate insulating layer covering the second semiconductor material layer on the substrate; partially removing the gate insulating layer and disposing first auxiliary holes and second auxiliary holes adjacent to both ends of the second semiconductor material layer, respectively; disposing an electrode conductive layer on the gate insulating layer; and partially removing the gate insulating layer while using the electrode conductive layer as a mask, and making a part of the second semiconductor material layer conductive to provide an active layer.

[0031] In the step of providing the second semiconductor material layer, the heat treatment on the first semiconductor material layer may be performed at a temperature of about 300 to 450 degrees Celsius.

[0032] In the step of providing the active layer, the process of partially removing the gate insulating layer may be performed using an etching material containing fluorine (F). The etching rate of the second semiconductor material layer with respect to the etching material containing fluorine (F) is lower than the etching rate of the first semiconductor material layer. Therefore, after the step of providing the active layer, the active layer is arranged in a complete island shape without any holes in a plan view.

[0033] The step of disposing the electrode conductive layer may include sequentially disposing a first metal layer containing titanium (Ti), a second metal layer containing a metal material having a lower resistance than the first metal layer, and a third metal layer containing ITO (Indium Tin Oxide) on the gate insulating layer, and partially removing a stack of the first metal layer, the second metal layer, and the third metal layer to provide the electrode conductive layer. The process of partially removing the stack of the first metal layer, the second metal layer, and the third metal layer may be performed using an etching material containing fluorine (F).

[0034] In the step of arranging the first auxiliary hole and the second auxiliary hole, after the first auxiliary hole and the second auxiliary hole are arranged, the first contact auxiliary portion and the second contact auxiliary portion of the second semiconductor material layer exposed through the first auxiliary hole and the second auxiliary hole, respectively, may be made conductive by contact with an etching material for partially removing the gate insulating layer.

[0035] In the step of providing the electrode conductive layer, the electrode conductive layer may include a gate electrode overlapping a central portion of the second semiconductor material layer, a source electrode overlapping one side of the second semiconductor material layer, and a drain electrode overlapping the other side of the second semiconductor material layer. The source electrode may be in contact with the first contact auxiliary portion of the second semiconductor material layer through the first auxiliary hole. The drain electrode may be in contact with the second contact auxiliary portion of the second semiconductor material layer through the second auxiliary hole.

[0036] In the step of providing the active layer, a portion of the second semiconductor material layer excluding a portion covered with the gate insulating layer may be made conductive to provide the active layer. The active layer may include a channel region overlapping the gate electrode, a source region contacting one side of the channel region, and a drain region contacting the other side of the channel region. The source region may include the first contact assistant portion, and the drain region may include the second contact assistant portion.

[0037] The method for manufacturing a transistor array substrate may further include, before the step of disposing the first semiconductor material layer, disposing a buffer layer covering the light-shielding conductive layer on the substrate. The method for manufacturing a transistor array substrate may further include, after the step of providing the active layer, disposing an interlayer insulating layer covering the electrode conductive layer and the active layer. After the step of disposing the interlayer insulating layer, separation regions of the active layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode may be in direct contact with the interlayer insulating layer and be disposed between the interlayer insulating layer and the buffer layer.

[0038] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0039] A thin film transistor according to one embodiment includes an active layer on a substrate, a gate insulating layer disposed on a portion of the active layer, and a gate electrode, a source electrode, and a drain electrode, each formed of an electrode conductive layer on the gate insulating layer.

[0040] In this way, by forming the gate electrode, source electrode, and drain electrode from the same layer, the number of mask steps required for manufacturing the thin film transistor can be reduced.

[0041] According to one embodiment, the active layer is made of an oxide semiconductor in a crystalline state formed by heat treatment, which has a lower etching rate with an etching material containing fluorine (F) than an oxide semiconductor in an amorphous state.

[0042] That is, a method for manufacturing a transistor array substrate according to one embodiment includes the steps of performing a heat treatment on a first semiconductor material layer made of an oxide semiconductor in an amorphous state to provide a second semiconductor material layer made of a crystalline state, arranging an electrode conductive layer, and making a part of the second semiconductor material layer conductive to provide an active layer.

[0043] In this way, an etching material containing fluorine (F) is used in the process of disposing the electrode conductive layer, and in this case, even if a portion of the second semiconductor material layer is exposed to the etching material, the second semiconductor material layer can be maintained without being partially removed.

[0044] Therefore, the thin film transistor and the transistor array substrate including the thin film transistor according to the embodiment can be formed with a relatively small number of mask processes, while maintaining reliability and uniformity of current characteristics.

[0045] Furthermore, according to the method for manufacturing a transistor array substrate of one embodiment, a transistor array substrate including thin film transistors exhibiting current characteristics with relatively high reliability and uniformity can be provided even with a relatively small number of masking steps.

[0046] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0047] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] FIG. 2 is a plan view showing the display device of FIG. [Figure 3] 2 is a cross-sectional view showing an example of a surface cut along the line AA' in FIG. 1. FIG. [Figure 4] FIG. 4 is a layout diagram showing an example of the circuit layer of FIG. 3. [Figure 5] FIG. 5 is an equivalent circuit diagram showing an example of one subpixel of FIG. 4. [Figure 6] 6 is a plan view showing an example of a first thin film transistor and a pixel capacitor in the pixel driving unit of FIG. 5. FIG. [Figure 7] FIG. 7 is a cross-sectional view showing an example of a surface cut along the line BB' in FIG. 6. [Figure 8] 1 is a flowchart illustrating a method for manufacturing a transistor array substrate according to an embodiment. [Figure 9] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 10] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 11] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 12] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 13] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 14] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 15] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 16] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 17] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 18] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 19] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 20] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 21] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 22] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 23] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 24] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 25] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 26] FIG. 9 is a flow chart for the stage of FIG. 8. [Figure 27] FIG. 9 is a flow chart for the stage of FIG. 8. DETAILED DESCRIPTION OF THE INVENTION

[0048] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0049] When elements or layers are referred to as being "on" other elements or layers, this includes all cases where other layers or elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the details shown in the drawings.

[0050] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0051] The features of the various embodiments of the present invention may be partially or wholly combined or combined with one another, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the others or in conjunction with one another.

[0052] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0053] Fig. 1 is a perspective view showing a display device according to an embodiment, Fig. 2 is a plan view showing the display device of Fig. 1, and Fig. 3 is a cross-sectional view showing an example of a surface cut along the line AA' in Fig. 1.

[0054] Referring to FIGS. 1 and 2, a display device 1 is a device for displaying moving images and still images, and can be used as a display screen for a variety of products, including portable electronic devices such as mobile phones, smartphones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), as well as televisions, notebook computers, monitors, billboards, and Internet of Things (IoT).

[0055] The display device 1 may be an emissive display device such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micro light-emitting display device using micro light-emitting diodes (micro LEDs or nano light-emitting diodes (nano LEDs)). The following description will focus on the organic light-emitting display device as the display device 1. However, the present invention is not limited thereto and may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0056] The display device 1 is formed flat, but is not limited to this. For example, the display device 1 may include curved portions formed on the left and right ends and having a constant or varying curvature. The display device 1 may also be formed to be flexible so that it can be bent, warped, bent, folded, or rolled.

[0057] The display device 1 may include a transistor array substrate 10 .

[0058] The display device 1 may further include a cover substrate 20 facing the transistor array substrate 10 and covering the light emitting element layer 13 .

[0059] Furthermore, the display device 1 may further include a display drive circuit 31 for supplying respective data signals to the data wiring (DL in FIG. 4) of the circuit layer (12 in FIG. 3) of the transistor array substrate 10, and a circuit board 32 for supplying various signals and power to the transistor array substrate 10 and the display drive circuit 31.

[0060] Referring to FIG. 3, a transistor array substrate 10 may include a substrate 11 and a circuit layer 12 disposed on the substrate 11 .

[0061] The transistor array substrate 10 may further include a light emitting element layer 13 disposed on the circuit layer 12 .

[0062] That is, the light emitting element layer 13 is disposed between the substrate 11 and the cover substrate 20 .

[0063] The circuit layer 12 supplies driving signals for the sub-pixels corresponding to the video signals to the light emitting element layer 13. The light emitting element layer 13 can emit light from the sub-pixels in response to the driving signals. The light from the light emitting element layer 13 is emitted to the outside through at least one of the substrate 11 and the cover substrate 20. This allows the display device 1 to provide the function of displaying images.

[0064] The display device 1 may further include a touch sensing unit (not shown) that senses the coordinates of a point touched by a user on a display surface that emits light for displaying an image.

[0065] The touch sensing unit can be attached to one side of the cover substrate 20 or embedded between the transistor array substrate 10 and the cover substrate 20 .

[0066] The touch sensing unit may include a touch electrode (not shown) made of a transparent conductive material, arranged in a touch sensing area corresponding to the display surface.

[0067] Such a touch sensing unit can detect whether a touch has been input and the coordinates of the point where the touch has been input by periodically sensing a change in the capacitance value of the touch electrode while applying a touch drive signal to the touch electrode.

[0068] The cover substrate 20 is bonded to the transistor array substrate 10 in a facing manner.

[0069] The cover substrate 20 can be a means for providing rigidity to protect against external physical and electrical shocks, and is made of a transparent material that is insulating and rigid.

[0070] In addition, the display device 1 may further include a sealing layer 30 disposed on the edge between the transistor array substrate 10 and the cover substrate 20 to bond the transistor array substrate 10 and the cover substrate 20 together.

[0071] The display device 1 may further include a filler layer (not shown) that fills the gap between the transistor array substrate 10 and the cover substrate 20 .

[0072] 1 and 2, the display surface of the display device 1 may be rectangular in shape, with a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) that intersects with the first direction (X-axis direction). However, this is merely an example, and the display surface of the display device 1 may be realized in various shapes.

[0073] For example, the display surface may have a shape where the corner where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect is rounded to have a predetermined curvature, or the display surface may have a shape such as a polygon, a circle, or an ellipse.

[0074] 1 shows the transistor array substrate 10 as being flat, but the present invention is not limited thereto. That is, the transistor array substrate 10 may have a shape in which both ends in the Y-axis direction are curved. Alternatively, the transistor array substrate 10 may be flexible so that it can be bent, warped, bent, folded, or rolled.

[0075] The display drive circuit 31 outputs signals and voltages for driving the transistor array substrate 10 .

[0076] For example, the display drive circuit 31 supplies a data signal to the data wiring (DL in FIG. 4) of the transistor array substrate 10, and supplies a first drive power supply to the first power wiring (VDL in FIG. 4) of the transistor array substrate 10. The display drive circuit 31 also supplies a scan control signal to a gate drive unit (33 in FIG. 4) built into the transistor array substrate 10.

[0077] The display driver circuit 31 may be provided as an integrated circuit (IC).

[0078] The integrated circuit chip of the display driving circuit 31 can be directly mounted on the transistor array substrate 10 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. In this case, as shown in FIG. 2, the integrated circuit chip of the display driving circuit 31 can be disposed in an area of ​​the transistor array substrate 10 that is not covered by the cover substrate 20.

[0079] Alternatively, the integrated circuit chip of the display driver circuit 31 can be mounted on the circuit board 32 .

[0080] The circuit board 32 may include an anisotropic conductive film, a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0081] The circuit board 32 is attached to the electrode pads of the transistor array substrate 10. This allows the lead wires of the circuit board 32 to be electrically connected to the electrode pads of the transistor array substrate 10.

[0082] FIG. 4 is a layout diagram showing an example of the circuit layer of FIG.

[0083] 4, the transistor array substrate 10 may include a display area DA that emits light for displaying images and a non-display area NDA that is the periphery of the display area DA. The non-display area NDA refers to the area from the edge of the display area DA to the edge of the substrate (11 in FIG. 3).

[0084] The transistor array substrate 10 includes sub-pixels PX arranged in a matrix in the vertical and horizontal directions in the display area DA. Each of the sub-pixels PX can be a unit that individually displays brightness and color.

[0085] The non-display area NDA may include a display pad area DPA disposed adjacent to an edge of the substrate 11. The transistor array substrate 10 may further include signal pads SPD disposed in the display pad area DPA of the non-display area NDA.

[0086] The circuit board 32 can be attached to the display pad area DPA of the transistor array substrate 10 and electrically connected to the signal pads SPD.

[0087] The transistor array substrate 10 further includes wirings arranged in the display area DA for supplying signals or power to the sub-pixels PX. The wirings of the transistor array substrate 10 may include scan gate wirings SGL, data wirings DL, and first power wirings VDL.

[0088] The scan gate lines SGL can extend in a first direction (DR1, the left-right direction in FIG. 4).

[0089] The data wiring DL can extend in a second direction (DR2, the vertical direction in FIG. 4).

[0090] The first power wiring VDL may extend in either a first direction DR1 or a second direction DR2. For example, the first power wiring VDL may extend in the second direction DR2 like the data wiring DL.

[0091] Here, the first direction DR1 and the second direction DR2 may be directions in a plane coordinate system perpendicular to the third direction DR3 or the thickness direction of the transistor array substrate 10.

[0092] Alternatively, the circuit layer 12 may further include a first power auxiliary wiring (not shown) extending in a direction intersecting the first power supply wiring VDL and electrically connected to the first power supply wiring VDL in order to reduce the RC delay of the first power supply due to the resistance of the first power supply wiring VDL.

[0093] The scan gate line SGL transmits a scan signal to the sub-pixel PX for controlling whether or not to transmit a data signal.

[0094] The scan gate line SGL may be connected to a gate driver 33 disposed in a part of the non-display area NDA of the transistor array substrate 10 .

[0095] The gate driver 33 can be electrically connected to the display driver circuit 31 or at least one of the signal pads SPD via at least one gate control supply wiring GCSPL.

[0096] The gate driver 33 can apply a scan signal to the scan gate line SGL based on a gate control signal and a gate level power supply supplied via at least one gate control supply line GCSPL.

[0097] 4, the gate driver 33 is disposed in a part of the non-display area NDA adjacent to one side of the display area DA in the first direction DR1 (i.e., the left side in FIG. 4). However, this is merely an example, and the gate driver 33 may be disposed in another part of the non-display area NDA adjacent to the right side of the display area DA. Alternatively, the gate driver 33 may be disposed on both the left and right sides of the display area DA.

[0098] The data wiring DL is electrically connected between the display drive circuit 31 and the sub-pixels PX, and transmits the data signals output from the display drive circuit 31 to the sub-pixels PX.

[0099] The display drive circuit 31 can be electrically connected to some of the signal pads SPD via the data connection lines DLL, i.e., the display drive circuit 31 can be electrically connected to the circuit board 32 via the data connection lines DLL and some of the signal pads SPD.

[0100] The circuit board 32 supplies the display driver circuit 31 with digital video data and timing signals corresponding to the video signal.

[0101] The circuit layer 12 may further include a first power supply wiring VDL and a second power supply wiring (not shown) extending from the non-display area NDA to the display area DA and transmitting a first power supply (ELVDD in FIG. 5) and a second power supply (ELVSS in FIG. 5), respectively, for driving the light emitting elements (EMD in FIG. 5). Here, the second power supply ELVSS may have a lower voltage level than the first power supply ELVDD.

[0102] Each of the first power supply wiring VDL and the second power supply wiring (not shown) can be electrically connected to at least one of the display drive circuit 31 and the signal pads SPD.

[0103] The circuit layer 12 includes pixel driving units (PXD in FIG. 5) that correspond to the sub-pixels PX and are electrically connected to the scan gate lines SGL, the data lines DL, and the first power supply lines VDL.

[0104] FIG. 5 is an equivalent circuit diagram showing an example of one of the subpixels of FIG.

[0105] Referring to FIG. 5, one of the pixel drivers PXD corresponding to the sub-pixels PX includes at least one thin film transistor T1, T2, or T3.

[0106] For example, one pixel driver PXD may include a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3, and may further include a pixel capacitor PC.

[0107] One pixel driver PXD is electrically connected to one of the light emitting elements EMD in the light emitting element layer 13. That is, one pixel driver PXD is electrically connected to the anode electrode (AND in FIGS. 6 and 7) of one light emitting element EMD and supplies a driving current to one light emitting element EMD.

[0108] One light-emitting element EMD may be an organic light-emitting diode including a light-emitting layer made of an organic material. Alternatively, one light-emitting element EMD may include a light-emitting layer made of an inorganic material. Alternatively, the light-emitting element EMD may be a quantum dot light-emitting element including a quantum dot light-emitting layer. Alternatively, the light-emitting element EMD may be a micro light-emitting diode.

[0109] The first thin film transistor T1 is connected in series with the light emitting element EMD between the first power supply wiring VDL and the second power supply wiring VSL, that is, a first electrode (e.g., a source electrode) of the first thin film transistor T1 is electrically connected to the first power supply wiring VDL, and a second electrode (e.g., a drain electrode) of the first thin film transistor T1 is electrically connected to the anode electrode AND of the light emitting element EMD.

[0110] However, the source electrode and the drain electrode of the first thin film transistor T1 can be changed differently from the example of FIG. 5 according to the structure type of the first thin film transistor T1.

[0111] The cathode electrode (CTD in FIG. 7) of the light emitting element EMD can be electrically connected to the second power supply wiring VSL.

[0112] In addition, the gate electrode of the first thin film transistor T1 may be electrically connected to the second thin film transistor T2.

[0113] The pixel capacitor PC may be electrically connected to a first node ND1 and a second node ND2. The first node ND1 is a junction between the gate electrode of the first thin film transistor T1 and the second thin film transistor T2. The second node ND2 is a junction between the first thin film transistor T1 and the light-emitting element EMD.

[0114] The second thin film transistor T2 is electrically connected between the data line DL and the gate electrode of the first thin film transistor T1, and is turned on according to the scan signal SCS of the scan gate line SGL.

[0115] That is, when a scan signal SCS is applied through the scan gate line SGL, the second thin film transistor T2 is turned on, electrically connecting the data line DL and the gate electrode of the first thin film transistor T1, and the data signal VDATA of the data line DL is supplied to the pixel capacitor PC and the gate electrode of the first thin film transistor T1 through the turned-on second thin film transistor T2 and the first node ND1.

[0116] The first thin film transistor T1 is turned on when the potential difference between its gate electrode and source electrode exceeds a threshold voltage. That is, when a data signal VDATA is applied through the first node ND1, the potential difference between the gate electrode and source electrode of the first thin film transistor T1 exceeds the threshold voltage due to the first power supply ELVDD and the data signal VDATA, turning on the first thin film transistor T1. In this case, a driving current Ids between the source electrode and drain electrode of the first thin film transistor T1 is supplied to the light emitting element EMD. The magnitude of the driving current Ids between the source electrode and drain electrode of the first thin film transistor T1 corresponds to the data signal VDATA. That is, when the driving current Ids corresponding to the data signal VDATA is supplied to the light emitting element EMD, the light emitting element EMD can emit light with a brightness corresponding to the data signal VDATA.

[0117] The pixel capacitor PC is electrically connected between the first node ND1 and the second node ND2, and can maintain the potential difference between the gate electrode and the drain electrode of the first thin film transistor T1 until the potential of the first node ND1 changes due to the data signal VDATA.

[0118] The third thin film transistor T3 may be electrically connected between the initialization voltage line VIL and the second node ND2, and the gate electrode of the third thin film transistor T3 may be electrically connected to the initialization gate line IGL.

[0119] That is, when the initialization control signal ICS is applied via the initialization gate line IGL, the third thin film transistor T3 is turned on, electrically connecting the initialization voltage line VIL to the second node ND2. In this case, the initialization voltage VINT of the initialization voltage line VIL is supplied to the anode electrode AND of the light emitting element EMD via the turned-on third thin film transistor T3 and the second node ND2. As a result, the potential of the anode electrode AND can be initialized to the initialization voltage VINT.

[0120] 5 shows the pixel driver PXD having a 3T1C structure including the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and one pixel capacitor PC, but this is merely an example. That is, the pixel driver PXD according to an embodiment is not limited to the 3T1C structure shown in FIG. 5 and can be modified as needed to differ from the structure shown in FIG. 5. As an example, the pixel driver PXD may further include a thin film transistor for initializing the potential of the first node ND1.

[0121] 5 shows a case where at least one thin film transistor T1, T2, T3 provided in the pixel driver PXD is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but this is merely an example, that is, at least one of the at least one thin film transistor T1, T2, T3 provided in the pixel driver PXD may be a P-type MOSFET.

[0122] Fig. 6 is a plan view showing an example of a first thin film transistor and a pixel capacitor in the pixel driving unit of Fig. 5. Fig. 7 is a cross-sectional view showing an example of a surface cut along the line BB' of Fig. 6.

[0123] Referring to FIG. 6, a first thin film transistor T1 according to an embodiment includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0124] Although not shown in detail, the second thin film transistor T2 and the third thin film transistor T3 of the pixel driving unit PXD are the same as or similar to the first thin film transistor T1 shown in Figures 6 and 7, and therefore will not be described again below. In the following description, the first thin film transistor T1 in Figures 6 and 7 may be abbreviated to thin film transistor T1.

[0125] 7, the active layer ACT is disposed on a substrate 11. The active layer ACT includes a channel region CA consisting of a central portion, a source region SA connected to one side of the channel region CA, and a drain region DA connected to the other side of the channel region CA.

[0126] According to one embodiment, the active layer ACT is made of an oxide semiconductor SEL in a state including crystals due to a heat treatment.

[0127] That is, the active layer ACT is not made of an oxide semiconductor in an amorphous state, but is made of an oxide semiconductor in a crystallized state by a heat treatment process, in which the heat treatment process is carried out at a temperature of about 350 to 450 degrees Celsius.

[0128] In this way, when the active layer ACT is made of a crystallized oxide semiconductor, its chemical resistance to etching materials containing fluorine (F) is improved compared to when it is in an amorphous state, and it is not easily removed even when exposed to the etching material. In other words, no separate etching prevention layer or mask is provided to preserve (remain) the active layer ACT, and even if a portion of the active layer ACT is exposed to the etching material to reduce the number of masking processes, the active layer ACT can be arranged in a complete island shape that does not include unnecessary holes in a plan view.

[0129] As a result, the current path in the active layer ACT is not reduced by holes, improving the reliability and uniformity of the current characteristics of the thin film transistor T1.

[0130] At least a portion of the active layer ACT excluding the channel region CA may be made conductive so as to have higher conductivity than the channel region CA. That is, at least a portion of the source region SA and at least a portion of the drain region DA may be made conductive. In particular, the separation region GA between the source electrode SE and the gate electrode GE and between the drain electrode DE and the gate electrode GE of the active layer ACT may be made conductive.

[0131] Here, the conductive state refers to a state in which the conductivity is increased by reducing the oxygen content or increasing the hydrogen content compared to the channel region CA.

[0132] The portion of the active layer ACT that is covered with the gate insulating layer GI, including the channel region CA, is not made conductive and can maintain its semiconductivity, whereas the portion of the active layer ACT that is not covered with the gate insulating layer GI comes into contact with the etching material when the gate insulating layer GI is removed, and reacts with the etching material to become conductive.

[0133] By making at least a part of the source region SA and at least a part of the drain region DA conductive in this way, the resistance of the thin film transistor T1 is reduced and the magnitude of the source-drain current of the thin film transistor T1 is increased, thereby improving the current characteristics of the thin film transistor T1.

[0134] According to one embodiment, the gate electrode GE, the source electrode SE, and the drain electrode DE are each made of an electrode conductive layer ECDL on a gate insulating layer GI that covers a part of the active layer ACT, thereby reducing the number of mask steps required to arrange the thin film transistor T1.

[0135] As shown in FIGS. 6 and 7, the gate electrode GE is made of an electrode conductive layer ECDL on a gate insulating layer GI, and overlaps with the channel region CA of the active layer ACT.

[0136] The source electrode SE is made of the electrode conductive layer ECDL on the gate insulating layer GI and may extend to the source region SA of the active layer ACT and contact a part of the source region SA. This allows the source electrode SE to be electrically connected to the source region SA of the active layer ACT. In particular, to reduce the resistance between the source electrode SE and the active layer ACT, the source electrode SE may be in contact with or adjacent to a conductive part of the source region SA.

[0137] The drain electrode DE is made of the electrode conductive layer ECDL on the gate insulating layer GI and may extend to the drain region DA of the active layer ACT and contact a part of the drain region DA. This allows the drain electrode DE to be electrically connected to the drain region DA of the active layer ACT. In particular, to reduce the resistance between the drain electrode DE and the active layer ACT, the drain electrode DE may be in contact with or adjacent to a conductive part of the drain region DA.

[0138] As described above, according to one embodiment, the gate electrode GE, source electrode SE, and drain electrode DE of the thin-film transistor T1 are all made of the electrode conductive layer ECDL on the gate insulating layer GI, thereby reducing the number of masking steps required to arrange the thin-film transistor T1.

[0139] According to one embodiment, the active layer ACT of the thin film transistor T1 is made of an oxide semiconductor SEL crystallized by heat treatment. The oxide semiconductor SEL crystallized by heat treatment can have improved chemical resistance to etching materials containing fluorine (F) compared to an amorphous state. Therefore, even if a portion of the active layer ACT is exposed to an etching material for disposing the electrode conductive layer ECDL due to the reduced number of masking steps, the portion of the active layer ACT is not easily lost and can remain as is.

[0140] Therefore, as shown in FIGS. 6 and 7, the active layer ACT can be arranged in a complete island shape without any holes in plan view.

[0141] In other words, not only the regions of the active layer ACT that overlap with the gate electrode GE, source electrode SE, and drain electrode DE, but also the isolated regions GA that do not overlap with the gate electrode GE, source electrode SE, and drain electrode DE can be arranged in a complete island shape that does not include holes in a planar view.

[0142] That is, the separation regions GA between the source electrode SE, the drain electrode DE, and the gate electrode GE in the active layer ACT may be arranged in a continuous form alongside the channel region CA.

[0143] The circuit layer 12 of the transistor array substrate 10 according to one embodiment may further include a buffer layer 121 disposed between the substrate 11 and the active layer ACT, and an interlayer insulating layer 122 covering the gate electrode GE, source electrode SE and drain electrode DE of the thin film transistor T1.

[0144] Furthermore, the circuit layer 12 of the transistor array substrate 10 according to the embodiment may further include a planarization layer 123 disposed flat on the interlayer insulating layer 122 .

[0145] That is, the active layer ACT may be disposed on a buffer layer 121 covering the substrate 11. The gate electrode GE, the source electrode SE, and the drain electrode DE of the thin film transistor T1 may be covered with an interlayer insulating layer 122.

[0146] As described above, according to one embodiment, the active layer ACT is made of a crystallized oxide semiconductor SEL and is therefore arranged in a complete island shape without holes in a planar view. As a result, the isolation regions GA of the active layer ACT between the source electrode SE and the gate electrode GE and between the drain electrode DE and the gate electrode GE are in contact with the interlayer insulating layer 122, and the planarization layer 123 can be separated from the buffer layer 121. That is, the isolation regions GA of the active layer ACT between the source electrode SE and the gate electrode GE and between the drain electrode DE and the gate electrode GE are arranged between the planarization layer 123 and the buffer layer 121. Therefore, the buffer layer 121 and the planarization layer 123 are not in direct contact with each other due to the presence of the active layer ACT.

[0147] This, according to one embodiment, improves the reliability and uniformity of the current characteristics of the thin film transistor T1, since the current path in the active layer ACT is not altered by the holes.

[0148] 6 and 7, the circuit layer 12 of the transistor array substrate 10 according to an embodiment may further include a light-shielding electrode LSL that is made of a light-shielding conductive layer BCDL on the substrate 11 and overlaps at least the channel region CA of the active layer ACT. Such a light-shielding electrode LSL can prevent leakage current from the active layer ACT due to external light incident through the substrate 11.

[0149] According to one embodiment, the circuit layer 12 of the transistor array substrate 10 may further include a scan gate line SGL that transmits a scan signal SCS to the pixel driver PXD, a data line DL that transmits a data signal VDATA to the pixel driver PXD, and an initialization voltage line VIL that transmits an initialization voltage VINT to the pixel driver PXD.

[0150] In addition, the circuit layer 12 of the transistor array substrate 10 may further include a first power supply line VDL that transmits a first power supply ELVDD to the pixel driving unit PXD.

[0151] In addition, the circuit layer 12 of the transistor array substrate 10 may further include an initialization gate line IGL that transmits an initialization control signal ICS to the pixel driving unit PXD.

[0152] The scan gate line SGL and the initialization gate line IGL extend in a first direction DR1 and are spaced apart from each other in a second direction DR2.

[0153] The data line DL, the first power supply line VDL, and the initialization voltage line VIL extend in the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0154] The wiring in the first direction DR1, including the scan gate wiring SGL and the initialization gate wiring IGL, is made of a conductive layer different from the wiring in the second direction DR2, including the data wiring DL, the first power supply wiring VDL, and the initialization voltage wiring VIL, and can be mutually insulated by the buffer layer 121.

[0155] As an example, the wiring in the second direction DR2, including the data wiring DL, the first power supply wiring VDL, and the initialization voltage wiring VIL, is made of a light-shielding conductive layer BCDL, and the wiring in the first direction DR1, including the scan gate wiring SGL and the initialization gate wiring IGL, is made of an electrode conductive layer ECDL.

[0156] The circuit layer 12 of the transistor array substrate 10 according to the embodiment may further include signal pads SPD disposed in the display pad area DPA.

[0157] As shown in FIG. 7, one of the signal pads SPD may include a first pad layer PDL1 made of the same layer as the light-shielding conductive layer BCDL on the substrate 11, and a second pad layer PDL2 made of the same layer as the electrode conductive layer ECDL on the gate insulating layer GI and electrically connected to the first pad layer PDL1.

[0158] The second pad layer PDL2 can be electrically connected to the first pad layer PDL1 through at least one hole that penetrates the buffer layer 121.

[0159] The interlayer insulating layer 122 may cover the edge of the second pad layer PDL2.

[0160] That is, a central portion of the second pad layer PDL2 is exposed and not covered by the interlayer insulating layer 122 for bonding to the circuit board 32. In addition, the edges of the side and top surfaces of the second pad layer PDL2 are covered with the interlayer insulating layer 122 to protect them from corrosion, physical impact, etc. In addition, to prevent corrosion of the second pad layer PDL2, the top layer of the electrode conductive layer ECDL is made of ITO (Indium Tin Oxide).

[0161] The substrate 11 is made of an insulating material such as a polymer resin. For example, the substrate 11 is made of polyimide. The substrate 11 may be a flexible substrate that allows bending, folding, rolling, and the like.

[0162] Alternatively, the substrate 11 is made of an insulating material such as rigid glass.

[0163] Each of the buffer layer 121, the gate insulating layer GI, and the interlayer insulating layer 122 is made of at least one inorganic film. For example, each of the buffer layer 121, the gate insulating layer GI, and the interlayer insulating layer 122 is made of a multilayer structure in which one or more inorganic films selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0164] The light-shielding conductive layer BCDL on the substrate 11 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0165] As shown in FIG. 6, the light-shielding conductive layer BCDL may include a first power supply line VDL and a light-shielding electrode LSL.

[0166] The light-shielding conductive layer BCDL may further include a data line DL and an initialization voltage line VIL extending in the second direction DR2.

[0167] In addition, the light-shielding conductive layer BCDL may further include a first pad layer PDL1 of the signal pad SPD.

[0168] One of the source electrode SE and drain electrode DE of the first thin film transistor T1 (the source electrode SE in FIG. 6) can be electrically connected to the first power supply wiring VDL through a first electrode connection hole ECH1 that penetrates the gate insulating layer GI and the buffer layer 121.

[0169] The other of the source electrode SE and drain electrode DE of the first thin film transistor T1 (the drain electrode DE in FIG. 6) can be electrically connected to the light-shielding electrode LSL through a second electrode connection hole ECH2 that penetrates the gate insulating layer GI and the buffer layer 121.

[0170] In this way, the light-shielding electrode LSL is not maintained in a floating state but is electrically connected to the drain electrode DE of the first thin film transistor T1, thereby stably maintaining the potential of the second node ND2 between the first thin film transistor T1 and the light-emitting element EMD.

[0171] The light emitting element layer 13 includes light emitting elements EMD corresponding to the sub-pixels PX, respectively. One of the light emitting elements EMD may include an anode electrode AND and a cathode electrode CTD facing each other, and an emitting layer EML made of a photoelectric conversion material and interposed between the anode electrode AND and the cathode electrode CTD.

[0172] The anode electrode AND is disposed on the planarization layer 123 and may be electrically connected to the drain electrode DE of the first thin film transistor T1 through an anode contact hole ANCH that penetrates the planarization layer 123 and the interlayer insulating layer 122.

[0173] In addition, the light emitting element layer 13 may further include a pixel definition layer PDL that covers the edge of the anode electrode AND.

[0174] The circuit layer 12 of the transistor array substrate 10 according to one embodiment may further include a capacitor electrode CPE for providing a pixel capacitor PC.

[0175] The capacitor electrode CPE is made of the same layer as the active layer ACT, that is, the capacitor electrode CPE is made of an oxide semiconductor that has been crystallized by heat treatment and made conductive.

[0176] The capacitor electrode CPE can be electrically connected to the gate electrode GE of the first thin film transistor T1 through a capacitor connection hole CPCH that penetrates the gate insulating layer GI. That is, the gate electrode GE of the first thin film transistor T1 can extend into the capacitor connection hole CPCH and contact a portion of the capacitor electrode CPE through the capacitor connection hole CPCH. Here, the gate electrode GE of the first thin film transistor T1 overlaps a portion of the capacitor connection hole CPCH.

[0177] Alternatively, although not shown separately, the capacitor electrode CPE may be exposed without being covered by the gate insulating layer GI. That is, according to one embodiment, the capacitor electrode CPE is made of a crystallized oxide semiconductor, and therefore has a relatively low etching rate due to the etching material. Therefore, the capacitor electrode CPE may be in a state where it is not covered by the gate insulating layer GI while the electrode conductive layer ECDL is disposed. Therefore, without a separate capacitor contact hole CPCH, the gate electrode GE of the first thin film transistor T1 extends toward the capacitor electrode CPE and contacts the capacitor electrode CPE, thereby being electrically connected to the capacitor electrode CPE.

[0178] As a result, the pixel capacitor PC is provided as an overlapping region between the capacitor electrode CPE and the light-shielding electrode LSL.

[0179] Furthermore, a part of the light-shielding electrode LSL overlaps with the capacitor electrode CPE, thereby providing a pixel capacitor PC.

[0180] 7, the light-shielding conductive layer BCDL has a double-layer structure including a diffusion prevention layer and a low-resistance layer. For example, the diffusion prevention layer of the light-shielding conductive layer BCDL is made of titanium (Ti), and the low-resistance layer of the light-shielding conductive layer BCDL is made of copper (Cu).

[0181] The electrode conductive layer ECDL on the gate insulating layer GI has a triple layer structure.

[0182] As shown in FIG. 6, the electrode conductive layer ECDL includes a gate electrode GE, a source electrode SE, and a drain electrode DE of the thin film transistor T1.

[0183] The electrode conductive layer ECDL may further include a scan gate line SGL and an initialization gate line IGL extending in the first direction DR1.

[0184] Moreover, the electrode conductive layer ECDL may further include a second pad layer PDL2 of the signal pad SPD.

[0185] As shown in FIG. 7, the electrode conductive layer ECDL may include a first metal layer ML1 disposed on the gate insulating layer GI, a second metal layer ML2 disposed on the first metal layer ML1, and a third metal layer ML3 disposed on the second metal layer ML2.

[0186] The first metal layer ML1 is intended to block the metal material of the second metal layer ML2 from diffusing into the surrounding area. The first metal layer ML1 is made of titanium (Ti).

[0187] The second metal layer ML2 is intended to reduce the resistance of the electrode conductive layer ECDL and is made of a metal material with relatively low resistance. That is, the second metal layer ML2 is made of at least one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu). As an example, the second metal layer ML2 may be made of copper (Cu).

[0188] The third metal layer ML3 is made of ITO for corrosion protection and easy bonding of the signal pads SPD.

[0189] The transistor array substrate 10 according to the embodiment may further include an encapsulation layer 14 disposed on the light emitting element layer 13 .

[0190] The sealing layer 14 has a structure in which at least one inorganic film and at least one organic film are alternately laminated. As an example, the sealing layer 14 may include a first inorganic layer 141 disposed on the light-emitting element layer 13 and made of an inorganic insulating material, an organic layer 142 disposed on the first inorganic layer 141 and made of an organic insulating material, and a second inorganic layer 143 disposed on the first inorganic layer 141, covering the organic layer 142, and made of an inorganic insulating material.

[0191] Next, a method for manufacturing the transistor array substrate 10 according to one embodiment will be described.

[0192] 8 is a flowchart illustrating a method for manufacturing a transistor array substrate according to an embodiment, and FIGS. 9 to 27 are process diagrams for each step of FIG.

[0193] 8, a method for manufacturing a transistor array substrate 10 according to an embodiment includes the steps of: disposing a first semiconductor material layer on a substrate 11 (S13); performing a heat treatment on the first semiconductor material layer to provide a second semiconductor material layer including crystals formed by the heat treatment (S14); disposing a gate insulating layer GI covering the second semiconductor material layer on the substrate 11 (S15); partially removing the gate insulating layer GI to provide first and second auxiliary holes (S16); disposing an electrode conductive layer ECDL on the gate insulating layer GI (S17); and partially removing the gate insulating layer GI using the electrode conductive layer ECDL as a mask, and making a portion of the second semiconductor material layer conductive to provide an active layer ACT (S18).

[0194] In addition, the manufacturing method of the transistor array substrate 10 according to one embodiment may further include, before the step of disposing the first semiconductor material layer (S13), the step of disposing a light-shielding conductive layer BCDL on the substrate 11 (S11) and the step of disposing a buffer layer 121 covering the light-shielding conductive layer BCDL on the substrate 11 (S12).

[0195] A manufacturing method of a transistor array substrate 10 according to one embodiment may further include, after the step of providing an active layer ACT (S18), a step of disposing an interlayer insulating layer 122 covering the electrode conductive layer ECDL and the active layer ACT, and a step of disposing a planarizing layer 123 flatly covering the interlayer insulating layer 122 (S19).

[0196] In addition, the manufacturing method of the transistor array substrate 10 according to one embodiment may further include, after the step of disposing the interlayer insulating layer 122 and the planarization layer 123 (S19), the step of disposing an anode contact hole ANCH penetrating the interlayer insulating layer 122 and the planarization layer 123 (S21), the step of disposing the light emitting element layer 13 on the planarization layer 123 (S22), and the step of disposing the encapsulation layer 14 on the light emitting element layer 13.

[0197] 9 and 10, after the substrate 11 including the display area DA and the non-display area NDA is provided, a light-shielding conductive layer (BCDL:VDL, LSL) may be disposed on the substrate 11 (S11).

[0198] The light-shielding conductive layer BCDL can include a light-shielding electrode LSL arranged in each of the sub-pixels PX.

[0199] The light-shielding conductive layer BCDL may further include wirings in the second direction DR2 that are arranged in the display area DA and extend in the second direction DR2. The wirings in the second direction DR2 may include the data wirings DL, the first power supply wirings VDL, and the initialization voltage wirings VIL.

[0200] Next, as shown in FIG. 10, a buffer layer 121 may be disposed by stacking an inorganic insulating material on the substrate 11 to cover the light-shielding conductive layer BCDL (S12).

[0201] 11 and 12, an amorphous oxide semiconductor may be stacked on the buffer layer 121, and the amorphous oxide semiconductor may be partially removed to form a first semiconductor material layer 211 in each of the sub-pixels PX (S13).

[0202] The oxide semiconductor of the first semiconductor material layer 211 can include one or more metal materials of indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al), and molybdenum (Mo).

[0203] In this case, a first capacitor electrode material layer 212 may further be disposed in each of the sub-pixels PX.

[0204] Referring to FIG. 13, the first semiconductor material layer 211 is subjected to a heat treatment (HEAT) to provide a second semiconductor material layer 221 in a state including crystals due to the heat treatment (S14).

[0205] In this case, the first capacitor electrode material layer 212 is also exposed to the heat treatment, and thus the second capacitor electrode material layer 222 is also provided in a state including crystals due to the heat treatment.

[0206] The heat treatment for the first semiconductor material layer 211 and the first capacitor electrode material layer 212 is carried out at a temperature of 300 to 450 degrees Celsius. The heat treatment is carried out for a process time of one hour or less.

[0207] Depending on the process temperature and process time of the heat treatment, at least a portion of each of the first semiconductor material layer 211 and the first capacitor electrode material layer 212 can be transformed into a crystallized state.

[0208] For example, the higher the process temperature or the longer the process time, the more portions of the first semiconductor material layer 211 and the first capacitor electrode material layer 212 may be converted into a crystallized state.

[0209] As another example, only a portion of the upper side of each of the first semiconductor material layer 211 and the first capacitor electrode material layer 212 can be converted to a crystallized state. That is, a portion of the upper side of the first semiconductor material layer 211 and a portion of the upper side of the first capacitor electrode material layer 212 can be converted to a crystallized state and provided as the second semiconductor material layer 221 and the second capacitor electrode material layer 222, respectively, and the remaining portions of the lower sides can be maintained in an amorphous state.

[0210] Referring to FIG. 14, an inorganic insulating material is stacked on the buffer layer 121 to cover the second semiconductor material layer 221, thereby forming a gate insulating layer GI (S15).

[0211] In this case, the gate insulating layer GI may further cover the second capacitor electrode material layer 222.

[0212] 15 and 16, the gate insulating layer GI may be partially removed to form a first auxiliary hole ASH1 and a second auxiliary hole ASH2 adjacent to each other at both ends of the second semiconductor material layer 221 (S16).

[0213] That is, the first auxiliary hole ASH1 and the second auxiliary hole ASH2 can be disposed by performing an etching process on the gate insulating layer GI to remove a portion of the gate insulating layer GI.

[0214] During the etching process for the gate insulating layer GI, portions of the second semiconductor material layer 221 corresponding to the first auxiliary hole ASH1 and the second auxiliary hole ASH2 are exposed to the etching process for partially removing the gate insulating layer GI through the first auxiliary hole ASH1 and the second auxiliary hole ASH2, respectively, and are made conductive, thereby providing the first contact auxiliary portion CTA1 and the second contact auxiliary portion CTA2.

[0215] That is, in the step of arranging the first auxiliary hole ASH1 and the second auxiliary hole ASH2 (S16), after the first auxiliary hole ASH1 and the second auxiliary hole ASH2 are arranged, the first contact auxiliary portion CTA1 and the second contact auxiliary portion CTA2 exposed through the first auxiliary hole ASH1 and the second auxiliary hole ASH2 of the second semiconductor material layer 221, respectively, can be converted into a conductive state by coming into contact with an etching material for partially removing the gate insulating layer GI.

[0216] Furthermore, in the step of forming the first auxiliary hole ASH1 and the second auxiliary hole ASH2 (S16), a capacitor connection hole CPCH may be further formed, penetrating the gate insulating layer GI and exposing a portion of the second capacitor electrode material layer 222. In this case, the portion of the second capacitor electrode material layer 222 may be exposed to an etching process through the capacitor connection hole CPCH and made conductive.

[0217] Alternatively, although not separately shown, in the step of forming the first auxiliary hole ASH1 and the second auxiliary hole ASH2 (S16), a portion of the gate insulating layer GI covering the second capacitor electrode material layer 222 may be removed. That is, the entire second capacitor electrode material layer 222 may be exposed to an etching process. In this case, the second capacitor electrode material layer 222 comes into contact with the etching material for partially removing the gate insulating layer GI and is converted into a conductive state, thereby providing the capacitor electrode CPE.

[0218] Furthermore, in the step (S16) of arranging the first auxiliary hole ASH1 and the second auxiliary hole ASH2, a first electrode connection hole ECH1 that penetrates the gate insulating layer GI and the buffer layer 121 and exposes a portion of the first power supply wiring VDL, and a second electrode connection hole ECH2 that penetrates the gate insulating layer GI and the buffer layer 121 and exposes a portion of the light-shielding electrode LSL are further provided.

[0219] In addition, as shown in FIG. 16, in the step (S16) of arranging the first auxiliary hole ASH1 and the second auxiliary hole ASH2, at least one pad connection hole PDCH may be further provided, penetrating the gate insulating layer GI and the buffer layer 121 and exposing a portion of the first pad layer PDL1.

[0220] As an example, the process of partially removing the gate insulating layer GI to form the first auxiliary hole ASH1 and the second auxiliary hole ASH2 is performed using an etching material containing fluorine (F).

[0221] Because the second semiconductor material layer 221 and the second capacitor electrode material layer 222 are in a crystallized state due to heat treatment, the etching rate of the second semiconductor material layer 221 and the second capacitor electrode material layer 222 by an etching material containing fluorine (F) is lower than that of the first semiconductor material layer 211 and the first capacitor electrode material layer 212, which are in an amorphous state. In other words, even when the second semiconductor material layer 221 and the second capacitor electrode material layer 222, which are in a crystallized state, are exposed to an etching material containing fluorine (F), they can remain without reacting with the etching material containing fluorine (F) and being removed.

[0222] As shown in Figures 17 and 18, the stack of the first metal layer ML1, the second metal layer ML2 and the third metal layer ML3 arranged on the gate insulating layer GI is partially removed and an electrode conductive layer ECDL is arranged (S17).

[0223] That is, the step of disposing the electrode conductive layer ECDL (S17) may include a step of sequentially disposing a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 on the gate insulating layer GI, and a step of partially removing the stack of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 to provide the electrode conductive layer ECDL.

[0224] The first metal layer ML1 may include titanium (Ti).

[0225] The second metal layer ML2 may include a metal material having a lower resistance than the first metal layer ML1. That is, the second metal layer ML2 may include at least one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu). For example, the second metal layer ML2 may include copper (Cu).

[0226] The third metal layer ML3 may include ITO.

[0227] Therefore, the process of partially removing the stack of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 can be performed using an etching material containing fluorine (F).

[0228] For example, the etching material used in the process of partially removing the stack of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 may be fluorine (F), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), phosphoric acid (H3O4 P ), nitric acid (HNO3), and acetic acid (CH3COOH).

[0229] The etching material may have a fluorine content of about 5% or less. The etching material may also have a hydrogen peroxide content of about 30% or less, a sulfuric acid content of about 10% or less, a phosphoric acid content of about 60% or less, a nitric acid content of about 30% or less, and an acetic acid content of about 10% or less. However, these are merely examples, and the components and composition ratios of the etching material according to one embodiment are not limited thereto.

[0230] As described above, the etching rate of the second semiconductor material layer 221 and the second capacitor electrode material layer 222 by an etching material containing fluorine (F) is lower than that of the amorphous first semiconductor material layer 211 and the first capacitor electrode material layer 212. Therefore, even if the etching material for partially removing the stack of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 contains fluorine (F), the second semiconductor material layer 221 and the second capacitor electrode material layer 222 (or the capacitor electrode CPE) can remain without reacting with the etching material.

[0231] The electrode conductive layer ECDL may include a gate electrode GE overlapping a central portion of the second semiconductor material layer 221, a source electrode SE overlapping one side of the second semiconductor material layer 221, and a drain electrode DE overlapping the other side of the second semiconductor material layer 221.

[0232] The source electrode SE may extend into the first auxiliary hole ASH1 and contact the first contact auxiliary portion CTA1 of the second semiconductor material layer 221 through the first auxiliary hole ASH1.

[0233] The drain electrode DE may extend into the second auxiliary hole ASH2 and be in contact with the second contact auxiliary portion CTA2 of the second semiconductor material layer 221 through the second auxiliary hole ASH2.

[0234] Here, the source electrode SE and the drain electrode DE do not entirely cover the first auxiliary hole ASH1 and the second auxiliary hole ASH2, respectively, because the remaining portions of the second semiconductor material layer 221, excluding the first contact assistant portion CTA1 and the second contact assistant portion CTA2, are covered with the gate insulating layer GI and cannot be electrically connected to the source electrode SE and the drain electrode DE.

[0235] That is, the source electrode SE may overlap with a part of the first auxiliary hole ASH1 and be in contact with a part of the first contact assistant portion CTA1, and the drain electrode DE may overlap with a part of the second auxiliary hole ASH2 and be in contact with a part of the second contact assistant portion CTA2.

[0236] In addition, the gate electrode GE of the first thin film transistor T1 can be electrically connected to the capacitor electrode CPE by extending until it contacts a part of the capacitor electrode CPE.

[0237] The source electrode SE of the first thin film transistor T1 can be electrically connected to the first power supply line VDL through the first electrode connection hole ECH1.

[0238] The drain electrode DE of the first thin film transistor T1 can be electrically connected to the light-shielding electrode LSL through the second electrode connection hole ECH2.

[0239] Referring to Figures 19 and 20, the gate insulating layer GI is partially removed using the electrode conductive layer (ECDL: GE, SE, DE) as a mask, and part of the second semiconductor material layer 221 is made conductive to provide an active layer ACT (S18).

[0240] That is, in the step of providing the active layer ACT (S18), the gate insulating layer GI covering the isolation region GA between the source electrode SE and the drain electrode DE and the gate electrode GE in the second semiconductor material layer 221 is removed, and the isolation region GA is converted into a conductive state, thereby providing the active layer ACT including the conductive isolation region GA. Here, the conductive state refers to a state having conductivity, unlike the channel region CA which maintains semiconductivity.

[0241] This provides a first thin film transistor T1 including an active layer ACT, a gate electrode GE, a source electrode SE and a drain electrode DE.

[0242] In the step of providing the active layer ACT (S18), the process of partially removing the gate insulating layer GI is performed using an etching material containing fluorine (F).

[0243] Because the second semiconductor material layer 221 and the second capacitor electrode material layer 222 are in a crystallized state due to heat treatment, the etching rate of the second semiconductor material layer 221 and the second capacitor electrode material layer 222 by an etching material containing fluorine (F) is lower than that of the first semiconductor material layer 211 and the first capacitor electrode material layer 212, which are in an amorphous state. In other words, even when the second semiconductor material layer 221 and the second capacitor electrode material layer 222, which are in a crystallized state, are exposed to an etching material containing fluorine (F), they can remain without reacting with the etching material containing fluorine (F) and being removed.

[0244] Therefore, after the step (S18) of providing the active layer ACT, the active layer ACT can be arranged in a complete island shape that does not include holes in a plan view.

[0245] In addition, in the step of providing the active layer ACT (S18), the portion of the second capacitor electrode material layer 222 that does not overlap with the gate electrode GE of the first thin film transistor T1 is converted into a conductive state, thereby providing the capacitor electrode CPE.

[0246] 21 and 22 are diagrams showing a general transistor array substrate REF.

[0247] Referring to FIGS. 21 and 22, a typical transistor array substrate REF includes an active layer made of an amorphous oxide semiconductor and a capacitor electrode.

[0248] Therefore, after the first auxiliary hole ASH1 and the second auxiliary hole ASH2 for electrical connection between the source electrode SE and the drain electrode DE, respectively, and the active layer ACT' are formed, during the process of forming the source electrode SE and the drain electrode DE, the portions of the active layer ACT' that are exposed by the first auxiliary hole ASH1 and the second auxiliary hole ASH2 but do not overlap with the source electrode SE and the drain electrode DE are removed by an etching material. Therefore, the active layer ACT' of the general transistor array substrate REF includes through holes THH that are disposed between the source electrode SE and the drain electrode DE, respectively, and the gate electrode GE. The through holes THH of the active layer ACT' deform or reduce the current path in the active layer ACT', which may reduce the reliability and uniformity of the current characteristics of the thin film transistors of the general transistor array substrate REF.

[0249] In addition, the capacitor electrode CPE' of the general transistor array substrate REF also includes a through hole THH' disposed around the capacitor connection hole CPCH, so that the resistance characteristic between the gate electrode GE of the first thin film transistor T1 and the capacitor electrode CPE' may increase or vary, and the capacitance of the pixel capacitor PC may vary.

[0250] However, as described above, the manufacturing method of the transistor array substrate 10 according to the embodiment includes the step (S14) of heat-treating the amorphous first semiconductor material layer 211 to form the crystallized second semiconductor material layer 221. In this case, the crystallized second semiconductor material layer 221 is less susceptible to etching by the etching material containing fluorine (F) than the amorphous first semiconductor material layer 211.

[0251] Therefore, since the source electrode SE and the drain electrode DE are arranged in the same layer as the gate electrode GE, the second semiconductor material layer 221 can remain intact even if it is exposed to an etching material one or more times, and the active layer ACT can be arranged in a complete island shape without any holes in a planar view, thereby improving the reliability and uniformity of the current characteristics of the thin film transistor T1.

[0252] That is, according to one embodiment, the source electrode SE and the drain electrode DE are arranged in the same layer as the gate electrode GE, thereby reducing the number of mask processes and allowing the active layer ACT to be arranged in a complete island shape.

[0253] In addition, since the capacitor electrode CPE can be arranged in a completely island-like planar shape, the uniformity of the resistance characteristics between the gate electrode GE of the first thin film transistor T1 and the capacitor electrode CPE' can be improved, and the uniformity of the capacitance of the pixel capacitor PC can be improved.

[0254] 23, an inorganic insulating material that covers the thin film transistor T1 may be applied on the buffer layer 121 to form an interlayer insulating layer 122. An organic insulating material may be applied on the interlayer insulating layer 122 to form a planarization layer 123 (S19).

[0255] The interlayer insulating layer 122 is made of a multi-layer structure in which one or more inorganic layers selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

[0256] The planarizing layer 123 is made of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0257] 24 and 25, the interlayer insulating layer 122 and the planarizing layer 123 may be partially removed, and an anode contact hole ANCH may be disposed through the interlayer insulating layer 122 and the planarizing layer 123 to expose a portion of the drain electrode DE of the first thin film transistor T1 (S21).

[0258] Referring to FIGS. 26 and 27, the light emitting element layer 13 may be disposed on the planarization layer 123 (S22).

[0259] The light-emitting element layer 13 may include an anode electrode AND electrically connected to the first thin-film transistor T1 through an anode contact hole ANCH, a pixel definition layer PDL disposed in a spaced apart portion between the anode electrodes AND of the sub-pixels PX, an emission layer EML disposed on the anode electrode AND, and a cathode electrode CTD disposed on the emission layer EML.

[0260] The anode electrodes AND may be pixel electrodes corresponding to the respective sub-pixels PX. The anode electrodes AND may reflect at least a portion of the light generated in the emitting layer EML.

[0261] The cathode electrode CTD may be a common electrode corresponding to the entire sub-pixel PX. The cathode electrode CTD may transmit at least a part of the light generated in the emitting layer EML.

[0262] The light-emitting layer EML is disposed in each of the sub-pixels PX, or when the display device 1 includes a color filter member (not shown) or a color conversion member (not shown) or displays a single color, the light-emitting layer EML may be disposed in the same layer across the sub-pixels PX.

[0263] Next, the sealing layer 14 is disposed on the light emitting element layer 13 (S23).

[0264] This provides a transistor array substrate 10 according to one embodiment.

[0265] As described above, according to one embodiment, the step of disposing the electrode conductive layer ECDL including the gate electrode GE, the source electrode SE, and the drain electrode DE (S17) is included, thereby reducing the number of mask processes.

[0266] Furthermore, by including the step (S14) of providing the second semiconductor material layer 221 in a crystallized state by heat treatment, it is possible to provide the active layer ACT in a complete island shape without holes, thereby reducing the number of mask processes and preventing a decrease in the uniformity and reliability of the current characteristics of the thin film transistor.

[0267] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting.

Claims

1. substrate; an active layer disposed on the substrate, the active layer including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region; a gate insulating layer disposed over a portion of the active layer; a gate electrode comprising an electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer; a source electrode made of the electrode conductive layer and in contact with a portion of the source region; and a drain electrode made of the electrode conductive layer and in contact with a part of the drain region; The active layer is made of an oxide semiconductor in a crystalline state and is arranged in a complete island shape that does not include holes when viewed from above.

2. The thin film transistor of claim 1 , wherein the active layer has separate regions between the source electrode and the drain electrode and the gate electrode, and the separate regions are disposed as a single, unseparated portion aligned with the channel region.

3. the active layer is disposed on a buffer layer overlying the substrate; the gate electrode, the source electrode, and the drain electrode are covered with an interlayer insulating layer; 3. The thin film transistor according to claim 2, wherein the active layer has isolation regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode, the isolation regions being in contact with the interlayer insulating layer and being disposed between the interlayer insulating layer and the buffer layer.

4. 3. The thin film transistor according to claim 2, wherein at least a portion of the active layer excluding the channel region is made conductive.

5. The thin film transistor according to claim 4 , wherein the active layer has regions separated from the gate electrode and the source electrode and regions separated from the gate electrode and the drain electrode, respectively, that are made conductive.

6. The electrode conductive layer is a first metal layer disposed on the gate insulating layer and made of titanium (Ti); a second metal layer disposed on the first metal layer and made of a metal material having a resistivity lower than that of the titanium (Ti); and 2. The thin film transistor of claim 1, further comprising a third metal layer disposed on the second metal layer and made of ITO (Indium Tin Oxide).

7. a substrate including a display area in which sub-pixels are arranged and a non-display area arranged around the display area; and a circuit layer disposed on the substrate and including pixel driving units corresponding to the sub-pixels, Each of the pixel drivers includes at least one thin film transistor; One thin film transistor in the circuit layer is an active layer disposed on the substrate, the active layer including a channel region, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region; a gate insulating layer disposed over a portion of the active layer; a gate electrode comprising an electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer; a source electrode comprising the electrode conductive layer, extending to and contacting a portion of the source region of the active layer; and a drain electrode made of the electrode conductive layer, extending to the drain region of the active layer and contacting a portion of the drain region; The circuit layer comprises: a buffer layer disposed on the substrate and covering the light-shielding conductive layer; and an interlayer insulating layer disposed on the buffer layer and covering the thin film transistor; The active layer is made of an oxide semiconductor in a crystalline state, In the transistor array substrate, isolation regions of the active layer between the source electrode and the gate electrode, and isolation regions of the active layer between the source electrode and the gate electrode and isolation regions of the drain electrode and isolation regions of the active layer directly contact the interlayer insulating layer and are disposed between the interlayer insulating layer and the buffer layer.

8. The transistor array substrate of claim 7 , wherein the separation regions of the active layer between the source electrode and the drain electrode and the gate electrode are arranged as a single, unseparated portion aligned with the channel region.

9. The circuit layer comprises: a light-shielding electrode made of a light-shielding conductive layer on the substrate, overlapping at least the channel region of the active layer and covered with the buffer layer; and The transistor array substrate of claim 7 , further comprising a planarization layer disposed on the interlayer insulating layer.

10. The transistor array substrate according to claim 9 , wherein at least a portion of the active layer excluding the channel region is made conductive.

11. The transistor array substrate according to claim 10 , wherein the active layer has conductive regions between the source electrode and the gate electrode, and between the drain electrode and the gate electrode.

12. The electrode conductive layer is a first metal layer disposed on the gate insulating layer and made of titanium (Ti); a second metal layer disposed on the first metal layer and made of a metal material having a resistivity lower than that of the titanium (Ti); and The transistor array substrate according to claim 9 , further comprising a third metal layer disposed on the second metal layer and made of ITO (Indium Tin Oxide).

13. the circuit layer further includes a signal pad disposed in a portion of the non-display area; One of the signal pads is a first pad layer formed in the same layer as the light-shielding conductive layer; and The transistor array substrate according to claim 12 , further comprising a second pad layer formed of the same layer as the electrode conductive layer and electrically connected to the first pad layer.

14. a light emitting element layer disposed on the circuit layer and including light emitting elements electrically connected to each of the pixel driving units; The circuit layer comprises: a scan gate line for transmitting a scan signal to the pixel driving unit; a data line for transmitting a data signal to the pixel driving unit; and an initialization voltage line for transmitting an initialization voltage to the pixel driving unit; One of the pixel drivers is a first thin film transistor connected in series with one of the light emitting elements between a first power supply wiring and a second power supply wiring, which respectively transmit a first power supply and a second power supply for driving the light emitting element; a second thin film transistor electrically connected between the data line and the gate electrode of the first thin film transistor, and turned on according to a scan signal of the scan gate line; a pixel capacitor electrically connected to a first node between the gate electrode of the first thin film transistor and the second thin film transistor and to a second node between the first thin film transistor and the one light emitting element; and 10. The transistor array substrate of claim 9, further comprising a third thin film transistor electrically connected between the initialization voltage wiring and the second node, and turned on according to an initialization control signal of an initialization gate wiring.

15. the first power supply wiring is made of the light-shielding conductive layer, one of a source electrode and a drain electrode of the first thin film transistor is electrically connected to the first power wiring through a first electrode connection hole that penetrates the gate insulating layer and the buffer layer; 15. The transistor array substrate of claim 14, wherein the other of the source electrode and the drain electrode of the first thin film transistor is electrically connected to the light-shielding electrode through a second electrode connection hole that penetrates the gate insulating layer and the buffer layer.

16. 16. The transistor array substrate of claim 15, wherein the one light emitting element comprises an anode electrode disposed on the planarization layer and electrically connected to the first thin film transistor through an anode contact hole penetrating the planarization layer and the interlayer insulating layer.

17. the circuit layer is formed in the same layer as the active layer, and further includes a capacitor electrode electrically connected to the gate electrode of the first thin film transistor; The transistor array substrate of claim 14 , wherein the pixel capacitor is provided as an overlapping region between the capacitor electrode and the light-shielding electrode.

18. disposing a first semiconductor material layer comprising an amorphous oxide semiconductor on a substrate; performing a heat treatment on the first semiconductor material layer to provide a second semiconductor material layer in a crystal-containing state due to the heat treatment; disposing a gate insulating layer on the substrate overlying the second semiconductor material layer; partially removing the gate insulating layer and disposing a first auxiliary hole and a second auxiliary hole adjacent to both ends of the second semiconductor material layer; disposing an electrode conductive layer on the gate insulating layer; and a step of partially removing the gate insulating layer using the electrode conductive layer as a mask, and making a portion of the second semiconductor material layer conductive to provide an active layer.

19. 20. The method for manufacturing a transistor array substrate according to claim 18, wherein in the step of providing the second semiconductor material layer, the heat treatment on the first semiconductor material layer is performed at a temperature of about 300 to 450 degrees Celsius.

20. In the step of providing the active layer, the process of partially removing the gate insulating layer is performed using an etching material containing fluorine (F), an etching rate of the second semiconductor material layer with respect to the etching material containing fluorine (F) is lower than an etching rate of the first semiconductor material layer; The method for manufacturing a transistor array substrate according to claim 19 , wherein after the step of providing the active layer, the active layer is arranged in a complete island shape without any holes in a plan view.

21. The step of disposing the electrode conductive layer includes: Sequentially disposing a first metal layer including titanium (Ti), a second metal layer including a metal material having a lower resistance than the first metal layer, and a third metal layer including indium tin oxide (ITO) on the gate insulating layer; and a step of partially removing a stack of the first metal layer, the second metal layer, and the third metal layer to provide the electrode conductive layer; 21. The method for manufacturing a transistor array substrate according to claim 20, wherein the process of partially removing the stack of the first metal layer, the second metal layer, and the third metal layer is performed using an etching material containing fluorine (F).

22. In the step of arranging the first auxiliary hole and the second auxiliary hole, 22. The method for manufacturing a transistor array substrate according to claim 21, wherein after the first auxiliary hole and the second auxiliary hole are arranged, the first contact auxiliary portion and the second contact auxiliary portion of the second semiconductor material layer exposed through the first auxiliary hole and the second auxiliary hole, respectively, are made conductive by contacting with an etching material for partially removing the gate insulating layer.

23. In the step of providing the electrode conductive layer, the electrode conductive layer includes a gate electrode overlapping a central portion of the second semiconductor material layer, a source electrode overlapping one side of the second semiconductor material layer, and a drain electrode overlapping the other side of the second semiconductor material layer; the source electrode is in contact with the first contact auxiliary portion of the second semiconductor material layer through the first auxiliary hole; The method for manufacturing a transistor array substrate according to claim 22 , wherein the drain electrode contacts the second contact auxiliary portion of the second semiconductor material layer through the second auxiliary hole.

24. In the step of providing the active layer, a portion of the second semiconductor material layer other than a portion covered with the gate insulating layer is made conductive to provide the active layer; the active layer includes a channel region overlapping the gate electrode, a source region contacting one side of the channel region, and a drain region contacting the other side of the channel region; the source region includes the first contact assistant portion, The method of manufacturing a transistor array substrate according to claim 23 , wherein the drain region includes the second contact assistant.

25. The method further includes, before the step of disposing the first semiconductor material layer, disposing a buffer layer covering the light-shielding conductive layer on the substrate; After the step of providing the active layer, the method further includes the step of disposing an interlayer insulating layer covering the electrode conductive layer and the active layer; 24. The method of claim 23, wherein after the step of disposing the interlayer insulating layer, separation regions of the active layer between the source electrode and the gate electrode, and between the drain electrode and the gate electrode directly contact the interlayer insulating layer and are disposed between the interlayer insulating layer and the buffer layer.

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