Bonding Layers and Processes

Abstract

The method includes providing a first bonding surface on a first substrate, the first bonding surface including a thermally or photocurable bonding layer. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by achieving physical contact between the first and second bonding surfaces. The method further includes applying thermal energy or light to the bonding layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 426,140, ​​entitled "BONDING LAYER AND PROCESS," filed November 17, 2022, and U.S. Non-Provisional Patent Application No. 18 / 320,781, entitled "BONDING LAYER AND PROCESS," filed May 19, 2023, the entire disclosures of which are incorporated herein by reference for all purposes.

[0002] The present disclosure relates to methods of semiconductor manufacturing, and more particularly to bonding multiple semiconductor substrates. [Background technology]

[0003] Wafer-to-wafer bonding, chip-to-chip bonding, and chip-to-wafer bonding (commonly referred to as substrate bonding) are being performed to continue the power-performance-area-cost (PPAC) scaling of complex circuits such as those implemented in systems-on-chips (SOCs). Many bonding techniques, such as direct bonding and hybrid bonding, often utilize high pressure and / or high temperature to achieve reliable oxide-to-oxide bonding adhesion between substrates. Lower temperature bonding techniques with excellent adhesion are desired.

[0004] FIG. 1 illustrates several steps of a conventional process for bonding two semiconductor substrates (e.g., wafers) to form a semiconductor structure 100, although the process is well known and is abbreviated and simplified here for illustrative purposes. The semiconductor substrate 101 includes a base substrate 102 and a plurality of active devices, metallization, and other circuit features disposed within and / or on the base substrate 102. A dielectric layer 104 is formed on the base substrate 102. A conductive feature 106 may include copper (Cu). The conductive feature 106 is formed on or below a bonding surface 108 of the dielectric layer 104. The bonding surface 108 is configured to engage and bond to another bonding surface 108 disposed on a different semiconductor substrate 101 to form the semiconductor structure 100. The dielectric layer 104 may include an oxide, nitride, carbide, or the like, or a combination thereof, as is well known and described elsewhere. The conductive features 106 are often recessed below the bonding surfaces 108 to ensure that a strongly bonded dielectric-dielectric interface is formed when the two bonding surfaces are brought together before the conductive features 106 protrude and contact each other across the bonding interface 110 between them. Referring to FIG. 1A, the bonding surfaces 108 are activated using a plasma (e.g., N2 plasma and / or O2 plasma) to prepare the surfaces for bonding. Referring to FIG. 1B, hydration is often provided to further enhance the bonding ability of the bonding surfaces 108. Referring to FIG. 1C, the bonding surfaces 108 of the two semiconductor substrates 101 are aligned and contacted at the bonding interface 110. As shown in FIG. 1D, an annealing step can improve the dielectric-dielectric bond and / or cause the conductive contacts to expand toward each other and form physical and electrical contact as part of the semiconductor structure 100. One or both of the substrates can be thinned (not shown) as needed for a given application.

[0005] Existing bonding processes can be complex and expensive to implement. Forming Si-O bonds at the bonding interface (between two opposing dielectric layers) can rely on an implementation of plasma activation, as illustrated in FIG. 1A, followed by a water treatment, as illustrated in FIG. 1B. In some cases, such treatment processes suffer from queue-time lag limitations. Furthermore, the bonding interface may exhibit limited bond strength, which may be reversible using certain techniques, such as inserting a blade into the bonding interface. In some cases, bond strength may be weakened due to environmental or processing issues. The hydration step (as illustrated in FIG. 1B) can also be problematic in that it can cause oxidation of copper-based conductive features, thereby increasing resistivity. Therefore, an alternative procedure for implementing a direct or hybrid bonding process without relying on activation and hydration processes is desirable. Summary of the Invention [Means for solving the problem]

[0006] Described herein are structures and techniques that provide improved bonding (e.g., hybrid bonding) between substrates. According to one embodiment, a direct covalent bond is formed between two surfaces by either thermal activation or UV activation, with the option of omitting surface treatment (e.g., plasma activation and / or water treatment), thereby reducing queue time requirements during the manufacturing process.

[0007] In one aspect, the present disclosure provides a method including providing a first bonding surface on a first substrate, the first bonding surface including a thermally or photocurable bonding layer. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by achieving physical contact between the first and second bonding surfaces. The method further includes applying thermal energy or light to the bonding layer.

[0008] In some embodiments, the top of the conductive feature is recessed so that the bonding layer protrudes from the recessed conductive feature, and applying thermal energy causes the recessed conductive feature to expand toward the second bonding surface.

[0009] In some embodiments, the bonding layer is a first bonding layer and the second bonding surface comprises a second bonding layer that is heat curable or photocurable.

[0010] In some embodiments, applying light comprises applying UV radiation at a wavelength of about 210 nm to about 260 nm.

[0011] In some embodiments, the bonding layer is covalently bonded to the first substrate at the first bonding surface and to the second substrate at the second bonding surface by application of thermal energy or light.

[0012] In some embodiments, the bonding layer comprises a precursor molecule having a silicon-containing ring structure, hi some implementations, the bonding layer comprises disilacyclobutane (DSCB).

[0013] In some embodiments, the first substrate includes a conductive feature disposed in a dielectric layer, whereby providing the first bonding surface includes depositing a bonding layer over the first substrate, and providing the first bonding surface further includes removing a portion of the bonding layer to expose the conductive feature, such that the first bonding surface includes the conductive feature and a remaining portion of the bonding layer.

[0014] In another aspect, the present disclosure provides a method including providing a first bonding surface on a first substrate, the first bonding surface including a thermally or photocurable first bonding layer. The method includes providing a second bonding surface on a second substrate, the second bonding layer including a second bonding layer. The method includes bonding the first substrate to the second substrate by achieving physical contact between the first bonding layer and the second bonding layer. The method further includes applying thermal energy or light to the first bonding layer and the second bonding layer.

[0015] In some embodiments, the second bonding layer is heat curable or photocurable.

[0016] In some embodiments, the first bonding layer is thermosetting such that the application of thermal energy is carried out at a temperature of at least about 250°C.

[0017] In some embodiments, the first bonding layer is photocurable and the method further comprises performing an annealing process after applying the light, hi some embodiments, applying the light comprises performing UV radiation at a wavelength of about 210 nm to about 260 nm.

[0018] In some embodiments, applying thermal energy or light comprises forming a first covalent bond at a first interface between the first bonding layer and the first substrate. Applying thermal energy or light comprises forming a second covalent bond at a second interface between the second bonding layer and the second substrate. Applying thermal energy or light further comprises forming a third covalent bond at a third interface between the first bonding layer and the second bonding layer. In some embodiments, at least one of the first covalent bond, the second covalent bond, and the third covalent bond comprises a carbosilane bond.

[0019] In some embodiments, the first bonding layer comprises a precursor molecule having a silicon-containing ring structure, hi some embodiments, the silicon-containing ring structure is bonded to an aryl group.

[0020] In another aspect, the present disclosure provides a semiconductor structure including a first substrate. The semiconductor structure includes a second substrate. The semiconductor structure further includes a bonding layer bonding the first substrate to the second substrate, the bonding layer having a polymer-based material including carbosilane bonds. In some implementations, the bonding layer includes disilacyclobutane (DSCB).

[0021] According to one embodiment, a curable bonding layer (e.g., a curable bonding agent) is formed on the dielectric layer and then activated thermally or by UV exposure during or immediately prior to bonding. In some embodiments, etching and / or polishing (e.g., chemical-mechanical polishing / planarization, or CMP) steps ensure that the top surface of the conductive feature is free or substantially free of the curable bonding layer. The curable bonding layer can be thermally curable or photocurable. As an example, a curable bonding layer comprising disilacyclobutane (DSCB) can be used and cured by exposure to specific elevated temperatures and / or light, such as UV light. The curing process occurs due to the ring-opening reaction of DSCB (e.g., by homolytic cleavage of the Si-C bond in the ring structure) to form radicals, which then form a network of covalent bonds, resulting in a curable bonding layer with ceramic-like properties. The thermodynamic driving force behind the opening of the ring structure in DSCB is a significant amount of strain in such ring structure.

[0022] The use of bonding and materials according to the methods described herein offers several advantages. Utilizing a curable bonding layer in a direct or hybrid bonding process results in a bond interface with nonpolar or less polar bonds (e.g., compared to the Si-O bonds typical at a bond interface without a curable bonding layer). Bonding with a curable bonding layer relies on irreversible or difficult-to-reverse back reactions, which can preserve bonding sites at the bond interface due to back reaction loss. The use of more stable functional groups can reduce, minimize, or eliminate queue time effects. In this embodiment, plasma activation and / or water treatment prior to the bonding process can be omitted, thus saving time and cost in the overall manufacturing process.

[0023] Non-limiting embodiments of the present disclosure will now be described by way of example with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. The drawings represent aspects of the present disclosure unless otherwise indicated as representing background art. For clarity, not every element is necessarily labeled in every drawing. [Brief explanation of the drawings]

[0024] [Figures 1A-1D] 1 illustrates generally an exemplary hybrid joining process according to the prior art. [Figure 2-5] 1A-1C each illustrate a flow diagram of an exemplary method for fabricating a semiconductor structure, according to some embodiments. [Figures 6A-6E] 6A-6C each depict a cross-sectional side view of an exemplary semiconductor structure at an intermediate step of the method depicted in one or more of FIGS. 2, 3, 4, and 5, according to some embodiments. [Figures 7A-7B] 6A-6C each depict a cross-sectional side view of an exemplary semiconductor structure at an intermediate step of the method depicted in one or more of FIGS. 2, 3, 4, and 5, according to some embodiments. [Figure 8A-8B] 6A-6C each depict a cross-sectional side view of an exemplary semiconductor structure at an intermediate step of the method depicted in one or more of FIGS. 2, 3, 4, and 5, according to some embodiments. [Figure 9A-9B] 6A-6C each depict a cross-sectional side view of an exemplary semiconductor structure at an intermediate step of the method depicted in one or more of FIGS. 2, 3, 4, and 5, according to some embodiments. [Figure 10] 1 shows a schematic reaction for forming a polymer-based material from a plurality of thermosetting precursor molecules, according to some embodiments. [Figure 11] 1 shows a schematic reaction for forming a polymer-based material from a plurality of photocurable precursor molecules, according to some embodiments. [Figure 12] 12 shows a table illustrating various examples of photocurable precursor molecules that may be realized by the schematic reactions of FIG. 10 and / or FIG. 11, according to some embodiments. [Figures 13A-13C] 6A-6C each depict a cross-sectional side view of an exemplary semiconductor structure at an intermediate step of the method depicted in one or more of FIGS. 2, 3, 4, and 5, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0025] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein. It will be understood, however, that no limitation on the scope of the claims or the present disclosure is intended in this regard. Variations and further modifications to the features of the invention illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which may occur to one skilled in the art in possession of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used, or other changes may be made, without departing from the spirit or scope of the disclosure. The exemplary embodiments described in the detailed description are not intended to limit the presented subject matter.

[0026] According to one embodiment, after a first semiconductor structure (e.g., a first semiconductor substrate, a first semiconductor wafer, a first semiconductor die, etc.) is formed and processed, it is bonded to a second semiconductor structure (e.g., a second semiconductor substrate, a second semiconductor wafer, a second semiconductor die, etc.), resulting in an improved direct or hybrid bonding technique in the manufacture of semiconductor devices. Prior to bonding, the bonding surfaces of the two semiconductor structures, each containing conductive features disposed in or adjacent to a dielectric layer, are treated to form a curable bonding layer on one or both of the bonding surfaces, the curable bonding layer comprising a thermosetting (e.g., thermally crosslinkable) material (e.g., disilacyclobutane, or DSCB) or a photocurable (e.g., photocrosslinkable) material. The curable bonding layer can be formed on at least the dielectric layer of each bonding surface.

[0027] For hybrid bonds where both the conductive features and the dielectric layer are exposed at the bonding surfaces, a curable bonding layer can be selectively formed on each bonding surface or a blanket dielectric layer deposited across the entire bonding surface, then thinned to expose the conductive features using polishing or etching techniques. The bonding layer can be about 1 nm to about 10 nm thick. The bonding surfaces are brought together by physical contact and exposure to a thermal treatment (e.g., application of thermal energy or heat) or a light treatment (e.g., application of UV radiation) to cure or crosslink the bonding layer across the bonding interface between the bonding surfaces. Upon bonding, the curable material in each curable bonding layer chemically reacts with the curable material in the opposing curable bonding layer across the bonding interface. The light treatment can be performed with UV radiation having a wavelength of about 210 nm to about 260 nm. In some examples, the heat treatment can be performed at a temperature of at least about 250°C. The heat treatment can also cause the conductive features to extend across the bonding interface during the bonding process.

[0028] By using a chemically driven process for bond formation, the thermal treatment temperature can be lower than some conventional bonding techniques. The use of chemical surface treatments can be selectively formed on oxides (e.g., silicon dioxide) or other insulating materials (e.g., silicon carbonitride) in the dielectric layer to avoid interference with the metal-to-metal contacts used to interconnect conductive features. The curable bond layer after curing can have a relatively low dielectric constant, which can hinder copper diffusion near the bond interface. For example, a dielectric constant of about 2.38 to about 2.5 can be achieved, and the more non-polar nature of the carbosilane-Si-C-Si-C- bond (compared to the siloxane-Si-O-Si-O- bond) makes the bond layer less susceptible to copper diffusion.

[0029] FIG. 2 shows a flowchart of an exemplary method 10 for forming a bonding surface on a semiconductor structure according to some embodiments of the present disclosure. FIGS. 3 and 4 show flowcharts of exemplary methods 30 and 50 for implementing portions (e.g., one or more operations) of method 10 according to some embodiments of the present disclosure. FIG. 5 shows a flowchart of an exemplary method 70 for bonding or joining bonding surfaces of two semiconductor structures (e.g., two semiconductor substrates, two semiconductor wafers, two semiconductor dies, etc.) according to some embodiments of the present disclosure. Note that methods 10, 30, 50, and 70 are merely examples and are not intended to limit the present disclosure. It is further understood that additional operations may be provided before, during, and after method 10 of FIG. 2, method 30 of FIG. 3, method 50 of FIG. 4, and / or method 70 of FIG. 5, and that some other operations may only be briefly described herein.

[0030] In various embodiments, the operations of method 10 may be associated with exemplary semiconductor structure 200 at various stages of fabrication, and the operations of method 70 may be associated with exemplary semiconductor structures 300 or 600 at various stages of fabrication, as described in further detail below. It should be understood that semiconductor structures 200, 300, and 600 may include a number of other devices, such as inductors, fuses, capacitors, coils, etc., without departing from the scope of the present disclosure.

[0031] 2 and 6A, the method 10 in operation 12 provides a semiconductor structure 200 including a semiconductor substrate (eg, a base substrate) 202.

[0032] The semiconductor substrate 202 may include a semiconductor material such as a bulk semiconductor, a semiconductor-on-insulator (SOI), or the like, which may be doped or undoped (e.g., with a p-type or n-type dopant). The semiconductor substrate 202 may be or correspond to a wafer (e.g., 202 or 204), such as a silicon wafer. Generally, SOI includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The semiconductor substrate 202 may include other semiconductor materials, such as multilayer semiconductor materials or graded semiconductor materials. In some examples, the semiconductor substrate 202 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0033] The method 10 continues, in operation 14, by forming a dielectric layer (e.g., an insulating layer) 204 on or over the semiconductor substrate 202. In this embodiment, the dielectric layer 204 and the conductive features subsequently formed in the dielectric layer 204 constitute a bonding surface 214 of the semiconductor structure 200. In some embodiments, the bonding surface 214 is on the front side of the semiconductor substrate 202 (e.g., on the surface of the semiconductor structure 200 that includes the device features). Alternatively, the bonding surface 214 may be on the back side of the semiconductor substrate 202 (e.g., on the surface of the semiconductor structure 200 opposite the device features).

[0034] Dielectric layer 204 may comprise any suitable material, such as an oxide, a nitride, a carbide, or the like, or a combination thereof. Non-limiting examples include silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiCN), a low-k dielectric material (e.g., a dielectric material having a dielectric constant lower than that of silicon oxide, which is about 3.9), or the like, or a combination thereof. Dielectric layer 204 may be formed or deposited using at least one suitable deposition technique, such as chemical vapor deposition (CVD), flowable CVD (FCVD), atomic layer deposition (ALD), spin coating, or the like, or a combination thereof.

[0035] Although not shown separately for simplicity, the semiconductor structure 200 may include several device features (e.g., transistors, diodes, resistors, etc.) in and / or on the semiconductor substrate 202 and several interconnect structures (alternatively referred to as conductive features, such as vias and conductive lines) formed on the device features. Exemplary transistors may include field-effect transistors (FETs), such as finFETs (e.g., FinFETs), multi-gate FETs, nanosheet FETs, etc., or combinations thereof. The interconnect structures are configured to electrically connect the device features to one another to form integrated circuits that may function as logic devices, memory devices, input / output devices, etc. The device features may include doped or undoped semiconductor materials that may be similar in composition to the semiconductor substrate 202.

[0036] The interconnect structures may include a conductive material such as Cu, tungsten (W), nickel (Ni), aluminum (Al), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), tantalum (Ta), TiN, TaN, etc., or combinations thereof, disposed in a dielectric (e.g., insulator) material such as an oxide, nitride, carbide, etc., or combinations thereof. The device features and interconnect structures may be formed in an intervening dielectric layer (e.g., an intermetal dielectric layer, an interlevel / interlayer dielectric layer, an etch stop layer, etc.) between the semiconductor substrate 202 and a dielectric layer 204, such as a front-end-of-line (FEOL) layer or a back-end-of-line (BEOL) layer. The intervening dielectric layer may be similar in composition to the dielectric layer 204.

[0037] Still referring to Figures 2 and 6A, in operation 16, method 10 forms conductive features 206 in dielectric layer 204 for interconnection to one or more underlying conductive features (e.g., metallization layers, interconnect structures, device features, etc.).

[0038] Conductive feature 206 may comprise any suitable conductive material, including Cu, W, Ni, Al, Ru, Ag, Au, Pt, Ti, Ta, TiN, TaN, etc., or combinations thereof. In the illustrated embodiment, conductive feature 206 comprises Cu.

[0039] In some implementations, forming the conductive features 206 includes forming recesses (not shown) in the dielectric layer 204 by performing a patterning process. For example, a patterned mask layer (not shown) can be formed over the dielectric layer 204 using suitable lithography techniques, the patterned mask layer formed with openings corresponding to the locations of the recesses, and the patterned mask layer can be used as an etch mask to etch or pattern the dielectric layer 204, resulting in the recesses in the dielectric layer 204.

[0040] Subsequently, a conductive layer may be deposited as a blanket layer over the semiconductor structure 200 to fill the recesses and cover the top surface of the dielectric layer 204. The conductive layer may be deposited by any suitable deposition technique, such as CVD, ALD, PVD, plating (e.g., electroplating, electroless plating, etc.), or the like, or a combination thereof. The blanket layer and any underlying layer may then be etched (e.g., by a dry etching, reactive ion etching (RIE), or wet etching process) or polished (e.g., by a chemical mechanical polishing / planarization, or CMP process) until the top surface of the dielectric layer 204 is exposed, thereby forming a conductive feature 206 in the dielectric layer 204. The conductive feature 206 may be formed as part of a FEOL process, a middle-end-of-line (MEOL) process, or a BEOL process. For example, the conductive feature 206 may be formed as a bond pad for bonding the semiconductor structure 200 to another semiconductor structure, die, substrate, etc. as part of a package.

[0041] 2, method 10, in operation 18, forms a curable bonding layer 209 over dielectric layer 204 and conductive feature 206, resulting in bonding surface 214 on semiconductor substrate 202. As shown, and with general reference to FIGS. 3 and 6B-6E, operation 18 may be performed by method 30.

[0042] 3 and 6B , in operation 32, method 30 recesses dielectric layer 204 to expose the tops of conductive features 206, including their sidewalls, thereby causing conductive features 206 to protrude from the top surface of recessed dielectric layer 204. Dielectric layer 204 can be recessed by any suitable method. In one example, dielectric layer 204 can be etched back using a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In another example, a sacrificial layer can be formed over dielectric layer 204 (e.g., in operation 14) before forming conductive features 206, and then selectively removed (e.g., in operation 16) after forming conductive features 206, thereby exposing the tops of the conductive features. In yet another example, to accommodate the formation of a thin layer of curable bonding layer 209, conductive features 206 can be flush with or slightly recessed from the top surface of dielectric layer 204. In this regard, operation 32 can be omitted.

[0043] As shown in FIGS. 3 and 6C, the method 30, in operation 34, deposits a curable bonding layer 209 over the recessed dielectric layer 204 and the conductive features 206.

[0044] In this embodiment, the curable bonding layer (e.g., curable adhesive) 209 comprises a polymer-based material that can be cured by the application of external energy. For example, the curable bonding layer 209 comprises a thermosetting material, a photocurable material, or a combination thereof. A thermosetting material can be cured or crosslinked when subjected to a heat or heat treatment at a sufficiently high temperature. A photocurable material can be cured or crosslinked when exposed to a light or radiation treatment. In some embodiments, a thermosetting material can be cured at a temperature of at least about 250°C. In some examples, the temperature at which activation of the curing or crosslinking reaction (e.g., ring-opening reaction) occurs does not exceed about 400°C. In some embodiments, a photocurable material can be cured by the application of UV radiation at a wavelength of about 210 nm to about 260 nm. In some embodiments, the polymer-based material of the curable bonding layer 209 can be configured to cure or crosslink in response to both thermal energy and light.

[0045] 10 and 11, a polymeric material is formed from precursor molecules each having a ring structure that exhibits strain energy that causes the ring structure to open during a subsequent curing or crosslinking reaction. In this embodiment, the ring structure includes one or more silicon (Si) atoms and one or more functional groups, such as R1, R2, R3, and R4 shown, as side chains attached to one or more of the silicon atoms.

[0046] 10 , a schematic reaction 400 is shown illustrating the curing or crosslinking of precursor molecules 402 to form a polymer-based material 404 via thermal treatment 403. In this embodiment, precursor molecules 402 are thermosetting and include a DSCB-based ring structure with a strain energy of approximately 72.2 kJ / mol, which, once overcome, activates a ring-opening reaction. As a non-limiting example, precursor molecule 402 has a four-membered ring structure containing two Si atoms, each bonded to functional groups R1 and R2. Precursor molecule 402 may include fewer or more suitable functional groups similar to functional groups R1 and R2.

[0047] In some embodiments, the thermal treatment 403 includes a ring-opening reaction and a polymerization (e.g., curing or crosslinking) reaction, which occurs when the precursor molecules 402 are heated to at least about 250° C. The ring-opening reaction may cause homolytic cleavage of Si—C bonds in the precursor molecules 402, which then release free radicals to react with other free radicals and polymerize into the polymeric material 404. The ring-opening reaction typically occurs at elevated temperatures, but can occur at temperatures as low as room temperature (e.g., about 25° C.) using various transition metal complex catalysts 405 (e.g., Pt, Pd, Cu, etc.).

[0048] As shown in FIG. 10 , the polymer-based material 404 includes a plurality of monomers 406 bonded together, where the subscript “n” can be any suitable number greater than two (e.g., n>2). The polymer-based material 404 includes at least two carbosilane (—Si—C—Si—C—) bonds linked together (e.g., forming a polycarbosilane), which can exhibit ceramic-like properties compared to siloxane (—Si—O—Si—O—) bonds typically found at the bonded interface between SiO 2 -based dielectric layers, such as untreated dielectric layer 204. Furthermore, the carbosilane bonds can exhibit reduced polarity (e.g., non-polar). In some examples, the polymer-based material 404 can be a hydrophobic material with good thermal stability, a relatively low dielectric constant (e.g., a low dielectric constant of about 2.3 to about 2.4, less than that of silicon dioxide), a relatively high modulus of elasticity (e.g., about 7.8 GPa to about 9.15 GPa), and resistance to copper diffusion. In some embodiments, the precursor molecules 402 are thermally stable at temperatures above about 400° C. In some embodiments, the precursor molecules 402 are thermally stable at room temperature, as defined herein.

[0049] In some implementations, the curable bonding layer 209 is deposited as a blanket layer over the dielectric layer 204 and the conductive feature 206, thereby completely covering the exposed top of the conductive feature 206. The curable bonding layer 209 may be deposited by any suitable method, such as spin coating, to form a thickness sufficient to cover the top surface of the conductive feature 206, as shown in FIG.

[0050] 3 and 6D , in operation 36, method 30 removes a portion of curable bonding layer 209 to expose a top surface of conductive feature 206, thereby leaving a remaining portion of curable bonding layer 209 adjacent to conductive feature 206 and overlying dielectric layer 204. In some implementations, the remaining portion of curable bonding layer 209 is substantially coplanar with conductive feature 206.

[0051] In some embodiments, portions of curable bonding layer 209 are removed by applying a CMP process to planarize the top surfaces of conductive features 206 with the top surface of curable bonding layer 209. In some embodiments, portions of curable bonding layer 209 are removed by a suitable etching process (e.g., a dry etching process, a wet etching process, etc.) to expose the top surfaces of conductive features 206.

[0052] 3 and 6E, method 30, in operation 38, recesses conductive feature 206 such that curable bonding layer 209 protrudes from an upper surface of recessed conductive feature 206, providing bonding surface 214 on semiconductor substrate 202. Conductive feature 206 may be selectively recessed by a suitable etching process (e.g., a dry etching process, a wet etching process, etc.). In some examples, conductive feature 206 may be recessed by about 1 nm to about 5 nm. In some implementations, recessed conductive feature 206 has an upper surface that is above the upper surface of dielectric layer 204 but below the upper surface of curable bonding layer 209. In some implementations, recessing conductive feature 206 creates a space above conductive feature 206 to allow its expansion across the bonding interface during subsequent thermal and / or annealing processes.

[0053] In some embodiments, and referring generally to FIGS. 4, 7A, and 7B, operation 18 may be implemented by method 50 to form interface 216 similar to interface 214.

[0054] After forming conductive feature 206 (see FIG. 7A , which is similar to FIG. 6A ), method 50, in operation 52, selectively deposits curable bonding layer 209 on dielectric layer 204 to expose a top surface of conductive feature 206, resulting in bonding surface 216, as shown in FIG. 7B . In some implementations, the top surface of conductive feature 206 is below the top surface of curable bonding layer 209. In some implementations, selectively depositing curable bonding layer 209 on dielectric layer 204 includes functionalizing dielectric layer 204 but not conductive feature 206, and selectively bonding curable bonding layer 209 to functionalized dielectric layer 204. The composition of the functionalization may depend on the composition of curable bonding layer 209 and is not limited by the present disclosure.

[0055] 4, method 50 may further recess conductive feature 206 in operation 54 such that the top surface of conductive feature 206 is about 1 nm to about 5 nm below the top surface of curable bonding layer 209. In some embodiments, operation 54 is omitted.

[0056] 5 and 8A-9B, method 70 provides an exemplary process for bonding or joining one bonding surface of a semiconductor structure to another bonding surface of another semiconductor structure. In the illustrated embodiment, FIGS. 8A and 8B correspond to an example of method 70 applied to bonding two bonding surfaces 214, and FIGS. 9A and 9B correspond to an example of method 70 applied to bonding two bonding surfaces 216.

[0057] 5, 8A, and 9A, method 70, in operation 72, provides two semiconductor structures 200, at least one of which includes a bonding surface 214 / 216 formed according to methods 10, 30, and / or 50 described herein. For example, each bonding surface 214 / 216 includes a curable bonding layer 209 on a dielectric layer 204 and a conductive feature 206 disposed within the dielectric layer 204. In some embodiments, the curable bonding layers 209 of opposing bonding surfaces 214 / 216 can include precursor molecules 402 / 408 of the same or different compositions.

[0058] 5, 8A, and 9A, method 70, in operation 74, aligns and bonds two opposing bonding surfaces 214 / 216 of corresponding semiconductor structures 200 to achieve direct physical contact therebetween, resulting in semiconductor structure (e.g., bonded structure) 300. In this embodiment, the direct physical contact establishes a bonding interface 302 / 304 between the opposing bonding surfaces 214 / 216. In some embodiments, one of semiconductor structures 200 is first flipped or inverted (e.g., rotated 180 degrees) so that during the alignment process, the two bonding surfaces 214 / 216 are positioned opposite each other and bonded in a face-to-face configuration.

[0059] The bonding surfaces 214 / 216 may be bonded by any suitable process, such as a hybrid bonding process. In this regard, the bonding process may be performed by aligning similar features of the opposing bonding surfaces 214 / 216 with one another, such that metal-to-metal contact may be formed across the bonding interface 302 / 304 between the conductive features 206 and dielectric-to-dielectric contact may be formed across the bonding interface 302 / 304 between the dielectric layers 204.

[0060] 8A-9B each show two identical but opposing bonding surfaces, it should be noted that the present disclosure does not require such a configuration. In one example, one of the bonding surfaces may include bonding surface 214, and the other of the bonding surfaces may include bonding surface 216. In another example, one of the bonding surfaces may include either bonding surface 214 or bonding surface 216, and the other of the bonding surfaces may include features and functionality that differ from the features and functionality of bonding surfaces 214 and 216. For example, one of the bonding surfaces may not include a curable bonding layer 209, such that the curable bonding layer 209 of the other of the bonding surfaces is in direct physical contact with the dielectric layer 204 of the other of the bonding surfaces (e.g., without any curable bonding layer 209).

[0061] 1A and 1B , the bonding process described in method 70 does not include any surface treatment processes, such as a plasma treatment to activate bonding surfaces 214 / 216 and a hydration process to enhance the bonding ability of bonding surfaces 214 / 216. As described in detail below, method 70 directly proceeds to apply a heat treatment (e.g., an annealing process) or a light treatment (e.g., a UV treatment) to the bonded bonding surfaces 214 / 216, thereby curing or crosslinking the curable bonding layer 209 on one of the bonded bonding surfaces 214 / 216 to form an irreversible or difficult-to-reverse covalent bond with the curable bonding layer 209 (or dielectric layer 204) on the other of the bonded bonding surfaces 214 / 216. In some instances, the irreversible covalent bond may preserve bonding sites at the bonding interface 302 / 304 due to back-reaction loss.

[0062] Among other things, eliminating the surface treatment process prior to aligning and contacting the mating surfaces 214 / 216 reduces the number of modules (e.g., operations) performed in the bonding platform (e.g., reducing processing complexity, time, and / or cost) and reduces queue time requirements for manufacturing. In existing implementations, the surface treatment process typically results in a reversible bond between the mating surfaces, which can be relatively unstable and result in processing constraints. Such processing constraints may include a reduction in the processing time allowed between the surface treatment process and the subsequent bonding process, thereby imposing stricter queue time requirements. In contrast, curing or crosslinking of the curable bonding layer 209 results in an irreversible covalent bond with improved bond strength across the bond interface 302 / 304, thereby mitigating queue time requirements that would otherwise exist for mating surfaces that have undergone surface treatment. Additionally, incorporating the curable bonding layer 209 into the bonding surfaces 214 / 216 allows more stable functional groups to participate in the bonding process, improving properties of the semiconductor structure 300 including, for example, resistance to metal (e.g., Cu) diffusion, thermal stability at high temperatures, lower dielectric constant, hydrophobicity, mechanical strength (e.g., Young's modulus), and / or the like.

[0063] 5, 8B, and 9B, the method 70, in operation 76a, performs a thermal treatment (e.g., an annealing process) 80 to cure the opposing curable bonding layers 209 across the bonding interfaces 302 / 304, thereby fusing the semiconductor structures 200 together. The thermal treatment 80 is performed by applying thermal energy to the semiconductor structures 300. In this embodiment, the thermal energy cures or crosslinks the precursor molecules 402 to form a polymer-based material 404 in the curable bonding layers 209 according to the general reaction 400 described above with reference to FIG. 10. As a result, the curable bonding layer 209 of one of the bonding surfaces 214 / 216 is covalently bonded to both the underlying dielectric layer 204 of the same bonding surface 214 / 216 and the curable bonding layer 209 of the opposing bonding surface 214 / 216.

[0064] Additionally, the thermal energy causes opposing conductive features 206 to expand across bond interface 302 / 304, thereby forming metal-to-metal contact. In this regard, the temperature of heat treatment 80 is configured to be at least as high as the temperatures suitable for heat treatment 403 described above. For example, heat treatment 80 may be performed at a temperature of at least about 250°C. In some embodiments, heat treatment 80 is applied at a temperature between about 200°C and about 400°C (e.g., about 350°C).

[0065] 13A-13C collectively illustrate an alternative embodiment of the method 70 shown in FIG. 5 during which a light (or UV) treatment 82 is applied rather than a heat treatment 80. In the present disclosure, FIG. 13A corresponds to FIGS. 8A and 9A and thus illustrates an embodiment similar to the embodiment associated with FIGS. 8A and 9A described in detail above.

[0066] 13A , method 70, in operation 72, provides two semiconductor structures 200, at least one of which includes a bonding surface 218. In this embodiment, bonding surface 218 includes conductive features 206 in dielectric layer 204 and a curable bonding layer 210 on dielectric layer 204, where curable bonding layer 210 includes precursor molecules 408 that are different from precursor molecules 402.

[0067] 11 illustrates schematic reaction 450, which is similar to schematic reaction 400, except that schematic reaction 450 is activated by light (e.g., UV) treatment 409. As shown, schematic reaction 450 begins with precursor molecule 402, which is similar to precursor molecule 408. Precursor molecule 408 is a light-curable molecule and includes a Si-containing four-membered ring structure, with each Si atom in the ring structure bonded to functional groups R3 and R4. In some embodiments, if one or both of functional groups R3 and R4 include an aryl group (e.g., an aromatic group), precursor molecule 408 may undergo a ring-opening reaction when activated by light treatment 409. In some examples, the aryl group may include a benzene ring. Precursor molecule 408 may include fewer or more suitable functional groups similar to functional groups R3 and R4.

[0068] In some embodiments, light treatment 409 further polymerizes activated precursor molecules 408 to form a polymeric material 412 having multiple (e.g., n>2) monomers 410 as shown. The polymeric material 412 includes two or more carbosilane (—Si—C—Si—C—) bonds linked together (e.g., forming polycarbosilane), which can exhibit less polar and ceramic-like properties similar to those of polymeric material 404.

[0069] 12, column 502 of table 500 provides non-limiting exemplary precursor molecules 408, each having an aryl group (e.g., a benzene ring) 503 attached to a four-membered ring structure containing a Si atom. Column 504 lists the wavelengths corresponding to each of the exemplary precursor molecules 408 in column 502, and column 506 provides the molar extinction coefficient (e.g., molar absorptivity), E, ​​corresponding to each of the exemplary precursor molecules 408. In some examples, the molar extinction coefficient, E, reflects the efficiency of the ring-opening reaction described above with respect to schematic reaction 450 of FIG. 11.

[0070] Curable bonding layer 210 and bonding surface 218 may be formed by a series of operations similar to those of methods 10, 30, and / or 50 described herein. Thus, in this embodiment, curable bonding layer 210 includes precursor molecules 408 that are configured to subsequently be cured or crosslinked according to general reaction 450 to form polymer-based material 412 in the cured bonding layer.

[0071] Continuing, and still referring to FIG. 13A, method 70, in operation 74, aligns and bonds two opposing bonding surfaces 218 of corresponding semiconductor structures 200 to achieve direct physical contact at bonding interface 602, resulting in semiconductor structure (e.g., bonded structure) 600.

[0072] 13B, in operation 76b, method 70 performs a light treatment (e.g., light treatment, UV treatment) 82 to activate and subsequently cure precursor molecules 408 of the bonded curable bonding layer 209 according to general reaction 450 described above. In this regard, light treatment 82 may be similar to light treatment 409 described herein. In some embodiments, light treatment 82 is performed by applying light, such as UV radiation, to bonding surface 218 at a shallow angle. In some examples, bonding surface 218 is exposed to UV radiation having a wavelength of about 210 nm to about 260 nm. Referring to FIG. 11, the applied radiation activates a ring-opening reaction of precursor molecules 408, subsequently curing or crosslinking activated precursor molecules 408 to form polymer-based material 412 in curable bonding layer 209. As a result, the curable bonding layer 209 on one of the bonding surfaces 218 is covalently bonded across the bonding interface 602 to both the dielectric layer 204 underlying the same bonding surface 218 and the curable bonding layer 209 on the opposing bonding surface 218.

[0073] In this embodiment, the resulting bond interface 602 is similar in structure and properties to bond interface 302 / 304 as described in detail above. For example, bond interface 602 may include irreversible covalent bonds with lower polarity and improved properties, including resistance to metal (e.g., Cu) diffusion, thermal stability at high temperatures, a relatively low dielectric constant, hydrophobicity, mechanical strength (e.g., Young's modulus), and / or the like.

[0074] 13C , method 70 completes the hybrid bonding process in operation 78 by performing a heat treatment 84 to establish metal-to-metal contact between opposing conductive features 206. In this embodiment, heat treatment 84 provides thermal energy at a temperature suitable to expand the conductive features 206 on the opposing faying surfaces 218 across the bond interface 602, thereby completing the hybrid bonding process. In this regard, heat treatment may be performed at a temperature similar to that of heat treatment 80, which is at least about 250°C. In some embodiments, heat treatment 84 is applied at a temperature between about 200°C and about 400°C (e.g., about 350°C). In some embodiments, light treatment 82 is applied immediately before or simultaneously with heat treatment 84 to avoid premature quenching of activated precursor molecules 408 before the hybrid bonding process is complete.

[0075] In some embodiments, curable bonding layer 210 includes precursor molecules 402 in addition to precursor molecules 408 such that curable bonding layer 210 can be cured or crosslinked by both a thermal treatment (e.g., thermal treatment 80) and a light treatment (e.g., light treatment 82), simultaneously or sequentially, in accordance with the operations of method 70 described herein.

[0076] In the foregoing description, specific details have been set forth, such as the particular configuration of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology described herein can be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional structure are designated by like reference numerals, and any redundant description may be omitted.

[0077] To facilitate understanding of various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described above may be performed in a different order than in the embodiments described above. Various additional operations may be performed and / or operations described above may be omitted in additional embodiments.

[0078] As used herein, "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor device or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer, a reticle, or a layer on or overlying the base substrate structure, e.g., a thin film. Thus, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. While particular types of substrates may be referenced herein, this is for illustrative purposes only.

[0079] Those skilled in the art will also appreciate that many variations are possible in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to fall within the scope of the present disclosure. Thus, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are presented in the following claims.

Claims

1. providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is heat-curable or photo-curable; providing a second bonding surface on a second substrate; bonding the first substrate to the second substrate by making physical contact between the first bonding surface and the second bonding surface; applying thermal energy or light to the bonding layer; A method comprising:

2. The method of claim 1 , wherein the bonding layer is a first bonding layer and the second bonding surface comprises a second bonding layer that is heat-curable or photo-curable.

3. The method of claim 1 , wherein applying the light comprises providing UV radiation at a wavelength of 210 nm to 260 nm.

4. The method of claim 1 , wherein the step of applying thermal energy comprises heating the bonding layer to a temperature of at least 250° C.

5. 2. The method of claim 1, wherein in the step of applying thermal energy or light, the bonding layer is covalently bonded to the first substrate at the first bonding surface and to the second substrate at the second bonding surface, respectively.

6. The method of claim 1 , wherein the bonding layer comprises precursor molecules having silicon-containing ring structures.

7. The method of claim 6 , wherein the bonding layer comprises disilacyclobutane (DSCB).

8. the first substrate includes a conductive feature disposed in a dielectric layer; The step of providing a first joining surface includes: depositing a bonding layer over the first substrate; removing a portion of the bonding layer to expose the conductive feature, such that the first bonding surface includes the conductive feature and a remaining portion of the bonding layer; 2. The method of claim 1, comprising:

9. further comprising the step of forming a recessed top portion of the conductive feature and causing the bonding layer to protrude from the recessed conductive feature; The method of claim 8 , wherein the step of applying thermal energy expands the recessed conductive feature toward the second bonding surface.

10. providing a first bonding surface on a first substrate, the first bonding surface including a first bonding layer that is heat-curable or photo-curable; providing a second bonding surface on a second substrate, the second bonding surface including a second bonding layer; bonding the first substrate to the second substrate by establishing physical contact between the first bonding layer and the second bonding layer; applying thermal energy or light to the first bonding layer and the second bonding layer; A method comprising:

11. The method of claim 10 , wherein the second bonding layer is heat-curable or photo-curable.

12. The method of claim 10 , wherein the first bonding layer is thermosetting and the step of applying thermal energy is carried out at a temperature of at least 250° C.

13. the first bonding layer is photocurable; The method of claim 10 , further comprising the step of performing an annealing process after the step of applying light.

14. 14. The method of claim 13, wherein applying the light comprises providing UV radiation at a wavelength of 210 nm to 260 nm.

15. The step of applying thermal energy or light includes: forming a first covalent bond at a first interface between the first bonding layer and the first substrate; forming a second covalent bond at a second interface between the second bonding layer and the second substrate; forming a third covalent bond at a third interface between the first bonding layer and the second bonding layer; 11. The method of claim 10, comprising:

16. 16. The method of claim 15, wherein at least one of the first covalent bond, the second covalent bond, and the third covalent bond comprises a carbosilane bond.

17. The method of claim 10 , wherein the first bonding layer comprises precursor molecules having silicon-containing ring structures.

18. 18. The method of claim 17, wherein the silicon-containing ring structure is bonded to an aryl group.

19. a first substrate; a second substrate; a bonding layer that bonds the first substrate to the second substrate, the bonding layer including a polymer-based material that includes a carbosilane bond; 1. A semiconductor structure comprising:

20. 20. The semiconductor structure of claim 19, wherein the bonding layer comprises disilacyclobutane (DSCB).

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