METHOD FOR OPERATION OF INFORMATION TECHNOLOGY SYSTEM, ... AND VEHICLE

Abstract

The present invention relates to a method for operating an information technology system, in which a program code usable by a processor for processing at least one task (1.1, 1.2) is divided by a compiler into at least two functional blocks (2) during a compilation step, which are arranged in a data flow graph (3), and the compiler analyzes the data flow graph (3) to determine the execution order of each functional block (2) by the processor. The method according to the present invention is characterized in that, when processing the at least one task (1.1, 1.2), the compiler identifies functional blocks (2) that can be executed in parallel by the processor, checks for each group (4) of functional blocks (2) that can be executed in parallel whether at least program code portions of at least two functional blocks (2) require the execution of the same instruction (5) by the processor, and assigns these program code portions to the same execution unit of the processor for simultaneous processing according to a single instruction, multiple data approach.

Description

[Technical Field]

[0001] The present invention relates to a method for operating an information technology system of the kind defined in the preamble of claim 1, to a corresponding information technology system, and to a vehicle equipped with such an information technology system. [Background technology]

[0002] Information technology systems such as computers, embedded systems, or similar computing devices are now an integral part of everyday life, solving a wide variety of problems. In this case, the development goal is to miniaturize and at the same time increase the performance of hardware components, which makes it possible to solve complex tasks, even in the context of automotive applications.

[0003] For example, with the advancement of digitalization, the importance of computer systems in vehicles is also increasing. Modern vehicles are equipped with various control devices, for example, for powertrain control, navigation route calculation, or vehicle-to-Internet communication. In this case, high-performance hardware components are essential to maintain the user experience by processing user inputs and outputting corresponding responses quickly enough, for example, to calculate time-sensitive control signals quickly enough. Furthermore, vehicles have limited mounting space for integrating computing components. In addition, the integration of such computing devices must not significantly increase the manufacturing costs of the vehicle. These factors make the development of computer systems in the automotive field particularly challenging. In short, there is a need to constantly improve the performance and efficiency of computing components.

[0004] A well-known approach to accelerating computer-aided problem solving is parallelism: modern processors are equipped with multiple execution units, e.g., arithmetic cores, which allows so-called multithreading, i.e. different tasks to be processed simultaneously by one and the same processor.

[0005] Another method for improving computational efficiency is the Single Instruction, Multiple Data (SIMD) approach. SIMD allows a computer system to apply the same computational operation to multiple data points simultaneously. For example, in a PC, this reduces the number of required write and read accesses to main memory and the number of computations performed by the processor (CPU). This can correspondingly reduce the time a program needs to solve a task. For example, D. Nuzman et al., "Vapor SIMD: Auto-vectorize once, run everywhere," International Symposium on Code Generation and Optimization (CGO 2011), 2011, pp. 151-160, doi:10.1109 / CGO.2011.5764683, describes how a compiler can transform loops to code multiple iterations of the same loop in parallel using SIMD instructions.

[0006] Furthermore, WO 2007 / 113369 discloses a method for generating a parallel executable program. This method describes compiling a computer program from source code into executable code, generating a data flow graph from the corresponding source code, and checking this data flow graph for data dependencies. The executable program thus generated is then distributed into individual packages, which are then distributed to the individual execution units of the processor of the currently used computing device. The execution order is then determined as late as possible to accommodate the computing architecture of the currently used computing device. This allows for particularly efficient load distribution to the individual execution units of the processor, regardless of the variety of computing devices available for program execution. Again, the increase in processing speed is based on distributing individual program parts to multiple execution units of one or more processors and parallelizing the program sequence. Summary of the Invention [Problem to be solved by the invention]

[0007] The object of the present invention is to provide an improved method for operating an information technology system, by means of which the performance of the information technology system is further improved. [Means for solving the problem]

[0008] According to the invention, this object is achieved by a method for operating an information technology system having the features of claim 1. Advantageous configurations and developments, as well as corresponding information technology systems suitable for carrying out the method according to the invention and vehicles equipped with such information technology systems, become apparent from the claims dependent on claim 1.

[0009] A standard operating method for an information technology system is that, in a compilation step, a compiler divides program code usable by a processor to process at least one task into at least two functional blocks, which are arranged in a data flow graph, and the compiler analyzes the data flow graph to determine the order in which the processor will execute each functional block. This standard operating method is further improved in the present invention, in that the compiler identifies functional blocks that can be executed in parallel when the processor processes the at least one task, and for each group of functional blocks that can be executed in parallel, checks whether at least program code portions of at least two functional blocks require the processor to execute the same instruction, and assigns these program code portions to the same execution unit of the processor for simultaneous processing according to a single instruction, multiple data approach.

[0010] By using the method according to the present invention, the degree of parallelism of a program can be further increased. For example, not only can different programs be processed simultaneously by a processor with multiple execution units, but a single and identical execution unit of the processor can also process different parts of the same program simultaneously in one calculation cycle. By simultaneously executing partial functions of one and the same task, cycle time in the processor can be saved, which allows the underlying tasks to be solved more quickly, i.e., the corresponding programs to be processed faster.

[0011] Here, a processor may have multiple execution units, e.g., processor cores, but not necessarily multiple physical execution units. The processor may also be implemented to execute multiple threads. The processor may be a central processing unit, better known as a central processing unit (CPU), a graphics processor, better known as a graphics processing unit (GPU), or other dedicated programmable computing device, for example, embedded on a system-on-chip (SoC).

[0012] To identify function blocks that can be executed in parallel, the compiler checks the interdependencies of individual function blocks in the data flow graph. Function blocks typically have input and output interfaces. The input interfaces provide the function blocks with the data they require, and the output interfaces provide the results generated by each function block. If one function block requires a specific result from another function block, or if a function block passes a calculation result to another function block, these function blocks cannot be executed in parallel. However, if two function blocks are not dependent on each other with respect to their respective input and output data, these function blocks can generally be executed in parallel.

[0013] A particularly efficient application of the method according to the invention is possible in function blocks containing loops if these function blocks or each loop has the same depth and, particularly preferably, the same upper limit.

[0014] In an advantageous development of the method, the compiler determines the number of instructions to be processed by the processor for each functional block executable in parallel and, for each group of functional blocks executable in parallel, incorporates a placeholder instruction into each functional block that contains fewer instructions than the functional block with the largest number of instructions in the respective group, so that all functional blocks in the respective group contain the same number of instructions. If the functional blocks of a group of functional blocks executable in parallel contain the same number of instructions to be executed by the processor, it is particularly simple and efficient to allocate program code portions to the same execution unit of the processor according to the single-instruction, multiple-data principle. By instruction in this context, we mean that the same instruction is present in all functional blocks included in the group of functional blocks executable in parallel. For example, this instruction can be an "add" or "multiply" command. If individual program code portions deviate from this instruction or are missing, for example, if a "multiply" instruction is used instead of "add" or if a command line is completely missing, it is necessary to insert a spaceholder instruction at the corresponding position in each functional block in order to be able to allocate the program code portions according to the single-instruction, multiple-data principle.

[0015] Furthermore, in a further advantageous embodiment of the method according to the invention, if a program code portion contained in a function block within a group of function blocks that can be executed in parallel comprises a loop, the following processing is further performed. - The compiler determines the number of iterations for each loop, - The compiler checks whether loops in a functional block containing program code portions that can be assigned to the same execution unit of a processor according to the single instruction, multiple data method have different iteration counts. If this is the case, then: The compiler causes the program code portions of each of the functional blocks to be processed simultaneously by the same execution unit of the processor according to the number of iterations with the smallest number, and causes the program code portions of the functional blocks with a larger number of iterations to be processed sequentially by the processor according to the remaining iterations.

[0016] The method according to the present invention is particularly simple and efficient when program code portions assigned to the same execution units of a processor according to the single-instruction, multiple-data approach consist only of instructions of the same type. However, the corresponding program code portions of functional blocks may also contain loops. In this case, if the loops corresponding to multiple functional blocks have different iteration counts, only program code portions consisting of identical instructions in functional blocks of a group of functional blocks executable in parallel can be parallelized according to the single-instruction, multiple-data approach, according to the iteration count of the loop with the fewest iteration count. In other words, for program code portions of functional blocks with a large number of iterations, the corresponding instructions from the remaining functional blocks cannot be used for simultaneous distribution to the execution units of the processor. Therefore, the corresponding excess portions are processed sequentially by the processor.

[0017] Preferably, in the case of a multithreaded processor, at least two different tasks are processed in parallel on at least two different execution units of the processor, thereby further increasing the degree of parallelism. It is also conceivable that the inventive method for allocating program code portions according to the single instruction, multiple data principle can be used for each task on each execution unit of the processor separately. This means that multiple tasks can be processed simultaneously on multiple execution units, with parallelization being achieved on each individual execution unit according to the inventive method.

[0018] According to the invention, an information technology system is provided for carrying out the above-mentioned method. This information technology system may be a known computing device such as a PC, an embedded system, an SoC, etc. The method according to the invention can be particularly advantageously applied in the context of embedded systems, since they are equipped with relatively low-performance hardware components and therefore require the use of other measures to improve computing efficiency.

[0019] Such an information technology system is particularly preferably integrated into a vehicle according to the present invention. The vehicle may be any vehicle, such as a passenger car, truck, transporter, bus, etc. The information technology system may form a central on-board computer, a control device for a vehicle subsystem, etc. A plurality of such information technology systems may also be integrated into a vehicle. As already mentioned at the beginning, there are limitations to integrating high-performance computing components into a vehicle. By using the method according to the present invention and integrating such an information technology system according to the present invention, the computing efficiency of the computing device installed in the vehicle is increased, thereby improving its performance. In this way, existing installation space can be utilized in a space-saving manner, ensuring low-cost vehicle production.

[0020] Further advantageous embodiments of the method for operating an information technology system according to the invention are evident from the examples which are explained in detail below with reference to the figures. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a diagram showing program code divided into individual functional blocks as a data flow graph. [Figure 2] 2 shows pseudocode for functional blocks C and D shown in FIG. 1 and the allocation of instructions contained in the pseudocode to the same execution unit of a processor according to a method according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0022] Figure 1 shows that, in an abstracted diagram (dataflow graph 3), program code executed on an information technology system to solve one or more tasks 1.1, 1.2 is divided into individual function blocks 2. Each function block 2 corresponds to a subproblem of each task 1.1, 1.2, which can be computed independently. The processor of this information technology system can be configured for multithreaded execution, allowing for parallel processing of multiple tasks 1.1, 1.2, i.e., multiple execution threads. These execution threads can have the same or different execution frequencies. Each task 1.1, 1.2 is then assigned to a separate execution unit of the processor, i.e., a separate computing core. This is the first possibility for parallelization of the program. For clarity, only some of the same types of reference objects are labeled in each diagram.

[0023] Each function block 2 has an input interface 2.E for reading input data and an output interface 2.A for outputting the calculation result. Taking into account the corresponding data dependencies, the execution order of the function blocks 2 can be derived. In information technology systems known from the prior art, the individual function blocks 2 of each task 1.1 and 1.2 are each executed sequentially. However, this wastes computational capacity, since usually the individual function blocks 2, or even the program code portions contained in each function block 2, can also be executed in parallel.

[0024] To further improve the efficiency of the computation, a method according to the present invention is used, which allows instructions in the individual functional blocks 2, including the instruction 5 shown in detail in FIG. 2, to be distributed among the processors, so that parts of a single task 1.1 can also be parallelized. In this case, the method according to the present invention assigns the same instructions 5 from the functional blocks 2 that can be executed in parallel to the same execution unit of the processor in accordance with the Single Instruction, Multiple Data (SIMD) method. Thus, in one computation cycle, the same instructions are applied to different register fields of the same register. "Homogenous" here means that the instructions are of the same type, for example, if all the lines of code to be parallelized contain an "add" command, which is a basic prerequisite for the SIMD method.

[0025] Additionally, in the method according to the present invention, a corresponding compiler analyzes the data flow graph 3 shown in Fig. 1 and determines the execution order of each function block 2. Function blocks 2 can be executed in parallel if there is no dependency between the data exchanged via the input interface 2.E and the output interface 2.A. This is true, for example, for function blocks C and D, and C and B in Fig. 1. Furthermore, function blocks A and H can also be parallelized. Function blocks E and F, as well as function blocks M, N, O, and Q of task 1.2, cannot be parallelized due to their dependency.

[0026] In the following, it is assumed that function blocks C and D are executable in parallel, which form a group 4 of parallel executable function blocks 2 shown in Figure 2. Depending on the complexity of the program code, such group 4 may include three, four, or more parallel executable function blocks 2.

[0027] 2 shows, in an abstract manner as pseudocode, a program code portion including the function blocks C and D. Depending on the specifications of the information technology system and the problem to be solved, all commonly conceivable programming languages ​​can be used to implement the method according to the invention.

[0028] The command "Mov" represents the movement of data from one register to another or from memory to a register. Accordingly, register r0 is assigned the value 42 or 30.

[0029] ":Loop" indicates the beginning of the loop, and "Bnz loop" indicates the end of the loop, assuming that r0=0 has been reached.

[0030] The commands "Mov" and "Add" are instructions 5 executed by a processor in an information technology system. Instead of addition, multiplication or a similar operation can be requested. The command "Add r1,[r2],+r0" indicates, for example, that the sum of the contents of register r2 and the value of r0 is to be assigned to register r1. The loop shown in function block C then counts backward from 42 to 0. This backward counting operation is performed by the code line "Add r0,r0,-1".

[0031] The two lines of code "Add r1,[r2],+r0" in functional block C and "Add r1,[r2],0" in functional block D correspond to the same instruction 5 for the processor and access the same register area. Therefore, they are suitable for applying the allocation of instruction 5 to the same execution unit of a processor of an information technology system according to the method of the present invention, in accordance with the single instruction multiple data method.

[0032] However, the loops contained in functional blocks C and D have different iteration counts and different numbers of instructions 5. To deal with this situation, a so-called spaceholder instruction 6 is first inserted into functional block C. This results in functional blocks C and D having the same number of instructions 5. For example, using the symbol "nop" as the spaceholder instruction 6 prevents the processor from performing any arithmetic operation when reading the spaceholder instruction 6.

[0033] Because the loops of function blocks C and D have different numbers of iterations, the program code portion of function block C is executed sequentially on the processor first, followed by parallel execution of the program code portions of function blocks C and D. For example, the loop of function block C has 42 iterations and the loop of function block D has 30 iterations. Thus, the loop of function block C is first executed sequentially 12 times, and then the program code of function blocks C and D is executed in parallel 30 times on the same execution unit of the processor. Depending on the design of the program code and the underlying programming language, parallel execution may occur first, followed by sequential execution.

[0034] The program code "Add r1a,[r2a],0&r1b,[r2b],+r0" shown in the dashed box in Figure 2 represents the portion of the parallelized program code that actually leads to improved computational efficiency. Furthermore, the portion "Add r0,r0,-1" is also executed fewer times. That is, the prior art executes 42 times sequentially and 30 times sequentially (i.e., a total of 72 times), whereas the proposed method executes 12 times in a sequential loop and 30 times in a parallelized loop (i.e., a total of 42 times).

[0035] At this time, register r1 and register r2 are each divided into register area a and register area b. That is, in this program code, access to register area b of the first and second registers is performed in accordance with function block C, and access to register area a of the first and second registers is performed in accordance with the program code of function block D. [Prior art documents] [Patent documents]

[0036] [Patent Document 1] German Patent Invention No. 102019206584 [Non-patent literature]

[0037] [Non-Patent Document 1] D. Nuzman et al. ;Vapor SIMD: Auto-vectorize once, run everywhere; International Symposium on Code Generation and Optimization (CGO 2011), 2011, pp. 151-160, doi: 10.1109 / CGO.2011.5764683

Claims

1. A method for operating an information technology system, comprising: a program code usable by a processor for processing at least one task (1.1, 1.2), wherein during a compilation step a compiler divides the program code into at least two function blocks (2) which are arranged in a data flow graph (3); and the compiler analyzes the data flow graph (3) to determine an execution order of each of the function blocks (2) by the processor, 1. A method according to claim 1, wherein, when processing at least one of said tasks (1.1, 1.2), said compiler identifies functional blocks (2) that can be executed in parallel by said processor, and for each group (4) of functional blocks (2) that can be executed in parallel, it checks whether at least portions of program code of at least two functional blocks (2) require the execution of the same instruction (5) by said processor, and assigns these portions of program code to the same execution unit of said processor for simultaneous processing according to a single instruction, multiple data approach.

2. 2. The method of claim 1, wherein the compiler identifies the number of instructions to be processed by the processor for each of the functional blocks executable in parallel, and for each group of functional blocks executable in parallel, inserts a placeholder instruction into each of the functional blocks that includes fewer instructions than the functional block having the maximum number of instructions in the group, so that all functional blocks in each group include the same number of instructions.

3. When a program code portion included in a function block (2) in a group (4) of function blocks (2) that can be executed in parallel includes a loop, the compiler identifies the number of iterations of each of the loops; the compiler checks whether the loops of the functional blocks (2) containing the program code portions that can be assigned to the same execution unit of the processor according to a single instruction, multiple data method have different iteration numbers, and if they do, the compiler causes the program code portions of each of the functional blocks (C, D) to be processed simultaneously by the same execution unit of the processor according to the number of iterations that is lowest, and causes the program code portions of the functional block (C) with a higher number of iterations to be processed sequentially by the processor according to the remaining iterations; 3. The method according to claim 1 or 2.

4. 4. The method according to claim 1, wherein in the case of a multithreaded processor, at least two different tasks (1.1, 1.2) are processed in parallel on at least two different execution units of said processor.

5. An information technology system, characterized in that it comprises a device for carrying out the method according to any one of claims 1 to 4.

6. A vehicle comprising an information technology system according to claim 5.

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