Metal Oxide Semiconductor Capacitor

Abstract

A metal-oxide-semiconductor (MOS) capacitor can include a substrate including a semiconductor material, an oxide layer formed on a first surface of the substrate, a resistive layer formed on at least a portion of the oxide layer, and a conductive layer formed on at least a portion of the resistive layer. Thus, the MOS capacitor can include a resistor and a capacitor formed in series with each other.

Description

[Technical Field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 418110, filed October 21, 2022, which is incorporated herein by reference. [Background technology]

[0002] Metal-oxide-semiconductor (MOS) capacitors offer various advantages, such as temperature stability, generally high breakdown voltage, and low leakage current. However, the frequency response of MOS capacitors can generally limit their end use. Increasing the equivalent series resistance (ESR) can expand the applications of MOS capacitors. Summary of the Invention

[0003] According to one embodiment of the present disclosure, a capacitor can include a substrate including a semiconductor material. The capacitor can include an oxide layer formed on a surface of the substrate and a resistive layer formed on at least a portion of the oxide layer. The capacitor can include a conductive layer formed on at least a portion of the resistive layer.

[0004] According to another embodiment of the present disclosure, a capacitor can include a substrate including a semiconductor material. The substrate can have a first surface opposite a second surface. The capacitor can include an oxide layer formed on the first surface of the substrate, a resistive layer formed on at least a portion of the oxide layer, a first conductive layer formed on at least a portion of the resistive layer, and a second conductive layer formed on at least a portion of the second surface of the substrate. The resistive layer can have a thickness of less than about 10 microns.

[0005] According to another embodiment of the present disclosure, a method of forming a capacitor includes forming an oxide layer on a surface of a substrate including a semiconductor material, depositing a resistive layer on at least a portion of the oxide layer, and depositing a conductive layer on at least a portion of the resistive layer.

[0006] According to another embodiment of the present disclosure, an embedded capacitor assembly can include a circuit board substrate having a mounting surface and a capacitor at least partially embedded within the circuit board substrate. The capacitor can include a substrate including a semiconductor material and having a first surface opposite a second surface. The capacitor can include an oxide layer formed on the first surface of the substrate and a resistive layer formed on at least a portion of the oxide layer. The capacitor can include a conductive layer formed on at least a portion of the resistive layer.

[0007] A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, which makes reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view of a capacitor according to an aspect of the present disclosure. [Figure 2A] FIG. 1 is a side view of a capacitor according to aspects of the present disclosure. [Figure 2B] FIG. 10 is a side view of another capacitor according to aspects of the present disclosure. [Figure 2C] FIG. 10 is a side view of yet another capacitor according to aspects of the present disclosure. [Figure 2D] FIG. 1 is a top view of a capacitor according to aspects of the present disclosure. [Figure 2E] FIG. 2E is a side view of the capacitor of FIG. 2D. [Figure 3A] FIG. 10 is a perspective view of yet another capacitor according to aspects of the present disclosure. [Figure 3B]3B shows the capacitor of FIG. 3A having an oxide layer within a first portion of a surface of the capacitor substrate and a second terminal within a second portion of the surface of the substrate. [Figure 4] FIG. 1 is a perspective view of a capacitor assembly including a capacitor and a mounting surface, such as a printed circuit board, according to aspects of the present disclosure. [Figure 5A] 1 illustrates an embedded capacitor assembly including a capacitor embedded in a circuit board substrate according to aspects of the present disclosure. [Figure 5B] FIG. 1 illustrates another embedded capacitor assembly including a capacitor embedded in a circuit board substrate, according to aspects of the present disclosure. [Figure 6A] FIG. 1 is an electrical diagram of a capacitor according to an aspect of the present disclosure. [Figure 6B] FIG. 1 is an electrical diagram of a high electron mobility transistor incorporating multiple capacitors according to an aspect of the present disclosure. [Figure 7] 1 is a flowchart of a method for forming a capacitor according to an aspect of the present disclosure. [Figure 8] 1 is a graph showing the change in Q value with the change in the ratio of the area of ​​the resistor to the area of ​​the conductive layer. DETAILED DESCRIPTION OF THE INVENTION

[0009] Repeat use of reference characters in the present specification and drawings is intended to represent same or analogous features or elements of the invention.

[0010] It should be understood by those skilled in the art that this discussion is merely a description of exemplary embodiments and is not intended as a limitation of the broader aspects of the present invention, the broader aspects of which are embodied in the exemplary configurations.

[0011] Generally speaking, the present invention relates to a metal-oxide-semiconductor (MOS) capacitor having a resistive layer. For example, a MOS capacitor (or simply "capacitor") can include a substrate, an oxide layer formed on a surface of the substrate, a resistive layer formed on at least a portion of the oxide layer, and a conductive layer formed on at least a portion of the resistive layer. As described herein, an additional conductive layer formed or positioned opposite the oxide layer with the substrate disposed therebetween completes the capacitor.

[0012] The effective circuit formed by a MOS capacitor with a resistive layer is a resistor in line with the capacitor, which allows the MOS capacitor to be a higher equivalent series resistance (ESR) capacitor. Increasing ESR can reduce the capacitor's Q factor, or quality factor, broadening the capacitor's frequency response. The broadened frequency response of a MOS capacitor can improve the performance of bias lines in active radio frequency (RF) devices, for example, by providing a filter voltage to the active RF device. It will be understood that the quality factor, or Q factor, is the reactance of a capacitor divided by the capacitor's ESR.

[0013] Additionally or alternatively, the extended frequency response due to increased ESR can improve the performance of MOS capacitors in RF shunt and noise filtering applications. For example, a bias bank for an RF active device utilizing one or more MOS capacitors described herein can have a reduced component count compared to, for example, a bias bank that does not utilize a MOS capacitor with a resistive layer described herein. Reducing the number of components in the bias bank can increase the reliability of the bias bank, reduce its size, and improve active device performance. Other applications can include VCOs, mixers, and cascaded amplifier voltage supplies.

[0014] As described above, a MOS capacitor can include a substrate and an oxide layer formed on the substrate. The substrate of a MOS capacitor can include a semiconductor material such as silicon, gallium arsenide, germanium, silicon carbide, strontium titanate, and / or mixtures thereof. The substrate can be doped with one or more suitable dopants, such as boron, arsenic, phosphorus, gallium, aluminum, indium, and antimony.

[0015] An oxide layer of a MOS capacitor can be formed on the surface of a substrate. The oxide layer can be or include silicon oxide and / or oxides of other exemplary semiconductor materials described herein. The oxide layer can be grown in situ on the substrate. Lithography (e.g., photolithography) techniques can be used to define the shape of the oxide layer. For example, portions of the oxide layer can be removed by etching so that the oxide layer has a desired shape.

[0016] As used herein, a layer "formed on" an object can include a layer formed directly on the object and a layer formed on one or more intermediate layers between the layer and the object. Additionally, formed "on" a bottom surface refers from the center outward of the component.

[0017] The surface of the substrate may be generally smooth. For example, the surface of the substrate may be free of pores, trenches, etc. The oxide layer may have a substantially uniform thickness across the surface of the substrate. For example, the thickness of the oxide layer may vary by less than 20%, in some embodiments, less than 10%, and in some embodiments, less than 5% across the oxide layer.

[0018] A resistive layer of the MOS capacitor can be formed on at least a portion of the oxide layer. In some embodiments, the resistive layer can be a thin film resistor. The thin film resistor can be configured to exhibit various resistance values, as desired. For example, in some embodiments, the thin film resistor can have a resistance in the range of about 1 Ω to about 2000 Ω, in some embodiments, about 2 Ω to about 1000 Ω, in some embodiments, about 5 Ω to about 750 Ω, in some embodiments, about 10 Ω to about 500 Ω, and in some embodiments, about 25 Ω to about 400 Ω.

[0019] The resistive layer of the thin film resistor can be formed using various thin film techniques as further described herein. The resistive layer of the thin film resistor can be formed from various suitable resistive materials. For example, the resistive layer can include tantalum nitride (TaN), silicon chromium (SiCr), nickel chromium (NiCr), tantalum aluminide, chromium silicon, titanium nitride, titanium tungsten, tantalum tungsten, oxides and / or nitrides of such materials, and / or any other suitable thin film resistive material.

[0020] A conductive layer of the MOS capacitor can be formed on at least a portion of the resistive layer. The conductive layer can be contained within the periphery of the oxide layer. The conductive layer may not include direct contact and / or direct electrical connection with the substrate. The conductive layer can be or include a metal such as aluminum, copper, gold, silver, nickel, or a mixture thereof.

[0021] The MOS capacitor may also include an additional or second conductive layer. For example, the conductive layer may be a first conductive layer, and the additional conductive layer may be a second conductive layer formed on the substrate and separate from the first conductive layer.

[0022] In some embodiments, a second conductive layer can be formed on a surface of the substrate opposite the oxide layer. For example, the substrate can have a first surface and a second surface opposite the first surface, the oxide layer can be formed on the first surface, and the second conductive layer can be formed on the second surface.

[0023] In other embodiments, the second conductive layer can be formed on the same surface as the oxide layer of the substrate. For example, the oxide layer can be formed on a first surface, and the second conductive layer can be formed on the first surface. In such embodiments, the second conductive layer may not include an electrical connection with the oxide layer.

[0024] In some embodiments, the second conductive layer can be one terminal of a pair of terminals. For example, a MOS capacitor can include a pair of terminals, individually referred to as a first terminal and a second terminal. The first terminal can be connected to the first conductive layer. The second terminal can be connected to a surface of the substrate, such as a first surface (on which the oxide layer is formed) or a second surface (opposite the surface on which the oxide layer is formed). As used herein, "connected to" can refer to components in direct physical contact. "Connected to" can also refer to items that are physically connected by one or an intermediate conductive layer such that the items are directly electrically connected (e.g., without a resistive or dielectric layer between them). For example, as described herein, the first terminal can be formed on the first conductive layer, and the second terminal can be formed on the first or second surface of the substrate.

[0025] In other embodiments, rather than the second conductive layer being one terminal of a pair of terminals, one terminal of the pair of terminals can be connected to the second conductive layer. For example, as described above, a MOS capacitor can include a pair of terminals, referred to individually as a first terminal and a second terminal. The first terminal can be connected to the first conductive layer. The second terminal can be connected to the second conductive layer. For example, the first terminal can be formed on the first conductive layer, and the second terminal can be formed on the second conductive layer.

[0026] One or more protective layers can be formed on the substrate. For example, if an oxide layer, a resistive layer, and a conductive layer are formed on a first surface of the substrate, one or more protective layers can be formed on a second surface of the substrate opposite the first surface. In some embodiments, the first and second terminals can be exposed through one or more protective layers for electrical connection when the capacitor is surface mounted. Examples of protective layer materials include benzocyclobutene (BCB), polyimide, silicon oxynitride, alumina (Al2O3), silica (SiO2), silicon nitride (Si3N4), epoxy, glass, or another suitable material.

[0027] In some embodiments, the first and second terminals can be connected and arranged such that the oxide layer covers less than all of the first surface of the substrate. For example, the first terminal can be spaced apart from the second terminal in the Y direction. The edge of the oxide layer can be aligned in the X direction, which is perpendicular to the Y direction. The edge of the oxide layer can be spaced apart from the edge of the substrate in the Y direction.

[0028] The second terminal can be connected to the first surface of the substrate at a location along the first surface of the substrate that is spaced apart from the oxide layer. For example, the second terminal can be located between an edge of the oxide layer and an end of the substrate. The edge of the oxide layer can be spaced apart from the second terminal by a distance greater than about 2 microns, in some embodiments, greater than about 5 microns, in some embodiments, greater than about 10 microns, and in some embodiments, greater than about 15 microns.

[0029] The oxide layer can cover a first portion of the first surface of the substrate that is distinct from a second portion of the first surface of the substrate that does not include the oxide layer. A second terminal can be connected to the first surface of the substrate within the second portion of the first surface of the substrate. The second terminal can include a conductive material that directly contacts the first surface of the substrate.

[0030] As described herein, in other embodiments, a second terminal can be formed on the second surface of the substrate such that the substrate is disposed between the oxide layer and the second terminal. In some embodiments, the second terminal can include a conductive material that directly contacts the second surface of the substrate, and in other embodiments, the second terminal can include a conductive material that directly contacts a second conductive layer formed on the second surface of the substrate.

[0031] Various thin film techniques can be used to form the thin film layers of the capacitor, such as the first conductive layer, second conductive layer, resistive layer, and terminals. Examples of such techniques that can be used include chemical deposition (e.g., chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition) processing, physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin film elements. Further examples include any suitable patterning technique (e.g., photolithography), etching, and any other suitable subtractive technique for forming thin film elements.

[0032] The thin film layer can have a range of thicknesses. For example, in some embodiments, the thin film layer can have a thickness that can range from about 0.001 micrometers (microns) to about 100 microns, in some embodiments, from about 0.0375 microns to about 40 microns, in some embodiments, from about 0.1 microns to about 30 microns, in some embodiments, from about 0.2 microns to about 20 microns, and in some embodiments, from about 0.4 microns to about 10 microns. For example, in some embodiments, the resistive layer can have a thickness of less than about 10 microns, in some embodiments, less than about 8 microns, in some embodiments, less than about 6 microns, and in some embodiments, less than about 4 microns.

[0033] In some embodiments, the conductive layer formed on the resistive layer may be relatively small compared to the resistive layer that defines the capacitive region. By providing a relatively small conductive layer, only a relatively small area is available for current to flow, which can force the current through the resistive layer and increase the resistance from the edges of the resistive layer to the relatively small conductive layer.

[0034] The relative size of the conductive layer compared to the resistive layer may be defined by the ratio of the area of ​​the resistive layer to the area of ​​the conductive layer. The area of ​​the resistive layer may be defined by the length of the resistive layer extending in the Y direction and the width of the resistive layer extending in the X direction. Similarly, the area of ​​the conductive layer may be defined by the length of the conductive layer extending in the Y direction and the width of the conductive layer extending in the X direction. In some embodiments, the ratio of the area of ​​the resistive layer to the area of ​​the conductive layer may be in the range of about 100:1, in the range of about 75:1, in the range of about 50:1, in the range of about 25:1, in the range of about 15:1, in the range of about 10:1, in the range of about 5:1, in the range of about 3:1, or in the range of about 1.5:1.

[0035] In some embodiments, the first terminal and the second terminal can be exposed along the same surface of a substrate for surface mounting the capacitor. Using surface mounting technology, MOS capacitors can be free of electrical connections, such as wirebond connections, which can cause high-frequency perturbations and adversely affect high-frequency performance. In this way, surface-mounted MOS capacitors can generally have excellent high-frequency performance.

[0036] For example, the capacitor may be configured for grid array-type mounting, such as a land grid array or a ball grid array. The terminals may be exposed along the first surface of the substrate and contained within the periphery of the first surface of the monolithic substrate. As another example, the substrate may have a pair of end faces perpendicular to the first surface of the monolithic substrate. The pair of end faces may not have terminations that include terminals. As a further example, the first terminal, the second terminal, or both may be spaced apart from a pair of opposing edges of the first surface of the monolithic substrate by respective distances. The distances may be 10 microns or more, in some embodiments 15 microns or more, in some embodiments 20 microns or more, in some embodiments 40 microns or more, and in some embodiments 50 microns or more.

[0037] In some aspects of the present subject matter, the MOS capacitor can be configured to be embedded within a circuit board substrate, such as a printed circuit board. For example, the first and second terminals can be exposed along opposing surfaces of the substrate, such as the top and bottom surfaces of the substrate, and can be contained within the periphery of each surface of the substrate. In other embodiments, the first and second terminals of the embedded capacitor can be exposed along the same surface of the substrate.

[0038] The present subject matter further relates to an embedded capacitor assembly including a circuit board substrate, such as a printed circuit board, in which a MOS capacitor is at least partially embedded. The circuit board substrate may be formed from any suitable material, such as FR4, polytetrafluoroethylene, etc. One or more electronic components, such as capacitors, resistors, transistors, switches, and / or other electronic components, may be mounted to the circuit board substrate. As used herein, "mounted to" a circuit board may include any type of connection to the circuit board substrate that provides electrical connectivity, such as surface mounting to the surface of the circuit board substrate, embedding within the circuit board substrate, etc.

[0039] In some embodiments, the circuit board substrate can have a recessed opening on a mounting surface of the circuit board substrate, such as the top or bottom surface. The recessed opening can be configured to receive an electrical component to be embedded within the circuit board substrate. For example, a capacitor, such as the capacitors described herein, can be inserted into the recessed opening for embedding within the circuit board substrate. One or more conductive terminations of the capacitor can be coupled to the circuit board substrate. For example, one or more vias can be formed in, on, or through the terminations to electrically connect the capacitor to the circuit board substrate and / or one or more conductive traces of one or more electronic components mounted on the circuit board substrate.

[0040] The first and second terminals of a capacitor can be formed from copper, such as by copper plating. Typically, solid copper is prone to oxidation upon exposure and may not be a suitable material for forming exposed terminations of electronic components. Thus, solder materials, such as copper-tin-gold alloys, are often used to form electrical terminations of electronic components, such as capacitors. However, the present inventors have discovered that forming the first and second terminals of an embeddable capacitor from copper, for example, by plating solid copper onto a conductive layer and / or onto one or more surfaces of a substrate, can provide excellent electrical connections without the risk of oxidation when the capacitor is embedded within a circuit board substrate. For example, the first and second terminals can be laser drilled to form direct electrical connections with the circuit board substrate and / or additional electronic components mounted on the circuit board substrate.

[0041] 1 is a perspective view of a capacitor 100 according to an embodiment of the present disclosure. The capacitor 100 can include a substrate 102 including a semiconductor material such as silicon. The substrate 102 can have a first surface 104 and a second surface 106 opposite the first surface 104.

[0042] The capacitor 100 may include an oxide layer 108 formed on the first surface 104 of the substrate 102. The oxide layer 108 may include silicon oxide. The capacitor 100 may include a resistive layer 110 formed on at least a portion of the oxide layer 108. The resistive layer 110 may be included within the periphery of the oxide layer 108 (FIGS. 3A, 3B). The resistive layer 110 may not include direct contact and / or a direct electrical connection with the substrate 102.

[0043] In some embodiments, resistive layer 110 can have a thickness of less than about 10 microns. In some embodiments, resistive layer 110 can be formed from tantalum nitride, and in other embodiments, resistive layer 110 can be formed from chromium silicon. Resistive layer 110 can have other thicknesses and / or can be formed from other materials as described elsewhere herein.

[0044] The capacitor 100 may further include a conductive layer 112 formed on at least a portion of the resistive layer 110. Similar to the resistive layer 110, the conductive layer 112 may be included within the periphery of the oxide layer 108 as well as the periphery of the resistive layer 110 ( FIGS. 3A and 3B ). The conductive layer 112 may not include direct contact and / or a direct electrical connection with the substrate 102. Additionally, the conductive layer 112 may not include direct contact and / or a direct electrical connection with the oxide layer 108.

[0045] 2A-2C, side views of various embodiments of a capacitor 200 according to aspects of the present disclosure are shown. Similar reference numerals are used in FIGS. 2A-2C as in FIG. 1. For example, capacitor 200 includes a substrate 202 including a semiconductor material, with an oxide layer 208 formed on a first surface 204 of substrate 202. A resistive layer 210 is formed on at least a portion of oxide layer 208, and a first conductive layer 212 is formed on at least a portion of resistive layer 210.

[0046] 2B and 2C, the second conductive layer 214 is formed on the second surface 206 of the substrate 202, the second surface 206 being opposite the first surface 204. The second conductive layer 214 can extend across the entire second surface 206, as shown in FIGS. 2B and 2C. Alternatively, the second conductive layer 214 can be offset from one or more edges of the substrate 202, similar to, for example, the oxide layer 208, the resistive layer 210, and the first conductive layer 212 formed on the first surface 204 of the substrate 202, such that the second conductive layer 214 extends over a portion of the second surface 206.

[0047] A pair of terminals may be connected to the capacitor. Each terminal of the pair of terminals may comprise a conductive material, such as gold, copper, another suitable metal, or other conductive material. In some embodiments, at least one of the first conductive layer 212 or the second conductive layer 214 is one terminal of the pair of terminals. For example, the first conductive layer 212 and the second conductive layer 214 may each form one terminal of the pair of terminals.

[0048] In other embodiments, only one of the first conductive layer 212 or the second conductive layer 214 may form one terminal of a pair of terminals, and in still other embodiments, neither the first conductive layer 212 nor the second conductive layer 214 may form one terminal of a pair of terminals. For example, as shown in Figures 2A-2C, the first terminal 216 of the pair of terminals may be connected to the first conductive layer 212.

[0049] Furthermore, the first terminal 216 can be located closer to one end face 234 of the pair of end faces 232, 234 of the substrate 202 than the other end face 232 of the pair of end faces 232, 234. For example, the substrate may include a first end face 232 and a second end face 234 that face each other along the Y direction and are perpendicular to the first surface 204 and the second surface 206 of the substrate 202. As shown in FIGS. 2A to 2C , the first terminal 216 may be located closer to the second end face 234 than the first end face 232. In other embodiments, the first terminal 216 may be located closer to the first end face 232 than the second end face 234. In still other embodiments, the first terminal 216 may be located equidistant from the first end face 232 and the second end face 234 along the Y direction.

[0050] The second terminal 218 of the pair of terminals can be connected to the substrate 202 or the second conductive layer 214. For example, the capacitor 200 can include the second terminal 218 on the second surface 206 of the substrate 202. As shown in FIG. 2A , the second terminal 218 can be formed integrally with the second surface 206 of the substrate 202. Alternatively, with reference to FIG. 2B , the second terminal 218 can be formed from a second conductive layer 214 formed on the second surface 206 of the substrate 202 opposite the first surface 204 in the Z direction. With reference to FIG. 2C , in other embodiments, the second terminal 218 can be formed on the second conductive layer 214 such that the second conductive layer 214 is disposed between the second terminal 218 and the substrate 202. 2C , the second terminal 218 may be aligned with the first terminal 216 in the Z direction, or the second terminal 218 may be offset from the first terminal 216 in the Z direction. For example, the second terminal 218 may be formed closer to the first end face 232 than to the second end face 234. In either of these configurations, the oxide layer 208 is connected in series between the first conductive layer 212 and the second conductive layer 214, forming a capacitor between the first terminal 216 and the second terminal 218.

[0051] In yet other embodiments, each of the second conductive layer 214 and the second terminal 218 can be formed on the second surface 206 of the substrate 202 without the second terminal 218 being formed on the second conductive layer 214; for example, the second conductive layer 214 can be formed on a portion of the second surface 206 and the second terminal 218 can be formed on another separate portion of the second surface 206.

[0052] In either case, the pair of terminals 216, 218, whether formed separately from the first conductive layer 212 and the second conductive layer 214 or formed by the first conductive layer 212 and / or the second conductive layer 214, are connected to various layers or substrates 202 of the capacitor 200 such that the capacitor 200 comprises a resistor and a capacitor formed in series with each other.

[0053] 2D and 2E , top and side views, respectively, of a capacitor 200 according to a further aspect of the present disclosure are shown. As previously mentioned, a first conductive layer 212 may be contained within the periphery 211 of the resistive layer 210 (which may be contained within the periphery 209 of the oxide layer 208). In the embodiment shown in FIG. 2D , the first conductive layer 212, which in some embodiments may form the first terminal 216, is relatively small compared to the resistive layer 210, which defines the capacitive region. By providing a relatively small first conductive layer 212, only a relatively small area is available for current to flow, thereby forcing the current through the resistive layer 210.

[0054] The relative size of the first conductive layer 212 compared to the resistive layer 210 may be defined by the ratio of the area of ​​the resistive layer 210 to the area of ​​the first conductive layer 212. The area of ​​the resistive layer 210 may be defined by the length L of the resistive layer 210 extending in the Y direction between the first edge 224 and the second edge 226 of the substrate 202. R and a width W of the resistive layer 210 extending in the X direction between the first side edge 228 and the second side edge 230 of the substrate 202. R Similarly, the area of ​​the first conductive layer 212 can be defined by the length L of the first conductive layer 212 extending in the Y direction. C1 and the width W of the first conductive layer 212 extending in the X direction. C1 In some embodiments, the ratio of the area of ​​the resistive layer 210 to the area of ​​the first conductive layer 212 may be in the range of about 100:1, in some embodiments in the range of about 75:1, in some embodiments in the range of about 50:1, in some embodiments in the range of about 25:1, in some embodiments in the range of about 15:1, in some embodiments in the range of about 10:1, in some embodiments in the range of about 5:1, in some embodiments in the range of about 3:1, and in some embodiments in the range of about 1.5:1.

[0055] 3A and 3B, perspective and bottom views of a capacitor 300 according to an embodiment of the present disclosure are shown. Similar reference numerals are used in FIGS. 3A and 3B to those in FIGS. 1 and 2. For example, the capacitor 300 includes a substrate 302 including a semiconductor material, with an oxide layer 308 formed on a first surface 304 of the substrate 302. A resistive layer 310 is formed on at least a portion of the oxide layer 308, and a conductive layer 312 is formed on at least a portion of the resistive layer 310. The resistive layer 310 may be included within a periphery 309 of the oxide layer 308, and the conductive layer 312 may be included within a periphery 311 of the resistive layer 310.

[0056] 3A and 3B , a first terminal 316 and a second terminal 318 may be exposed along a first surface 304 of a substrate 302 for surface mounting the capacitor 300. The first terminal 316 may be formed on the conductive layer 312. The first terminal 316 may be spaced apart in the Y direction from the second terminal 318. An edge 320 of the oxide layer 308 may be aligned in the X direction, which is perpendicular to the Y direction. The edge 320 of the oxide layer 308 may be spaced apart in the Y direction from an edge 322 of the substrate 302.

[0057] The second terminal 318 may be flush with the oxide layer 308. For example, the second terminal 318 and the oxide layer 308 may each be formed only on the first surface 304 of the substrate 302. The second terminal 318 may be connected to the first surface 304 of the substrate 302 at a location along the first surface 304 of the substrate 302 that is spaced apart from the oxide layer 308. For example, the second terminal 318 may be located between an edge 320 of the oxide layer 308 and an end 322 of the substrate 302. The edge 320 of the oxide layer 308 may be spaced apart from the second terminal 318 by a distance 324. In some embodiments, the distance 324 may be greater than about 2 microns.

[0058] 3A and 3B, an oxide layer 308 may be formed in a first portion 326 of a first surface 304 of a substrate 302. The first portion 326 of a first surface 304 of a substrate 302 may be different from a second portion 328 of a first surface 304 of a substrate 302. The second portion 328 of a first surface 304 may be free of an oxide layer 308.

[0059] The second terminal 318 may be connected to the first surface 304 of the substrate 302 within a second portion 328 of the first surface 304 of the substrate 302. In some embodiments, the second terminal 318 may directly contact the first surface 304 of the substrate 302. However, in other embodiments, the second terminal 318 may be electrically connected to the first surface 304 of the substrate 302 via one or more suitable conductive layers between the second terminal 318 and the first surface 304. In either case, the pair of terminals 316, 318 are connected to various layers or the substrate 302 of the capacitor 300 such that the capacitor 300 comprises a resistor and a capacitor formed in series with each other.

[0060] Each of the first terminal 316 and the second terminal 318 can include a conductive material such as gold, copper, another suitable metal, or other conductive material. The substrate 302 can include a semiconductor material such as silicon. The oxide layer 308 can include silicon oxide.

[0061] The capacitor 300 may be configured for grid array mounting, such as ball grid array mounting or land grid array mounting. The terminals 316, 318 may be exposed along the first surface 304 and may be contained within an XY plane in each of the X and Y directions within a periphery 330 of the first surface 304 of the monolithic substrate 302.

[0062] As another example, the substrate 302 can have a pair of end faces 332, 334 perpendicular to the first surface 304 of the monolithic substrate 302. The pair of end faces 332, 334 can be free of terminations that include the terminals 316, 318. As a further example, the first terminal 316, the second terminal 318, or both, can be spaced apart from a pair of opposing edges 322, 323 of the first surface 304 of the monolithic substrate 302 by respective distances 333, 335. The distances 333, 335 can be 10 microns or greater. Furthermore, the distances 333, 335 can be equal to or different from one another, e.g., one of the distances 333, 335 can be greater than the other of the distances 333, 335.

[0063] 4 is a perspective view of a capacitor assembly 450 including the capacitor 300 of FIGS. 3A and 3B and a mounting surface 452, such as a printed circuit board. A first terminal 316 of the capacitor 300 is connectable to a first conductive trace 454 on the mounting surface 452. A second terminal 318 of the capacitor 300 is connectable to a second conductive trace 456 on the mounting surface 452. As shown in FIG. 4, the capacitor 300 may be configured as a flip chip, with the first surface 304 ( FIGS. 3A and 3B ) facing the mounting surface 452.

[0064] 5A and 5B each illustrate an embedded capacitor assembly 560 including a capacitor 300 embedded in a circuit board substrate 562 according to an aspect of the present disclosure. The circuit board substrate 562 may be, for example, a printed circuit board and may be formed from any suitable material, such as FR4, polytetrafluoroethylene, or the like. The circuit board substrate 562 includes a mounting surface 564. The capacitor 300 may be generally configured similarly to the capacitor 300 of FIGS. 3A and 3B, although in other embodiments, the capacitor embedded in the embedded capacitor assembly 560 may be configured similarly to the capacitor 100 of FIG. 1 or the capacitor 200 of FIGS. 2A-2C.

[0065] The capacitor can be at least partially embedded within a circuit board substrate 562 of an embedded capacitor assembly 560. As shown in FIG. 5A , a first via 566 can extend from the first terminal 316 of the capacitor 300 toward the mounting surface 564 and connect to a first conductive layer 568 formed on the mounting surface 564. The first via 566 in the circuit board 560 can electrically connect the first terminal 316 and the first conductive layer 568 of the circuit board 560.

[0066] 5A , a second via 570 can extend from the second terminal 318 of the capacitor 300 toward the mounting surface 564 and connect to a second conductive layer 572 formed on the mounting surface 564. The second via 570 in the circuit board 560 can electrically connect the second terminal 318 and the second conductive layer 572 of the circuit board 560.

[0067] Alternatively, the vias 566, 570 can extend toward the mounting surface 564 and connect to one or more intermediate layers (e.g., embedded within the circuit board substrate 562), which can be electrically connected to the first conductive layer 568 and / or the second conductive layer 572. The first via 566 can form at least a portion of the electrical connection between the first terminal 316 of the capacitor 300 and the first conductive layer 568 of the circuit board 560. Similarly, the second via 570 can form at least a portion of the electrical connection between the second terminal 318 of the capacitor 300 and the second conductive layer 572 of the circuit board 560. Thus, the conductive layers 568, 572 can be used to facilitate electrical connection to the capacitor 300. However, it should be understood that in other embodiments, one or both of the terminals 316, 318 can be exposed along the mounting surface 564. In such embodiments, the circuit board 560 need not include one or both of the vias 566, 570.

[0068] As previously mentioned, the capacitor embedded in the circuit board substrate 562 may be configured similarly to the capacitor 100 of FIG. 1 or the capacitor 200 of FIGS. 2A-2C. For example, referring to FIG. 5B , where the embedded capacitor is configured similarly to the capacitor 200 described herein, the embedded capacitor assembly 560 may include a via and a conductive layer on the mounting surface 564, such as a via 566 extending between the first terminal 216 and a conductive layer 568 on the mounting surface 564. In such an embodiment, a via 570 may extend between the second terminal 218 and a conductive layer 572 disposed in or at another location on the circuit board 560. More specifically, as shown in FIG. 5B , the mounting surface 564 may have an opening 565 recessed in the circuit board substrate 562. To minimize its height profile above the substrate, the capacitor 200 may be embedded in the opening 565 and attached to the circuit board substrate 562 using known techniques. For example, as described further herein, using known techniques, one or more vias can connect one or more terminals of capacitor 200 with one or more conductive traces of circuit board substrate 562.

[0069] 5B , the first terminal 216 and the second terminal 218 are formed on opposing surfaces of the substrate 202 of the illustrated capacitor 200. For example, the first terminal 216 is formed on the first surface 204, which may be the top surface of the substrate 202, and the second terminal 218 is formed on the second surface 206, which may be the bottom surface of the substrate 202. As shown in FIG. 5B , a via 566 can extend from the first terminal 216 of the capacitor 200 toward the mounting surface 564 and connect to a conductive layer 568 formed on the mounting surface 564. The via 566 of the embedded capacitor assembly 560 can electrically connect the first terminal 216 to the first conductive layer 568, which may be, for example, a conductive trace of the circuit board substrate 562. Alternatively, the via 566 can extend toward the mounting surface 564 and connect to one or more intermediate layers (e.g., embedded within the circuit board substrate 562), which can then electrically connect the intermediate layers to the conductive layer 568. Via 566 may form at least a portion of an electrical connection between first terminal 216 of capacitor 200 and conductive layer 568 of embedded capacitor assembly 560. However, it should be understood that in other embodiments, terminal 216 may be exposed along mounting surface 564. In such embodiments, embedded capacitor assembly 560 may not include via 566.

[0070] In some embodiments, the circuit board substrate 562 can include multiple conductive layers 568, 572, e.g., multiple conductive traces, and the capacitor 200 can include multiple terminals 216 and / or 218 exposed along the first surface 204. Multiple vias 566, 570 can extend from the terminals to the conductive layers of the circuit board substrate 562, e.g., at least one via can extend from each one of the terminals 216, 218 of the capacitor 200 to each one of the conductive layers 568, 572 of the circuit board substrate 562.

[0071] The extent to which the capacitors are embedded depends on various factors, such as the thickness of the circuit board substrate 562, the depth of the opening 565, and the thickness of the capacitors 100, 200, and 300. The thickness of the circuit board substrate 562 (not including attached electronic components) may be about 0.1 to about 5 millimeters in some embodiments, about 0.2 to about 3 millimeters in some embodiments, and about 0.4 to about 1.5 millimeters in some embodiments. Thus, depending on the particular thickness used, the capacitors may be embedded such that the exposed surfaces of the first terminals 116, 216, and 316 are substantially flush with or below the mounting surface 564 of the circuit board substrate 562. For example, the capacitors 100, 200, and 300 may be embedded and encapsulated within the opening 565 of the circuit board substrate 562. Alternatively, the capacitors 100, 200, and 300 may be embedded such that the exposed surfaces of the first terminals 116, 216, and 316 extend slightly above the mounting surface 564 of the circuit board substrate 562. Nevertheless, by at least partially embedding the capacitors 100, 200, 300 within the circuit board substrate 562, the height profile or thickness occupied by the capacitors is reduced and can be controlled depending on the desired application.

[0072] It should be understood that various other electronic components may be mounted on circuit board substrate 562 as is known in the art, and a single capacitor is shown in Figures 5A and 5B for illustrative purposes only.

[0073] Referring to FIGS. 6A and 6B, electrical diagrams illustrating capacitors 100, 200, and 300 described herein are provided. As shown in FIG. 6A, each capacitor 100, 200, and 300 includes a resistor R and a capacitor C arranged in series with one another. Referring to FIG. 6B, one or more of the exemplary capacitors 100, 200, and 300 described with respect to FIGS. 1-3B may be used in various electrical systems or devices. For example, FIG. 6B illustrates an exemplary high electron mobility transistor (HEMT) according to embodiments of the present subject matter. On the left side of the electrical diagram shown in FIG. 6B, multiple capacitors described herein, represented as R6 / C18, R5 / C10, and R14 / C32, are arranged in a negative bias bank, and on the right side, multiple capacitors described herein, represented as R15 / C33, R3 / C8, and R4 / C17, are arranged in a Vdd bias bank. As previously mentioned, the MOS capacitors described herein, such as capacitors 100, 200, and 300 described above, can have increased ESR, which can reduce the number of components in a bias bank, such as the bias bank shown in the HEMT of Figure 6B, thereby increasing reliability, reducing size, and improving device performance. It will be understood that the HEMT depicted in Figure 6B is merely an example, and that capacitors 100, 200, and 300 described herein can be used in a variety of applications.

[0074] Referring now to FIG. 7 , an aspect of the present subject matter relates to a method 700 for forming a capacitor as described herein. Generally, method 700 is described herein with reference to capacitor 200 of FIGS. 2A-2C . However, it should be understood that the disclosed method 700 may be practiced with any suitable capacitor. Additionally, while FIG. 7 depicts steps performed in a particular order for purposes of illustration and explanation, the methods described herein are not limited to any particular order or arrangement. Using the disclosure provided herein, one skilled in the art will understand that various steps of the methods disclosed herein may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present subject matter.

[0075] The method 700 may include forming (702) an oxide layer 208 on a first surface 204 of a substrate 202 comprising a semiconductor material. For example, the oxide layer 208 may be grown in situ on the substrate 202. Lithography (e.g., photolithography) techniques may be used to define the shape of the oxide layer 208. For example, for a capacitor 300 having an oxide layer 308 as described with respect to FIGS. 3A and 3B , a portion of the oxide layer 308 may be etched away such that the oxide layer 308 is located within the first portion 326 of the first surface 304 of the substrate 302.

[0076] The method 700 may include depositing (704) a resistive layer 210 over at least a portion of the oxide layer 208. The resistive layer 210 may be contained within a periphery 209 of the oxide layer 208. The resistive layer 210 may not include direct contact and / or a direct electrical connection with the substrate 202. The resistive layer 210 may have a thickness of less than about 10 microns. The resistive layer 210 may be formed from tantalum nitride, chromium silicon, or other suitable resistive materials as described herein.

[0077] The method 700 may include depositing (706) a first conductive layer 212 over at least a portion of the resistive layer 210. The first conductive layer 212 may be contained within the periphery 211 of the resistive layer 210. The first conductive layer 212 may not include direct contact and / or direct electrical connection with the oxide layer 208 and / or the substrate 202.

[0078] The method 700 may optionally include depositing (708) a second conductive layer 214 on at least a portion of the second surface 206 of the substrate 202. The second surface 206 of the substrate 202 may be opposite the first surface 204 of the substrate 202.

[0079] The method 700 may optionally include depositing (710) a first terminal 216 on the first conductive layer 212. For example, in some embodiments, a separate first terminal 216 may be formed on the first conductive layer 212, while in other embodiments, the first conductive layer 212 may form the first terminal 216. The method may optionally include depositing (712) a second terminal 218 such that at least the substrate 202, the oxide layer 208, and the resistive layer 210 are disposed between the first conductive layer 212 and the second terminal 218. For example, as described herein, in some embodiments, the second conductive layer 214 may form the second terminal 218. In other embodiments, the second terminal 218 may be deposited on the second conductive layer 214 such that the substrate 202, the oxide layer 208, the resistive layer 210, and the second conductive layer 214 are disposed between the first conductive layer 212 and the second terminal 218.

[0080] Alternatively, in some embodiments such as those described with respect to capacitor 300, second terminal 318 may be deposited on first surface 304 of substrate 302 such that second terminal 318 is connected to substrate 302. In this manner, both first terminal 316 and second terminal 318 are formed on first surface 304 of substrate 302, and capacitor 300 can be surface mounted with both first terminal 316 and second terminal 318 exposed along first surface 304 of substrate 302. In either case, the pair of terminals 216, 218 or 316, 318 are connected to various layers or substrates of the respective capacitors 200, 300 such that a resistor and a capacitor are formed in series with one another.

[0081] Referring now to FIG. 8, the insertion loss (S) of various capacitors 800, 802, 804 formed as described herein and a MOS capacitor 10 formed according to known or standard designs is shown. 21 ) is shown, where a first capacitor 800, a second capacitor 802, and a third capacitor 804 are MOS capacitors that include a resistive layer, and a standard MOS capacitor 10 does not include a resistive layer.

[0082] The first capacitor 800 has a resistive layer and a first conductive layer (e.g., resistive layer 110, 210, 310 and first conductive layer 112, 212, 312 described herein), and among the three capacitors 800, 802, 804, the first capacitor 800 has the largest ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer. The third capacitor 804 has a resistive layer and a first conductive layer (e.g., resistive layer 110, 210, 310 and first conductive layer 112, 212, 312 described herein), and among the three capacitors 800, 802, 804, the third capacitor 804 has the largest ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer. The second capacitor 802 has a resistive layer and a first conductive layer (e.g., resistive layers 110, 210, 310 and first conductive layers 112, 212, 312 described herein), with the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer being between that of the first capacitor 800 and that of the third capacitor 804. As described herein, for example, with reference to FIG. 2D , the area of ​​the resistive layer of each capacitor 800, 802, 804 is proportional to the length L of the respective resistive layer. R and the width of each resistive layer W R and the area of ​​the first conductive layer is the product of the length L of each first conductive layer. C1 and the width W of each first conductive layer C1 It is the product of

[0083] The Q factor of each capacitor 800, 802, 804, and 10 is indicated by the resonance point of the respective capacitor's insertion loss. As shown in Figure 8, for each capacitor 800, 802, 804, and 10, its Q factor decreases as the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer increases. Thus, of the four capacitors in Figure 8, the first capacitor 800 has the lowest Q factor, the second capacitor 802 has the next lowest Q factor, the third capacitor 804 has the third lowest Q factor, and the standard MOS capacitor 10 has the highest Q factor.

[0084] Thus, the resistive layers 112, 212, 312 of the various embodiments described herein can lower the Q-factor of the respective capacitor. As discussed above, a lower Q-factor can broaden the frequency response of the capacitor, which can improve the performance of bias lines in active radio frequency (RF) devices, for example, by providing a filtered voltage to the active RF device. Additionally or alternatively, the broadened frequency response can improve the performance of MOS capacitors in RF shunt and noise filtering applications. Other benefits and advantages can also be realized from reducing or lowering the Q-factor of a capacitor, as described herein. Purpose

[0085] The capacitors described herein are useful in a variety of applications. Because the capacitors exhibit excellent performance at high frequencies, such as frequencies of 20 GHz or higher, they may be particularly useful in devices that process wideband, high-frequency signals. Exemplary devices include mobile devices (e.g., cell phones, tables, etc.), cell phone towers, receiver optical subassemblies (ROSAs), transmit optical subassemblies (TOSAs), and other RF communication devices. Such devices may be particularly useful in military and space applications.

[0086] These and other modifications and variations of the present invention may be practiced by those skilled in the art without departing from the spirit and scope of the present invention. Additionally, it should be understood that aspects of the various embodiments may be interchanged in whole or in part. Furthermore, those skilled in the art will appreciate that the foregoing description is merely illustrative and is not intended to limit the invention as so further described in the appended claims. [Explanation of symbols]

[0087] 100 capacitors 102 Base material 104 First Surface 106 Second Surface 108 oxide layer 110 resistance layer 112 Conductive layer 116 First terminal 200 capacitors 202 Base material 204 First Surface 206 Second Surface 208 Oxide layer 209 Periphery 210 resistance layer 211 Periphery 212 first conductive layer 214 Second conductive layer 216 First Terminal 218 Second Terminal 224 First Edge 226 Second Edge 228 First Side Edge 230 Second Side Edge 232 first end face 234 Second end face 300 capacitor 302 Base material 304 First Surface 308 Oxide layer 309 Periphery 310 resistance layer 311 Periphery 312 Conductive layer 316 First Terminal 318 Second Terminal 320 Edge 322 Edge 323 Edge 324 distance 326 First Part 328 Second Part 330 Periphery 332 End face 333 distance 334 End face 335 distance 450 Capacitor Assembly 452 Mounting surface 454 First Conductive Trace 456 Second Conductive Trace 560 Circuit board, capacitor assembly 562 Circuit board base material 564 Mounting surface 565 Opening 566 First Via 568 First Conductive Layer 570 Second Via 572 Second Conductive Layer 10 Standard MOS Capacitors 800 First Capacitor 802 Second Capacitor 804 Third Capacitor

Claims

1. a substrate comprising a semiconductor material; an oxide layer formed on a first surface of the substrate; a resistive layer formed on at least a portion of the oxide layer; a first conductive layer formed on at least a portion of the resistive layer; A capacitor comprising:

2. The capacitor of claim 1 , further comprising a second conductive layer formed on a second surface of the substrate opposite the first surface of the substrate.

3. a first terminal connected to the first conductive layer; a second terminal connected to the second conductive layer; The capacitor of claim 2 further comprising:

4. The capacitor of claim 1 , wherein the resistive layer has a thickness of less than about 10 microns.

5. The capacitor of claim 1 wherein the resistive layer is formed from tantalum nitride.

6. The capacitor of claim 1 wherein the resistive layer is formed from chrome silicon.

7. a first terminal connected to the first conductive layer; a second terminal connected to the first surface of the substrate, the oxide layer is in turn connected between the substrate and the first conductive layer to form a capacitor between the first terminal and the second terminal; The capacitor of claim 1 further comprising:

8. The capacitor of claim 7 , wherein each of the first and second terminals is exposed along the first surface of the substrate for surface mounting the capacitor.

9. The capacitor of claim 7 , wherein the second terminal comprises a conductive material in direct contact with a surface of the substrate.

10. The capacitor of claim 1 , wherein the semiconductor material of the substrate comprises silicon.

11. The capacitor of claim 1 , wherein the oxide layer comprises silicon oxide.

12. 10. The capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 1.5:

1.

13. 10. The capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 10:

1.

14. 10. The capacitor of claim 1, wherein the ratio of the area of ​​the resistive layer to the area of ​​the first conductive layer is at least about 20:

1.

15. a substrate comprising a semiconductor material, the substrate having a first surface opposite a second surface; an oxide layer formed on the first surface of the substrate; a resistive layer formed on at least a portion of the oxide layer; a first conductive layer formed on at least a portion of the resistive layer; a second conductive layer formed on at least a portion of the second surface of the substrate; A capacitor comprising: the resistive layer has a thickness of less than about 10 microns; Capacitor.

16. a first terminal connected to the first conductive layer; a second terminal connected to the second conductive layer; 16. The capacitor of claim 15 further comprising:

17. 16. The capacitor of claim 15, wherein at least one of the first conductive layer and the second conductive layer is one of a pair of terminals.

18. a first terminal connected to the first conductive layer; a second terminal connected to the first surface of the substrate; and Further provided with 16. The capacitor of claim 15.

19. 1. An embedded capacitor assembly comprising: a circuit board substrate having a mounting surface; a capacitor at least partially embedded within the circuit board substrate, a substrate comprising a semiconductor material and having a first surface opposite a second surface; an oxide layer formed on the first surface of the substrate; a resistive layer formed on at least a portion of the oxide layer; a conductive layer formed on at least a portion of the resistive layer; a capacitor; 1. An embedded capacitor assembly comprising:

20. The capacitor a first terminal connected to the conductive layer; a second terminal connected to the substrate; Furthermore, the first terminal and the second terminal are each formed on the first surface of the substrate; the second terminal does not include an electrical connection to the oxide layer.

20. The embedded capacitor assembly of claim 19.

21. the capacitor further comprises at least one via connected to one of the first terminal or the second terminal, the at least one via extending toward the mounting surface of the circuit board substrate; 21. The embedded capacitor assembly of claim 20.

22. 22. The embedded capacitor assembly of claim 21, wherein the circuit board substrate further includes a conductive layer, and the at least one via is connected to the conductive layer of the circuit board substrate.

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