Protective treatment for the surfaces of semiconductor manufacturing equipment

Abstract

A method for preparing a semiconductor manufacturing component is described. In an embodiment, the method includes forming a first layer on a surface of the semiconductor manufacturing component. The first layer is characterized by a porosity of about 0.01 vol.% or greater. The method further includes depositing a second layer on the first layer, the second layer being characterized by a porosity of about 20 vol.% or less. A processed semiconductor manufacturing component is also described. In an embodiment, the processed component includes a first layer formed on a surface of the semiconductor manufacturing component, the first layer being characterized by a porosity of about 0.01 vol.% or greater, and a second layer positioned on the first layer, the second layer being characterized by a porosity of about 20 vol.% or less.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. patent application Ser. No. 17 / 981,394, filed Nov. 5, 2022, the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to protective coatings on components of semiconductor manufacturing equipment that are subject to large and rapid temperature changes. In embodiments, the protective layer includes a first layer embedded in a surface of the component and a second layer formed on the first layer. [Background technology]

[0003]

[0003] Semiconductor manufacturing processes typically involve heating a semiconductor substrate, such as a semiconductor wafer, to a high temperature and cooling it to a low temperature. In most manufacturing processes, such processes have a thermal budget, which sets a maximum heating temperature that cannot be exceeded without risking thermal damage to structures being formed on the substrate. Components of semiconductor manufacturing equipment that are in thermal contact with the substrate are selected in part for their ability to raise and lower the substrate to precise temperatures during the manufacturing process.

[0004] Conventional manufacturing components that contact substrates often contain ceramic materials that are stable and inert during manufacturing processes. These ceramics generate few contaminants to the substrate and do not react with corrosive species, such as reactive halogen, oxide, and nitride species, that are generated during many semiconductor manufacturing and cleaning processes. Unfortunately, these ceramic materials typically have poor thermal conductivity and are unable to rapidly change the temperature of adjacent substrates. Poor thermal conductivity can result in substrates remaining at high temperatures for extended periods of time, potentially resulting in operation beyond the thermal budget. Poor thermal conductivity also increases the time to complete thermal cycles, potentially reducing the productivity of manufacturing systems. The present technology addresses these and other problems with conventional components.

[0005] The nature and advantages of the present invention may be further understood by reference to the remaining portions of the specification and drawings, in which the same reference numerals are used throughout the several views to refer to like components. In some instances, a sub-label is associated with the reference numeral and follows a hyphen to indicate one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components. Summary of the Invention

[0006]

[0011] Embodiments of the present technology include a method of preparing a semiconductor manufacturing component. In embodiments, the method includes forming a first layer on a surface of the semiconductor manufacturing component. The first layer is characterized by a porosity of about 0.01 vol.% or greater. The method further includes depositing a second layer on the first layer, the second layer being characterized by a porosity of about 20 vol.% or less.

[0007]

[0012] In further embodiments, the first layer may be characterized by a thickness of about 0.01 μm or greater. In further embodiments, the first layer may be formed on the surface of the semiconductor fabrication component by an anodizing technique selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, thick barrier oxidation, and plasma electrolytic oxidation. In yet additional embodiments, the second layer may be characterized by a thickness of about 10 μm or less. In further embodiments, the second layer may be formed by a metal, metal boride, metal carbide, metal nitride, metal oxide, metal fluoride, metal oxyfluoride, or M1 x M2 y M3 z C a B b N c O d F ewhere M1, M2, and M3 are independently metals and x, y, z, a, b, c, d, and e are equal to or greater than 0. In further embodiments, the second layer may include a metal selected from the group consisting of aluminum, yttrium, erbium, scandium, zirconium, and magnesium. In more embodiments, the semiconductor manufacturing component may include aluminum. In even more embodiments, the surface in the semiconductor manufacturing component is a surface on a faceplate or heater element operable to be incorporated into a semiconductor manufacturing chamber.

[0008]

[0013] Additional embodiments of the present technology include methods of treating a semiconductor manufacturing component. In embodiments, the method includes forming a first layer on a surface of the semiconductor manufacturing component, the first layer including a grain structure characterized as amorphous, polycrystalline, crystalline, or mixed phase. The method further includes depositing a second layer on the first layer, the second layer characterized by an amorphous, polycrystalline, crystalline, or mixed phase grain structure. In some embodiments, the second layer is also characterized by a higher hardness than the first layer.

[0009]

[0014] In further embodiments, the first layer is characterized by a thickness of about 0.01 μm or greater. In additional embodiments, the first layer is formed on the surface of the semiconductor manufacturing component by plasma electrolytic oxidation. In further embodiments, the second layer is characterized by a thickness of about 1 μm or less. In further embodiments, the second layer is formed on the first layer by atomic layer deposition. In more embodiments, the second layer comprises a metal oxide, a metal fluoride, or a metal oxyfluoride.

[0010]

[0015] A further embodiment of the present technology includes a semiconductor manufacturing component. In an embodiment, the component includes a surface of the semiconductor manufacturing component. The component further includes a first layer formed on the surface of the semiconductor manufacturing component, the first layer characterized by a porosity of about 0.01 vol.% or greater. The component also includes a second layer positioned on the first layer, the second layer characterized by a porosity of about 20 vol.% or less.

[0011]

[0016] In many embodiments, the surface of the semiconductor manufacturing component comprises aluminum. In even more embodiments, the first layer is characterized by a thickness of about 50 μm or greater, and further characterized by an amorphous grain structure. In additional embodiments, the second layer is characterized by a thickness of about 10 μm or less, and further characterized by a crystalline grain structure. In further embodiments, the second layer comprises a metal oxide, a metal fluoride, a metal oxyfluoride, a metal nitride, a metal oxynitride, a metal carbide, a metal oxycarbide, a metal boride, or a stoichiometric mixture thereof. In further embodiments, the semiconductor manufacturing component can be a faceplate or a heater element operable to be incorporated into a semiconductor manufacturing chamber.

[0012]

[0017] The present technology offers several advantages over conventional semiconductor manufacturing components that do not include a protective layer or that have a single protective layer. When these conventional semiconductor manufacturing components include unprotected metal surfaces that contact a semiconductor substrate, such as a semiconductor wafer, they are prone to contaminating the substrate with metal from the surface. When the surface is protected by a single protective layer, such as a metal oxide layer deposited on the surface by atomic layer deposition (ALD), the difference in thermal expansion properties between the protective layer and the surface of the component can create significant thermal stresses, potentially causing the protective layer to crack and peel. The present technology addresses this issue by forming a first layer on the surface of the semiconductor manufacturing component, thereby reducing the thermal stress experienced by a second layer deposited on the first layer. The second layer can be characterized by lower porosity and higher crystallinity and hardness than the first layer. This helps prevent contaminant migration in either direction between the substrate processing area of ​​the manufacturing chamber and the metal on the surface of the semiconductor manufacturing component that it is protecting. These and other embodiments of the present method and component, along with many of their advantages and features, are described in more detail below in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 shows a flowchart including selected steps of an exemplary method for processing a manufacturing component, in accordance with an embodiment of the present technique. [Figure 2]

[0007] FIG. 1 shows a simplified cross-sectional view of a manufacturing component surface including a protective layer, according to an embodiment of the present technique. [Figure 3A]

[0008] FIG. 1 shows a simplified cross-sectional view of a manufacturing component surface including a first layer of a protective layer, in accordance with an embodiment of the present technique. [Figure 3B]

[0009] FIG. 1 illustrates a simplified cross-sectional view of a manufacturing component surface including first and second layers of a protective layer, in accordance with an embodiment of the present technique. [Figure 4] 1 shows a simplified cross-sectional view of a semiconductor manufacturing pedestal including a surface including a protective layer, in accordance with an embodiment of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0018] Many semiconductor manufacturing processes require rapid temperature changes of a substrate, such as a semiconductor wafer. These processes involve rapidly increasing the substrate temperature to facilitate the deposition or curing of a material on the substrate. The processes also involve rapidly decreasing the substrate temperature to maintain the manufacturing process within a thermal budget. To achieve these rapid substrate temperature changes, components of the manufacturing equipment are made from materials with enhanced thermal conductivity. These materials include metals and metal alloys, among others.

[0015]

[0019] Fabricating components from metals presents many challenges, including the potential for metal contamination of the substrate. Component manufacturers have addressed these challenges by depositing protective layers on surfaces of the component that come into direct or close contact with the substrate. For example, a thin protective layer of an inert material may be deposited on the component surface to prevent migration of metal species from the surface to the substrate. The protective layer may also prevent reactive species found in the fabrication chamber from migrating to the metal component surface and corroding the component. In a further embodiment, the protective layer may be made of a dielectric material that also prevents plasma arcing between the plasma generating equipment in the fabrication chamber and the coated metal surface of the component.

[0016]

[0020] Unfortunately, many conventional protective layers consist of a single thin coating layer with a significantly different thermal expansion coefficient than the underlying metal surface. When components are subjected to rapid temperature changes, the different expansion rates place severe mechanical stresses on the protective layer. After a relatively short number of thermal cycles, the protective layer can crack, flake off, and begin to delaminate from the underlying metal surface. This increases the amount of contaminants that can migrate between the metal surface and the substrate, creating a conductive path for plasma arc discharge. This results in significant chamber downtime while components with damaged protective layers are refurbished or replaced.

[0017]

[0021] The present technology addresses these and other problems with conventional protective layers by forming a protective layer that includes at least one intermediate layer between the surface of the component and the outer layer directly exposed to the substrate. In embodiments, the at least one intermediate layer can be formed on the surface of the component, for example, by anodization techniques. The intermediate layer is characterized by higher porosity and lower crystallinity than the outer layer. In embodiments, the one or more intermediate layers reduce mechanical stress on the outer layer during rapid temperature changes of the component. The more amorphous the structure of the intermediate layer, the shorter and more closed the pathway for contaminant migration between the metal surface of the component and the substrate. In further embodiments, the intermediate layer is complemented by an outer layer characterized by lower porosity, higher crystallinity, and increased corrosion resistance to reactive species in the chamber processing region. The combination of the intermediate layer and outer layer results in a multi-layer protective layer that can protect metal-containing components for many more process cycles than conventional single-layer protective layers.

[0018]

[0022] FIG. 1 illustrates a flowchart including selected steps in a method 100 of preparing a manufacturing component including a multilayer protective layer according to an embodiment of the present technology. Method 100 may or may not include one or more steps prior to the start of the method, including molding, stamping, machining, polishing, cleaning, or any other steps that may be performed before the described steps. The method may include optional steps that may or may not be particularly relevant to some embodiments of methods according to the present technology. Method 100 describes steps for preparing the surface of a manufacturing component, some of which are shown in FIG. 2 as component 200, some of which are shown in FIGS. 3A-B as component 300, and some of which are shown in FIG. 4 as pedestal component 402. It should be understood that FIGS. 2-4 illustrate only partial schematic views with limited detail. In further embodiments not illustrated, the exemplary component and protective layer structures may include additional layers, regions, and materials having the aspects as illustrated, as well as alternative structural and material aspects that may still benefit from any aspect of the present technology.

[0019]

[0023] Method 100 includes providing a manufacturing component in step 105. In embodiments, the manufacturing component processed by the method may include, among other manufacturing components, faceplates, heating elements, wafer chucks, and pedestals. In further embodiments, the manufacturing component includes a component that contacts or supports and positions a substrate (e.g., a semiconductor wafer) within a manufacturing processing chamber. In further embodiments, the manufacturing component is operable for use in corrosive processing environments where the component is frequently exposed to highly reactive species such as halogen species (e.g., chlorine-containing species, fluorine-containing species), oxide species, and nitride species, among other reactive species. In yet additional embodiments, the manufacturing component is operable even when exposed to frequent ion bombardment.

[0020]

[0024] As shown in FIG. 2 , layer 205 represents a portion of fabrication component 200 on which first layer 210 of the protective layer is formed. In embodiments, fabrication component 200 includes layer 205 having one or more surfaces of a material characterized by an increased thermal conductivity, which enables more rapid temperature changes of a substrate in thermal contact with the component. In additional embodiments, the material may be characterized by a thermal conductivity of about 25 W / (m·K) or greater, about 50 W / (m·K) or greater, about 75 W / (m·K) or greater, about 100 W / (m·K) or greater, about 125 W / (m·K) or greater, about 150 W / (m·K) or greater, about 175 W / (m·K) or greater, or about 200 W / (m·K) or greater.

[0021]

[0025] As noted above, many of the materials with enhanced thermal conductivity that can be incorporated into fabricated components are also characterized by an increased coefficient of thermal expansion. In embodiments, the material used to form one or more surfaces of the fabricated component has a linear coefficient of thermal expansion of about 10×10 -6 / ℃ or more, approximately 11 × 10 -6 / ℃ or more, approximately 12 × 10 -6 / ℃ or more, approximately 13 × 10 -6 / ℃ or more, approximately 14 × 10 -6 / ℃ or more, approximately 15 × 10 -6 / ℃ or more, approximately 16×10 -6 / ℃ or more, approximately 17×10 -6 / ℃ or more, approximately 18 × 10 -6 / ℃ or more, approximately 19 × 10 -6 / ℃ or more, approximately 20 × 10 -6 / °C or higher. In further embodiments, the fabricated component includes one or more metal-containing surfaces. In additional embodiments, the metal-containing surfaces of layer 205 may include one or more metals selected from the group consisting of aluminum, iron, copper, nickel, and titanium, among other metals.

[0022]

[0026] Method 100 may further include forming a first layer (e.g., first layer 210) on a surface of a layer (e.g., layer 205) of the fabrication component at step 110. In embodiments, a portion of the surface of layer 205 of the fabrication component may be incorporated into the first layer during step 110. In further embodiments, first layer 210 may be formed by an anodization technique that forms an anodic oxide layer on the surface of layer 205. In even more embodiments, the anodization technique may be selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, thick barrier oxidation, and plasma electrolytic oxidation, among other anodization techniques. In additional embodiments, first layer 210 may be characterized by a thickness of about 0.01 μm or greater, about 1 μm or greater, about 10 μm or greater, about 25 μm or greater, about 30 μm or greater, about 35 μm or greater, about 40 μm or greater, about 45 μm or greater, about 50 μm or greater, or greater.

[0023]

[0027] In embodiments, the first layer 210 may be characterized as being more porous and amorphous than the subsequently deposited second layer 215. In additional embodiments, the increased porosity of the first layer 210 provides mechanical stress buffering to the second layer 215 by having an intermediate coefficient of thermal expansion (CTE) between the component surface layer 205 and the second layer. In further embodiments, the more amorphous grain structure of the first layer 210 results in fewer channels extending through the first layer from the surface layer 205 to the second layer 215. The fewer these channels, the fewer opportunities there are for metal contaminants from the surface layer 205 to migrate through the first layer 210 and for reactive species from the processing chamber to migrate to the surface layer. Additionally, the reduced number of long channels in the first layer 210 reduces plasma arcing between the plasma region of the processing chamber and the conductive metal on the surface layer 205.

[0024]

[0028] In additional embodiments, the first layer 210 may be characterized by a porosity of about 0.01 vol.% or greater of the total volume of the layer. In more embodiments, the first layer 210 may be characterized by a porosity of about 0.1 vol.% or greater, about 0.5 vol.% or greater, about 1 vol.% or greater, about 2 vol.% or greater, about 3 vol.% or greater, about 4 vol.% or greater, about 5 vol.% or greater, or greater. In further embodiments, the first layer 210 may be characterized as an amorphous layer or a polycrystalline layer. In further embodiments, the first layer 210 may be characterized by an average crystallinity of about 50% or less, about 40% or less, about 30% or less, about 20% or less, about 10% or less, or less. In even more embodiments, the first layer 210 may be characterized by a linear thermal expansion coefficient less than the CTE of the material of the surface layer 205. In embodiments, first layer 210 may be characterized by a CTE that is reduced to about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, or less than the CTE of the material of surface layer 205. In more embodiments, first layer 210 may be characterized by a CTE that is greater than the CTE of second layer 215. In additional embodiments, first layer 210 may be characterized by a CTE that is about 50% or more, about 60% or more, about 90% or more, about 80% or more, about 90% or more, or more than the CTE of second layer 215.

[0025]

[0029] In more embodiments, first layer 210 may include one or more metals selected from the group consisting of aluminum, iron, copper, nickel, titanium, and chromium, among other metals. In additional embodiments, first layer 210 may include at least one oxide of one or more metals, such as aluminum oxide (Al2O3) or titanium oxide (TiO2), among other metal oxides.

[0026]

[0030] In some embodiments, forming the first layer of the protective layer in step 110 can include anodizing the surface of the metal-containing component by plasma electrolytic oxidation (PEO). FIG. 3A shows a portion of a metal-containing component 302 having a first layer 304 incorporated by PEO on the exposed surface of the component. In embodiments, the PEO process includes exposing one or more surfaces of the metal-containing component 302 to an electrolyte solution while applying a bias voltage to the component. In further embodiments, the electrolyte solution can be an alkaline aqueous solution characterized by a pH greater than 7, about 8 or greater, about 9 or greater, about 10 or greater, or greater. In further embodiments, the electrolyte solution can include one or more dissolved alkali metal hydroxides and alkaline earth metal hydroxides, among other salts. In more embodiments, the voltage applied to the component during the PEO process can be about 200 volts or greater, about 250 volts or greater, about 300 volts or greater, about 350 volts or greater, about 400 volts or greater, about 450 volts or greater, about 500 volts or greater, or greater.

[0027]

[0031] In embodiments, the PEO-formed first layer 304 may include multiple cracks, exemplified by crack 306, that form during the anodization process. In further embodiments, crack 306 may extend from the top surface of the first layer down to the surface of the metal-containing component 302. If left exposed, crack 306 could provide a path for contaminants and plasma arcing. As described below, the multiple cracks, including crack 306, are sealed by second layer 308 to prevent contaminant migration and plasma arcing.

[0028]

[0032] The method 100 may further include depositing a second layer (e.g., second layer 215, 308) on the first layer (e.g., first layer 210) at step 115. The second layer 215 may have a lower porosity than the first layer 210. The low porosity of the second layer 215 may hinder the migration of contaminants between the surface of layer 215 and a substrate (not shown) in contact with the component 200. In embodiments, the second layer 215 may be characterized by a porosity of about 20 vol.% or less, about 15 vol.% or less, about 10 vol.% or less, about 5 vol.% or less, about 1 vol.% or less, about 0.1 vol.% or less, about 0.05 vol.% or less, about 0.001 vol.% or less, or less. As shown in FIG. 3B, the second layer 308 can also fill cracks 306 in the PEO-formed first layer 304 to prevent contaminant migration and plasma arcing during substrate processing steps.

[0029]

[0033] In embodiments, the second layer may comprise one or more of a metal, a metal boride, a metal carbide, a metal oxide, a metal nitride, a metal oxynitride, a metal fluoride, a metal oxyfluoride, a metal fluoronitride, and a metal oxyfluoronitride, among other materials. In further embodiments, the second layer may comprise a metal of the formula MO x , M.N. y , M.O. x N y , M.F. z , M.O. x F z , M.O. x N y F z where M represents one or more metals selected from the group consisting of Al, Y, Er, Sc, Zr, Ni, Cr, Mg, Ti, Ta, and W, among other metals, and x, y, and z may comprise integers from 1 to 6. In more embodiments, M represents one or more rare earth elements. In even more embodiments, the second layer may include one or more materials selected from the group consisting of AlO3, AlF3, and AlF3-MgF2, among other materials. In further embodiments, the second layer may include one or more materials represented by the formula M1 x M2 y M3 z C aB b N c O d F e wherein M1, M2, and M3 are independently metals and x, y, z, a, b, c, d, and e are independently greater than or equal to 0. In more embodiments, x, y, z, a, b, c, d, and e are independently greater than 0. In still additional embodiments, metals M1, M2, and M3 may each independently be selected from the group consisting of Al, Y, Er, Sc, Zr, Ni, Cr, Mg, Ti, Ta, and W, among other metals.

[0030]

[0034] In further embodiments, the second layer may have improved corrosion resistance compared to the first layer formed on the component surface. In further embodiments, corrosion resistance may include resistance of the second layer to reaction with one or more reactive species in contact with the second layer. In embodiments, these reactive species may include oxygen-containing species and halogen-containing species (such as chlorine-containing and fluorine-containing species), among other reactive species. In more embodiments, corrosion resistance may include a slower etch rate of the second layer when exposed to one or more reactive species. In further embodiments, the second layer may be characterized by improved corrosion resistance, as measured by a reduction in etch rate of about 10% or more, about 25% or more, about 50% or more, about 75% or more, about 100% or more, compared to the first layer.

[0031]

[0035] In additional embodiments, the second layer 215 comprising a metal oxide can be deposited using an ALD process that includes alternating exposure of the substrate to a first precursor and a second precursor. In further embodiments, the first precursor can be a metal-containing precursor and the second precursor can be an oxygen-containing precursor. The ALD process can be advantageously performed when the substrate exhibits a non-planar topography as a result of the conformal nature of the ALD process. The ALD process is also suitable for deposition on substantially planar surfaces.

[0032]

[0036] In further embodiments, ALD depositing the second layer 215, which is a metal oxide, can include depositing a metal oxide material on the first layer 210. In more embodiments, the metal oxide material can include one or more of aluminum oxide, lanthanum oxide, hafnium oxide, yttrium oxide, zirconium oxide, and cerium oxide, among other metal oxide materials. In additional embodiments, the metal oxide material can be deposited by alternatingly exposing the first layer 210 to a first metal-containing precursor and a second oxygen-containing precursor. In embodiments, the first metal-containing precursor may include one or more precursors such as (tert-butylimido)tris(diethylamido)tantalum (TBTDET), tetrakis(diethylamido)titanium (TDEAT), tetrakis(dimethylamino)titanium (TDMAT), tetrakis(ethylmethylamido)titanium (TEMAT), trimethylaluminum (TMA), pentakis(dimethylamino)tantalum(V) (PDMAT), tetrakis(dimethylamido)hafnium (Hf(NMe2)4)(TDMAH), tetrakis(dimethylamido)zirconium (Zr(NMe2)4)(TDMAZ), [Ce(thd)4], [Ce(thd)3phen], [Ce(Cp)3], [Ce(CpMe)3], [Ce(iprCp)3], among other metal-containing precursors. In further embodiments, the second oxygen-containing precursor may include one or more of nitrous oxide (NO), oxygen (O), ozone (O), water vapor (HO), carbon monoxide (CO), carbon dioxide (CO), among other oxygen-containing precursors.

[0033]

[0037] In additional embodiments, the component including the first layer 210 may be heated during deposition of the second layer 215. In further embodiments, the component may be heated to about 100° C. or greater, about 150° C. or greater, about 200° C. or greater, about 250° C. or greater, about 300° C. or greater, about 350° C. or greater, about 400° C. or greater, or greater.

[0034]

[0038] In embodiments, the first metal-containing precursor for the second layer 215 may be flowed into the processing chamber at a flow rate of about 200 sccm or more, about 400 sccm or more, about 600 sccm or more, about 800 sccm or more, about 1000 sccm or more, or more. In additional embodiments, the first metal-containing precursor is introduced into the processing chamber with a carrier gas (e.g., an inert gas such as nitrogen). In yet other embodiments, the first precursor may be pulsed into the processing chamber. As used herein, the term "pulse" is intended to refer to an amount of a particular compound that is intermittently or discontinuously introduced into the reaction zone of the processing chamber. In embodiments, a monolayer of the first precursor may be formed on the substrate as a result of the pulsing. In more embodiments, the first metal-containing precursor can be pulsed into the processing chamber for about 100 milliseconds (ms) or more, about 200 ms or more, about 300 ms or more, about 400 ms or more, about 500 ms or more, about 600 ms or more, about 700 ms or more, about 800 ms or more, about 900 ms or more, about 1000 ms or more, or more. In even more embodiments, the first metal-containing precursor can be heated to a temperature of about 25°C or more, about 50°C or more, about 75°C or more, about 100°C or more, about 125°C or more, or more.

[0035]

[0039] In more embodiments, a purge step can be performed before flowing the second oxygen-containing precursor into the processing chamber. In further embodiments, the purge step can include flowing a purge gas into the processing chamber after reducing or stopping the supply of the first metal-containing precursor to the substrate. In further embodiments, the purge process can include pulsing a purge gas, such as argon gas or nitrogen gas, into the processing chamber for about 0.5 seconds or more, about 1 second or more, about 2.5 seconds or more, about 5 seconds or more, about 7.5 seconds or more, about 10 seconds or more, or more.

[0036]

[0040] In yet additional embodiments, the second oxygen-containing precursor may be pulsed into the processing chamber for about 0.15 seconds or more, about 0.5 seconds or more, about 1 second or more, about 2.5 seconds or more, about 5 seconds or more, about 10 seconds or more, about 15 seconds or more, about 20 seconds or more, about 25 seconds or more, about 30 seconds or more, or more. In additional embodiments, the second oxygen-containing precursor may be flowed into the processing chamber at a flow rate of about 50 sccm or more, about 100 sccm or more, about 200 sccm or more, about 400 sccm or more, about 600 sccm or more, about 800 sccm or more, about 1000 sccm or more, or more. In even more embodiments, the second oxygen-containing precursor may be heated to about 20° C. or more, about 25° C. or more, about 30° C. or more, or more. In embodiments, a plasma is generated in the processing chamber while the second oxygen-containing precursor is flowed into the processing chamber. In a further embodiment, the plasma can be generated by applying RF power to a plasma generator, such as an ICP coil assembly or a CCP assembly. For example, the RF generator can apply RF power of between about 100 W and about 300 W (e.g., about 200 W) to the ICP coil assembly or the CCP assembly at a frequency of 13.56 MHz.

[0037]

[0041] In yet further embodiments, following the pulsing of the second oxygen-containing precursor, another purge process can be performed. The second purge process can be performed to remove any remaining second precursor in the processing chamber. Similar to the purge process for the first metal-containing precursor, the additional purge process can include pulsing a purge gas, such as argon, into the processing chamber for about 0.5 seconds or more, about 1 second or more, about 2.5 seconds or more, about 5 seconds or more, about 7.5 seconds or more, about 10 seconds or more, or more.

[0038]

[0042] In embodiments, the pulsing of the first metal-containing precursor and the second oxygen-containing precursor into the processing chamber can be a cycle. The cycle can include first and second purge processes after the first precursor is flowed into the processing chamber and after the second precursor is flowed into the processing chamber. In further embodiments, the cycle is repeated to grow a metal oxide layer. The number of cycles is based on the final thickness of the metal oxide layer. In embodiments, the growth rate of the metal oxide layer can be about 0.25 Å / cycle or more, about 0.5 Å / cycle or more, about 0.75 Å / cycle or more, about 1 Å / cycle or more, about 1.5 Å / cycle or more, about 2 Å / cycle or more, or more. For example, the growth rate of the metal oxide layer can be about 1 Å per cycle, depending on the precursor material used. The final thickness of the metal oxide layer can be about 1 μm or less, about 0.9 μm or less, about 0.8 μm or less, about 0.7 μm or less, about 0.6 μm or less, about 0.5 μm or less, about 0.4 μm or less, about 0.3 μm or less, about 0.2 μm or less, about 0.1 μm or less, or less.

[0039]

[0043] In a further embodiment, the second layer 215 comprises a metal nitride, which may be deposited using an ALD process that includes alternatingly exposing the substrate to a first precursor and a second precursor. In a further embodiment, the first precursor may be a metal-containing precursor and the second precursor may be a nitrogen-containing precursor. The ALD process may be advantageously performed when the substrate exhibits a non-planar topography as a result of the conformal nature of the ALD process. The ALD process is also suitable for deposition on substantially planar surfaces.

[0040]

[0044] In still additional embodiments, the first metal-containing precursor can include any suitable metal-containing precursor for forming a metal nitride film, such as aluminum, titanium, or tantalum. In embodiments, the first metal-containing precursor is selected from the group including (tert-butylimido)tris(diethylamido)tantalum (TBTDET), tetrakis(diethylamido)titanium (TDEAT), tetrakis(dimethylamino)titanium (TDMAT), tetrakis(ethylmethylamido)titanium (TEMAT), trimethylaluminum (TMA), pentakis(dimethylamino)tantalum(V) (PDMAT), and combinations thereof. In some embodiments, the metal-containing precursor does not include fluorine. In more embodiments, the second nitrogen-containing precursor is selected from the group including ammonia (NH), hydrazine (NH), methylhydrazine (CH(NH)NH), dimethylhydrazine (CHN), t-butylhydrazine (CH), among other nitrogen-containing precursors. 12 N2), phenylhydrazine (C6H8N2), azoisobutane (C4H8N2), ethyl azide (CH3N3).

[0041]

[0045] In additional embodiments, the second layer 215 comprising a metal oxyfluoride or metal fluoronitride can be deposited using an ALD process comprising alternating exposure of the substrate to a first precursor, a second precursor, and a third precursor. In additional embodiments, the first precursor can be a metal-containing precursor, the second precursor can be an oxygen-containing and / or nitrogen-containing precursor, and the third precursor can be a fluorine-containing precursor. In yet additional embodiments, the metal oxyfluoride or metal fluoronitride layer can be deposited by ALD using alternating exposure of a first metal-containing precursor and a second oxyfluoride-containing and / or fluoronitride-containing precursor. In embodiments, the ALD process can be advantageously performed when the substrate exhibits a non-planar topography as a result of the conformal nature of the ALD process. The ALD process is also suitable for deposition on substantially planar surfaces.

[0042]

[0046] FIG. 4 illustrates a heated pedestal 400 including a substrate chuck 402 including a multi-layer protective layer in accordance with an embodiment of the present technology. A substrate 404 is placed in direct contact with the substrate chuck 402 during one or more substrate processing steps. These steps may include raising and lowering the temperature of the substrate during one or more of the processing steps. The substrate chuck 402 includes one or more metals, such as aluminum, which has a higher thermal conductivity than conventional ceramic materials, facilitating more rapid temperature changes of the substrate 404 during processing steps. A multi-layer protective layer (not shown) positioned between the substrate 404 and the metal surface of the substrate chuck 402 prevents contaminants within the chuck, including metals used in fabricating the chuck, from migrating to the substrate. The protective layer also reduces plasma arcing between the substrate chuck 402 and the plasma during plasma generation steps.

[0043]

[0047] It should be understood that the substrate chuck 402 including a multi-layer protective coating according to embodiments of the present technology is just one of many types of substrate processing components that may include a protective coating. Additional substrate processing components include faceplates and heating elements, among other substrate processing components. The multi-layer protective coating provides several benefits to the components, including improved corrosion resistance, increased hardness, reduced metal contamination of substrates contacting the components, and reduced incidence of plasma arcing during plasma operation, among other benefits.

[0044]

[0048] While several embodiments have been described, those skilled in the art will recognize that various modifications, alternative configurations, or equivalents may be used without departing from the essence of the invention. Additionally, in order to avoid unnecessarily obscuring the invention, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the invention.

[0045]

[0049] Where a range of values ​​is provided, it is understood that each intervening value between the upper and lower limits of that range is also expressly disclosed, to the tenth of the unit of the lower limit, unless the context clearly indicates otherwise. Each narrower range between any stated or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these narrower ranges may be individually included or excluded within the range, and each range where either limit is included within the narrower range, neither limit is included within the narrower range, or both limits are included within the narrower range, is also encompassed within the invention, subject to any explicitly excluded limit in the stated range. When a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0046]

[0050] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a process" includes a plurality of such processes; a reference to "the pixel structure" includes a reference to one or more pixel structures and equivalents thereof known to those skilled in the art, and so forth.

[0047]

[0051] The words "comprise" and "include" when used in this specification and the claims that follow are also intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A method for preparing a semiconductor manufacturing component, comprising: forming a first layer on a surface of the semiconductor manufacturing component, the first layer being characterized by a porosity of about 0.01 vol. % or greater; depositing a second layer on the first layer, the second layer being characterized by a porosity of about 20 vol. % or less; A method comprising:

2. 10. The method of claim 1, wherein the first layer has a thickness of about 0.01 μm or greater.

3. 10. The method of claim 1, wherein the first layer is formed on the surface by an anodizing technique selected from the group consisting of anodic aluminum oxidation, anodic titanium oxidation, thick barrier oxidation, and plasma electrolytic oxidation.

4. 10. The method of claim 1, wherein the second layer has a thickness of about 10 [mu]m or less.

5. The second layer may be a metal, a metal boride, a metal carbide, a metal nitride, a metal oxide, a metal fluoride, a metal oxyfluoride, or a metal oxide. ｘ M2 ｙ M3 ｚ C ａ B ｂ N ｃ O ｄ F ｅ wherein M1, M2, and M3 are independently metals, and x, y, z, a, b, c, d, and e are 0 or greater.

6. The method of claim 5 , wherein the second layer comprises a metal selected from the group consisting of aluminum, yttrium, ebullium, scandium, zirconium, and magnesium.

7. The method of claim 1 , wherein the surface of the semiconductor manufacturing component comprises aluminum.

8. 10. The method of claim 1, wherein the surface on the semiconductor manufacturing component is a surface on a faceplate or heater element operable to be incorporated into a semiconductor manufacturing chamber.

9. 1. A method for processing a semiconductor manufacturing component, the method comprising: forming a first layer on a surface of the semiconductor fabrication component, the first layer comprising a grain structure characterized as amorphous, polycrystalline, crystalline, or mixed phase; depositing a second layer on the first layer, the second layer being characterized by an amorphous, polycrystalline, crystalline, or mixed phase grain structure; A method comprising:

10. 10. The method of claim 9, wherein the first layer has a thickness of about 0.01 μm or greater.

11. The method of claim 9 , wherein the first layer is formed on the surface by plasma electrolytic oxidation.

12. 10. The method of claim 9, wherein the second layer has a thickness of about 10 μm or less.

13. 10. The method of claim 9, wherein the second layer is formed on the first layer by atomic layer deposition.

14. The method of claim 9 , wherein the second layer comprises a metal oxide, a metal fluoride, or a metal oxyfluoride.

15. 1. A semiconductor manufacturing component comprising: a surface of the semiconductor manufacturing component; a first layer formed on the surface of the semiconductor manufacturing component, the first layer being characterized by a porosity of about 0.01 vol. % or greater; a second layer positioned on the first layer, the second layer having a porosity of about 20 vol. % or less; 1. A semiconductor manufacturing component comprising:

16. The semiconductor manufacturing component of claim 15 , wherein the surface of the semiconductor manufacturing component comprises aluminum.

17. 16. The semiconductor manufacturing component of claim 15, wherein the first layer is characterized by a thickness of about 0.01 μm or greater, and further characterized by the first layer having an amorphous grain structure.

18. 16. The semiconductor manufacturing component of claim 15, wherein the second layer is characterized by a thickness of about 10 microns or less, and further characterized by the second layer being crystalline in grain structure.

19. 16. The semiconductor manufacturing component of claim 15, wherein the second layer comprises a metal oxide, a metal fluoride, a metal oxyfluoride, a metal nitride, a metal oxynitride, a metal carbide, a metal oxycarbide, a metal boride, or a stoichiometric mixture thereof.

20. 16. The semiconductor manufacturing component of claim 15, wherein the component is a faceplate or heater element operable to be incorporated into a semiconductor manufacturing chamber.

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