Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed below the first insulating layer, and an electrode portion including a through electrode that penetrates at least one of the first to third insulating layers, wherein the electrode portion includes a first electrode portion including a 1-1 pad electrode disposed on the upper surface of the first insulating layer, a 1-2 pad electrode disposed on the lower surface of the first insulating layer, and a first through electrode that penetrates the first insulating layer and is connected to the 1-1 and 1-2 pad electrodes, and a second electrode portion including a 2-1 pad electrode disposed on the upper surface of the second insulating layer, a 2-2 pad electrode disposed on the lower surface of the third insulating layer, and a second through electrode that commonly penetrates the first to third insulating layers and is connected to the 2-1 and 2-2 pad electrodes, wherein the electrode portion includes a first electrode pattern that horizontally overlaps the second through electrode of the second electrode portion, and the second through electrode is horizontally spaced apart from the first electrode pattern.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a board with limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which the semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). Therefore, semiconductor packages include interposers to connect multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in response to the trend toward high integration. Here, high performance includes the ability to transmit signals at high speeds, integration of the semiconductor package, and a high allowable current for transmittable signals.

[0005] In order to achieve miniaturization and integration of semiconductor packages, pad sizes are being reduced. The pads may be mounting pads connected to a chip or bump pads connected to various substrates. Here, the various substrates may include additional packages such as memory substrates, interposers connecting a chip to a circuit board, and main boards of electronic devices to which the semiconductor package is applied.

[0006] Such circuit boards are provided with a multi-layer structure, including an insulating layer such as a copper clad laminate (CCL) and a through electrode disposed in a through hole that penetrates the insulating layer.

[0007] However, since the through electrodes according to the prior art have a structure that penetrates only at least one specific insulating layer, and therefore at least one pad is provided between the through electrodes spaced apart in the thickness direction, the signal transmission distance of the circuit board according to the prior art can be increased by the pad provided in the through electrode, and the signal transmission loss can increase as the signal transmission distance increases. Summary of the Invention [Problem to be solved by the invention]

[0008] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0009] The present embodiment also provides a circuit board including a through electrode that commonly penetrates a plurality of insulating layers, and a semiconductor package including the circuit board.

[0010] Furthermore, this embodiment provides a circuit board in which a plurality of through electrodes have different through structures depending on the function of the through electrodes, and a semiconductor package including the same.

[0011] In addition, the present embodiment provides a circuit board having a structure in which the side of a through electrode that penetrates a plurality of insulating layers is not directly connected to another pad, and a semiconductor package including the same.

[0012] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0013] A circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed below the first insulating layer, and an electrode portion including a through electrode that penetrates at least one of the first to third insulating layers, wherein the electrode portion includes a first electrode portion including a 1-1 pad electrode disposed on an upper surface of the first insulating layer, a 1-2 pad electrode disposed on a lower surface of the first insulating layer, and a first through electrode that penetrates the first insulating layer and is connected to the 1-1 and 1-2 pad electrodes, and a second electrode portion including a 2-1 pad electrode disposed on an upper surface of the second insulating layer, a 2-2 pad electrode disposed on a lower surface of the third insulating layer, and a second through electrode that commonly penetrates the first to third insulating layers and is connected to the 2-1 and 2-2 pad electrodes, wherein the electrode portion includes a first electrode pattern that horizontally overlaps the second through electrode of the second electrode portion, and the second through electrode is horizontally spaced apart from the first electrode pattern.

[0014] Additionally, the first insulating layer includes a first insulating material that includes glass fibers, and the second and third insulating layers include a second insulating material that does not include glass fibers.

[0015] The first through electrode also includes a first slope adjacent to the upper surface of the first insulating layer and having a width that decreases toward the lower surface of the first insulating layer, and a second slope adjacent to the lower surface of the first insulating layer and having a width that decreases toward the upper surface of the first insulating layer.

[0016] The second through electrode also includes a third slope adjacent to the upper surface of the second insulating layer and having a width that decreases toward the lower surface of the third insulating layer, and a fourth slope adjacent to the lower surface of the third insulating layer and having a width that decreases toward the upper surface of the second insulating layer.

[0017] The side surfaces of the second through electrode having the third and fourth inclinations are not connected to the first electrode pattern and are entirely covered with the first to third insulating layers.

[0018] The second through electrode also includes a portion where the slope changes between the third slope and the fourth slope, and the portion where the slope changes is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer.

[0019] The electrode portion also includes a third electrode portion including a 3-1 pad electrode arranged on the lower surface of the first insulating layer, a 3-2 pad electrode arranged on the upper surface of the second insulating layer, and a third through electrode that commonly penetrates the first and second insulating layers and is connected to the 3-1 and 3-2 pad electrodes.

[0020] In addition, the electrode unit includes a second electrode pattern that horizontally overlaps the third through-electrode of the third electrode unit, and the third through-electrode is horizontally spaced apart from the second electrode pattern and is not directly connected to the second electrode pattern.

[0021] In addition, the third through electrode has a fifth slope whose width decreases from the 3-1 pad electrode to the 3-2 pad electrode, a lower end of the fifth slope of the third through electrode is directly connected to the 3-1 pad electrode, an upper end of the fifth slope of the third through electrode is directly connected to the 3-2 pad electrode, and a side of the third through electrode having the fifth slope is entirely covered via the first and second insulating layers.

[0022] The electrode portion also includes a fourth electrode portion including a 4-1 pad electrode arranged on the lower surface of the first insulating layer, a 4-2 pad electrode arranged on the upper surface of the second insulating layer, and a fourth through electrode that penetrates the second insulating layer and is connected to the 4-1 and 4-2 pad electrodes.

[0023] On the other hand, a circuit board according to another embodiment includes a first insulating layer, a second insulating layer arranged on the first insulating layer, a third insulating layer arranged below the first insulating layer, and an electrode portion including a through electrode that penetrates at least one of the first to third insulating layers, wherein the electrode portion includes a first electrode portion including a 1-1 pad electrode arranged on an upper surface of the first insulating layer, a 1-2 pad electrode arranged on a lower surface of the first insulating layer, and a first through electrode that penetrates the first insulating layer and is connected to the 1-1 and 1-2 pad electrodes, and a second electrode portion including a 2-1 pad electrode arranged on an upper surface of the second insulating layer, a 2-2 pad electrode arranged on a lower surface of the third insulating layer, and a second through electrode that commonly penetrates the first to third insulating layers and is connected to the 2-1 and 2-2 pad electrodes, wherein the electrode portion includes a first electrode pattern that horizontally overlaps the second through electrode of the second electrode portion, and the second through electrode is spaced apart horizontally from the first electrode pattern.

[0024] Additionally, the first insulating layer includes a first insulating material that includes glass fibers, and the second and third insulating layers include a second insulating material that does not include glass fibers.

[0025] The first through electrode also includes a first slope adjacent to the upper surface of the first insulating layer and having a width that decreases toward the lower surface of the first insulating layer, and a second slope adjacent to the lower surface of the first insulating layer and having a width that decreases toward the upper surface of the first insulating layer.

[0026] The second through electrode also includes a third slope adjacent to the upper surface of the second insulating layer and having a width that decreases toward the lower surface of the third insulating layer, and a fourth slope adjacent to the lower surface of the third insulating layer and having a width that decreases toward the upper surface of the second insulating layer.

[0027] The side surfaces of the second through electrode having the third and fourth inclinations are not connected to the first electrode pattern and are entirely covered with the first to third insulating layers.

[0028] The second through electrode also includes an inflection portion where the inclination changes between the third inclination and the fourth inclination, and the inflection portion is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer.

[0029] The electrode portion also includes a third electrode portion including a 3-1 pad electrode arranged on the lower surface of the first insulating layer, a 3-2 pad electrode arranged on the upper surface of the second insulating layer, and a third through electrode that commonly penetrates the first and second insulating layers and is connected to the 3-1 and 3-2 pad electrodes.

[0030] The electrode unit includes a second electrode pattern that horizontally overlaps the third through-electrode of the third electrode unit, and the third through-electrode is not directly connected to the second electrode pattern.

[0031] In addition, the third through electrode has a fifth slope whose width decreases from the 3-1 pad electrode to the 3-2 pad electrode, a lower end of the fifth slope of the third through electrode is directly connected to the 3-1 pad electrode, an upper end of the fifth slope of the third through electrode is directly connected to the 3-2 pad electrode, and a side of the third through electrode having the fifth slope is entirely covered via the first and second insulating layers.

[0032] The electrode portion also includes a fourth electrode portion including a 4-1 pad electrode arranged on the lower surface of the first insulating layer, a 4-2 pad electrode arranged on the upper surface of the second insulating layer, and a fourth through electrode that penetrates the second insulating layer and is connected to the 4-1 and 4-2 pad electrodes.

[0033] The electrode portion also includes a fifth electrode portion including a 5-1 pad electrode arranged on the upper surface of the first insulating layer, a 5-2 pad electrode arranged on the lower surface of the third insulating layer, and a fifth through electrode that commonly penetrates the first and third insulating layers and is connected to the 5-1 and 5-2 pad electrodes.

[0034] The electrode unit includes a third electrode pattern that horizontally overlaps the fifth through-electrode of the fifth electrode unit, and the fifth through-electrode is not directly connected to the third electrode pattern.

[0035] In addition, the fifth through electrode has a seventh slope whose width increases from the 5-1 pad electrode to the 5-2 pad electrode, an upper end of the seventh slope of the fifth through electrode is directly connected to the 5-1 pad electrode, a lower end of the seventh slope of the fifth through electrode is directly connected to the 5-2 pad electrode, and a side of the fifth through electrode having the seventh slope is entirely covered via the first and third insulating layers.

[0036] The electrode portion also includes a sixth electrode portion including a 6-1 pad electrode arranged on the lower surface of the first insulating layer, a 6-2 pad electrode arranged on the lower surface of the third insulating layer, and a sixth through electrode that penetrates the third insulating layer and is connected to the 6-1 and 6-2 pad electrodes.

[0037] The second through electrode includes a 2-1 through electrode that commonly penetrates the first to third insulating layers, and a 2-2 through electrode that commonly penetrates the first to third insulating layers and is horizontally spaced apart from the 2-1 through electrode, and the upper surfaces of the 2-1 and 2-2 through electrodes are commonly connected to the 2-1 pad electrode, and the lower surfaces of the 2-1 and 2-2 through electrodes are commonly connected to the 2-2 pad electrode.

[0038] On the other hand, a semiconductor package according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed below the first insulating layer, an electrode portion including a through electrode penetrating at least one of the first to third insulating layers, a connection portion disposed on the electrode portion, and a linking member disposed on the connection portion, wherein the electrode portion includes a first electrode portion including a 1-1 pad electrode disposed on an upper surface of the first insulating layer, a 1-2 pad electrode disposed on a lower surface of the first insulating layer, and a first through electrode penetrating the first insulating layer and connected to the 1-1 and 1-2 pad electrodes, a 2-1 pad electrode disposed on an upper surface of the second insulating layer, a 2-2 pad electrode disposed on a lower surface of the third insulating layer, and a 2-3 pad electrode commonly penetrating the first to third insulating layers and connected to the 2- a second electrode unit including a second through electrode connected to the first and second pad electrodes; a third electrode unit including a 3-1 pad electrode arranged on the lower surface of the first insulating layer, a 3-2 pad electrode arranged on the upper surface of the second insulating layer, and a third through electrode that commonly penetrates the first and second insulating layers and is connected to the 3-1 and 3-2 pad electrodes; and a fourth electrode unit including a 4-1 pad electrode arranged on the upper surface of the first insulating layer, a 4-2 pad electrode arranged on the lower surface of the third insulating layer, and a fourth through electrode that commonly penetrates the first and third insulating layers and is connected to the 4-1 and 4-2 pad electrodes, wherein the electrode unit includes a first electrode pattern that horizontally overlaps the second through electrode of the second electrode unit, and the second through electrode is not directly connected to the first electrode pattern.

[0039] The connecting member may include at least one of a package substrate, an interposer, a semiconductor device, a silicon bridge substrate, and an organic bridge substrate. [Effects of the Invention]

[0040] The circuit board of the embodiment may include first to third insulating layers. The circuit board may also include a first through-hole electrode that penetrates the first insulating layer alone and a second through-hole electrode that penetrates the first to third insulating layers in common. The side surfaces of the first through-hole electrode may include first and second slopes that are different from each other. The side surfaces of the second through-hole electrode may include third and fourth slopes that are different from each other. The side surfaces of the second through-hole electrode having the third and fourth slopes may not be directly connected to other pad electrodes or traces. This minimizes the transmission distance of signals transmitted through the second through-hole electrode, thereby minimizing signal transmission loss of signals transmitted through the second through-hole electrode.

[0041] For example, according to the prior art, a pad electrode is provided between the first insulating layer and the second insulating layer, thereby directly connecting the second through electrode to the pad electrode provided between the first insulating layer and the second insulating layer. As a result, a signal transmitted through the second through electrode in the prior art can be transmitted along the pad electrode provided between the first insulating layer and the second insulating layer. For example, when a high-frequency signal is transmitted, the signal can flow along the surface of the electrode portion. According to the prior art, the signal flows along the pad electrode provided between the first insulating layer and the second insulating layer, thereby increasing the signal transmission distance. Furthermore, as the signal distance increases, signal transmission loss also increases.

[0042] In contrast, an embodiment may include a second through-hole electrode disposed between the 2-1 pad electrode and the 2-2 pad electrode and penetrating multiple insulating layers. The second through-hole electrode may not be directly connected to pad electrodes other than the 2-1 pad electrode and the 2-2 pad electrode. For example, the circuit board may include a pad electrode and a trace that horizontally overlaps a side surface of the second through-hole electrode, and the pad electrode and the trace that horizontally overlaps a side surface of the second through-hole electrode may not be directly connected to the side surface of the second through-hole electrode. As a result, the embodiment may reduce the transmission distance of signals flowing through the second through-hole electrode and minimize resulting signal transmission loss. Therefore, the embodiment may improve the communication characteristics of the circuit board and a semiconductor package including the same, and further may enable stable operation of a semiconductor device included in the semiconductor package.

[0043] Meanwhile, the second through electrode may include a 2-1 through electrode and a 2-2 through electrode spaced apart in the horizontal direction. The 2-1 and 2-2 through electrodes may be commonly connected to a 2-1 pad electrode and a 2-2 pad electrode, respectively. The 2-1 and 2-2 through electrodes may perform a heat dissipation function. Furthermore, a plurality of through electrodes performing the heat dissipation function may be provided spaced apart from each other in the horizontal direction, and the plurality of through electrodes may be connected to a common pad electrode. This may improve the heat dissipation characteristics of a circuit board and a semiconductor package including the same, thereby enabling stable operation of a semiconductor device. [Brief explanation of the drawings]

[0044] [Figure 1a] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a cross-sectional view showing a semiconductor package according to a sixth embodiment. [Figure 1g] FIG. 13 is a cross-sectional view showing a semiconductor package according to a seventh embodiment. [Figure 2] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 5] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 6] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 7] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 8] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 9] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 10] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 11] 3A to 3C are cross-sectional views showing a method for manufacturing the circuit board of the first embodiment shown in FIG. 2 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0045] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0046] However, the technical concept of the present invention is not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0047] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings commonly understood by those of ordinary skill in the art to which the present invention belongs, and commonly used terms such as predefined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to describe the embodiments and do not limit the present invention.

[0048] In this specification, unless otherwise stated in the phrase, the singular can also include the plural, and when referring to "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. Furthermore, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the present invention.

[0049] Such terms are used merely to distinguish a component from other components, and are not intended to limit the essence, order, or sequence of the components. When a component is described as being "coupled," "bonded," or "connected" to another component, it can include not only a case where the component is directly coupled, coupled, or connected to the other component, but also a case where the component is "coupled," "coupled," or "connected" by another component between the component and the other component.

[0050] Furthermore, when it is stated that something is formed or placed "above or below" each component, "above" or "below" not only refers to the case where two components are in direct contact with each other, but also includes the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above or below," it can mean not only the upper direction based on one component, but also the lower direction.

[0051] -Electronic Devices-

[0052] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various semiconductor elements may be mounted in the semiconductor package.

[0053] The semiconductor device may include active devices and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0054] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0055] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0056] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0057] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0058] In one embodiment, the circuit board may be the first board described below.

[0059] In other embodiments, the circuit board may be a second board, as described below.

[0060] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0061] Referring to FIG. 1 a, the semiconductor package of the first embodiment may include a first substrate 1100 , a second substrate 1200 , and a semiconductor device 1300 .

[0062] The first substrate 1100 may refer to a package substrate.

[0063] For example, the first substrate 1100 may provide a space to which at least one external substrate is coupled. The external substrate may refer to a second substrate 1200 coupled on the first substrate 1100. The external substrate may also refer to a main board included in an electronic device coupled to a lower portion of the first substrate 1100.

[0064] Although not shown in the drawings, the first substrate 1100 may provide a space in which at least one semiconductor device is mounted.

[0065] The first substrate 1100 may include at least one insulating layer and an electrode portion disposed on the at least one insulating layer.

[0066] A second substrate 1200 may be disposed on the first substrate 1100 .

[0067] The second substrate 1200 may be an interposer. For example, the second substrate 1200 may provide a space in which at least one semiconductor device is mounted. The second substrate 1200 may be connected to the at least one semiconductor device 1300. For example, the second substrate 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are mounted. The second substrate 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320, and may also electrically connect the first and second semiconductor devices 1310 and 1320 to the first substrate 1100. That is, the second substrate 1200 may function as a horizontal connection between a plurality of semiconductor devices and a vertical connection between the semiconductor device and a package substrate.

[0068] 1a illustrates two semiconductor elements 1310 and 1320 disposed on the second substrate 1200. However, this is not limiting. For example, one semiconductor element may be disposed on the second substrate 1200, or alternatively, three or more semiconductor elements may be disposed on the second substrate 1200.

[0069] A second substrate 1200 may be disposed between the at least one semiconductor element 1300 and the first substrate 1100 .

[0070] In one embodiment, the second substrate 1200 may be an active interposer that functions as a semiconductor device. When the second substrate 1200 functions as a semiconductor device, the semiconductor package of the embodiment may have a vertically stacked structure on the first substrate 1100 and may have the functions of multiple logic chips. Having the functions of a logic chip may mean having the functions of both active and passive devices. Unlike passive devices, active devices do not need to have linear current-voltage characteristics. An active interposer may have the functions of an active device. Furthermore, the active interposer may perform the functions of a logic chip while also performing the signal transmission function between the first substrate 1100 and a second logic chip disposed thereon.

[0071] According to another embodiment, the second substrate 1200 may be a passive interposer. For example, the second substrate 1200 may function as a signal relay between the semiconductor device 1300 and the first substrate 1100 and may have passive element functions such as a resistor, capacitor, or inductor. For example, the number of terminals in the semiconductor device 1300 is gradually increasing due to factors such as 5G, Internet of Things (IoT), improved image quality, and increased communication speed. That is, the number of terminals provided on the semiconductor device 1300 is increasing, and as a result, the width of the terminals and the spacing between the terminals are decreasing. In this case, the first substrate 1100 may be connected to a main board of an electronic device. Therefore, in order for the electrodes provided on the first substrate 1100 to have the width and spacing required for connection to the semiconductor device 1300 and the main board, respectively, the thickness of the first substrate 1100 increases or the layer structure of the first substrate 1100 becomes complex. Therefore, in the first embodiment, a second substrate 1200 may be disposed between the first substrate 1100 and the semiconductor device 1300. The second substrate 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300.

[0072] The semiconductor device 1300 may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of the above. The memory chip may be a stacked memory such as HBM. The memory chip may also include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0073] On the other hand, the semiconductor package of the first embodiment can include a connecting portion.

[0074] For example, the semiconductor package may include a first connection part 1410 disposed between the first substrate 1100 and the second substrate 1200. The first connection part 1410 may electrically connect the first substrate 1100 and the second substrate 1200 while coupling them to each other.

[0075] For example, the semiconductor package may include a second connection part 1420 disposed between the second substrate 1200 and the semiconductor device 1300. The second connection part 1420 may electrically connect the semiconductor device 1300 to the second substrate 1200 while mounting the semiconductor device 1300 on the second substrate 1200.

[0076] The semiconductor package may include a third connection part 1430 disposed on the lower surface of the first substrate 1100. The third connection part 1430 may couple the first substrate 1100 to a main board and electrically connect them.

[0077] In this case, the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 may electrically connect the multiple components using at least one bonding method selected from wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first connecting unit 1410, the second connecting unit 1420, and the third connecting unit 1430 have the function of electrically connecting the multiple components, when direct metal-to-metal bonding is used, the semiconductor package may be understood as the electrically connected part, rather than the solder or wire.

[0078] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between multiple components without using a material such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a bonding method using the second connecting part 1420. In this case, the second connecting part 1420 may refer to a metal layer formed between multiple components through the recrystallization.

[0079] Specifically, the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 may be bonded to each other by a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430 by applying heat and pressure to the first connecting portion 1410, the second connecting portion 1420, and the third connecting portion 1430.

[0080] In this case, in at least one of the first substrate 1100 and the second substrate 1200, the electrodes on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are disposed may have protrusions that protrude outward away from the insulating layer of the substrate. The protrusions may protrude outward from the first substrate 1100 or the second substrate 1200.

[0081] The protrusions may be referred to as bumps, posts, or pillars. Preferably, the protrusions may refer to electrodes of the second substrate 1200 on which second connection portions 1420 for coupling with the semiconductor device 1300 are disposed. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, short circuits may occur between the second connection portions 1420, which are respectively connected to the terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in this embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portions 1420. As a result, in the embodiment, the electrode of the second substrate 1200 on which the second connection portion 1420 is disposed may include a protrusion in order to ensure the degree of matching, the diffusion force, and the diffusion prevention force that prevents the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the substrate.

[0082] Meanwhile, referring to FIG. 1B, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in that a connecting member 1210 is disposed on the second substrate 1200. The connecting member may be referred to as a bridge substrate. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may electrically connect a plurality of semiconductor devices horizontally to each other. Exemplarily, since a semiconductor device generally requires a large area, the connecting member 1210 may include a redistribution layer. Since the semiconductor package and the semiconductor device have a large difference in the width of the circuit pattern, etc., a buffering function for the circuit pattern is required for electrical connection. The buffering function may mean having an intermediate size between the width of the circuit pattern of the semiconductor package and the width of the circuit pattern of the semiconductor device, and the redistribution layer may function as a buffer.

[0083] In one embodiment, the connecting member 1210 may be an inorganic bridge. Exemplarily, the inorganic bridge may be a silicon bridge. That is, the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate.

[0084] In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic circuit board that includes an organic material instead of the silicon substrate.

[0085] The connecting member 1210 may be, but is not limited to, embedded in the second substrate 1200. For example, the connecting member 1210 may be disposed on the second substrate 1200 to have a protruding structure.

[0086] Also, the second substrate 1200 may include a cavity, and the connecting member 1210 may be disposed within the cavity of the second substrate 1200 .

[0087] The connecting members 1210 may horizontally connect the semiconductor devices disposed on the second substrate 1200 together.

[0088] 1c, the semiconductor package of the third embodiment may include a second substrate 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first substrate 1100 is omitted compared to the semiconductor package of the second embodiment.

[0089] That is, the second substrate 1200 of the third embodiment can function as both an interposer and a package substrate.

[0090] The first connection part 1410 disposed on the lower surface of the second substrate 1200 can couple the second substrate 1200 to a main board of an electronic device.

[0091] Referring to FIG. 1 d, the semiconductor package of the fourth embodiment may include a first substrate 1100 and a semiconductor device 1300 .

[0092] In this case, the semiconductor package of the fourth embodiment may have a structure in which the second substrate 1200 is omitted compared to the semiconductor package of the second embodiment.

[0093] That is, the first substrate 1100 of the fourth embodiment can function as a package substrate and also as a connection between the semiconductor device 1300 and the main board. To this end, the first substrate 1100 can include a connecting member 1110 for connecting between the plurality of semiconductor devices. The connecting member 1110 can be an inorganic bridge or an organic bridge for connecting between the plurality of semiconductor devices.

[0094] Referring to FIG. 1e, the semiconductor package of the fifth embodiment may further include a third semiconductor element 1330 compared to the semiconductor package of the fourth embodiment.

[0095] For this purpose, a fourth connection portion 1440 may be disposed on the lower surface of the first substrate 1100.

[0096] A third semiconductor element 1330 may be disposed in the fourth connection portion 1400. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor elements are mounted on both the upper and lower sides.

[0097] In this case, the third semiconductor device 1330 may have a structure in which it is disposed on the lower surface of the second circuit board 1220 in the semiconductor package of FIG. 1c.

[0098] 1f, the semiconductor package of the sixth embodiment may include a first substrate 1100. A first semiconductor device 1310 may be disposed on the first substrate 1100. To this end, a first connection part 1410 may be disposed between the first substrate 1100 and the first semiconductor device 1310.

[0099] The first substrate 1100 may also include a conductive coupling part 1450. The conductive coupling part 1450 may further protrude from the first substrate 1100 toward the second semiconductor device 1320. The conductive coupling part 1450 may be referred to as a bump or alternatively as a post. The conductive coupling part 1450 may be disposed to have a protruding structure on an electrode disposed on the top side of the first substrate 1100.

[0100] A second semiconductor device 1320 may be disposed on the conductive coupling part 1450. In this case, the second semiconductor device 1320 may be connected to the first substrate 1100 via the conductive coupling part 1450. In addition, a second connection part 1420 may be disposed on the first semiconductor device 1310 and the second semiconductor device 1320.

[0101] Thus, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0102] That is, the second semiconductor device 1320 may be connected to the first substrate 1100 through a conductive coupling part 1450. The second semiconductor device 1320 may also be selectively connected to the first semiconductor device 1310 through a connection part (not shown).

[0103] At this time, the second semiconductor device 1320 may receive a power signal and / or power through the conductive coupling part 1450. In addition, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through a connection part (not shown), and may transmit and receive communication signals therebetween.

[0104] The semiconductor package of the sixth embodiment supplies a power signal and / or power to the second semiconductor element 1320 through the conductive coupling part 1450, thereby providing sufficient power for driving the second semiconductor element 1320 and smoothly controlling the power supply operation.

[0105] As a result, the embodiment may improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment may solve the problem of insufficient power provided to the second semiconductor device 1320. Furthermore, the embodiment may provide at least one of a power signal, power, and a communication signal of the second semiconductor device 1320 via different paths via the conductive coupling part 1450 and the second connection part 1420. As a result, the embodiment may solve the problem of loss of the communication signal due to the power signal. For example, the embodiment may minimize mutual interference between the power signal and the communication signal.

[0106] Meanwhile, in the sixth embodiment, the second semiconductor device 1320 may be disposed on the first substrate 1100 in a package-on-package (POP) structure in which a plurality of package substrates are stacked. For example, the second semiconductor device 1320 may be a memory package including a memory chip. The memory package may be coupled to the conductive coupling part 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0107] Meanwhile, the semiconductor package according to the sixth embodiment may include a molding member 1460. The molding member 1460 may be disposed between the first substrate 1100 and the second semiconductor element 1320. For example, the molding member 1460 may mold the first connection portion 1410, the first semiconductor element 1310, and the conductive coupling portion 1450.

[0108] Referring to FIG. 1g, the semiconductor package of the seventh embodiment may include a first substrate 1100, a first connecting portion 1410, a semiconductor device 1300, and a third connecting portion 1430.

[0109] The semiconductor package of the seventh embodiment may differ from the semiconductor package of the fourth embodiment in that the connecting member 1110 is omitted and the first substrate 1100 includes a plurality of substrate layers.

[0110] The first substrate 1100 may include multiple substrate layers, such as a first substrate layer 1100A corresponding to a package substrate and a second substrate layer 1100B corresponding to a connecting member.

[0111] In other words, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B in which the first substrate 1100 (package substrate) and the second substrate 1200 (interposer) disclosed in FIG. 1A are integrally formed. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photo-curable material. For example, the second substrate layer 1100B may be a photo-imageable dielectric (PID). Furthermore, the second substrate layer 1100B may include a photo-curable material, thereby enabling miniaturization of electrodes. Therefore, in the seventh embodiment, the second substrate layer 1100B may be formed by sequentially stacking insulating layers of a photo-curable material on the first substrate layer 1100A and forming miniaturized electrodes on the insulating layers of the photo-curable material. Thus, the second substrate layer 1100B may have a function of a redistribution layer including miniaturized electrodes, and may have a function of horizontally connecting a plurality of semiconductor elements 1310 and 1320.

[0112] Prior to describing the circuit board of the embodiments, the board described below may refer to any one of the boards included in the semiconductor package. For example, the board described below may refer to any one of the first board 1100 and the second board 1200 included in the semiconductor packages of the first to seventh embodiments.

[0113] FIG. 2 is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 3 is a cross-sectional view showing a circuit board according to a second embodiment, and FIG. 4 is a cross-sectional view showing a circuit board according to a third embodiment.

[0114] Referring to FIG. 2, the circuit board of the first embodiment may include an insulating layer, a protective layer, and an electrode portion.

[0115] The insulating layer 110 may include multiple layers. The insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The first insulating layer 111 may constitute an inner layer of the insulating layer 110. The second insulating layer 112 may be disposed on the first insulating layer 111. The third insulating layer 113 may be disposed below the first insulating layer 111.

[0116] In one embodiment, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include different insulating materials. In this case, the interface between the first insulating layer 111 and the second insulating layer 112 may be distinct from each other. Also, the interface between the first insulating layer 111 and the third insulating layer 113 may be distinct from each other.

[0117] In another embodiment, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may include the same insulating material. In this case, the interface between the first insulating layer 111 and the second insulating layer 112 and the interface between the first insulating layer 111 and the third insulating layer 113 may not be distinguished. In this case, the stacked structure of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be distinguished by the pad electrodes and through electrodes of the electrode unit. For example, a plurality of pad electrodes may be spaced apart from one another in the vertical direction. Furthermore, the through electrodes may be disposed between a plurality of pad electrodes spaced apart from one another in the vertical direction. The pad electrodes and the through electrodes may have different vertical cross-sectional shapes and / or different horizontal widths. Based on this, the interfaces of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be distinguished. Through the above-described stacked structure, the substrate of the embodiment can efficiently electrically connect at least one semiconductor device and / or the second substrate to the main board.

[0118] 2 shows the insulating layer 110 of the substrate as having a three-layer structure, but is not limited thereto. For example, the insulating layer 110 may have a layer structure of two or less layers, or may have a layer structure of four or more layers.

[0119] In the following description, it is assumed that first insulating layer 111 contains an insulating material different from that of second insulating layer 112 and third insulating layer 113.

[0120] The first insulating layer 111 may include a reinforcing member. The reinforcing member may include glass fiber. For example, the first insulating layer 111 may include a resin and glass fiber impregnated with the resin.

[0121] The second insulating layer 112 and the third insulating layer 113 may be disposed on the top and bottom of the first insulating layer 111, respectively. The second insulating layer 112 and the third insulating layer 113 may not include a reinforcing member. For example, the second insulating layer 112 and the third insulating layer 113 may not include glass fiber.

[0122] Each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a thickness in the range of 10 μm to 60 μm. For example, each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a thickness in the range of 15 μm to 55 μm. For example, each of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may have a thickness in the range of 20 μm to 50 μm. If the thickness of at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 is less than 10 μm, the electrodes included in the circuit board may not be reliably protected. If the thickness of at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 exceeds 60 μm, the overall thickness of the circuit board may increase. Furthermore, if the thickness of at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 exceeds 60 μm, the thickness of the electrode portion increases accordingly, which can increase the transmission distance and transmission loss of signals transmitted through the electrode portion.

[0123] A first protective layer 180 may be disposed on the second insulating layer 112 .

[0124] In addition, a second protective layer 190 may be disposed below the third insulating layer 113.

[0125] The first and second protective layers 180 and 190 may function to protect the surface of the insulating layer 110 and / or the surface of the electrode portion.

[0126] The first protective layer 180 and the second protective layer 190 may be solder resist layers including an organic polymer material. For example, the first protective layer 180 and the second protective layer 190 may include an epoxy acrylate resin. In particular, the first protective layer 180 and the second protective layer 190 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 180 and the second protective layer 190 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0127] The thickness of each of the first protective layer 180 and the second protective layer 190 may be 1 μm to 20 μm. The thickness of each of the first protective layer 180 and the second protective layer 190 may be 1 μm to 15 μm. For example, the thickness of each of the first protective layer 180 and the second protective layer 190 may be 5 μm to 20 μm. When the thickness of each of the first protective layer 180 and the second protective layer 190 exceeds 20 μm, the thickness of the circuit board may increase. When the thickness of each of the first protective layer 180 and the second protective layer 190 is less than 1 μm, the electrodes included in the circuit board may not be stably protected, which may reduce electrical reliability or physical reliability.

[0128] Although not shown in the drawings, each of the first protective layer 180 and the second protective layer 190 may include an opening, and a surface treatment layer may be disposed on the electrode portion that vertically overlaps the opening. The surface treatment layer may be provided to prevent corrosion and oxidation of the surface of the electrode portion that vertically overlaps the opening and to improve soldering characteristics.

[0129] The circuit board of the embodiment may include an electrode portion.

[0130] The electrode portion may be provided to penetrate at least a portion of the insulating layer 110. The electrode portion may be roughly divided into pad electrodes and through electrodes. The pad electrodes may function to transmit signals in a horizontal direction. The through electrodes may be connected to the pad electrodes and thereby function to transmit signals in a vertical direction.

[0131] In the following, a plurality of electrode portions provided on the circuit board will be described with reference to the through electrodes.

[0132] The electrode unit of the embodiment may include a plurality of electrode units each having a through electrode with a different through structure, where the different through structures may refer to the through structures of the through electrodes of the electrode units in the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0133] The electrode portion of the embodiment may include a first electrode portion 120 .

[0134] The first electrode portion 120 may be provided through the first insulating layer 111 .

[0135] The first electrode unit 120 may include a first through-hole electrode 123. The first electrode unit 120 may include pad electrodes disposed on the upper and lower surfaces of the first through-hole electrode 123, respectively.

[0136] For example, the first electrode unit 120 may include a first through electrode 123 that penetrates the first insulating layer 111, a 1-1 pad electrode 121 arranged on the first through electrode 123, and a 1-2 pad electrode 122 arranged below the first through electrode 123.

[0137] The 1-1 pad electrode 121 may be disposed on the upper surface of the first insulating layer 111. The 1-1 pad electrode 121 may refer to a pad electrode that vertically overlaps the first through electrode 123 among a plurality of pad electrodes disposed on the upper surface of the first insulating layer 111.

[0138] The first and second pad electrodes 122 may be disposed on the lower surface of the first insulating layer 111. The first and second pad electrodes 122 may refer to pad electrodes that vertically overlap the first through electrode 123 among a plurality of pad electrodes disposed on the lower surface of the first insulating layer 111.

[0139] The first through electrode 123 may penetrate only the first insulating layer 111. Here, the fact that the first through electrode 123 penetrates only the first insulating layer 111 may mean that the first through electrode 123 is provided between a pad electrode disposed on the upper surface of the first insulating layer 111 and a pad electrode disposed on the lower surface of the first insulating layer 111. For example, the second insulating layer 112 may be provided with another through electrode that vertically overlaps the first through electrode 123. When the first through electrode 123 and the other through electrode are viewed as one electrode portion, the one electrode portion may penetrate the first insulating layer 111 and the second insulating layer 112. However, a pad electrode may be provided between the first through electrode 123 and the other through electrode, and the first through electrode 123 and the other through electrode may be distinguished from each other based on the pad electrode.

[0140] For example, the through electrodes described below may be classified based on the connection structure with the pad electrodes, for example, the classification of the through electrodes in the embodiments may be performed based on the number of pad electrodes directly connected to the upper surface, the lower surface, and the side surface of the through electrode.

[0141] For example, when a specific through electrode penetrates a plurality of insulating layers and pad electrodes directly connected to the specific through electrode include a first pad electrode connected to the top surface of the specific through electrode, a second pad electrode connected to the bottom surface of the specific through electrode, and a third pad electrode connected to a side surface between the top and bottom surfaces of the specific through electrode, the specific through electrode may be defined as consisting of a first through electrode between the first and third pad electrodes and a second through electrode between the second and third pad electrodes. In this case, when the specific through electrode does not include a third pad electrode connected to the side surface, the specific through electrode may be defined as consisting of one through electrode.

[0142] The first through-hole electrodes 123 of the first electrode unit 120 may have a specific slope within the first insulating layer 111. For example, the first through-hole electrodes 123 of the first electrode unit 120 may have a plurality of slopes that are different from each other.

[0143] The first through electrode 123 may have a first slope 123S1 adjacent to an upper surface of the first insulating layer 111 and whose width decreases toward a lower surface of the first insulating layer 111. The first through electrode 123 may have a second slope 123S2 adjacent to a lower surface of the first insulating layer 111 and whose width decreases toward the upper surface of the first insulating layer 111. An upper end of the first slope 123S1 may be directly connected to the 1-1 pad electrode 121. A lower end of the first slope 123S1 may be connected to an upper end of the second slope 123S2 of the first through electrode 123. A lower end of the second slope 123S2 may be directly connected to the 1-2 pad electrode 122. The first through electrode 123 may have an inflection portion where the slope changes between the first slope 123S1 and the second slope 123S2. The side surface of the first through electrode 123 having the first inclined portion 123S1 and the second inclined portion 123S2 may not be directly connected to another pad electrode.

[0144] Meanwhile, the electrode unit may include a second electrode unit 130. The second electrode unit 130 may include a second through-electrode 133 that commonly penetrates a plurality of insulating layers.

[0145] At least a portion of the second through electrode 133 may overlap horizontally with the first through electrode 123 of the first electrode unit 120, and the remaining portion may not overlap horizontally with the first through electrode 123 of the first electrode unit 120.

[0146] The second electrode unit 130 may include a pad electrode connected to the second through-hole electrode 133. For example, the second electrode unit 130 may include pad electrodes disposed on the upper and lower surfaces of the second through-hole electrode 133, respectively.

[0147] For example, the second electrode unit 130 may include a second through electrode 133 that commonly penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113, a 2-1 pad electrode 131 arranged on the second through electrode 133, and a 2-2 pad electrode 132 arranged below the second through electrode 133.

[0148] The 2-1 pad electrode 131 may be disposed on the upper surface of the second insulating layer 112. The 2-1 pad electrode 131 may refer to a pad electrode that vertically overlaps the second through electrode 133 among a plurality of pad electrodes disposed on the upper surface of the second insulating layer 112.

[0149] The 2-2 pad electrode 132 may be disposed on the lower surface of the third insulating layer 113. The 2-2 pad electrode 132 may refer to a pad electrode that vertically overlaps the second through electrode 133 among a plurality of pad electrodes disposed on the lower surface of the third insulating layer 113.

[0150] The second through electrode 133 of the second electrode unit 130 may have a specific slope within the first to third insulating layers 111, 112, and 113. For example, the second through electrode 133 of the second electrode unit 130 may have a plurality of slopes that are different from each other.

[0151] The second through electrode 133 may have a third slope 133S1 adjacent to the upper surface of the second insulating layer 112 and whose width decreases toward the lower surface of the third insulating layer 113. The second through electrode 133 may have a fourth slope 133S2 adjacent to the lower surface of the third insulating layer 113 and whose width decreases toward the upper surface of the second insulating layer 112. An upper end of the third slope 133S1 of the second through electrode 133 may be directly connected to the 2-1 pad electrode 131. A lower end of the third slope 133S1 of the second through electrode 133 may be connected to an upper end of the fourth slope 133S2 of the second through electrode 133. A lower end of the fourth slope 133S2 of the second through electrode 133 may be directly connected to the 2-2 pad electrode 132. The second through electrode 133 may have an inflection portion where the slope changes between the third slope 133S1 and the fourth slope 133S2. The inflection portion of the second through-hole electrode 133 may be located lower than the upper surface of the first insulating layer 110 and higher than the lower surface of the first insulating layer 110. Preferably, the inflection portion of the second through-hole electrode 133 may be located between the upper surface of the first insulating layer 111 and the lower surface of the first insulating layer 111.

[0152] Furthermore, the side surface of the second through electrode 133 having the third inclined portion 133S1 and the fourth inclined portion 133S2 may not be directly connected to another pad electrode. For example, the side surface of the second through electrode 133 may overlap another pad electrode in the horizontal direction. However, the side surface of the second through electrode 133 may not be directly connected to the other pad electrode.

[0153] For example, the electrode portion of the circuit board may include a plurality of first electrode patterns that horizontally overlap the side surfaces of the second through electrodes 133. The first electrode patterns may be pad electrodes or traces.

[0154] Specifically, the first electrode pattern may refer to the 1-1 pad electrode 121, the 1-2 pad electrode 122, the 3-1 pad electrode 141, the 4-1 pad electrode 151, the 5-1 pad electrode 161, and the 6-1 pad electrode 171 shown in FIG. 2.

[0155] For example, the first electrode pattern may refer to pad electrodes or trace electrodes disposed on the upper and lower surfaces of the first insulating layer 111 .

[0156] In addition, the second through electrode 133 may not be directly connected to the first electrode pattern. For example, the side surface of the second through electrode 133 including the third slope 133S1 and the fourth slope 133S2 may be entirely covered with the first to third insulating layers.

[0157] For example, according to the prior art, a pad electrode is provided between the first and second insulating layers, thereby directly connecting the second through-electrode 133 to the pad electrode provided between the first and second insulating layers. Therefore, a signal transmitted through the second through-electrode 133 in the prior art can be transmitted along the pad electrode provided between the first and second insulating layers. For example, when a high-frequency signal is transmitted, the signal has the characteristic of flowing along the surface of the electrode portion. According to the prior art, the signal flows along the pad electrode provided between the first and second insulating layers, thereby increasing the signal transmission distance. Furthermore, as the signal distance increases, signal transmission loss also increases.

[0158] In contrast, the embodiment includes a second through electrode 133 that penetrates multiple insulating layers, and the second through electrode 133 is not directly connected to other pad electrodes between the 2-1 pad electrode 131 and the 2-2 pad electrode 132. As a result, the embodiment can reduce the transmission distance of a signal that flows through the second through electrode 133, thereby minimizing signal transmission loss. Therefore, the embodiment can improve communication characteristics of a circuit board and a semiconductor package including the same, and further, can ensure stable operation of a semiconductor device included in the semiconductor package.

[0159] Meanwhile, the electrode unit may include a third electrode unit 140. The third electrode unit 140 may include a third through-electrode 143 that commonly passes through a plurality of insulating layers.

[0160] At least a portion of the third through-electrode 143 may overlap the first through-electrode 123 of the first electrode unit 120 and the second through-electrode 133 of the second electrode unit 130 in the horizontal direction.

[0161] The third electrode unit 140 may include a pad electrode connected to the third through-hole electrode 143. For example, the third electrode unit 140 may include pad electrodes disposed on the upper and lower surfaces of the third through-hole electrode 143, respectively.

[0162] For example, the third electrode unit 140 may include a third through electrode 143 that commonly penetrates the first insulating layer 111 and the second insulating layer 112, a 3-1 pad electrode 141 arranged below the third through electrode 143, and a 3-2 pad arranged on the third through electrode 143.

[0163] The 3-1 pad electrode 141 may refer to a pad electrode that vertically overlaps the third through electrode 143 among a plurality of pad electrodes disposed on the lower surface of the first insulating layer 111 .

[0164] The 3-2 pad electrode 142 may be disposed on the upper surface of the second insulating layer 112. The 3-2 pad electrode 142 may refer to a pad electrode that vertically overlaps the third through electrode 143 among a plurality of pad electrodes disposed on the upper surface of the second insulating layer 112.

[0165] The third through electrode 143 of the third electrode unit 140 may have a specific inclination within the first and second insulating layers 111 and 112. For example, unlike the first through electrode 123 and the second through electrode 133, the third through electrode 143 of the third electrode unit 140 may not have an inflection portion.

[0166] The third through-hole electrode 143 may include a fifth slope 143S whose width decreases from the upper surface of the second insulating layer 112 toward the lower surface of the first insulating layer 111. A lower end of the fifth slope 143S of the third through-hole electrode 143 may be directly connected to the 3-1 electrode 141. In addition, an upper end of the fifth slope 143S of the third through-hole electrode 143 may be directly connected to the 3-2 electrode 142.

[0167] The side surface of the third through-hole electrode 143 having the fifth inclined portion 143S may not be directly connected to another pad electrode. For example, the side surface of the third through-hole electrode 143 may overlap the second electrode pattern in the horizontal direction. The side surface of the third through-hole electrode 143 may not be directly connected to the second electrode pattern overlapping in the horizontal direction.

[0168] Specifically, the second electrode pattern may refer to the 1-1 pad electrode 121, the 4-1 pad electrode 151, and the 5-1 pad electrode 161 shown in Fig. 2. For example, the second electrode pattern may refer to a pad electrode or a trace electrode disposed on the upper surface of the first insulating layer 111.

[0169] Meanwhile, the electrode unit may include a fourth electrode unit 150. The fourth electrode unit 150 may include a fourth through-electrode 153 commonly penetrating a plurality of insulating layers.

[0170] The fourth through-hole electrode 153 may overlap the second through-hole electrode 133 and the third through-hole electrode 143 in the horizontal direction.

[0171] The fourth electrode unit 150 may include a pad electrode connected to the fourth through-hole electrode 153. For example, the fourth electrode unit 150 may include pad electrodes disposed on the upper and lower surfaces of the fourth through-hole electrode 153, respectively.

[0172] For example, the fourth electrode unit 150 may include a fourth through-electrode 153 that penetrates only the second insulating layer 112, a 4-1 pad electrode 151 arranged below the fourth through-electrode 153, and a 4-2 pad electrode 152 arranged on the fourth through-electrode 153.

[0173] The 4-1 pad electrode 151 may refer to a pad electrode that vertically overlaps the fourth through electrode 153 among a plurality of pad electrodes disposed on the upper surface of the first insulating layer 111 .

[0174] The 4-2 pad electrode 152 may be disposed on the upper surface of the second insulating layer 112. The 4-2 pad electrode 152 may refer to a pad electrode that vertically overlaps the fourth through electrode 153 among a plurality of pad electrodes disposed on the upper surface of the second insulating layer 112.

[0175] The fourth through electrode 153 of the fourth electrode unit 150 may have a specific inclination within the second insulating layer 112. For example, unlike the first through electrode 123 and the second through electrode 133, the fourth through electrode 153 of the fourth electrode unit 150 may not have an inflection portion.

[0176] The fourth through-hole electrode 153 may include a sixth slope 153S whose width decreases from the upper surface of the second insulating layer 112 toward the lower surface of the second insulating layer 112. A lower end of the sixth slope 153S of the fourth through-hole electrode 153 may be directly connected to the 4-1 electrode 151. In addition, an upper end of the sixth slope 153S of the fourth through-hole electrode 153 may be directly connected to the 4-2 electrode 152.

[0177] The side surface of the fourth through electrode 153 having the sixth inclined portion 153S may not be directly connected to another pad electrode.

[0178] Meanwhile, the electrode unit may include a fifth electrode unit 160. The fifth electrode unit 160 may include a fifth through-electrode 163 that commonly passes through a plurality of insulating layers.

[0179] At least a portion of the fifth through-hole electrode 163 may overlap the first through-hole electrode 123 and the second through-hole electrode 133 in the horizontal direction.

[0180] The fifth electrode unit 160 may include a pad electrode connected to the fifth through-hole electrode 163. For example, the fifth electrode unit 160 may include pad electrodes disposed on the upper and lower surfaces of the fifth through-hole electrode 163, respectively.

[0181] For example, the fifth electrode unit 160 may include a fifth through-electrode 163 that penetrates the first insulating layer 111 and the third insulating layer 113, a 5-1 pad electrode 161 arranged on the fifth through-electrode 163, and a 5-2 pad electrode 161 arranged below the fifth through-electrode 163.

[0182] The 5-1 pad electrode 161 may refer to a pad electrode that vertically overlaps the fifth through-electrode 163 among a plurality of pad electrodes disposed on the upper surface of the first insulating layer 111 .

[0183] The 5-2 pad electrode 162 may be disposed on the lower surface of the third insulating layer 113. The 5-2 pad electrode 162 may refer to a pad electrode that vertically overlaps the fifth through-hole electrode 163 among a plurality of pad electrodes disposed on the lower surface of the third insulating layer 113.

[0184] The fifth through electrode 163 of the fifth electrode unit 160 may have a specific inclination within the first insulating layer 111 and the third insulating layer 113. For example, unlike the first through electrode 123 and the second through electrode 133, the fifth through electrode 163 of the fifth electrode unit 160 may not have an inflection portion.

[0185] The fifth through-hole electrode 163 may include a seventh slope 163S whose width increases from the upper surface of the first insulating layer 111 toward the lower surface of the third insulating layer 113. An upper end of the seventh slope 163S of the fifth through-hole electrode 163 may be directly connected to the 5-1 electrode 161. In addition, a lower end of the seventh slope 163S of the fifth through-hole electrode 163 may be directly connected to the 5-2 electrode 162.

[0186] In addition, at least one third electrode pattern may be provided that horizontally overlaps a side surface of the fifth through-hole electrode 163 having the seventh inclined portion 163S. The side surface of the fifth through-hole electrode 163 does not need to be directly connected to another third electrode pattern.

[0187] Specifically, the third electrode pattern may refer to the 1-2 pad electrode 122, the 3-1 pad electrode 141, and the 6-1 pad electrode 171 shown in Fig. 2. For example, the third electrode pattern may refer to a pad electrode or a trace electrode disposed on the lower surface of the first insulating layer 111.

[0188] Meanwhile, the electrode unit may include a sixth electrode unit 170. The sixth electrode unit 170 may include a sixth through-electrode 173 that penetrates the third insulating layer 113.

[0189] At least a portion of the sixth through-hole electrode 173 may overlap the second through-hole electrode 133 in the horizontal direction.

[0190] The sixth electrode unit 170 may include a pad electrode connected to the sixth through-hole electrode 173. For example, the sixth electrode unit 170 may include pad electrodes disposed on the upper and lower surfaces of the sixth through-hole electrode 173, respectively.

[0191] For example, the sixth electrode unit 170 may include a sixth through-hole electrode 173 that penetrates the third insulating layer 113, a sixth through-hole electrode 171 that is disposed on the sixth through-hole electrode 173, and a sixth through-hole electrode 172 that is disposed below the sixth through-hole electrode 173.

[0192] The 6-1 pad electrode 171 may refer to a pad electrode that vertically overlaps the sixth through-electrode 173 among a plurality of pad electrodes disposed on the lower surface of the first insulating layer 111 .

[0193] The 6-2 pad electrode 172 may be disposed on the lower surface of the third insulating layer 113. The 6-2 pad electrode 172 may refer to a pad electrode that vertically overlaps the sixth through-hole electrode 173 among a plurality of pad electrodes disposed on the lower surface of the third insulating layer 113.

[0194] The sixth through-hole electrode 173 of the sixth electrode unit 170 may have a specific inclination within the third insulating layer 113. For example, unlike the first through-hole electrode 123 and the second through-hole electrode 133, the sixth through-hole electrode 173 of the sixth electrode unit 170 may not have an inflection portion.

[0195] The sixth through-hole electrode 173 may include an eighth slope 173S whose width increases from the upper surface of the third insulating layer 113 toward the lower surface of the third insulating layer 113. An upper end of the eighth slope 173S of the sixth through-hole electrode 173 may be directly connected to the 6-1 electrode 171. In addition, a lower end of the eighth slope 173S of the sixth through-hole electrode 173 may be directly connected to the 6-2 electrode 172.

[0196] Also, at least one pad electrode may be provided that horizontally overlaps the side surface of the sixth through-hole electrode 173 having the eighth inclined portion 173S. The side surface of the sixth through-hole electrode 173 may not be directly connected to another pad electrode.

[0197] 3, at least two of the through electrodes included in the circuit board of the second embodiment may be commonly connected to the same pad electrode. Hereinafter, only the differences from the circuit board of FIG. 2 will be described.

[0198] The second electrode unit 130a may include a through electrode that commonly passes through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. For example, the second electrode unit 130a may include a 2-1 through electrode 133a and a 2-2 through electrode 133b that are spaced apart in the horizontal direction.

[0199] The second electrode unit 130a may also include a 2-1 pad electrode 131 disposed on the upper surface of the second insulating layer 112. The second electrode unit 130a may also include a 2-2 pad electrode 132 disposed on the lower surface of the third insulating layer 113.

[0200] The upper surfaces of the 2-1 through-hole electrode 133 a and the 2-2 through-hole electrode 133 b may be commonly connected to the 2-1 pad electrode 131 .

[0201] The lower surfaces of the 2-1 through-hole electrode 133 a and the 2-2 through-hole electrode 133 b may be commonly connected to the 2-2 pad electrode 132 .

[0202] The second electrode unit 130a of the second embodiment may function as a heat dissipation electrode. For example, the second electrode unit 130a of the embodiment may transfer heat generated in the semiconductor device to the upper and / or lower sides of the circuit board. In this case, the second electrode unit 130a may include a plurality of through-hole electrodes, which may be commonly connected to the same pad electrode. As a result, the embodiment may improve the heat dissipation characteristics of the circuit board and a semiconductor package including the same, thereby enabling the semiconductor device to operate stably.

[0203] Referring to FIG. 4, the circuit board of the third embodiment may differ from the circuit board of the first embodiment in the structure of the insulating layer and the electrode portion.

[0204] For example, the insulating layer 210 of the circuit board of the third embodiment can include a first insulating layer 211 , a second insulating layer 212 , a third insulating layer 213 , a fourth insulating layer 214 , and a fifth insulating layer 215 .

[0205] Specifically, the first insulating layer 211 may be disposed in the center of the circuit board. The second insulating layer 212 may be disposed on the first insulating layer 211. The third insulating layer 213 may be disposed on the second insulating layer 212. The fourth insulating layer 214 may be disposed below the first insulating layer 211. The fifth insulating layer 215 may be disposed below the fourth insulating layer 214.

[0206] In addition, the first insulating layer 211, the second insulating layer 212, the third insulating layer 213, the fourth insulating layer 214, and the fifth insulating layer 215 may be provided with electrode portions. Each electrode portion may include a pad electrode and a through electrode. Here, the basic structures of the pad electrode and the through electrode have already been described with reference to FIG. 2, so detailed description thereof will be omitted.

[0207] The following description focuses on the through electrodes provided on the circuit board of the third embodiment. The through electrodes described below have a structure in which they are directly connected to only two pad electrodes. For example, the side surfaces of the through electrodes described below may not be directly connected to other pad electrodes.

[0208] The first through-hole electrode 221 may commonly penetrate a plurality of insulating layers. For example, the first through-hole electrode 221 may commonly penetrate the first insulating layer 211, the second insulating layer 212, the third insulating layer 213, the fourth insulating layer 214, and the fifth insulating layer 215. Each of the upper and lower surfaces of the first through-hole electrode 221 may be connected to a pad electrode, and the side surface of the first through-hole electrode 221 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the first through-hole electrode 221, and the pad electrode that horizontally overlaps the first through-hole electrode 221 may not be directly connected to the first through-hole electrode 221.

[0209] The second through electrode 222 may commonly penetrate a plurality of insulating layers. For example, the second through electrode 222 may commonly penetrate the first insulating layer 211, the second insulating layer 212, the fourth insulating layer 214, and the fifth insulating layer 215. Each of the upper and lower surfaces of the second through electrode 222 may be connected to a pad electrode, and the side surface of the second through electrode 222 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the second through electrode 222, and the pad electrode that horizontally overlaps the second through electrode 222 may not be directly connected to the second through electrode 222.

[0210] The third through-hole electrode 223 may penetrate only the first insulating layer 211. The upper and lower surfaces of the third through-hole electrode 223 may be connected to pad electrodes. In this case, the circuit board may not include pad electrodes that overlap the third through-hole electrode 223 horizontally.

[0211] The fourth through electrode 224 may penetrate multiple insulating layers. The fourth through electrode 224 may commonly penetrate the first insulating layer 211 and the second insulating layer 212. Each of the upper and lower surfaces of the fourth through electrode 224 may be connected to a pad electrode, and the side surface of the fourth through electrode 224 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the fourth through electrode 224, and the pad electrode that horizontally overlaps the fourth through electrode 224 may not be directly connected to the fourth through electrode 224.

[0212] The fifth through-hole electrode 225 may penetrate only the second insulating layer 212. The upper and lower surfaces of the fifth through-hole electrode 225 may be connected to pad electrodes. In this case, the circuit board may not include a pad electrode that overlaps the fifth through-hole electrode 225 horizontally.

[0213] The sixth through-hole electrode 226 may penetrate multiple insulating layers. The sixth through-hole electrode 226 may commonly penetrate the second insulating layer 212 and the third insulating layer 213. Each of the upper and lower surfaces of the sixth through-hole electrode 226 may be connected to a pad electrode, and the side surface of the sixth through-hole electrode 226 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the sixth through-hole electrode 226, and the pad electrode that horizontally overlaps the sixth through-hole electrode 226 may not be directly connected to the sixth through-hole electrode 226.

[0214] The seventh through-hole electrode 227 may penetrate multiple insulating layers. The seventh through-hole electrode 227 may commonly penetrate the first insulating layer 211, the second insulating layer 212, and the third insulating layer 213. Each of the upper and lower surfaces of the seventh through-hole electrode 227 may be connected to a pad electrode, and the side surface of the seventh through-hole electrode 227 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the seventh through-hole electrode 227, and the pad electrode that horizontally overlaps the seventh through-hole electrode 227 may not be directly connected to the seventh through-hole electrode 227.

[0215] The eighth through-hole electrode 228 may penetrate only the third insulating layer 213. The upper and lower surfaces of the eighth through-hole electrode 228 may be connected to pad electrodes. In this case, the circuit board may not include a pad electrode that overlaps the eighth through-hole electrode 228 horizontally.

[0216] The ninth through-hole electrode 229 may penetrate multiple insulating layers. The ninth through-hole electrode 229 may commonly penetrate the first insulating layer 211 and the fourth insulating layer 214. Each of the upper and lower surfaces of the ninth through-hole electrode 229 may be connected to a pad electrode, and the side surface of the ninth through-hole electrode 229 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the ninth through-hole electrode 229, and the pad electrode that horizontally overlaps the ninth through-hole electrode 229 may not be directly connected to the ninth through-hole electrode 229.

[0217] The tenth through-hole electrode 230 may penetrate only the fourth insulating layer 214. The upper and lower surfaces of the tenth through-hole electrode 230 may be connected to pad electrodes. In this case, the circuit board may not include a pad electrode that overlaps the tenth through-hole electrode 230 horizontally.

[0218] The eleventh through-hole electrode 231 may penetrate multiple insulating layers. The eleventh through-hole electrode 231 may commonly penetrate the first insulating layer 211, the fourth insulating layer 214, and the fifth insulating layer 215. Each of the upper and lower surfaces of the eleventh through-hole electrode 231 may be connected to a pad electrode, and the side surface of the eleventh through-hole electrode 231 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the eleventh through-hole electrode 231, and the pad electrode that horizontally overlaps the eleventh through-hole electrode 231 may not be directly connected to the eleventh through-hole electrode 231.

[0219] The twelfth through electrode 232 may penetrate multiple insulating layers. The twelfth through electrode 232 may commonly penetrate the first insulating layer 211, the second insulating layer 212, the fourth insulating layer 214, and the fifth insulating layer 215. Each of the upper and lower surfaces of the twelfth through electrode 232 may be connected to a pad electrode, and the side surface of the twelfth through electrode 232 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the twelfth through electrode 232, and the pad electrode that horizontally overlaps the twelfth through electrode 232 may not be directly connected to the twelfth through electrode 232.

[0220] The thirteenth through-hole electrode 233 may penetrate multiple insulating layers. The thirteenth through-hole electrode 233 may commonly penetrate the fourth insulating layer 214 and the fifth insulating layer 215. Each of the upper and lower surfaces of the thirteenth through-hole electrode 233 may be connected to a pad electrode, and the side surface of the thirteenth through-hole electrode 233 may not be directly connected to another pad electrode. For example, the circuit board may include a pad electrode that horizontally overlaps the thirteenth through-hole electrode 233, and the pad electrode that horizontally overlaps the thirteenth through-hole electrode 233 may not be directly connected to the thirteenth through-hole electrode 233.

[0221] The fourteenth through-hole electrode 234 may penetrate only the fifth insulating layer 215. The upper and lower surfaces of the fourteenth through-hole electrode 234 may be connected to pad electrodes. In this case, the circuit board may not include a pad electrode that overlaps the fourteenth through-hole electrode 234 horizontally.

[0222] The circuit board of the embodiment may include first to third insulating layers. The circuit board may also include a first through-hole electrode that penetrates the first insulating layer alone and a second through-hole electrode that penetrates the first to third insulating layers in common. The side surfaces of the first through-hole electrode may include first and second slopes that are different from each other. The side surfaces of the second through-hole electrode may include third and fourth slopes that are different from each other. The side surfaces of the second through-hole electrode that have the third and fourth slopes may not be directly connected to other pad electrodes or traces. This allows the embodiment to minimize the transmission distance of signals transmitted through the second through-hole electrode, thereby minimizing signal transmission loss of signals transmitted through the second through-hole electrode.

[0223] For example, according to the prior art, a pad electrode is provided between the first insulating layer and the second insulating layer, thereby directly connecting the second through electrode to the pad electrode provided between the first insulating layer and the second insulating layer. As a result, a signal transmitted through the second through electrode in the prior art can be transmitted along the pad electrode provided between the first insulating layer and the second insulating layer. For example, when a high-frequency signal is transmitted, the signal can flow along the surface of the electrode portion. According to the prior art, the signal flows along the pad electrode provided between the first insulating layer and the second insulating layer, thereby increasing the signal transmission distance. Furthermore, as the signal distance increases, signal transmission loss also increases.

[0224] In contrast, an embodiment may include a second through-hole electrode disposed between the 2-1 pad electrode and the 2-2 pad electrode and penetrating multiple insulating layers. The second through-hole electrode may not be directly connected to pad electrodes other than the 2-1 pad electrode and the 2-2 pad electrode. For example, the circuit board may include a pad electrode and a trace that horizontally overlaps a side surface of the second through-hole electrode, and the pad electrode and the trace that horizontally overlaps a side surface of the second through-hole electrode may not be directly connected to the side surface of the second through-hole electrode. As a result, the embodiment may reduce the transmission distance of signals flowing through the second through-hole electrode and minimize resulting signal transmission loss. Therefore, the embodiment may improve the communication characteristics of the circuit board and a semiconductor package including the same, and further may enable stable operation of a semiconductor device included in the semiconductor package.

[0225] Meanwhile, the second through electrode may include a 2-1 through electrode and a 2-2 through electrode spaced apart in the horizontal direction. The 2-1 and 2-2 through electrodes may be commonly connected to a 2-1 pad electrode and a 2-2 pad electrode, respectively. The 2-1 and 2-2 through electrodes may perform a heat dissipation function. Furthermore, a plurality of through electrodes performing the heat dissipation function may be provided spaced apart from each other in the horizontal direction, and the plurality of through electrodes may be connected to a common pad electrode. This may improve the heat dissipation characteristics of a circuit board and a semiconductor package including the same, thereby enabling stable operation of a semiconductor device.

[0226] 5 to 11 are cross-sectional views showing the manufacturing method of the circuit board of the first embodiment shown in FIG. 2 in the order of steps.

[0227] 5, a basic component for manufacturing a circuit board may be prepared. For example, in an embodiment, a first insulating layer 111 may be prepared. The first insulating layer 111 may be, but is not limited to, a CCL (Copper Clad Laminate).

[0228] Referring to FIG. 6, in the embodiment, a process of forming a first through hole TH1 penetrating the upper and lower surfaces of the first insulating layer 111 may be performed.

[0229] 7, in the embodiment, a process of forming the first electrode unit 120 including the first through electrode 123 filling the first through hole TH1 may be performed. At this time, when forming the first electrode unit 120, a pad electrode connected to another through electrode may be formed at the same time.

[0230] 8, in the embodiment, a process of stacking a second insulating layer 112 on an upper surface of a first insulating layer 111 may be performed. Also, in the embodiment, a process of stacking a third insulating layer 113 on a lower surface of the first insulating layer 111 may be performed.

[0231] 9, in the embodiment, a process of forming through holes penetrating at least one of the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be performed. For example, in the embodiment, a process of forming second to sixth through holes TH2, TH3, TH4, TH5, and TH6 may be performed.

[0232] Specifically, in the embodiment, a step of forming a second through hole TH2 that commonly penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be performed. Also, in the embodiment, a step of forming a third through hole TH3 that commonly penetrates the first insulating layer 111 and the second insulating layer 112 may be performed. Also, in the embodiment, a step of forming a fourth through hole TH4 that penetrates only the second insulating layer 112 may be performed. Also, in the embodiment, a step of forming a fifth through hole TH5 that commonly penetrates the first insulating layer 111 and the third insulating layer 113 may be performed. Also, in the embodiment, a step of forming a sixth through hole TH6 that penetrates only the third insulating layer 113 may be performed. At this time, the second to sixth through holes TH2, TH3, TH4, TH5, and TH6 may be formed simultaneously through a laser process, but this is not limited to this.

[0233] Referring to FIG. 10, in the embodiment, a process of forming an electrode part including through electrodes filling the second to sixth through holes TH2, TH3, TH4, TH5, and TH6 may be performed.

[0234] For example, in an embodiment, a step of forming a second electrode unit 130 including a second through electrode 133 filling the second through hole TH2 may be performed. Also, in an embodiment, a step of forming a third electrode unit 140 including a third through electrode 143 filling the third through hole TH3 may be performed. Also, in an embodiment, a step of forming a fourth electrode unit 150 including a fourth through electrode 153 filling the fourth through hole TH4 may be performed. Also, in an embodiment, a step of forming a fifth electrode unit 160 including a fifth through electrode 163 filling the fifth through hole TH5 may be performed. Also, in an embodiment, a step of forming a sixth electrode unit 170 including a sixth through electrode 173 filling the sixth through hole TH6 may be performed. In this case, the second to sixth electrode units 130, 140, 150, 160, and 170 may be formed simultaneously in a single plating process, but is not limited to this.

[0235] 11, in this embodiment, a process of forming a first protective layer 180 on the second insulating layer 112 and a process of forming a second protective layer 190 under the third insulating layer 113 may be performed. In this case, if an additional insulating layer is provided between the second insulating layer 112 and the first protective layer 180 or between the third insulating layer 113 and the second protective layer 190, a process of laminating the additional insulating layer, a process of forming a through hole penetrating at least one insulating layer, and a process of forming an electrode unit including a through electrode filling the formed through hole may be further performed.

[0236] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, a circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0237] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0238] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0239] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a first insulating layer; a second insulating layer disposed on the first insulating layer; a third insulating layer disposed below the first insulating layer; an electrode portion including a through electrode that penetrates at least one of the first to third insulating layers, The electrode portion is a first electrode unit including a first-1 pad electrode disposed on an upper surface of the first insulating layer, a first-2 pad electrode disposed on a lower surface of the first insulating layer, and a first through electrode passing through the first insulating layer and connected to the first-1 and first-2 pad electrodes; a second electrode unit including a 2-1 pad electrode disposed on an upper surface of the second insulating layer, a 2-2 pad electrode disposed on a lower surface of the third insulating layer, and a second through electrode commonly penetrating the first to third insulating layers and connected to the 2-1 and 2-2 pad electrodes, the electrode portion includes a first electrode pattern that horizontally overlaps the second through-electrode of the second electrode portion, The second through electrode is spaced apart from the first electrode pattern in a horizontal direction.

2. the first insulating layer includes a first insulating material comprising glass fibers; 10. The circuit board of claim 1, wherein the second and third insulating layers comprise a second insulating material that is glass-free.

3. The first through electrode is a first slope adjacent to the upper surface of the first insulating layer and decreasing in width toward the lower surface of the first insulating layer; 2. The circuit board of claim 1, further comprising: a second slope adjacent the lower surface of the first insulating layer and decreasing in width toward the upper surface of the first insulating layer.

4. The second through electrode is a third slope adjacent to the upper surface of the second insulating layer and decreasing in width toward the lower surface of the third insulating layer; 2. The circuit board of claim 1, further comprising: a fourth slope adjacent the lower surface of the third insulating layer and decreasing in width toward the upper surface of the second insulating layer.

5. The circuit board of claim 4 , wherein the third and fourth inclined side surfaces of the second through electrode are not connected to the first electrode pattern and are entirely covered with the first to third insulating layers.

6. the second through electrode includes a portion where the slope changes between the third slope and the fourth slope, The circuit board according to claim 4 , wherein the portion where the slope changes is located between the upper surface of the first insulating layer and the lower surface of the first insulating layer.

7. The electrode portion is The circuit board according to any one of claims 4 to 6, comprising a third electrode portion including a 3-1 pad electrode arranged on the lower surface of the first insulating layer, a 3-2 pad electrode arranged on the upper surface of the second insulating layer, and a third through electrode that commonly penetrates the first and second insulating layers and is connected to the 3-1 and 3-2 pad electrodes.

8. the electrode portion includes a second electrode pattern horizontally overlapping the third through electrode of the third electrode portion, The circuit board of claim 7 , wherein the third through-hole electrode is horizontally spaced apart from the second electrode pattern and is not directly connected to the second electrode pattern.

9. the third through-electrode has a fifth slope whose width decreases from the 3-1 pad electrode toward the 3-2 pad electrode; a fifth inclined lower end of the third through-electrode is directly connected to the 3-1 pad electrode; an upper end of the fifth inclined portion of the third through-hole electrode is directly connected to the 3-2 pad electrode; The circuit board according to claim 8 , wherein the side surface of the third through electrode having the fifth inclination is entirely covered via the first and second insulating layers.

10. The electrode portion is The circuit board according to any one of claims 4 to 6, comprising a fourth electrode portion including a 4-1 pad electrode arranged on the lower surface of the first insulating layer, a 4-2 pad electrode arranged on the upper surface of the second insulating layer, and a fourth through electrode that penetrates the second insulating layer and is connected to the 4-1 and 4-2 pad electrodes.

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