Accelerating Fetch Target Queue (FTQ) Processing in Processors

Abstract

Disclosed herein is acceleration of fetch target queue (FTQ) processing. In some aspects, a processor includes an FTQ and an FTQ acceleration cache (FAC), and is configured to generate a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries of the FTQ, the FTQ entry including a fetch address bundle including a plurality of sequential virtual addresses (VAs), and the FAC entry including metadata for the FTQ entry. The processor is further configured to receive a request to access the FTQ entry using the FTQ. In response to receiving the request to access the FTQ entry, the processor is also configured to use the FAC to locate a FAC entry among the plurality of FAC entries of the FAC that corresponds to the FTQ entry. The processor is further configured to perform accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

Description

[Technical Field]

[0001] Field of Disclosure The techniques of this disclosure relate to fetching instructions for execution within a microprocessor ("processor"), and in particular to processing the contents of a fetch target queue (FTQ). [Background technology]

[0002] background The execution performance of conventional modern processors is limited by the fetch performance of the processor's "front end," which generally refers to the portion of the processor responsible for fetching and preparing instructions for execution. A processor's front-end architecture can employ several different approaches to improve fetch performance. One approach involves the use of an instruction cache, which is a memory device that is smaller in capacity than system memory but that the processor can access more quickly depending on the type of memory used and / or the cache's physical location relative to the processor. An instruction cache can be used to improve fetch performance by storing copies of instructions previously retrieved from frequently accessed locations in system memory or from another higher-level cache (i.e., a cache further away from the processor).

[0003] Another approach involves using a branch predictor to speculatively predict the path a branch instruction will take (e.g., based on the outcomes of previously executed branch instructions) and basing the fetching of subsequent instructions on the branch prediction. When a branch instruction reaches the execution stage of the processor's instruction pipeline and is executed, the resulting target address of the branch instruction is confirmed by comparing it with the previously predicted target address when the branch instruction was fetched. If the predicted target address and the actual target address match (i.e., the branch prediction was correct), the subsequent instruction at the target address will already have been fetched and will be in the instruction pipeline, and instruction execution can proceed without delay.

[0004] To further improve processor fetch performance, processors can implement a decoupled front-end architecture in which a structure known as a fetch target queue (FTQ) is inserted between the instruction cache and the branch predictor. The branch predictor in such a processor generates fetch address bundles containing blocks of sequential virtual addresses (VAs), which are inserted into the FTQ as FTQ entries. The instruction cache then retrieves each FTQ entry and fetches the instruction indicated by the VA in each fetch address bundle. In this way, the FTQ decouples the instruction cache and the branch predictor by acting as a buffer that allows the branch predictor to continue generating branch predictions even if accesses to the instruction cache result in a miss.

[0005] However, misses to the instruction cache can still adversely affect fetch performance even when using a separated front-end architecture by reducing the rate at which FTQ entries can be processed. The occurrence of instruction cache misses can be reduced by increasing the size of the instruction cache and using a more intelligent replacement policy when evicting contents from the instruction cache. However, a larger instruction cache may incur higher access latency and may require the expenditure of more energy per access. The latency and energy cost incurred by accessing the instruction cache can be exacerbated when processing FTQ entries that require multiple accesses to the instruction cache, such as when an FTQ entry spans multiple cache lines or when reading an instruction cache entry provides only a subset of the requested cache lines. Summary of the Invention

[0006] overview Aspects disclosed herein include accelerating fetch target queue (FTQ) processing in a processor. In one example aspect, the processor includes an FTQ acceleration cache (FAC), where the FAC includes multiple FAC entries, each corresponding to an FTQ entry among multiple FTQ entries in the processor's FTQ. The processor generates each FAC entry (e.g., when enqueuing the corresponding FTQ entry) including metadata for the corresponding FTQ entry, which can be used to accelerate processing of the FTQ entry. Upon receiving a subsequent request for access to the FTQ entry, the processor locates the FAC entry in the FAC and uses the metadata of the FAC entry to perform accelerated processing of the request. In this manner, the FAC can reduce power consumption by avoiding redundant accesses to the processor's instruction cache and can enable higher throughput by improving fetch performance. The FAC can further improve processor performance by accelerating the detection of future cache misses and avoiding potential structural hazards in the instruction cache (e.g., port contention or port limitations).

[0007] In some aspects, the metadata may include a translation mapping corresponding to the fetch address bundle of the corresponding FTQ entry. A processor in such aspects may obtain the translation mapping as part of a process of generating a FAC entry, and may then perform accelerated processing of the request by using the translation mapping when fetching instructions corresponding to multiple sequential virtual addresses (VAs) of the fetch address bundle. Some such aspects further provide that when the processor detects a change in the translation state of the translation mapping, the processor may invalidate all of the FAC entries in the FAC, or may invalidate only specific FAC entries based on tags that store the translation states of the FAC entries.

[0008] According to some aspects, the metadata may include a set value and a way value indicating a set and a way, respectively, in which a cache line of a plurality of cache lines corresponding to the plurality of sequential VAs is stored in an instruction cache of the processor. After generating the FAC entry, the processor in such aspects may identify a set and a way of the instruction cache in which the cache line is stored in the instruction cache and may update the set and way values ​​of the FAC entry to indicate the set and way. The processor then performs accelerated processing of the request by using the processor's fetch circuitry to access the instruction cache's data array using the set and way values ​​without accessing the instruction cache's tag array. Some such aspects further provide that upon detecting eviction of the cache line from the instruction cache, the FAC may invalidate the entire FAC entry or set valid indicators in the metadata to indicate that the cache line's corresponding set and way values ​​are invalid.

[0009] Some aspects may provide that the metadata includes one or more instructions corresponding to one or more VAs of the plurality of sequential VAs. In such aspects, the processor may perform accelerated processing of the request by fetching one or more instructions from the FAC entry rather than from an instruction cache of the processor using the fetch circuitry. According to some aspects, the metadata may include one or more instructions corresponding to a first subset of the plurality of sequential VAs, and may further include set and way values ​​for each of one or more cache lines corresponding to a second subset of the plurality of sequential VAs.

[0010] In this regard, in another exemplary aspect, a processor for accelerating FTQ processing is disclosed. The processor includes an FTQ and a FAC, and is configured to use the FAC to generate a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries in the FTQ, the FTQ entry including a fetch address bundle including a plurality of sequential VAs, and the FAC entry including metadata for the FTQ entry. The processor is further configured to receive a request to access the FTQ entry using the FTQ. In response to receiving the request to access the FTQ entry, the processor is also configured to use the FAC to locate the FAC entry among the plurality of FAC entries in the FAC that corresponds to the FTQ entry. The processor is further configured to perform accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

[0011] In another exemplary aspect, a method for accelerating FTQ processing is disclosed. The method includes using a FAC of a processor to generate a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries of an FTQ of the processor, the FTQ entry including a fetch address bundle including a plurality of sequential VAs, and the FAC entry including metadata for the FTQ entry. The method further includes receiving a request to access the FTQ entry. The method also includes, in response to receiving the request to access the FTQ entry, using the FAC to locate the FAC entry among the plurality of FAC entries of the FAC that corresponds to the FTQ entry. Additionally, the method further includes using the metadata of the FAC entry to perform accelerated processing of the request to access the FTQ entry.

[0012] In another exemplary aspect, a non-transitory computer-readable medium having computer-executable instructions stored thereon is disclosed. The computer-executable instructions cause the processor to generate a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries of an FTQ of the processor, the FTQ entry including a fetch address bundle including a plurality of sequential VAs, and the FAC entry including metadata for the FTQ entry. The computer-executable instructions further cause the processor to receive a request to access the FTQ entry. In response to receiving the request to access the FTQ entry, the computer-executable instructions further cause the processor to locate, within the FAC, a FAC entry among the plurality of FAC entries of the FAC that corresponds to the FTQ entry. The computer-executable instructions further cause the processor to perform accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

[0013] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0014] Brief description of the drawing figures The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram of an exemplary processor-based system including a processor including a fetch target queue (FTQ) and an FTQ acceleration cache (FAC) for accelerating FTQ processing, according to some aspects. [Figure 2] FIG. 1 illustrates an example FAC whose metadata includes translation mappings for virtual addresses (VAs) in corresponding FTQ entries, according to some aspects. [Figure 3]FIG. 10 illustrates an example FAC whose metadata includes a set value and a way value for a cache line corresponding to a VA in a corresponding FTQ entry, according to some aspects. [Figure 4] FIG. 10 illustrates an example FAC whose metadata includes instructions corresponding to a VA in a corresponding FTQ entry, according to some aspects. [Figure 5] FIG. 10 illustrates an example FAC whose metadata includes both an instruction corresponding to a first subset of VAs in a corresponding FTQ entry and a set value and a way value for a cache line corresponding to a second subset of VAs in the corresponding FTQ entry, according to some aspects. [Figure 6A] 1 provides a flowchart illustrating exemplary operations for accelerating FTQ processing using the FAC of FIGS. 1-5, according to some embodiments. [Figure 6B] 1 provides a flowchart illustrating exemplary operations for accelerating FTQ processing using the FAC of FIGS. 1-5, according to some embodiments. [Figure 6C] 1 provides a flowchart illustrating exemplary operations for accelerating FTQ processing using the FAC of FIGS. 1-5, according to some embodiments. [Figure 7] FIG. 6 is a block diagram of an exemplary processor-based system including a processor including a FAC, such as the FAC of FIGS. 1-5, for accelerating FTQ processing. DETAILED DESCRIPTION OF THE INVENTION

[0016] Detailed Description Aspects disclosed herein include accelerating fetch target queue (FTQ) processing in a processor. In one example aspect, the processor includes an FTQ acceleration cache (FAC), where the FAC includes multiple FAC entries, each corresponding to an FTQ entry among multiple FTQ entries in the processor's FTQ. The processor generates each FAC entry (e.g., when enqueuing the corresponding FTQ entry) including metadata for the corresponding FTQ entry, which can be used to accelerate processing of the FTQ entry. Upon receiving a subsequent request for access to the FTQ entry, the processor locates the FAC entry in the FAC and uses the metadata of the FAC entry to perform accelerated processing of the request. In this manner, the FAC can reduce power consumption by avoiding redundant accesses to the processor's instruction cache and can enable higher throughput by improving fetch performance. The FAC can further improve processor performance by accelerating the detection of future cache misses and avoiding potential structural hazards in the instruction cache (e.g., port contention or port limitations).

[0017] In some aspects, the metadata may include a translation mapping corresponding to the fetch address bundle of the corresponding FTQ entry. A processor in such aspects may obtain the translation mapping as part of a process of generating a FAC entry, and may then perform accelerated processing of the request by using the translation mapping when fetching instructions corresponding to multiple sequential virtual addresses (VAs) of the fetch address bundle. Some such aspects further provide that when the processor detects a change in the translation state of the translation mapping, the processor may invalidate all of the FAC entries in the FAC, or may invalidate only specific FAC entries based on tags that store the translation states of the FAC entries.

[0018] According to some aspects, the metadata may include a set value and a way value indicating a set and a way, respectively, in which a cache line of a plurality of cache lines corresponding to the plurality of sequential VAs is stored in an instruction cache of the processor. After generating the FAC entry, the processor in such aspects may identify a set and a way of the instruction cache in which the cache line is stored in the instruction cache and may update the set and way values ​​of the FAC entry to indicate the set and way. The processor then performs accelerated processing of the request by using the processor's fetch circuitry to access the instruction cache's data array using the set and way values ​​without accessing the instruction cache's tag array. Some such aspects further provide that upon detecting eviction of the cache line from the instruction cache, the FAC may invalidate the entire FAC entry or set valid indicators in the metadata to indicate that the cache line's corresponding set and way values ​​are invalid.

[0019] Some aspects may provide that the metadata includes one or more instructions corresponding to one or more VAs of the plurality of sequential VAs. In such aspects, the processor may perform accelerated processing of the request by fetching one or more instructions from the FAC entry rather than from an instruction cache of the processor using the fetch circuitry. According to some aspects, the metadata may include one or more instructions corresponding to a first subset of the plurality of sequential VAs, and may further include set and way values ​​for each of one or more cache lines corresponding to a second subset of the plurality of sequential VAs.

[0020] In this regard, Figure 1 is a diagram of an exemplary processor-based system 100 that includes a processor 102. Processor 102, which may also be referred to as a "processor core" or "central processing unit (CPU) core," may be an in-order processor or an out-of-order processor (OoP) and / or may be one of multiple processors 102 provided by processor-based system 100. In the example of Figure 1, processor 102 includes one or more instruction pipelines I0-I1 for processing instructions 106 fetched by fetch circuitry 110 from instruction memory (labeled in Figure 1 as "INSTR memory") 108 for execution. N The instruction processing circuit 104 includes:

[0021] Instruction memory 108 may be provided, by way of non-limiting example, within or as part of system memory within processor-based system 100. An instruction cache (denoted in FIG. 1 as "INSTR cache") 112 may also be provided within processor 102 for caching instructions 106 fetched from instruction memory 108 to reduce latency within fetch circuitry 110. As used herein, "instruction cache 112" generally refers to both the elements used to tag and store cached data and the cache controller circuitry used to manage access to the cached data.

[0022] 1, the fetch circuit 110 transfers the instruction 106 as a fetched instruction 106F to one or more instruction pipelines I0-I1 in the instruction processing circuit 104 for preprocessing before the fetched instruction 106F reaches the execution circuit (shown as "EXEC circuit" in FIG. 1) 114 for execution. N The instruction pipelines I0 to I Nare provided across different processing circuits or stages of the instruction processing circuitry 104 to pre-process and process the fetched instructions 106F in a series of steps that can be executed simultaneously to increase throughput, prior to execution of the fetched instructions 106F by the execution circuitry 114.

[0023] 1, instruction processing circuitry 104 includes decode circuitry 116 configured to decode fetched instructions 106F fetched by fetch circuitry 110 into decoded instructions 106D to determine the type and action of the required instruction. The type and action of the required instruction encoded within decoded instructions 106D determines which instruction pipeline 100-1000 the decoded instructions 106D will be assigned to. N In this example, the decoded instruction 106D is placed in the instruction pipeline I0-I1. N and then provided to renaming circuitry 118 within instruction processing circuitry 104. Renaming circuitry 118 is configured to determine whether any register names within decoded instruction 106D should be renamed to break any register dependencies that would prevent parallel or out-of-order processing.

[0024] 1 also includes register access circuitry (denoted in FIG. 1 as "RACC circuitry") 120. Register access circuitry 120 is configured to access physical registers in a physical register file (PRF) (not shown) based on mapping entries mapped to logical registers in a register mapping table (RMT) (not shown) of source register operands of decoded instruction 106D to obtain values ​​derived from executed instruction 106E in execution circuitry 114. Register access circuitry 120 is also configured to provide the derived values ​​derived from executed instruction 106E as source register operands of decoded instruction 106D to be executed.

[0025] Furthermore, the instruction processing circuit 104 includes instruction pipelines I0 to IN A scheduler circuit 122 (denoted in FIG. 1 as "SCHED circuit") is provided within the instruction processing circuit 104 and configured to store the decoded instructions 106D in reservation entries until all source register operands for the decoded instructions 106D are available. The scheduler circuit 122 issues the decoded instructions 106D that are ready for execution to the execution circuit 114. A write circuit 124 is also provided within the instruction processing circuit 104 and writes or commits values ​​generated from the executed instructions 106E back to memory (such as the PRF), cache memory, or system memory.

[0026] 1, instruction processing circuitry 104 also includes branch predictor circuitry 126. Branch predictor circuitry 126 determines whether instructions corresponding to a taken path or a not-taken path within an instruction control flow path are being routed to instruction pipelines I0-I1 for execution. N The execution circuitry 114 is configured to speculatively predict the outcome of a fetched branch instruction, which controls whether the instruction processing circuitry 104 will be fetched within the execution circuitry 114. In this way, the outcome of a fetched branch instruction does not need to be resolved at execution time by the execution circuitry 114 before the instruction processing circuitry 104 can continue processing other fetched instructions.

[0027] To decouple branch prediction operations from instruction fetch operations, processor 102 provides FTQ 128 communicatively coupled to both instruction cache 112 and branch predictor circuit 126. FTQ 128 includes multiple FTQ entries 130(0)-130(Q), each of which stores a fetch address bundle (denoted as a "bundle" in FIG. 1 ) 132(0)-132(Q) generated by branch predictor circuit 126. Each fetch address bundle 132(0)-132(Q) stores multiple sequential VAs (denoted as "VAs" in FIG. 1 ) 134(0)-134(Q), 134'(0)-134'(Q) corresponding to a sequence of instructions predicted by branch predictor circuit 126 to be executed next. Instruction cache 112 and fetch circuitry 110 operate on FTQ entries 130(0)-130(Q) of FTQ 128 to fetch instructions to be processed by instruction processing circuitry 104. FTQ 128 thus acts as a buffer between instruction cache 112 and branch predictor circuitry 126, allowing branch predictor circuitry 126 to continue generating branch predictions (represented by fetch address bundles 132(0)-132(Q) in FIG. 1 ) even if an access to instruction cache 112 results in a miss.

[0028] However, as discussed above, misses to instruction cache 112 can still adversely affect the fetch performance of processor 102, even with FTQ 128, by slowing the rate at which FTQ entries 130(0)-130(Q) can be processed. Therefore, processor 102 provides FAC 136 to accelerate the processing of FTQ entries 130(0)-130(Q). As used herein, "FAC 136" generally refers to both the elements used to store cached data and the cache controller circuitry used to manage access to the cached data. FAC 136 includes multiple FAC entries 138(0)-138(F), each of which corresponds to an FTQ entry in the multiple FTQ entries 130(0)-130(Q). In some aspects, FAC entries 138(0)-138(F) may be virtually indexed and virtually tagged using the VAs of corresponding FTQ entries 130(0)-130(Q), such as the first sequential VA 134(0), 134′(0) of the corresponding FTQ entries 130(0), 130(Q).

[0029] Each of FAC entries 138(0)-138(F) stores metadata (denoted as "meta" in FIG. 1 ) 140(0)-140(F) of the corresponding FTQ entry 130(0)-130(Q), which may be used to accelerate processing of requests for the corresponding FTQ entry 130(0)-130(Q). Thus, in exemplary operation, processor 102 is configured to generate a FAC entry, such as FAC entry 138(0), corresponding to an FTQ entry (e.g., FTQ entry 130(0)) when FTQ entry 130(0) is enqueued by FTQ 128 (i.e., using FAC 136). Thereafter, when a request 142 to access FTQ entry 130(0) is received by FTQ 128 (e.g., as a non-limiting example, from instruction cache 112), processor 102 is configured to locate, within FAC 136, FAC entry 138(0) that corresponds to FTQ entry 130(0). Processor 102 is then configured to perform accelerated processing of request 142 using metadata 140(0) of FAC entry 138(0).

[0030] The use of different types of metadata 140(0)-140(F) and how each may be used in the aspects disclosed herein to perform accelerated processing of request 142 are discussed in more detail below with respect to Figures 2-5. In particular, Figure 2 illustrates an aspect in which metadata 140(0)-140(F) include translation mappings for FTQ entries 130(0)-130(Q) corresponding to FAC entries 138(0)-138(F), while Figure 3 illustrates an area-efficient aspect in which metadata 140(0)-140(F) include set and way data indicating where in instruction cache 112 cache lines corresponding to sequential VAs 134(0)-134(Q), 134'(0)-134'(Q) are stored. Figure 4 illustrates a high performance embodiment in which metadata 140(0)-140(F) contains the actual instructions corresponding to sequential VAs 134(0)-134(Q), 134'(0)-134'(Q), and Figure 5 illustrates a hybrid embodiment that combines features of the embodiments shown in Figures 3 and 4. It should be understood that in some embodiments disclosed herein, the features shown in Figures 2-5 may be combined.

[0031] Referring now to Figure 2, the FAC 136, FAC entries 138(0)-138(F), and metadata 140(0)-140(F) of Figure 1 are shown in more detail, in accordance with some aspects. The metadata 140(0)-140(F) shown in Figure 2 each correspond to one of the fetch address bundles 132(0)-132(Q) of the FTQ entries 130(0)-130(Q) of Figure 1, and include a plurality of translation mappings 200(0)-200(F) that represent a mapping from a virtual address to a physical address for the corresponding fetch address bundle 132(0)-132(Q). In some aspects, the translation mappings 200(0)-200(F) may be obtained by the processor 102 of Figure 1 during conventional operation. For example, if instruction cache 112 of Figure 1 is a virtually indexed physical tag (VIPT) cache or a physically indexed physical tag (PIPT) cache, processor 102 may perform translation mapping as part of an access to instruction cache 112 and capture the results of such translation mapping as translation mappings 200(0)-200(F). Processor 102 of an embodiment according to Figure 2 may then use metadata 140(0)-140(F) to perform accelerated processing of request 142 of Figure 1 by using translation mappings 200(0)-200(F) to fetch instructions corresponding to multiple VAs 134(0)-134(Q), 134'(0)-134'(Q) of Figure 1 without having to access other data structures such as a translation lookaside buffer (TLB).

[0032] Changes in the translation state of the plurality of translation mappings 200(0)-200(F) can cause the FAC entries 138(0)-138(F) to become stale over time, which may result in incorrect memory accesses. Accordingly, some aspects may provide that the processor 102 is configured to detect changes in the translation state of the plurality of translation mappings 200(0)-200(F). In response to detecting a change in the translation state, the processor 102 may simply invalidate all of the plurality of FAC entries 138(0)-138(F) (e.g., using the FAC 136). Some aspects may provide that each of the FAC entries 138(0)-138(F) includes a corresponding tag 202(0)-202(F) in which the translation state of the corresponding translation mapping 200(0)-200(F) is stored. If a change in the translation state of one or more of the FAC entries 138(0)-138(F) is detected, the FAC 136 in such an embodiment can invalidate only one or more of the FAC entries 138(0)-138(F) based on the corresponding tags 202(0)-202(F).

[0033] FIG. 3 illustrates an area-efficient aspect of FAC 136 of FIG. 1 , showing FAC entries 138(0)-138(F) and metadata 140(0)-140(F) of FIG. 1 in accordance with some aspects. FIG. 3 also illustrates instruction cache 112 of FIG. 1 in more detail in accordance with some aspects. As seen in FIG. 3 , instruction cache 112 includes a tag array 300 in which tag data (not shown) for data stored therein is maintained, and a data array 302 in which the actual cached data is stored. Data array 302 is organized into a number of sets 304(0)-304(S), each of which is further organized into a number of ways 306(0)-306(W), 306′(0)-306′(W). Ways 306(0)-306(W), 306'(0)-306'(W) store corresponding cache lines 308(0)-308(W), 308'(0)-308'(W), each of which may represent one or more cached instructions (not shown).

[0034] In the example of FIG. 3, metadata 140(0)-140(F) stores set values ​​310(0)-310(C), 310'(0)-310'(C) and way values ​​312(0)-312(C), 312'(0)-312'(C) that indicate where cache lines such as cache lines 308(0)-308(W), 308'(0)-308'(W) corresponding to the VAs of the multiple sequential VAs 134(0)-134(Q), 134'(0)-134'(Q) in FIG. 1 are stored within the instruction cache 112. Thus, for example, metadata 140(0) of FAC entry 138(0) stores set values ​​310(0)-310(C) and way values ​​312(0)-312(C) that indicate the set and way, respectively, in which a cache line (e.g., cache line 308(0)) corresponding to multiple sequential VAs 134(0)-134(Q) of FTQ entry 130(0) is stored in instruction cache 112. 3 can then use metadata 140(0)-140(F) to perform accelerated processing of request 142 of FIG. 1 by using set values ​​310(0)-310(C), 310′(0)-310′(C) and way values ​​312(0)-312(C), 312′(0)-312′(C) to obtain cache lines 308(0)-308(W), 308′(0)-308′(W) by directly accessing data array 302 of instruction cache 112, without accessing tag array 300 of instruction cache 112. This allows processor 102 to store only a relatively small amount of data in FAC 136, while accessing cached data in instruction cache 112 in a more power-efficient manner.

[0035] 1 may be configured, after generating FAC entry 138(0) (e.g., when storing cache line 308(0) in instruction cache 112), to identify set 304(0) and way 306(0) of instruction cache 112 in which cache line 308(0) is stored in instruction cache 112. Processor 102 may then be configured to update set value 310(0) and way value 312(0) of FAC entry 138(0) to indicate set 304(0) and way 306(0).

[0036] Eviction of cache lines among cache lines 308(0)-308(W), 308'(0)-308'(W) by instruction cache 112 can cause FAC entries 138(0)-138(F) of FIG. 3 to become stale over time, which may result in incorrect fetches using set values ​​310(0)-310(C), 310'(0)-310'(C) and way values ​​312(0)-312(C), 312'(0)-312'(C). Accordingly, to maintain coherence between FAC 136 and instruction cache 112, some aspects may provide that processor 102 may be configured to detect eviction of cache lines, such as cache line 308(0), from instruction cache 112. In response to detecting the eviction, FAC 136 may perform one or more of several operations. In some aspects, FAC 136 invalidates corresponding FAC entry 138(0) along with any other of FAC entries 138(0)-138(F) that store the same pair of set values ​​310(0)-310(C), 310'(0)-310'(C) and way values ​​312(0)-312(C), 312'(0)-312'(C) for cache line 308(0). Some aspects may provide that corresponding pairs of set values ​​310(0)-310(C), 310'(0)-310'(C) and way values ​​312(0)-312(C), 312'(0)-312'(C) are associated with valid indicators (labeled "valid" in FIG. 3 ) 314(0)-314(C), 314'(0)-314'(C). In such an aspect, upon detecting the eviction of cache line 308(0), FAC 136 may set valid indicator 314(0) associated with set value 310(0) and way value 312(0) to indicate that set value 310(0) and way value 312(0) of cache line 308(0) are invalid.FAC 136 may similarly set other valid indicators 314(0)-314(C), 314'(0)-314'(C) to indicate that the corresponding set values ​​310(0)-310(C), 310'(0)-310'(C) and way values ​​312(0)-312(C), 312'(0)-312'(C) stored in other FAC entries 138(0)-138(F) for cache line 308(0) are invalid.

[0037] FIG. 4 illustrates a high-performance aspect of FAC 136 of FIG. 1 according to some aspects, further illustrating FAC entries 138(0)-138(F) and metadata 140(0)-140(F) of FIG. 1 according to some aspects. In the example of FIG. 4, metadata 140(0)-140(F) include instructions 400(0)-400(Q), 400'(0)-400'(Q) corresponding to multiple sequential VAs 134(0)-134(Q), 134'(0)-134'(Q) of FIG. 1. Instructions 400(0)-400(Q), 400'(0)-400'(Q) in some aspects may be captured as they are fetched by fetch circuitry 110 and used to populate FAC entries 138(0)-138(F). Processor 102 of FIG. 1 can then use metadata 140(0)-140(F) to perform accelerated processing of request 142 of FIG. 1 by using fetch circuitry 110 to fetch instructions 400(0)-400(Q), 400′(0)-400′(Q) from FAC entries 138(0)-138(F) rather than from instruction cache 112 of FIG. 1 , thus reducing the energy consumption that would otherwise be incurred by accessing instruction cache 112.

[0038] 4 is kept coherent with the contents of instruction cache 112. Thus, for example, FAC 136 may be configured to detect a cache line invalidation by instruction cache 112 and to update one or more of FAC entries 138(0)-138(F) and / or individual metadata 140(0)-140(F) of instructions 400(0)-400(Q), 400'(0)-400'(Q) to indicate that instructions 400(0)-400(Q), 400'(0)-400'(Q) corresponding to the cache line invalidation by instruction cache 112 are invalid.

[0039] Figure 5 illustrates a hybrid embodiment of the FAC 136 of Figure 1 that incorporates features of the embodiments illustrated in Figures 3 and 4. As seen in Figure 5, FAC entries 138(0)-138(F) and metadata 140(0)-140(F) according to some embodiments are shown. The metadata 140(0)-140(F) includes one or more instructions 500(0)-500(X), 500'(0)-500'(X) corresponding to a first subset of the plurality of sequential VAs 134(0)-134(Q), 134'(0)-134'(Q) of FIG. 1, respectively, and further includes one or more pairs of set values ​​502(0)-502(Z), 502'(0)-502'(Z) and way values ​​504(0)-504(Z), 504'(0)-504'(Z) for each cache line corresponding to a second subset of the plurality of sequential VAs 134(0)-134(Q), 134'(0)-134'(Q) of FIG. 1. 1 can then use metadata 140(0)-140(F) to perform accelerated processing of request 142 of FIG. 1 by fetching instructions 500(0)-500(X), 500′(0)-500′(Q) from FAC entries 138(0)-138(F) using fetch circuitry 110, and further fetching subsequent instructions from instruction cache 112 using set values ​​502(0)-502(Z), 502′(0)-502′(Z) and way values ​​504(0)-504(Z), 504′(0)-504′(Z). In some aspects, each of FAC entries 138(0)-138(F) can be configured to store a different number of instructions 500(0)-500(X), 500′(0)-500′(X). Some such aspects may associate each of FAC entries 138(0)-138(F) with a hit counter (not shown). If the hit counter for a FAC entry, such as FAC entry 138(0), is determined to exceed a threshold value (not shown), FAC entry 138(0) may be configured to store more instructions 500(0)-500(X), 500′(0)-500′(X), or may otherwise be configured to store fewer instructions 500(0)-500(X), 500′(0)-500′(X), or no instructions.

[0040] To illustrate example operations performed by the FAC 136 of Figures 1-5 to accelerate FTQ processing, Figures 6A-6C provide a flowchart illustrating example operations 600. For clarity, reference will be made to elements of Figures 1-5 when describing Figures 6A-6C. 6A, the exemplary operations 600 begin with the processor 102 (e.g., using the FAC 136 of FIGS. 1-5) generating a FAC entry (e.g., FAC entry 138(0) of FIGS. 1-5) corresponding to an FTQ entry among a plurality of FTQ entries in the FTQ of the processor 102 (e.g., FTQ entry 130(0) of a plurality of FTQ entries 130(0)-130(Q) of the FTQ 128 of FIG. 1), where the FTQ entry 130(0) includes a fetch address bundle (e.g., fetch address bundle 132(0) of FIG. 1) that includes a plurality of sequential VAs (e.g., sequential VAs 134(0)-134(Q) of FIG. 1), and the FAC entry 138(0) includes metadata (e.g., metadata 140(0) of FIGS. 1-5) for the FTQ entry 130(0) (block 602). In an aspect such as that shown in FIG. 2, the operations of block 602 to generate FAC entry 138(0) may include obtaining a transformation mapping, such as transformation mapping 200(0) of FIG. 2 (block 604).

[0041] 3 and 5, processor 102 may identify a set and a way (e.g., set 304(0) and way 306(0), respectively, of instruction cache (e.g., instruction cache 112 of FIGS. 1 and 3) in which a plurality of cache lines corresponding to a plurality of sequential VAs 134(0)-134(Q) (e.g., cache line 308(0) of a plurality of cache lines 308(0)-308(W) of FIG. 3) are stored in instruction cache 112 (block 606). Processor 102 then updates the set and way values ​​(e.g., set value 310(0) and way value 312(0) of FIG. 3) of FAC entry 138(0) to indicate set 304(0) and way 306(0) (block 608).

[0042] Thereafter, FTQ 128 of processor 102 receives a request to access FTQ entry 130(0) (e.g., request 142 of FIG. 1) (block 610). In response to receiving request 142 to access FTQ entry 130(0), a series of operations are performed (block 612). FAC 136 locates FAC entry 138(0) among multiple FAC entries of FAC 136 (e.g., FAC entries 138(0)-138(F) of FIGS. 1-5) that corresponds to FTQ entry 130(0) (block 614). The example operations 600 then proceed to block 616 of FIG. 6B.

[0043] 6B, the operations of block 612 of FIG. 6A continue with processor 102 performing accelerated processing of request 142 to access FTQ entry 130(0) using metadata 140(0) of FAC entry 138(0) (block 616). According to some aspects as shown in FIG. 2, the operations of block 616 to perform accelerated processing of request 142 may include fetching circuitry of instruction processing circuitry of processor 102 (e.g., fetch circuitry 110 of instruction processing circuitry 104 of FIG. 1) fetching one or more instructions using translation mapping 200(0) (block 618). 3 and 5, the operations of block 616 to perform accelerated processing of request 142 may include fetch circuitry 110 accessing a data array (e.g., data array 302 of FIG. 3 ) of instruction cache 112 using set value 310(0) and way value 312(0) without accessing a tag array (e.g., tag array 300 of FIG. 3 ) of instruction cache 112 (block 620). In some aspects, such as those shown in FIGS. 4 and 5, the operations of block 616 to perform accelerated processing of request 142 may include fetch circuitry 110 fetching one or more instructions (e.g., instructions 400(0)-400(Q) of FIG. 4 ) from FAC entry 138(0) rather than from instruction cache 112 of processor 102 (block 622). In some aspects, the example operations 600 may continue at block 624 of FIG. 6C.

[0044] 6C , in some aspects, processor 102 may detect a change in translation mapping 200(0) (block 624). In response to detecting a change in translation state, in some aspects, FAC 136 may perform one or more of several actions (block 626). According to some aspects, FAC 136 may invalidate multiple FAC entries 138(0)-138(F) (block 628). Some aspects may provide that FAC 136 may invalidate FAC entry 138(0) based on a tag of FAC entry 138(0) (e.g., tag 202(0) of FIG. 2) (block 630).

[0045] In some aspects, processor 102 may detect the eviction of cache line 308(0) from instruction cache 112 (block 632). In response to detecting the eviction, FAC 136 may perform one or more of several actions (block 634). Some aspects may provide that FAC 136 invalidates FAC entry 138(0) (block 636). According to some aspects, FAC 136 may set a valid indicator in metadata 140(0) (e.g., valid indicator 314(0) in FIG. 3 ) to indicate that set value 310(0) and way value 312(0) of cache line 308(0) are invalid (block 638).

[0046] 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 (e.g., a microprocessor) that includes an instruction processing circuit 704 and an FAC 706 that corresponds in function to FAC 136 of FIG. 1. The instruction processing circuit 704 may, by way of example, be the instruction processing circuit 104 in processor 102 of FIG. 1. The processor-based system 700 may, by way of example, be processor-based system 100 of FIG. 1. The processor-based system 700 may be circuitry contained within an electronic board card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and may represent, for example, a server or a user's computer.

[0047] In this example, processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. Processor 702 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 708 for temporary, fast-access memory storage of instructions accessible by instruction processing circuitry 704. Instructions fetched or prefetched from a memory, such as system memory 710, over system bus 712 are stored in instruction cache 708. Instruction processing circuitry 704 is configured to process instructions fetched into instruction cache 708 and process the instructions for execution.

[0048] The processor 702 and system memory 710 are coupled to a system bus 712, which may interconnect peripheral devices included within the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information over the system bus 712. For example, the processor 702 may communicate bus transaction requests to a memory controller 714 within the system memory 710, serving as an example of a slave device. Although not shown in FIG. 7, multiple system buses 712 may be provided, with each system bus comprising a different fabric. In this example, the memory controller 714 is configured to provide memory access requests to a memory array 716 within the system memory 710. The memory array 716 comprises an array of storage bit cells for storing data. The system memory 710 may be, by way of non-limiting example, a read-only memory (ROM), flash memory, a dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0049] Other devices may be connected to the system bus 712. As shown in FIG. 7, these devices may include, by way of example, a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input devices 718 may include any type of input device, including but not limited to, input keys, switches, audio processors, etc. The output devices 720 may include any type of output device, including but not limited to, audio, video, other visual indicators, etc. The modem 722 may be any device configured to enable data exchange with a network 726. The network 726 may be any type of network, including but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 722 may be configured to support any type of communication protocol desired. The processor 702 may also be configured to access a display controller 724 over the system bus 712 to control information sent to one or more displays 728. The displays 728 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0050] 7 may include a set of instructions 730 that are executed by processor 702 for any desired application in accordance with the instructions. The instructions 730 may be stored in system memory 710, processor 702, and / or instruction cache 708, as examples of non-transitory computer-readable medium 732. The instructions 730 may also reside completely or at least partially within system memory 710 and / or processor 702 during execution. The instructions 730 may further be transmitted or received over network 726 via modem 722, such that network 726 includes computer-readable medium 732.

[0051] Although the computer-readable medium 732 is illustrated in the exemplary embodiment as being a single medium, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0052] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be performed by machine-executable instructions that may be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0053] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory, etc.).

[0054] Unless otherwise specified, and as is evident from the preceding discussion, discussions utilizing terms such as "processing," "computing," "determining," "displaying," and the like throughout this specification should be understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display device.

[0055] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it may prove more convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0056] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the systems described herein may, by way of example, be employed within any circuit, hardware component, integrated circuit (IC), or IC chip. The memories disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present invention.

[0057] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0058] The embodiments disclosed herein may be implemented by hardware and instructions stored in the hardware, such as RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0059] It should also be noted that the operational steps described in any of the exemplary embodiments herein have been set forth to provide examples and explanations. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, operations described within a single operational step may actually be performed in several different steps. In addition, one or more operational steps discussed in an exemplary embodiment may be combined. Those skilled in the art will also appreciate that information and signals may be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0060] Unless otherwise specified, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps should be followed, or unless the claim or description is otherwise specifically stated to limit the steps to a particular order, no particular order is intended to be inferred.

[0061] It will be apparent to those skilled in the art that various modifications and alterations are possible without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations, and alterations of the disclosed embodiments incorporating the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed as including all those within the scope of the appended claims and their equivalents.

Claims

1. 1. A processor including a fetch target queue (FTQ) and an FTQ acceleration cache (FAC), generating a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries of the FTQ using the FAC; The FTQ entry includes a fetch address bundle that includes multiple sequential virtual addresses (VAs); and generating the FAC entry, the FAC entry including metadata for the FTQ entry; receiving a request to access the FTQ entry using the FTQ; In response to receiving the request to access the FTQ entry, using the FAC to locate a FAC entry among a plurality of FAC entries in the FAC that corresponds to the FTQ entry; using the metadata of the FAC entry to perform accelerated processing of the request to access the FTQ entry; a processor configured to:

2. an instruction processing circuit including a fetch circuit; Instruction cache and Further comprising: The metadata includes a translation mapping corresponding to the fetch address bundle of the FTQ entry; and The processor: configured to obtain the transformation mapping to generate the FAC entry; using the fetch circuitry to fetch one or more instructions using the translation mapping, thereby performing the accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry; The processor of claim 1 configured to:

3. detecting a change in a transformation state of the transformation mapping; invalidating the plurality of FAC entries in response to detecting the change in the translation state; The processor of claim 2 , further configured to:

4. The FAC entry includes a tag containing the transformation state of the transformation mapping; and The processor: detecting a change in the transformation state of the transformation mapping; In response to detecting the change in the translation state, invalidating the FAC entry based on the tag of the FAC entry; The processor of claim 2 , further configured to:

5. an instruction processing circuit including a fetch circuit; an instruction cache including a tag array and a data array; Further comprising: the metadata includes, for each cache line among a plurality of cache lines corresponding to the plurality of sequential VAs, corresponding set and way values ​​that indicate a set and a way, respectively, in which the cache line is stored within the instruction cache; The processor: identifying a set and way of the instruction cache in which cache lines of the plurality of cache lines corresponding to the plurality of sequential VAs are stored within the instruction cache; updating the set value and the way value of the FAC entry to indicate the set and the way; and 2. The processor of claim 1, wherein the processor is configured to use the fetch circuitry to access the data array of the instruction cache using the set value and the way value without accessing the tag array of the instruction cache, thereby using the metadata of the FAC entry to perform the accelerated processing of the request to access the FTQ entry.

6. detecting an eviction of the cache line from the instruction cache; In response to detecting the eviction, invalidating the FAC entry. The processor of claim 5 , further configured to:

7. the metadata further includes a valid indicator for each cache line of the plurality of cache lines; and The processor: detecting an eviction of the cache line from the instruction cache; responsive to detecting the eviction, setting the valid indicator to indicate that the set value and the way value of the cache line are invalid; The processor of claim 5 , further configured to:

8. an instruction processing circuit including a fetch circuit; Instruction cache and Further comprising: The metadata includes one or more instructions corresponding to one or more VAs of the plurality of sequential VAs; and 2. The processor of claim 1, wherein the processor is configured to use the fetch circuitry to fetch the one or more instructions from the FAC entry rather than from the instruction cache, thereby using the metadata of the FAC entry to perform the accelerated processing of the request to access the FTQ entry.

9. the instruction cache includes a tag array and a data array; the one or more instructions include one or more instructions corresponding to a first subset of the plurality of sequential VAs; The metadata further includes, for each cache line corresponding to a second subset of the plurality of sequential VAs, corresponding set and way values ​​that indicate a set and a way, respectively, in which the cache line is stored within the instruction cache; and 9. The processor of claim 8, wherein the processor is further configured to use the fetch circuitry to access the data array of the instruction cache using the set value and the way value without accessing the tag array of the instruction cache, thereby configuring the accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry.

10. 1. A method for accelerating fetch target queue (FTQ) processing, comprising: generating, using an FTQ acceleration cache (FAC) of a processor, a FAC entry corresponding to an FTQ entry among a plurality of FTQ entries of an FTQ of the processor; The FTQ entry includes a fetch address bundle that includes multiple sequential virtual addresses (VAs); and generating the FAC entry, the FAC entry including metadata for the FTQ entry; receiving a request to access the FTQ entry; In response to receiving the request to access the FTQ entry, using the FAC to locate a FAC entry among a plurality of FAC entries in the FAC that corresponds to the FTQ entry; using the metadata of the FAC entry to perform accelerated processing of the request to access the FTQ entry; A method comprising:

11. the metadata includes a translation mapping corresponding to the fetch address bundle of the FTQ entry; generating the FAC entry includes obtaining the transformation mapping; and 11. The method of claim 10, wherein using the metadata of the FAC entry to perform the accelerated processing of the request to access the FTQ entry comprises using fetch circuitry of instruction processing circuitry of the processor to fetch one or more instructions using the translation mapping.

12. detecting a change in a transformation state of the transformation mapping; invalidating the plurality of FAC entries in response to detecting the change in the translation state; The method of claim 11 further comprising:

13. The FAC entry includes a tag containing the transformation state of the transformation mapping; and The method comprises: detecting a change in the transformation state of the transformation mapping; In response to detecting the change in the translation state, invalidating the FAC entry based on the tag of the FAC entry; The method of claim 11 further comprising:

14. The metadata includes, for each cache line of a plurality of cache lines corresponding to the plurality of sequential VAs, corresponding set and way values ​​that indicate a set and a way, respectively, in which the cache line is stored within an instruction cache of the processor; and The method comprises: identifying a set and way of the instruction cache in which cache lines of the plurality of cache lines corresponding to the plurality of sequential VAs are stored within the instruction cache; updating the set value and the way value of the FAC entry to indicate the set and the way; and 11. The method of claim 10, wherein performing the accelerated processing of the request to access the FTQ entry using the metadata of the FAC entry comprises using fetch circuitry of instruction processing circuitry of the processor to access a data array of the instruction cache using the set value and the way value without accessing a tag array of the instruction cache.

15. The metadata includes one or more instructions corresponding to one or more VAs of the plurality of sequential VAs; and 11. The method of claim 10, wherein using the metadata of the FAC entry to perform the accelerated processing of the request to access the FTQ entry comprises using fetch circuitry of instruction processing circuitry of the processor to fetch the one or more instructions from the FAC entry rather than from an instruction cache of the processor.

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