Fully differential ESD circuit for high frequency applications

Abstract

A differential ESD circuit is provided for protecting a differential terminal pair of an integrated circuit from electrostatic shock. A first diode is coupled between a first terminal of the differential terminal pair and a first resistor coupled to a voltage node of the integrated circuit. Similarly, a second diode is coupled between a second terminal of the differential terminal pair and a second resistor coupled to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from capacitive loads that would otherwise be present from the first and second diodes.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED ART)

[0001] This application claims priority to and the benefit of U.S. patent application Ser. No. 18 / 070,386, filed Nov. 28, 2022, the entire disclosure of which is incorporated herein by reference as if fully disclosed and for all applicable purposes.

[0002] This application relates to electrostatic discharge (ESD) circuits, and more particularly to fully differential ESD circuits for high frequency applications. [Background technology]

[0003] High-speed data protocols generally use differential signaling due to the resulting robustness against common-mode noise. Accordingly, integrated circuits for such differential high-speed data protocols will have a pair of differential terminals or pins for differential signaling. For example, a universal serial bus (USB) interface for an integrated circuit includes a data positive (DP) terminal and a data negative (DN) terminal. To receive differential signaling, such integrated circuits will typically include a differential pair of transistors. A first transistor in the differential pair has a gate coupled to the D+ terminal, while a second transistor in the differential pair has a gate coupled to the D− terminal. As a result of this coupling of transistors to the differential pair, the differential pair of terminals is highly susceptible to electrostatic damage, such as that caused when one terminal is grounded while the other terminal is exposed to an electrostatic shock-induced charge. Integrated circuits having a pair of differential terminals therefore typically include electrostatic discharge (ESD) circuitry coupled to the differential terminal pair. The ESD circuitry safely conducts the charge induced by an electrostatic shock from the energized terminal to the grounded terminal. However, conventional electrostatic discharge circuits typically load a significant amount of capacitance onto the differential terminals. Summary of the Invention

[0004]

[0004] According to one aspect of the present disclosure, an electrostatic discharge (ESD) circuit is provided, including a first integrated circuit terminal, a second integrated circuit terminal, a voltage node, a first resistor having a first terminal coupled to the voltage node, a second resistor having a first terminal coupled to the voltage node, a first ESD diode coupled between the first integrated circuit terminal and the second terminal of the first resistor, a second ESD diode coupled between the second integrated circuit terminal and the second terminal of the second resistor, a first ESD clamp circuit coupled between the second terminal of the first resistor and ground, and a second ESD clamp circuit coupled between the second terminal of the second resistor and ground.

[0005]

[0005] According to another aspect of the present disclosure, a method of electrostatic discharge is provided, including receiving a first charge from a first electrostatic shock at a first terminal of an integrated circuit, conducting the first charge from the first terminal through a first diode to a power supply node, conducting the first charge from the power supply node through a first RC clamp circuit to a ground node, conducting the first charge from the ground node through a second RC clamp circuit to a first node, the first node being separated from a negative voltage node for a negative voltage by a first resistor, and conducting the first charge from the first node through a second diode to a second terminal of the integrated circuit to dissipate the first electrostatic shock.

[0006]

[0006] According to yet another aspect of the present disclosure, an integrated circuit is provided that includes a first terminal, a second terminal, a first resistor, a second resistor, a first ESD diode coupled between the first terminal and the first resistor, the first ESD diode being coupled to the first resistor through a first node, a second ESD diode coupled between the second terminal and the second resistor, the second ESD diode being coupled to the second resistor through a second node, a first ESD clamp circuit coupled to the first node, and a second ESD clamp circuit coupled to the second node.

[0007]

[0007] These and other advantageous features can be better understood through the following detailed description. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram of an integrated circuit that drives both high-speed data and audio data through a differential terminal pair protected by ESD diodes. [Figure 2]

[0009] FIG. 1 is a circuit diagram of an integrated circuit having an improved differential ESD circuit according to one aspect of the present disclosure. [Figure 3]

[0010] FIG. 1 is a circuit diagram of an integrated circuit having an improved differential ESD circuit according to one aspect of the present disclosure. [Figure 4]

[0011] FIG. 2 is a circuit diagram of an exemplary ESD clamp circuit according to one embodiment of the present disclosure. [Figure 5]

[0012] 1 is a flowchart of a method of operating a differential ESD circuit according to one embodiment of the present disclosure. [Figure 6]

[0013] 1 illustrates several example electronic systems including a differential ESD circuit, according to an embodiment of the present disclosure.

[0009]

[0014] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description, it being understood that like reference numerals are used to identify like elements shown in one or more of the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0015] To better understand capacitive loading from ESD diodes, an exemplary integrated circuit 100 including a differential terminal pair formed by a USB data positive (DP) terminal and a data negative (DN) terminal is shown in FIG. 1. ESD diode D1 has its anode coupled to the DP terminal and its cathode coupled to the node for the power supply voltage Vdd. Similarly, ESD diode D2 has its anode coupled to the node or rail for the negative voltage Vneg and its cathode coupled to the DP terminal. The DN terminal is protected by a similar pair of ESD diodes D3 and D4. The anode of diode D3 is coupled to the DN terminal, while the cathode of diode D3 is coupled to the power supply node. The anode of diode D4 is coupled to the negative voltage rail, while the cathode of diode D4 is coupled to the DN terminal.

[0011]

[0016] Assume that the DP terminal becomes positively charged due to an electrostatic shock while the DN terminal is grounded. The charging of the DP terminal forward biases diode D1, which allows charge to flow from the DP terminal through diode D1 to the power supply node (which may also be referred to as the positive voltage rail). An ESD clamp circuit, such as an RC clamp circuit (not shown), is coupled between the positive and negative voltage rails. As described further herein, the RC clamp circuit is edge-triggered, such that a sudden charging of the positive voltage rail due to an electrostatic discharge causes the RC clamp circuit to conduct, resulting in the charge being transferred to the negative voltage rail. This charging of the negative voltage rail causes diode D4 to conduct, resulting in the charge ultimately being transferred to the DN terminal. The same process described above for an ESD discharge from the DP terminal to the DN terminal will occur if the DN terminal receives a negative charge from an electrostatic shock while the DP terminal is grounded. Conversely, assume that the DN terminal becomes positively charged due to an electrostatic shock while the DP terminal is grounded. Diode D3 then becomes forward biased and conducts positive charge from the DN terminal to the positive voltage rail. The RC clamp circuit then conducts, conducting positive charge from the positive voltage rail to the negative voltage rail. The positive charge on the negative voltage rail forward biases diode D2, which then conducts positive charge through diode D2 to the DP terminal. A similar process to that for an ESD discharge from the DN terminal to the DP terminal will occur if the DP terminal receives a negative charge from an electrostatic shock while the DN terminal is grounded. The combination of diodes D1, D2, D3, and D4 and the RC clamp circuit forms a differential ESD circuit that protects circuitry within integrated circuit 100, such as the differential pair of transistors described above.

[0012]

[0017] The resulting ESD protection of the DP and DN terminals poses problems, especially when the DP and DN terminals are also used for audio signals (e.g., headphone right (HPHR) and headphone left (HPHL) signals). In that regard, integrated circuit 100 may include a pair of switches S1 and S3 that are closed during a high-speed data mode of operation and a pair of switches S2 and S4 that are closed during an audio mode of operation. During the audio mode of operation, integrated circuit 100 may generate audio signals HPHR and HPHL (or these signals may be generated in another integrated circuit and coupled to integrated circuit 100). Audio signal HPHR is coupled to an external device through switch S2 and the DP terminal via USB plug 105. Similarly, audio signal HPHL is coupled to an external device through switch S4 and the DN terminal via USB plug 105. During the audio mode of operation, switches S1 and S3 are open.

[0013]

[0018] During the high-speed data mode of operation, integrated circuit 100 may generate a DP signal (DPin) that couples to an external device (not shown) through switch S1 and the DP terminal, with the external device coupling to the DP and DN terminals through USB plug 105. Similarly, integrated circuit 100 may generate a DN signal (DNin) that couples to the external device via USB plug 105 through switch S3 and the DN terminal. Due to the bidirectional nature of the DP and DN terminals, the external device may instead drive the DP and DN terminals, such that the DPin and DNin signals are received signals rather than signals generated by integrated circuit 100. During the data mode of operation, switches S2 and S4 are open.

[0014]

[0019] During data operation mode, switches S2 and S4 are open, but these switches and associated audio driver circuitry (not shown) load capacitance onto the DP and DN terminals. This capacitive load is exacerbated by the capacitive load from the ESD diodes. For example, diode D2 loads the DP terminal with a parasitic capacitance, represented as Cdiode, that exists between the DP terminal and the negative voltage rail. Similarly, diode D4 loads the DN terminal with a parasitic capacitance that can be equivalently represented as the capacitance Cdiode between the DP terminal and the negative voltage rail. Diodes D1 and D3 introduce similar parasitic capacitance between terminals DP and DN and the positive voltage rail. The parasitic capacitance resulting from the ESD diodes is problematic during high-speed data mode and can result in an undesirable increase in bit error rate.

[0015]

[0020] ESD diodes undesirably load parasitic capacitance on the DP and DN terminals, which require ESD protection. To reduce the capacitive loading on the differential terminals while still providing ESD protection, an improved differential ESD circuit is provided as follows. This improved differential ESD circuit can be used to protect any suitable pair of differential terminals. Thus, while the following description will be directed to a USB implementation, it will be understood that the improved differential ESD circuit disclosed herein can be used to protect differential terminals in other types of high-speed data protocols in addition to the USB protocol.

[0016]

[0021] An exemplary integrated circuit 200 having an improved differential ESD circuit 205 is shown in FIG. 2. As described for integrated circuit 100, integrated circuit 200 includes a USB data positive (DP) terminal and a data negative (DP) terminal. The DP terminal may be referred to herein as a first terminal. Similarly, the DN terminal may be referred to herein as a second terminal. An external device (not shown) is coupled to the DP terminal and the DN terminal through a USB plug 105, similar to that described for integrated circuit 100. As described for integrated circuit 100, ESD diode D1 has an anode coupled to the DP terminal and a cathode coupled to a power supply node for power supply voltage Vdd. However, the anode of ESD diode D2 is no longer directly coupled to the negative voltage rail for negative voltage Vneg, but instead is coupled to a Vneg_R node, which is then coupled to a negative voltage node through a first resistor R. The first resistor R has a first terminal coupled to the negative node and a second terminal coupled to the DP terminal. The Vneg_R node is also referred to herein as the first node. The cathode of diode D2 is coupled to the DP terminal. Diode D3 functions similarly to integrated circuit 100, with the anode of diode D3 coupled to the DN terminal while the cathode of diode D3 is coupled to the power supply node. Similar to diode D2, the anode of diode D4 is coupled to the Vneg_L node, which in turn is coupled to the negative voltage rail through a second resistor R. The second resistor R has a first terminal coupled to the negative voltage node and a second terminal coupled to the DN terminal. The Vneg_L node is also referred to herein as the second node. The cathode of diode D4 is coupled to the DN terminal.

[0017]

[0022] The first and second resistors R may have a resistance, such as 1 KΩ, that is easily formed as on-die resistors on the semiconductor die forming integrated circuit 200. Such resistors effectively isolate or isolate the parasitic capacitance of diodes D2 and D4 from their respective terminals DP and DN. For example, if the parasitic capacitance of diodes D2 and D4 is approximately 1 pF, then including resistor R and the Vneg_L and Vneg_R nodes in differential ESD circuit 205 reduces the capacitive load on terminal DP by approximately 1 pF and reduces the capacitive load on terminal DN by approximately 1 pF. Such a significant reduction in capacitance is advantageous because terminal DP is coupled to switches S1 and S2 (not shown in FIG. 2 for clarity, but positioned as described with respect to integrated circuit 100) so that integrated circuit 200 can drive terminal DP in either a high-speed data mode or an audio mode. Similarly, terminal DN is advantageously coupled to switches S3 and S4 (not shown in FIG. 2 for clarity, but arranged as described with respect to integrated circuit 100), thereby enabling integrated circuit 200 to drive terminal DN in either high-speed data mode or audio mode. Without the advantageous reduction in capacitive loading provided by ESD circuit 205, integrated circuit 200 could suffer from an undesirably high bit error rate during high-speed data mode, as also described with respect to integrated circuit 100.

[0018]

[0023] To provide differential electrostatic discharge despite the presence of resistor R, differential ESD circuit 205 includes a Vdd-Vss RC clamp circuit 204 coupled between the power supply node and ground. Additionally, differential ESD circuit 205 includes a Vss-Vneg_L RC clamp circuit 210 coupled between ground and the Vneg_L node. The differential ESD circuit also includes a VSS-Vneg_R RC clamp circuit 215 coupled between ground and the Vneg_R node. The RC clamp circuit 215 is also referred to herein as a first ESD clamp circuit. Similarly, RC clamp circuit 210 is also referred to herein as a second ESD clamp circuit. Exemplary implementations of various RC clamp circuits disclosed herein are described below. The ground node is an example of a first voltage node, as defined herein. Similarly, the negative voltage rail is an example of a second voltage node, as defined herein. The function of ESD circuit 205 to protect integrated circuit 200 from electrostatic shock will now be described.

[0019]

[0024] Assume that the DP terminal becomes positively charged due to an electrostatic shock while the DN terminal is grounded. The charging of the DP terminal forward biases diode D1, allowing charge to flow from the DP terminal through diode D1 to the power supply node (which may also be referred to as the positive voltage rail). This sudden charging of the positive voltage rail due to an electrostatic shock causes the Vdd-Vss RC clamp circuit 204 to conduct, resulting in the charge being transferred to the ground node. This charging of the ground node or rail causes the Vss-Vneg_L RC clamp circuit 210 to conduct, resulting in the charge ultimately being transferred to the Vneg_L node. The charging of the Vneg_L node forward biases diode D4, resulting in the electrostatic discharge being conducted from terminal DP through ESD circuit 205 to terminal DN, safely dissipating the electrostatic shock. The ESD circuit 205 would function in a similar manner as described above if the DN terminal received a negative charge from an electrostatic shock while the DP terminal was grounded.

[0020]

[0025] Conversely, assume that the DN terminal becomes positively charged due to an electrostatic shock while the DP terminal is grounded. Diode D3 then becomes forward biased and conducts the positive charge from the DN terminal to the positive voltage rail. The Vdd-Vss RC clamp circuit 204 then conducts, conducting the positive charge from the positive voltage rail to the ground node. The positive charge on the ground node then causes the Vss-Vneg_R RC clamp circuit 215 to conduct, passing the charge to the Vneg_R node. The charge on the Vneg_R node then forward biases diode D2, so that the electrostatic discharge is conducted from terminal DN through ESD circuit 205 to terminal DP, safely dissipating the electrostatic shock. A similar process occurs if the DP terminal receives a negative charge from an electrostatic shock while the DN terminal is grounded.

[0021]

[0026] It should be noted that an improved ESD circuit may be implemented, similar to that described for ESD circuit 205, to isolate the parasitic capacitances of diodes D1 and D3 from their respective terminals DP and DN. An exemplary integrated circuit 300 having such an improved differential ESD circuit 305 is shown in FIG. 3. As described for integrated circuit 200, integrated circuit 300 includes a USB data positive (DP) terminal and a data negative (DN) terminal. An external device (not shown) is coupled to the DP and DN terminals through USB plug 105, similar to that described for integrated circuit 100. The cathode of ESD diode D1 in ESD circuit 305 is no longer directly coupled to the power supply node, but instead is coupled to a Vpos_R node, which is then coupled to the power supply node through a first resistor R. The first resistor R has a first terminal coupled to the power supply node and a second terminal coupled to the DP terminal. Similar to diode D1, the cathode of diode D3 is coupled to the Vpos_L node, which in turn is coupled to the power supply node through a second resistor R. The second resistor R has a first terminal coupled to the power supply node and a second terminal coupled to the DN terminal. The anode of diode D3 is coupled to the DN terminal. Diodes D4 and D2 are arranged as described for integrated circuit 100. The Vpos_R node is another example of a first node. Similarly, the Vpos_L node is another example of a second node.

[0022]

[0027] The first and second resistors R in ESD circuit 305 may have a resistance such as 1 KΩ, as described for ESD circuit 205. Such a resistor effectively isolates or isolates the parasitic capacitance of diodes D1 and D3 from their respective terminals DP and DN. For example, if the parasitic capacitance of diodes D1 and D3 is approximately 1 pF, then the inclusion of resistor R and the Vpos_L and Vpos_R nodes in differential ESD circuit 305 reduces the capacitive load on terminal DP by approximately 1 pF and the capacitive load on terminal DN by approximately 1 pF. Such a significant reduction in capacitance is advantageous because terminal DP is coupled to switches S1 and S2 (not shown in FIG. 3 for clarity, but positioned as described for integrated circuit 100) so that integrated circuit 300 can drive terminal DP in either high-speed data mode or audio mode. Similarly, terminal DN is advantageously coupled to switches S3 and S4 (not shown in FIG. 3 for clarity, but arranged as described with respect to integrated circuit 100), thereby allowing integrated circuit 300 to drive terminal DN in either high-speed data mode or audio mode. Without the advantageous reduction in capacitive loading provided by ESD circuit 305, integrated circuit 300 could suffer from an undesirably high bit error rate during high-speed data mode, as also described with respect to integrated circuit 100.

[0023]

[0028] To provide differential electrostatic discharge despite the presence of the first and second resistors R, the differential ESD circuit 305 includes a Vdd-to-ground RC clamp circuit 315 coupled between the power supply node and ground. In addition, the differential ESD circuit 305 includes a Vpos_L-to-ground RC clamp circuit 310 coupled between the Vpos_L node and ground. The differential ESD circuit 305 also includes a Vpos_R-to-ground RC clamp circuit 325 coupled between the Vpos_R node and ground. The Vpos_R-to-ground RC clamp circuit 325 is also referred to herein as a first ESD clamp circuit, while the Vpos_L-to-ground RC clamp circuit 310 is also referred to herein as a second ESD clamp circuit. In addition, a Vneg-to-ground RC clamp circuit 320 is coupled between ground and a negative voltage node for the negative voltage Vneg. The Vdd-to-ground RC clamp circuit 315 is also referred to herein as a third ESD clamp circuit, while the Vneg-to-ground RC clamp circuit 320 is also referred to herein as a fourth ESD clamp circuit. The function of the ESD circuit 305 to protect the integrated circuit 300 from electrostatic shock will now be described.

[0024]

[0029] Assume that the DP terminal becomes positively charged due to an electrostatic shock while the DN terminal is grounded. The charge on the DP terminal forward biases diode D1, allowing charge to flow from the DP terminal through diode D1 to the Vpos_R node. This sudden charge on the Vpos_R node due to the electrostatic shock causes the Vpos_R-to-ground RC clamp circuit 325 to conduct, resulting in the charge being transferred to ground. This charge on the ground node causes the Vneg-to-ground RC clamp circuit 320 to conduct, resulting in the charge finally being transferred to the Vneg node. The charge on the Vneg node forward biases diode D4, resulting in the electrostatic discharge being conducted from the DP terminal through the ESD circuit 305 to the DN terminal, safely dissipating the electrostatic shock. The ESD circuit 305 would function in the same manner as described above even if the DN terminal received a negative charge from an electrostatic shock while the DP terminal was grounded.

[0025]

[0030] Conversely, assume that the DN terminal becomes positively charged due to an electrostatic shock while the DP terminal is grounded. Diode D3 then becomes forward biased and conducts the positive charge to the Vpos_L node. The Vpos_L-to-ground RC clamp circuit 310 then conducts the positive charge from the Vpos_L node to ground. The sudden charging of the ground node causes the Vneg-to-ground RC clamp circuit 320 to conduct, passing the charge to the negative voltage node. The charge on the negative voltage node then forward biases diode D2, which then conducts the charge from terminal DN through ESD circuit 305 to terminal DP, safely dissipating the electrostatic shock. A similar process would occur if the DP terminal received a negative charge from an electrostatic shock while the DN terminal was grounded. It will be understood that the isolation of capacitive loads from diodes D4 and D2, as described with respect to ESD circuit 205, can be combined in alternative implementations with the isolation of capacitive loads from diodes D1 and D2, as described with respect to ESD circuit 305.

[0026]

[0031] The various RC clamp circuits disclosed herein are sometimes referred to as edge-triggered RC clamp circuits because they function to conduct in response to an edge trigger of an electrostatic shock. There are various implementations for suitable RC clamp circuits. A simplified version of RC clamp circuit 400 is shown in FIG. 4. RC clamp circuit 400 includes an n-type metal-oxide-semiconductor (NMOS) transistor having its drain coupled to a first voltage node and its source coupled to a second voltage node. The RC time constant of RC clamp circuit 400 is established by a resistor R1 and a capacitor C1 coupled in series between the first and second voltage nodes. Inverter 405 inverts the voltage Vfilter at the node between resistor R1 and capacitor C1 to drive the gate of transistor M1. More generally, inverter 405 represents a series chain of an odd number of inverters (e.g., three inverters) such that there is a sufficient time delay between the electrostatic shock-triggered charging of the Vfilter voltage and the switching on of transistor M1.

[0027]

[0032] A method of operating the ESD discharge circuit will now be described with reference to the flowchart shown in FIG. 5 . The method includes an operation 500 of receiving a first charge from a first electrostatic shock at a first terminal of an integrated circuit. Charging terminal DP or terminal DN of ESD circuit 205 or 305 is an example of operation 500. The method also includes an operation 505 of conducting the first charge from the first terminal through a first diode to a power supply node. Conducting through either diode D1 or D3 in ESD circuit 205 is an example of operation 505. The method further includes an operation 510 of conducting the first charge from the power supply node through a first RC clamp circuit to a ground node. Conducting through RC clamp circuit 204 in ESD circuit 205 is an example of operation 510. The method also includes an operation 515 of conducting the first charge from the ground node through a second RC clamp circuit to a first node separated from a negative voltage node for a negative voltage by a first resistor. Conducting through either of RC clamp circuits 210 and 215 in ESD circuit 205 is an example of operation 515. Finally, the method includes operation 520 of conducting a first charge from the first node through a second diode to a second terminal of the integrated circuit to dissipate the first electrostatic shock. Conducting through either diode D4 or D2 in ESD circuit 205 is an example of operation 520.

[0028]

[0033] The differential ESD circuits disclosed herein can be incorporated into any suitable mobile device or electronic system. For example, as shown in Figure 6, a mobile phone 600, a laptop computer 605, and a tablet PC 610 can all include differential ESD circuits according to the present disclosure. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, can also be configured with differential ESD circuits constructed according to the present disclosure.

[0029]

[0034] The disclosure is now summarized in the following series of clauses.

[0030] Article 1. a first integrated circuit terminal; a second integrated circuit terminal; a voltage node; a first resistor having a first terminal coupled to the voltage node; a second resistor having a first terminal coupled to the voltage node; a first ESD diode coupled between the first integrated circuit terminal and the second terminal of the first resistor; a second ESD diode coupled between the second integrated circuit terminal and the second terminal of the second resistor; a first ESD clamp circuit coupled between the second terminal of the first resistor and ground; a second ESD clamp circuit coupled between the second terminal of the second resistor and ground; Electrostatic discharge (ESD) circuitry comprising:

[0031] Clause 2. The electrostatic discharge circuit of clause 1, wherein the first integrated circuit terminal is a positive data terminal of a universal serial bus interface and the second integrated circuit terminal is a negative data terminal of the universal serial bus interface.

[0032] Clause 3. The electrostatic discharge circuit of clause 2, wherein the universal serial bus interface is a Type C universal serial bus interface.

[0033] Clause 4. The electrostatic discharge circuit of clause 3, wherein the first integrated circuit terminal is also a first audio terminal of a Type-C Universal Serial Bus interface, and the second integrated circuit terminal is a second audio terminal of a Type-C Universal Serial Bus interface.

[0034] Clause 5. The electrostatic discharge circuit of any one of clauses 1 to 4, wherein the voltage node is a negative voltage node.

[0035] Article 6. a power supply node for a power supply voltage; a third ESD clamp circuit coupled between the power supply node and ground; 6. The electrostatic discharge circuit of clause 5, further comprising:

[0036] Article 7. a third ESD diode having an anode coupled to the first integrated circuit terminal and a cathode coupled to the power supply node; a fourth ESD diode having an anode coupled to the second integrated circuit terminal and a cathode coupled to the power supply node; 7. The electrostatic discharge circuit of clause 6, further comprising:

[0037] Clause 8. The electrostatic discharge circuit of clause 6, wherein the first ESD clamp circuit, the second ESD clamp circuit, and the third ESD clamp circuit each comprise an edge-triggered RC clamp circuit.

[0038] Clause 9. The electrostatic discharge circuit of clause 1, wherein the voltage node comprises a power supply node for a power supply voltage.

[0039] Article 10. a negative voltage node for a negative voltage; a third ESD clamp circuit coupled between the power supply node and ground; a fourth ESD clamp circuit coupled between the negative voltage node and ground; 10. The electrostatic discharge circuit of clause 9, further comprising:

[0040] Article 11. a third ESD diode having an anode coupled to the negative voltage node and a cathode coupled to the first integrated circuit terminal; a fourth ESD diode having an anode coupled to the negative voltage node and a cathode coupled to the second integrated circuit terminal; 11. The electrostatic discharge circuit of clause 10, further comprising:

[0041] Clause 12. The electrostatic discharge circuit of clause 1, wherein the electrostatic discharge circuit is incorporated within an integrated circuit included in a mobile telephone.

[0042] Clause 13. The electrostatic discharge circuit of any one of clauses 1 to 12, wherein the first resistor and the second resistor each have a resistance of approximately 1000 Ω.

[0043] Article 14. receiving a first charge from a first electrostatic shock at a first terminal of the integrated circuit; conducting a first charge from the first terminal through a first diode to a power supply node; conducting a first charge from a power supply node through a first RC clamp circuit to a ground node; conducting a first charge from the ground node through a second RC clamp circuit to a first node, the first node being separated from a negative voltage node for the negative voltage by a first resistor; conducting a first charge from the first node through a second diode to a second terminal of the integrated circuit to dissipate the first electrostatic shock; Electrostatic discharge method, comprising:

[0044] Clause 15. The method of clause 14, wherein the first charge is a positive charge.

[0045] Article 16. receiving a second charge from a second electrostatic shock at a second terminal; conducting the second charge from the second terminal through the third diode to the power supply node; conducting a second charge from the power supply node through a first RC clamp circuit to a ground node; conducting a second charge from the ground node through a third RC clamp circuit to a second node, the second node being separated from the negative voltage node by a second resistor; conducting a second charge from the second node through a fourth diode to a first terminal of the integrated circuit to dissipate the second electrostatic shock; The method according to any one of clauses 14 to 5, further comprising:

[0046] Article 17. A first terminal; a second terminal; a first resistor; a second resistor; a first ESD diode coupled between the first terminal and the first resistor, the first ESD diode being coupled to the first resistor through a first node; a second ESD diode coupled between the second terminal and the second resistor, the second ESD diode being coupled to the second resistor through a second node; a first ESD clamp circuit coupled to the first node; a second ESD clamp circuit coupled to the second node; 1. An integrated circuit comprising:

[0047] Clause 18. The integrated circuit of clause 17, wherein a first ESD clamp circuit is coupled between the first node and a ground node, and a second ESD clamp circuit is coupled between the second node and the ground node.

[0048] Clause 19. The integrated circuit of clause 17, wherein the first terminal is a positive data terminal of a universal serial bus interface and the second terminal is a negative data terminal of the universal serial bus interface.

[0049] Clause 20. The integrated circuit of clause 17, wherein the first resistor and the second resistor are both coupled to a power supply node for a power supply voltage.

[0050] Clause 21. The integrated circuit of clause 17, wherein the first resistor and the second resistor are both coupled to a negative voltage node for a negative voltage.

[0051]

[0035] It will be understood that many modifications, substitutions, and variations can be made in and to the materials, apparatus, configurations, and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the specific implementations illustrated and described herein are merely some examples, and therefore the scope of the present disclosure should not be limited to the scope of such specific implementations, but rather should be fully equivalent to the scope of the following appended claims and their functional equivalents.

Claims

1. a first integrated circuit terminal; a second integrated circuit terminal; a voltage node; a first resistor having a first terminal coupled to the voltage node; a second resistor having a first terminal coupled to the voltage node; a first ESD diode coupled between the first integrated circuit terminal and the second terminal of the first resistor; a second ESD diode coupled between the second integrated circuit terminal and a second terminal of the second resistor; a first ESD clamp circuit coupled between the second terminal of the first resistor and ground; a second ESD clamp circuit coupled between the second terminal of the second resistor and ground; 1. An electrostatic discharge (ESD) circuit comprising:

2. 2. The electrostatic discharge circuit of claim 1, wherein the first integrated circuit terminal is a positive data terminal of a universal serial bus interface and the second integrated circuit terminal is a negative data terminal of the universal serial bus interface.

3. 3. The electrostatic discharge circuit of claim 2, wherein the Universal Serial Bus interface is a Type C Universal Serial Bus interface.

4. 4. The electrostatic discharge circuit of claim 3, wherein the first integrated circuit terminal is also a first audio terminal of the Type-C Universal Serial Bus interface, and the second integrated circuit terminal is a second audio terminal of the Type-C Universal Serial Bus interface.

5. 2. The electrostatic discharge circuit of claim 1, wherein the voltage node is a negative voltage node.

6. a power supply node for a power supply voltage; a third ESD clamp circuit coupled between the power supply node and ground; The electrostatic discharge circuit of claim 5 further comprising:

7. a third ESD diode having an anode coupled to the first integrated circuit terminal and a cathode coupled to the power supply node; a fourth ESD diode having an anode coupled to the second integrated circuit terminal and a cathode coupled to the power supply node; 7. The electrostatic discharge circuit of claim 6, further comprising:

8. 7. The electrostatic discharge circuit of claim 6, wherein the first ESD clamp circuit, the second ESD clamp circuit, and the third ESD clamp circuit each comprise an edge-triggered RC clamp circuit.

9. 2. The electrostatic discharge circuit of claim 1, wherein the voltage node comprises a power supply node for a power supply voltage.

10. a negative voltage node for a negative voltage; a third ESD clamp circuit coupled between the power supply node and ground; a fourth ESD clamp circuit coupled between the negative voltage node and ground; 10. The electrostatic discharge circuit of claim 9, further comprising:

11. a third ESD diode having an anode coupled to the negative voltage node and a cathode coupled to the first integrated circuit terminal; a fourth ESD diode having an anode coupled to the negative voltage node and a cathode coupled to the second integrated circuit terminal; 11. The electrostatic discharge circuit of claim 10, further comprising:

12. 10. The electrostatic discharge circuit of claim 1, wherein the electrostatic discharge circuit is incorporated into an integrated circuit included in a mobile phone.

13. 2. The electrostatic discharge circuit of claim 1, wherein the first resistor and the second resistor each have a resistance of approximately 1000 ohms.

14. receiving a first charge from a first electrostatic shock at a first terminal of the integrated circuit; conducting the first charge from the first terminal through a first diode to a power supply node; conducting the first charge from the power supply node through a first RC clamp circuit to a ground node; conducting the first charge from the ground node through a second RC clamp circuit to a first node separated by a first resistor from a negative voltage node for a negative voltage; conducting the first charge from the first node through a second diode to a second terminal of the integrated circuit to dissipate the first electrostatic shock; Electrostatic discharge method, comprising:

15. The method of claim 14 , wherein the first charge is a positive charge.

16. receiving a second charge from a second electrostatic shock at the second terminal; conducting the second charge from the second terminal through a third diode to the power supply node; conducting the second charge from the power supply node through the first RC clamp circuit to the ground node; conducting the second charge from the ground node through a third RC clamp circuit to a second node separated from the negative voltage node by a second resistor; conducting the second charge from the second node through a fourth diode to the first terminal of the integrated circuit to dissipate the second electrostatic shock; The method of claim 14 further comprising:

17. a first terminal; a second terminal; and a first resistor; a second resistor; and a first ESD diode coupled between the first terminal and the first resistor, the first ESD diode being coupled to the first resistor through a first node; a second ESD diode coupled between the second terminal and the second resistor, the second ESD diode being coupled to the second resistor through a second node; a first ESD clamp circuit coupled to the first node; a second ESD clamp circuit coupled to the second node; 1. An integrated circuit comprising:

18. 18. The integrated circuit of claim 17, wherein the first ESD clamp circuit is coupled between the first node and a ground node, and the second ESD clamp circuit is coupled between the second node and the ground node.

19. 18. The integrated circuit of claim 17, wherein the first terminal is a positive data terminal of a Universal Serial Bus interface and the second terminal is a negative data terminal of the Universal Serial Bus interface.

20. 20. The integrated circuit of claim 17, wherein the first resistor and the second resistor are both coupled to a power supply node for a power supply voltage.

21. 18. The integrated circuit of claim 17, wherein the first resistor and the second resistor are both coupled to a negative voltage node for a negative voltage.

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