System and method for synchronizing processors
The synchronization system addresses the challenge of synchronizing clock signals and counts across distributed processors by using a phase-locked loop and delay lines to adjust clock signals and counts, ensuring consistent timing and improved system performance.
Patent Information
- Application Number
- JP2025524782
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-19
- Filing Date
- 2023-10-24
- Publication Date
- 2025-12-09
AI Technical Summary
Synchronizing clock signals and counts across different parts of a system, particularly in very high frequency systems with distributed processors, becomes challenging due to the difficulty in maintaining consistent timing across various physical locations and semiconductor dies.
A synchronization system utilizing a phase-locked loop and delay lines, coupled with a synchronization circuit and control circuitry, adjusts clock signals and counts by measuring count phases and adjusting delay lines to synchronize clock signals and counts across multiple integrated circuit dies.
Ensures consistent timing and synchronization of clock signals and counts across distributed processors, enhancing system performance and reliability.
Smart Images
Figure 2025539716000001_ABST
Abstract
Description
[Technical Field]
[0001] background TECHNICAL FIELD This disclosure relates generally to synchronizing electronic systems, and more particularly to systems and methods for synchronizing processors. [Background technology]
[0002] Many electronic systems use clocks to synchronize the timing of operations throughout the system. A microprocessor is an example of a synchronous system that performs operations in clock cycles. Such systems may also keep a count, and at certain values of the count, system operations will occur. In very high frequency systems, it is important to synchronize the clock (and count). For example, as system speeds increase and systems grow in size, it can become difficult to synchronize the clock and count values across all parts of the system. [Brief explanation of the drawings]
[0003] BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] 1 illustrates a synchronization system according to one embodiment. [Figure 2] 1 illustrates a method for synchronizing a system according to one embodiment. [Figure 3] 1 illustrates a detailed example of a synchronization system according to one embodiment. [Figure 4] 1 illustrates a phase-locked loop and a delay line in a synchronization system according to one embodiment. [Figure 5] 1 illustrates an example of a delay line according to one embodiment. [Figure 6] 1 illustrates an example of multiple processor cores coupled to a clock generator on a single die, according to one embodiment. [Figure 7] 1 illustrates an example of a system counter within each processor core according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0004] Detailed Description Techniques for synchronizing systems are described herein. In the following description, for purposes of explanation, numerous examples and specific details are set forth to provide a thorough understanding of some embodiments. Various embodiments as defined by the claims may include some or all of the features in these examples, either alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
[0005] Features and advantages of the present disclosure include techniques for synchronizing clock signals and, in some embodiments, for synchronizing counts across different parts of a system that may, for example, reside in different physical locations and even across different physical semiconductor dies.
[0006] FIG. 1 illustrates a synchronization system according to one embodiment. System 100 can include multiple physical integrated circuit (IC) dies 101 a-n. Each IC die 101 a-n can include one or more digital processors (denoted 110 a-n) that can receive a clock signal (CK) to control the timing of each processor. The clock signal can be generated, for example, by a clock generator 111 a-n on the IC die 101 a-n. The clock generator 111 a-n can include, for example, a phase-locked loop (described below) and delay lines 112 a-n. Processors 110 a-n can also have a count (e.g., a system count), which can be a value (e.g., the number of clock cycles since the last system reset) that represents the amount of time (or number of clock cycles) the processor has been active. In some cases, multiple processors (e.g., central processing units, CPUs) can be distributed across different locations on each die, and the clock signals and system counts of processors on different dies may need to be synchronized.
[0007] In this example, IC die 101a includes synchronization (“sync”) circuit 150. Sync circuit 150 uses count phases from digital processors 110a-n to synchronize clock signals (and counts, in some cases). More specifically, sync circuit 150 receives count phases from different IC circuit dies 101a-n and adjusts delay lines 112a-n in clock generators 110a-n to synchronize clock signals CK (and counts) to digital processors 110a-n. As described above, one or more processors 110a-n on each IC die 110a-n can each have a count, which may be a digital value in a system counter, for example. Each count has a phase relative to various clocks in the system. Features and advantages of the present disclosure include measuring the count phases from IC die 101a-n and adjusting delay lines 112a-n to adjust clock signal CK to synchronize clock signals to digital processors 110a-n on IC die 101a-n.
[0008] 2 illustrates a method for synchronizing a system according to one embodiment. Initially, at power-up or reset of an IC die, at 201, when multiple phase-locked loops on the multiple integrated circuit dies are locked to a reference clock, the IC die can generate a clock signal to one or more digital processors on the multiple integrated circuit dies. At 202, a first integrated circuit die of the multiple integrated circuit dies can measure a count phase from the multiple integrated circuit dies. In one embodiment, the count phase can be received at the first integrated circuit die from at least one of the multiple processors on the multiple integrated circuit dies. At 203, the first integrated circuit die can adjust a delay line on the multiple integrated circuit dies to adjust the clock signal to synchronize the clock signal to the one or more digital processors on the multiple integrated circuit dies.
[0009] FIG. 3 shows a detailed example of a synchronization system according to one embodiment. In this example, a reference clock (RefCk) is received at the root integrated circuit 301a. RefCk may be received at a general-purpose input / output port (GPIO) 302 from an external system clock generator, such as a crystal-based system clock generator. In some system examples, RefCk may be 100 MHz, for example. RefCk may be coupled to other IC dies 301b-n via another GPIO driver 303. Advantageously, each IC die 301a-n may include a clock generator (CK GEN) 307 and 320b-n having a RefCk input coupled to receive RefCk. As described in more detail below, the CK GEN includes a PLL, and RefCk is the input reference signal to which the PLL locks. When RefCk begins, the root IC 301a may wait for all PLLs on the other IC dies to lock. In various embodiments, each PLL may send a lock signal to the root IC 301a, or the root IC 301a may wait a predetermined time for all PLLs to lock. After the PLLs lock, a synchronous reset signal may be generated by the SyncReset circuit 304. To ensure consistent timing across all dies, the SyncReset 304 is coupled to the sys-sync input of each CK GEN circuit 307 and 320b-n external to the IC dies 301a-n. The SyncReset output signal causes the CK GEN circuit to begin outputting a clock CK_root, which may be a multiplied version of a reference frequency (e.g., 1 GHz). The CK_root is coupled to system counters (SysCntr(DP)) 309 and 322b-n via clock trees 308 and 321b-n on each IC die. Each processor on each die may have a SysCntr(DP) circuit, which generates a local counter for each processor on each die. Thus, there may be a clock tree between the CK GEN and each processor on each die, and when the CK_root reaches the other end of each clock tree, it can be called, for example, a Ck_leaf.Additionally, as illustrated herein, the CK GEN circuitry can generate a count offset signal cnt_os to adjust the count in each SysCntr in each processor, for example.
[0010] Synchronization can be achieved by coupling the count phase from at least one processor on each IC die to a synchronization circuit. In this example, the system count value sys_cnt is coupled to multiplexers 310 and 323b-n. The system count can vary at a frequency related to Ck_root (e.g., 1 GHz or 1 ns). Thus, the least significant bit of sys_cnt, sys_cnt[0], can vary every 1 ns, the second bit, sys_cnt[1], can vary at a frequency of 2 ns, and so on. To select which bit to measure the count phase of the count based on the desired granularity, a particular bit can be selected by the count divide signal cnt_div. For example, multiplexer 310 may be coupled to sys_cnt[4] (a 16 ns signal), sys_cnt[5] (32 ns), sys_cnt[6] (64 ns), and sys_cnt[7] (128 ns), with a particular bit selected based on how frequently one wishes to perform synchronous measurements (e.g., faster updates can counteract more voltage and temperature variations, but at the expense of, e.g., higher power). The selected bit of count is an example of a count phase. The count phase is externally coupled to IC die 301a-n via GPIOs 311 and 324b-n into GPIOs 311a-n for path matching.
[0011] In this example, the synchronization circuit includes a phase detector (Ph Det) 309 and a control circuit (e.g., a finite state machine FSM) 313. The Ph Det 309 receives count phases (ph0, ph1, ph2, ..., phn) from the IC dies 301a-n. The Ph Det 309 can measure the phase difference and generate an "early" or "late" (E / L) signal for each die to the finite state machine (FSM) 313. The FSM 313 generates "n" (e.g., n = number of IC dies) phase increment signals (ph_inc[n]), phase decrement signals (ph_dec[n]), and count offset increment signals (offset_inc[n]). The phase increment signals, phase decrement signals, and offset increment signals are coupled to respective CK GENs 307 and 320b-n on each IC die 301a-n. The phase increase and decrease signals increase or decrease the delay of the Ck_root clock, and the increase in count offset results in a count offset (cnt_os) that is coupled from CK GEN to each SysCntr 309 and 322b-n. In this manner, Ph Det 312 and FSM 313 adjust the delay to synchronize the clock signals and adjust the count to synchronize the count across all digital processors in the system. Accordingly, FSM 313 outputs phase alignment information to each chip to adjust the clock phase and count, and determines when the phase of the entire chip is locked. Once the entire system is locked, the FSM can, for example, write to a "done" register.
[0012] FIG. 4 illustrates a phase-locked loop and delay line (DL) in a clock generator 400 according to one embodiment. In this example, a PLL 401 is coupled to a reference clock ref_clk, which can be multiplied to provide a PLL clock output Φpll. The PLL clock output is coupled to a delay line (DL) that provides a delayed clock Φdl. The delayed clock can be gated by a clock gate (CLK GATE) 403. The clock gate can be activated by a system synchronization signal sys_tc_sync, which is coupled to the CLK GATE 403 via two flip-flops 405 and 406, to pass the clock to the output. The DL 402 can receive a delay select signal dl_sel[7:0] to make the delay programmable. The delay selection can be generated by another control circuit (here another FSM) 404 in response to the phase increase and phase decrease signals described above. Additionally, the control circuit 404 can provide a count offset signal cnt_offset[2:0] in response to the count offset signal described above. A count offset signal may be coupled to the processor to change the count, for example to synchronize the counts between different processors.
[0013] 5 shows an example of a delay line (DL) according to one embodiment. In this example, the DL includes multiple delay lines 520 coupled via multiplexers 501-505 to provide a clock output signal. Multiplexers 501-505 receive control signals from synchronization / control circuitry 510. Synchronization / control circuitry 510 receives DL select inputs dl_sel[7:0], which may be from the FSM as described above.
[0014] 6 illustrates an example of multiple processor cores coupled to a clock generator on a single die, according to one embodiment. As discussed above, IC die 600 may include multiple processor cores (CPUs), such as processor 610, labeled DP (i.e., data path). In this example, a global system counter FSM 601 and a PLL 602 may be coupled to a clock trunk gate 603, which routes clock signals to the processors (DPs) within a clock tree (CT). The synchronization circuits described herein may be used to synchronize clock signals and counts across multiple processor cores on multiple IC dies 600, for example.
[0015] 7 illustrates an example of a system counter within each processor core according to one embodiment. System counter 700 includes counter 701, which includes a load input, a count enable input, and a count reset input. Counter 701 is clocked by a leaf clock signal and provides a digital value sys_count[63:0]. An offset can be added to the count by a count offset signal cnt_offset[2:0], which is coupled through two flip-flops 702 and 703. The counter offset value, which can be negative or positive, is added to the output of the counter to provide the system count value.
[0016] Further examples Each of the following non-limiting features in the following examples may stand alone or may be combined in various permutations or combinations with one or more of the other features in the following examples.
[0017] In one embodiment, the present disclosure includes a synchronization system including a first integrated circuit die including one or more first digital processors, a synchronization circuit, and a first clock generator, and one or more second integrated circuit dies including one or more second digital processors and a second clock generator, wherein the synchronization circuit receives count phases from the first and second integrated circuit dies and adjusts delay lines in the first and second clock generators to synchronize clock signals to the first and second digital processors.
[0018] In one embodiment, the synchronization circuit includes a phase detector coupled to measure phase on the first integrated circuit die and one or more second integrated circuit dies to determine a phase difference between the counts, and a synchronization control circuit that generates control signals to adjust the phase and counts on the one or more first digital processors and one or more second digital processors.
[0019] In one embodiment, the first and second clock generators include a phase-locked loop, a delay line, and control circuitry that adjusts the delay of the delay line to change the phase of corresponding ones of the clock signals and adjust the counts of the one or more first digital processors and the one or more second digital processors.
[0020] In one embodiment, after the phase-locked loop of each clock generator on each integrated circuit die locks onto the reference clock, clock signals are generated for the first and second digital processors.
[0021] In one embodiment, a first integrated circuit die measures count phases from a first and a second integrated circuit die.
[0022] In one embodiment, the first integrated circuit die adjusts each delay line on the first and second integrated circuit die to adjust the clock signal to synchronize the clock signals to the first and second digital processors.
[0023] In one embodiment, the first integrated circuit die and one or more second integrated circuit dies include a single clock generator and a plurality of digital processors each including a system counter configured to receive the clock signal from a corresponding delay line and generate a count, and particular bits of the count from one system counter on each of the one or more second integrated circuit dies are selectively coupled to a phase detector on the first integrated circuit die to determine a phase difference and adjust the delay and count of the delay lines of the one or more first digital processors and the one or more second digital processors accordingly.
[0024] In one embodiment, the first integrated circuit die and the one or more second integrated circuit dies include multiple processors, each processor receiving a clock signal of the clock signals to generate a count, and a count phase is generated from the count. In one embodiment, the system further includes multiple clock trees coupled between the first clock generator and the one or more first digital processors and between the second clock generator and the one or more second digital processors.
[0025] In another embodiment, the present disclosure includes a method of synchronizing processors, including generating a clock signal to one or more digital processors on the multiple integrated circuit dies when multiple phase-locked loops on the multiple integrated circuit dies are locked to a reference clock; measuring, by a first integrated circuit die of the multiple integrated circuit dies, a count phase from the multiple integrated circuit dies; and adjusting, by the first integrated circuit die, a delay line on the multiple integrated circuit dies to adjust the clock signal to synchronize the clock signal to the one or more digital processors on the multiple integrated circuit dies.
[0026] In one embodiment, the method further includes adjusting counting in one or more digital processors on the multiple integrated circuit dies in response to measuring the counting phase.
[0027] In one embodiment, adjusting the delay line includes adjusting a single delay line on each of a plurality of integrated circuit dies.
[0028] In one embodiment, measuring the count phase includes receiving, on a single integrated circuit die of the multiple integrated circuit dies, a local count phase and one or more remote count phases at a phase detector, determining by the phase detector whether each count phase is early or late, and generating, by a state machine, control signals to adjust the phase and count, the control signals being sent to the multiple integrated circuit dies.
[0029] In one embodiment, the control signals include a count offset signal and one or more phase adjustment signals.
[0030] In one embodiment, each digital processor of the one or more digital processors on the multiple integrated circuit dies includes a system counter having the counting phase described above.
[0031] In one embodiment, each digital processor of the one or more digital processors on the multiple integrated circuit dies includes a system counter having the counting phase described above.
[0032] In another embodiment, the present disclosure includes a synchronization system including means for generating clock signals to one or more digital processors on a plurality of integrated circuit dies when a plurality of phase-locked loops on the plurality of integrated circuit dies are locked to a reference clock; means for measuring count phases from the plurality of integrated circuit dies; and means for adjusting delay lines on the plurality of integrated circuit dies to adjust the clock signals to synchronize the clock signals to the one or more digital processors on the plurality of integrated circuit dies.
[0033] In one embodiment, the means for generating the clock signal includes a phase locked loop and a delay line.
[0034] In one embodiment, the means for measuring the count phase includes a phase detector coupled to receive at least one bit of the count from the multiple integrated circuit dies.
[0035] In one embodiment, the means for adjusting the delay line includes a plurality of multiplexers coupled to the control circuit.
[0036] The above description illustrates various embodiments with examples of how aspects of some embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the flexibility and advantages of some embodiments as defined by the appended claims. Other configurations, embodiments, implementations, and equivalents may be employed based on the above disclosure and the appended claims without departing from the scope of this specification as defined by the claims.
Claims
1. 1. A synchronization system comprising: one or more first digital processors; Synchronous circuits, and First Clock Generator a first integrated circuit die including: one or more second digital processors; and Second Clock Generator one or more second integrated circuit dies including wherein the synchronization circuit receives count phases from the first and second integrated circuit dies and adjusts delay lines in the first and second clock generators to synchronize clock signals to the first and second digital processors. Synchronous system.
2. The synchronization circuit a phase detector coupled to measure phase on the first integrated circuit die and the one or more second integrated circuit dies to determine a phase difference between counts; a synchronization control circuit that generates control signals to adjust the phase and count on the one or more first digital processors and the one or more second digital processors; The system of claim 1 , comprising:
3. The first and second clock generators a phase-locked loop; a delay line; a control circuit for adjusting a delay of the delay line to change a phase of a corresponding clock signal of the clock signal and to adjust the count of the one or more first digital processors and the one or more second digital processors; The system of claim 1 , comprising:
4. 4. The system of claim 3, wherein the clock signals are generated for the first and second digital processors after the phase-locked loop of each clock generator on each integrated circuit die locks onto a reference clock.
5. The system of claim 3 , wherein the first integrated circuit die measures count phases from the first and second integrated circuit dies.
6. 4. The system of claim 3, wherein the first integrated circuit die adjusts each delay line on the first and second integrated circuit die to adjust the clock signal to synchronize the clock signals to the first and second digital processors.
7. 4. The system of claim 3, wherein the first integrated circuit die and one or more second integrated circuit dies include a single clock generator and a plurality of digital processors each including a system counter configured to receive the clock signal from a corresponding delay line and generate a count, and wherein particular bits of the count from one system counter on each of the one or more second integrated circuit dies are selectively coupled to a phase detector on the first integrated circuit die to determine a phase difference and adjust the delay and count of the delay lines of the one or more first digital processors and the one or more second digital processors accordingly.
8. 2. The system of claim 1, wherein the first integrated circuit die and one or more second integrated circuit dies include a plurality of processors, each processor receiving a clock signal of the clock signals to generate a count from which the count phase is generated.
9. 2. The system of claim 1, further comprising a plurality of clock trees coupled between the first clock generator and the one or more first digital processors and between the second clock generator and the one or more second digital processors.
10. generating a clock signal to one or more digital processors on the plurality of integrated circuit dies when a plurality of phase-locked loops on the plurality of integrated circuit dies are locked to a reference clock; measuring a count phase from the plurality of integrated circuit dies by a first integrated circuit die of the plurality of integrated circuit dies; and adjusting, by the first integrated circuit die, delay lines on the plurality of integrated circuit dies to adjust the clock signal to synchronize clock signals to the one or more digital processors on the plurality of integrated circuit dies. A method for synchronizing processors, including:
11. 11. The method of claim 10, further comprising adjusting counting in the one or more digital processors on the multiple integrated circuit dies in response to measuring the counting phase.
12. The method of claim 10 , wherein adjusting the delay line comprises adjusting a single delay line in each of the plurality of integrated circuit dies.
13. measuring the count phase receiving, on a single integrated circuit die of the plurality of integrated circuit dies, a local count phase and one or more remote count phases at a phase detector; determining by the phase detector whether each count phase is early or late; and generating control signals by a state machine to adjust said phase and count; wherein the control signals are transmitted to the plurality of integrated circuit dies. The method of claim 10.
14. The control signal is a count offset signal, and one or more phase adjustment signals 14. The method of claim 13, comprising:
15. 11. The method of claim 10, wherein each digital processor of the one or more digital processors on the multiple integrated circuit dies includes a system counter having the counting phase.