Post-load wafer centering system for semiconductor processing tools

Abstract

Disclosed herein are systems and techniques for post-load centering of a semiconductor wafer, i.e., centering a semiconductor wafer after it has already been loaded onto a pedestal, more specifically, onto a pedestal base. Such systems also enable such centering to be performed in an open-loop manner, for example, without the need to determine how off-center the semiconductor wafer is from a desired location. Such functionality enables centering of a wafer relative to a pedestal base in multi-station semiconductor processing tools such as those described above (semiconductor processing tools that have limited or no availability of AWC systems).

Description

[Technical Field]

[0001] Related Applications: A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] When a semiconductor wafer is placed on a pedestal within a semiconductor processing tool, such as a semiconductor processing chamber of the semiconductor processing tool, it is typically desirable to manage the placement of the semiconductor wafer on the pedestal so that the center of the wafer is centered on the pedestal (or within some predetermined zone associated with an acceptable level of process uniformity). This is typically done using an automatic wafer centering system (AWC). In an AWC, two or more optical beam sensors are positioned at the entrance to the semiconductor processing chamber to detect the edge of a semiconductor wafer being transported by a wafer handling robot passing through them. By using the kinematic configuration of the wafer handling robot at the time of each such edge detection event, in combination with a known wafer diameter and calibration data relating the location of the optical beam sensors to a desired target zone for the wafer center relative to the pedestal, the AWC can determine how much the center of the semiconductor wafer will deviate from the target zone after being placed by the wafer handling robot (assuming the wafer handling robot follows its default path). The AWC can then cause the wafer handling robot to modify the path followed to compensate for such deviation, resulting in the semiconductor wafer being placed at the center of the pedestal. Summary of the Invention

[0003] The details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, drawings, and claims.

[0004] In some embodiments, a semiconductor processing tool for processing a semiconductor wafer having a diameter D and a thickness T can be provided. The semiconductor processing tool can include a semiconductor processing chamber having a plurality of surfaces defining an interior volume thereof. The semiconductor processing tool can also include a pedestal base configured to support the semiconductor wafer during wafer processing operations, the pedestal base including one or more wafer support features located within the interior volume and configured to support the semiconductor wafer when the semiconductor wafer is placed on the pedestal base. The one or more wafer support features can define a first reference plane that coincides with a bottom surface of the semiconductor wafer when the semiconductor wafer is supported by the one or more wafer support features. The semiconductor processing tool may further include a showerhead having a first surface with a plurality of gas distribution ports distributed thereon, the first surface facing the pedestal base and positioned above the pedestal base; one or more wafer centering features collectively having one or more radially inward-facing wafer centering surfaces positioned radially outward from or circumscribing a reference circle having a diameter greater than or equal to D; and one or more movement mechanisms including at least a first movement mechanism configured to laterally move the pedestal base or the one or more wafer centering features. The first movement mechanism may enable the one or more wafer centering features to adjust the position of the semiconductor wafer relative to the pedestal base while the semiconductor wafer is supported by the pedestal base. The semiconductor processing tool may also include a controller configured to control the at least first movement mechanism to move the pedestal base or the one or more wafer centering features relative to the other of the pedestal base or the one or more wafer centering features.

[0005] In some implementations of the semiconductor processing tool, the one or more wafer centering features may be spatially fixed relative to the showerhead, and at least a portion or portions of the one or more radially inward-facing surfaces may be located at a lower elevation than the first surface.

[0006] In some embodiments of the semiconductor processing tool, one or more wafer centering features may project downwardly from the showerhead toward the pedestal base.

[0007] In some implementations of the semiconductor processing tool, the one or more wafer centering features may be spatially fixed relative to the semiconductor processing chamber and may extend downwardly into a through opening in the showerhead.

[0008] In some implementations of the semiconductor processing tool, both the showerhead and the pedestal base may be configured to be movable relative to the semiconductor processing chamber along an axis perpendicular to the first reference plane; the showerhead may be configured to be movable between a first configuration and a second configuration relative to the semiconductor processing chamber; first ends of the one or more wafer centering features may extend beyond a first surface of the showerhead toward the pedestal base when the showerhead is in the first configuration and the first ends of the one or more wafer centering features may not extend beyond the first surface of the showerhead when the showerhead is in the second configuration; the pedestal base may be configured to be movable between a third configuration and a fourth configuration relative to the semiconductor processing chamber; the first reference plane may be within a distance T from the first ends of the one or more wafer centering features when the pedestal base is in the third configuration and the first reference plane may be more than a distance T from the first ends of the one or more wafer centering features when the pedestal base is in the fourth configuration.

[0009] In some implementations of the semiconductor processing tool, the one or more wafer centering features may extend downward into the through opening in the showerhead, and the semiconductor processing tool may further include one or more actuators configured to be movable between a first position and a second position, and the one or more wafer centering features may be directly or indirectly connected to the one or more actuators such that the one or more wafer centering features move along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position, and the one or more wafer centering features may protrude beyond the first surface of the showerhead when the one or more actuators are in the first position, and the one or more wafer centering features may be above the first surface of the showerhead when the one or more actuators are in the second position.

[0010] In some implementations of the semiconductor processing tool, the one or more wafer centering features may be spatially fixed relative to the semiconductor processing chamber and may extend upwardly into a through opening in the pedestal base.

[0011] In some implementations of the semiconductor processing tool, the first moving mechanism may be configured to move the pedestal base laterally relative to the one or more wafer centering features and along an axis perpendicular to the first reference plane, and the first moving mechanism may be further configured to move the pedestal base between the first and second configurations relative to the semiconductor processing chamber, wherein the first ends of the one or more wafer centering features may extend beyond the first reference plane when the pedestal base is in the first configuration and the first ends of the one or more wafer centering features may not extend beyond the first reference plane when the pedestal base is in the second configuration.

[0012] In some embodiments of the semiconductor processing tool, the one or more wafer centering features may extend upward into the through opening in the pedestal base, and the semiconductor processing tool may further include one or more actuators configured to be movable between a first position and a second position, and the one or more wafer centering features may be directly or indirectly connected to the one or more actuators such that the one or more wafer centering features move relative to the semiconductor processing chamber along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position, and the one or more wafer centering features may protrude beyond the first reference plane when the one or more actuators are in the first position and the one or more wafer centering features may be below the first reference plane when the one or more actuators are in the second position.

[0013] In some implementations of the semiconductor processing tool, the one or more wafer centering features may include an annular wall element surrounding the showerhead, and the semiconductor processing tool may further include one or more actuators configured to be movable between a first position and a second position, and the annular wall element may be directly or indirectly connected to the one or more actuators such that the annular wall element moves along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position, the annular wall element may protrude beyond the first surface when the one or more actuators are in the first position, and the annular wall element may be at a higher position when the one or more actuators are in the second position than when the one or more actuators are in the first position.

[0014] In some implementations of the semiconductor processing tool, the first moving mechanism may be configured to move the pedestal base at least laterally relative to the semiconductor processing chamber and the showerhead.

[0015] In some implementations of the semiconductor processing tool, the first moving mechanism may be configured to move the showerhead at least laterally relative to the semiconductor processing chamber and the pedestal base.

[0016] In some implementations of the semiconductor processing tool, the one or more wafer centering features may be cylindrical posts.

[0017] In some embodiments of the semiconductor processing tool, one or more radially inwardly facing wafer centering surfaces may be provided by an axisymmetric wall surface having an inner diameter greater than D.

[0018] In some embodiments of the semiconductor processing tool, the one or more radially inwardly facing wafer centering surfaces may be multiple arcuate surfaces, each of which may have a radius greater than one-half of D, and all of which may have the same radius and share a common center point.

[0019] In some implementations of the semiconductor processing tool, the one or more radially inwardly facing wafer centering surfaces may be multiple radially inwardly facing centering surfaces, and the radially inwardly facing centering surfaces may circumscribe a reference circle.

[0020] In some implementations of the semiconductor processing tool, the first mover mechanism may be a hexapod mechanism including a base mount, a movable mount supporting a pedestal base and one of the one or more wafer centering features that the first mover mechanism is configured to move, and six linear actuators, each linear actuator connected at one end to the base mount and at the other end to the movable mount. In such implementations, the hexapod mechanism may be configured to move the movable mount at least laterally relative to the base mount via actuation of the linear actuators in response to one or more control signals provided by a controller.

[0021] In some implementations of the semiconductor processing tool, the first movement mechanism may include an XY translation stage having a first linear translation mechanism configured to translate the pedestal base along which the first movement mechanism is configured to move and one of the one or more wafer centering features along a first horizontal axis in response to one or more control signals provided by the controller. The XY translation stage may also have a second linear translation mechanism configured to translate the pedestal base along which the first movement mechanism is configured to move and one of the one or more wafer centering features along a second horizontal axis in response to one or more control signals provided by the controller. In such implementations, the first and second horizontal axes may not be parallel to each other, and in some further implementations thereof, the first horizontal axis may be orthogonal to the second horizontal axis.

[0022] In some implementations of the semiconductor processing tool, the first movement mechanism may include an R-theta mechanism having a rotary actuator having a base portion and a rotatable portion and a linear translation mechanism having a first portion and a second portion. The rotary actuator may be configured to rotate the rotatable portion relative to the base portion about a rotational axis in response to one or more control signals provided by a controller, the linear translation mechanism may be configured to translate the second portion along a radial axis relative to the first portion in response to one or more control signals provided by the controller, the second portion of the linear translation mechanism may support one of the pedestal base and the one or more wafer centering features configured to move the first movement mechanism, the rotatable portion of the rotary actuator may support the first portion of the linear translation mechanism, and the radial axis may be orthogonal to an axis parallel to the rotational axis.

[0023] In some implementations of the semiconductor processing tool, the controller may be further configured to control the one or more movement mechanisms to transition the pedestal base and one or more wafer centering features between at least a first relative configuration and a second relative configuration, wherein at least a portion of at least one of the one or more wafer centering features may be between a first reference surface and a second reference surface parallel to the first reference surface and positioned above the first reference surface by a distance T in the first relative configuration, and may not be between the first reference surface and the second reference surface in the second relative configuration.

[0024] In some implementations of the semiconductor processing tool, the controller may be further configured to control the first movement mechanism such that the pedestal base performs one or more circular orbits having one or more diameters less than or equal to the diameter of the reference circle minus D.

[0025] In some implementations of the semiconductor processing tool, the controller may be further configured to control the first movement mechanism such that the pedestal base performs a plurality of circular orbits, each having an increasingly larger diameter less than or equal to the diameter of the reference circle minus D.

[0026] In some implementations of the semiconductor processing tool, the controller may be further configured to control the first movement mechanism so that the pedestal base follows a path that spirals outward from a center point and then follows an arcuate or circular path having a diameter equal to the diameter of the reference circle minus D.

[0027] In some implementations of the semiconductor processing tool, the controller may be further configured to control the first movement mechanism to move the pedestal base along a plurality of paths radiating outward from a central region to a plurality of locations along one or more radially inward-facing wafer centering surfaces. In addition to the implementations listed above, other implementations apparent from the following description and figures are understood to be within the scope of the present disclosure. [Brief explanation of the drawings]

[0028] In the following description, reference will be made to the following figures, which are not intended to be limiting in scope but are provided merely to facilitate the following description:

[0029] [Figure 1] FIG. 1 is a diagram illustrating an exemplary simplified representation of a pedestal, a semiconductor wafer, a showerhead, and a wafer centering feature.

[0030] [Figure 2a] 2a is a plan view of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2b] 2b are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2c] 2c are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2d] 2d are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2e] 2e are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2f] 2f are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2g] 2g are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2h] 2h are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2i] 2i is a plan view of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2j] 2j are plan views of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2k]2k is a plan view of the elements shown in FIG. 1 at various stages of the wafer centering process. [Figure 2l] 2l is a plan view of the elements shown in FIG. 1 at various stages of the wafer centering process.

[0031] [Figure 3a] FIG. 3a is a diagram illustrating different movement paths that may be used to perform wafer centering as described herein. [Figure 3b] FIG. 3b is a diagram illustrating different movement paths that may be used to perform wafer centering as described herein. [Figure 3c] FIG. 3c is a diagram illustrating different movement paths that may be used to perform wafer centering as described herein. [Figure 3d] FIG. 3d is a diagram illustrating different movement paths that may be used to perform wafer centering as described herein.

[0032] [Figure 4a] FIG. 4a is a diagram illustrating an exemplary semiconductor processing tool having wafer centering capabilities as described herein. [Figure 4b] FIG. 4b illustrates an exemplary semiconductor processing tool having wafer centering capabilities as described herein. [Figure 4c] FIG. 4c illustrates an exemplary semiconductor processing tool having wafer centering capabilities as described herein.

[0033] [Figure 5] FIG. 5 is a diagram illustrating an exemplary movement mechanism that may be used as the first movement mechanism.

[0034] [Figure 6] FIG. 6 is a diagram illustrating another exemplary movement mechanism that can be used as the first movement mechanism.

[0035] [Figure 7]FIG. 7 illustrates an example semiconductor processing tool configured for post-placement wafer centering using a movable showerhead.

[0036] [Figure 8a] FIG. 8a is a diagram illustrating an exemplary semiconductor processing tool in which the wafer centering feature is spatially fixed relative to the semiconductor processing chamber. [Figure 8b] FIG. 8b is a diagram illustrating an exemplary semiconductor processing tool in which the wafer centering feature is spatially fixed relative to the semiconductor processing chamber.

[0037] [Figure 9a] FIG. 9a illustrates a semiconductor processing tool similar to that of FIGS. 8a and 8b, but with some modifications. [Figure 9b] FIG. 9b illustrates a semiconductor processing tool similar to that of FIGS. 8a and 8b, but with some modifications.

[0038] [Figure 10a] FIG. 10a illustrates an exemplary semiconductor processing tool in which the wafer centering feature is not fixed relative to the semiconductor processing chamber or showerhead. [Figure 10b] FIG. 10b illustrates an exemplary semiconductor processing tool in which the wafer centering feature is not fixed relative to the semiconductor processing chamber or showerhead.

[0039] [Figure 11a] FIG. 11a illustrates an embodiment similar to FIGS. 10a and 10b, but with some important differences. [Figure 11b] FIG. 11b illustrates an embodiment similar to FIGS. 10a and 10b, but with some important differences.

[0040] [Figure 12a] FIG. 12a is a diagram illustrating an exemplary semiconductor processing tool having a single wafer centering feature. [Figure 12b] FIG. 12b is a diagram illustrating an exemplary semiconductor processing tool having a single wafer centering feature.

[0041] [Figure 13a] FIG. 13a is a plan view of a showerhead having a wafer-centering feature consisting of axisymmetric walls. [Figure 13b] FIG. 13b is a cross-sectional side view of a showerhead having a wafer-centering feature consisting of an axisymmetric wall.

[0042] [Figure 14a] FIG. 14a is a plan view of a showerhead having multiple wafer centering features, each providing an arcuate, radially inward-facing wafer centering surface. [Figure 14b] FIG. 14b is a cross-sectional side view of a showerhead having multiple wafer centering features, each providing an arcuate, radially inward-facing wafer centering surface.

[0043] [Figure 15a] FIG. 15a is a top view of an exemplary showerhead and pedestal base including wafer centering features similar to those shown in FIGS. 14a and 14b. [Figure 15b] FIG. 15b is a side view of an exemplary showerhead and pedestal base including wafer centering features similar to those shown in FIGS. 14a and 14b. [Figure 15c] FIG. 15c is a side view of an exemplary showerhead and pedestal base including wafer centering features similar to those shown in FIGS. 14a and 14b.

[0044] [Figure 16a]FIG. 16a is a plan view of a showerhead having multiple wafer-centering features, each of which is a cylindrical post. [Figure 16b] FIG. 16b is a side cross-sectional view of a showerhead having multiple wafer-centering features, each of which is a cylindrical post.

[0045] The above-described figures are provided to facilitate understanding of the concepts described in this disclosure and are intended to illustrate some embodiments falling within the scope of this disclosure, but are not intended to be limiting; embodiments consistent with this disclosure and not shown in the figures are also considered to be within the scope of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0046] While AWC systems are widely used and generally provide reliable and highly accurate wafer placement, such systems have limitations that make them unsuitable for use in certain situations, such as systems that simultaneously transport multiple semiconductor wafers to a chamber, systems in which the device that places the semiconductor wafer on the pedestal may not have enough degrees of freedom or sufficient precision to actually correct for misalignment of the semiconductor wafer, and / or systems in which the location of the semiconductor wafer relative to the wafer transport system that is moving it cannot be measured.

[0047] For example, some semiconductor processing tools may have chambers with multiple pedestals located therein to allow multiple semiconductor wafers to be processed simultaneously. In some such systems, a wafer handling robot that may be used to move semiconductor wafers in and out of the chamber may have an end effector that supports two wafers in a stacked arrangement. Therefore, when stacked wafers pass through the optical beam of the AWC, the AWC may not be able to determine which wafer edge is being detected, making it impossible to determine which wafer each measurement belongs to.

[0048] In another example, a semiconductor processing tool having multiple pedestals within a common chamber can use a rotary indexer to move wafers from pedestal to pedestal within the chamber. In such a system, the pedestals can be arranged in a circular array around a central axis of the rotary indexer. The rotary indexer can have multiple arms extending radially outward from a central hub configured to rotate about the central axis. Each arm can have a wafer support at an end radially outward from the central hub. When semiconductor wafers are transferred between such pedestals, the semiconductor wafers can be first lifted from their respective pedestals, for example, by a lift pin mechanism. The rotary indexer can then be rotated to position each wafer support under one of the semiconductor wafers, and the lift pins can then be lowered to place the semiconductor wafer on the wafer support. The rotary indexer can then be rotated to position each semiconductor wafer on a new pedestal, and the lift pins can then be raised again to lift the semiconductor wafer from the wafer support. The rotary indexer can then be rotated to a position where the indexer arm is no longer interposed between the semiconductor wafer and the pedestal, and the lift pins are then lowered to lower the semiconductor wafer onto the pedestal. Such rotary indexers typically have one degree of freedom (rotation about a central axis) or very limited degrees of freedom and cannot correct for potential wafer misalignment.

[0049] In such systems, it can also be difficult to determine what the wafer misalignment is in the first place; since it is typically not feasible to place an optical beam sensor inside the semiconductor processing chamber, there may be no way to determine how off-center each semiconductor wafer is relative to its ideally centered location.

[0050] The systems described herein enable post-load centering of a semiconductor wafer, i.e., centering the semiconductor wafer after it has already been loaded onto the pedestal, or more specifically, onto the pedestal base. Such systems also enable such centering to be performed in an open-loop manner, for example, without the need to determine how far the semiconductor wafer is off-center from a desired location. Such functionality enables centering of the wafer relative to the pedestal base in multi-station semiconductor processing tools such as those described above (semiconductor processing tools that have limited or no AWC system availability).

[0051] A pedestal generally includes a stem or other support structure and a pedestal base supported by the stem or support structure, which supports a semiconductor wafer during wafer processing operations. The pedestal base is located within the interior volume of a semiconductor processing chamber. The stem can be located within the interior volume of a semiconductor processing tool, but it can also extend through a wall of the semiconductor processing chamber and be supported by equipment outside the semiconductor processing chamber. For example, the pedestal may be connected to a vertical lift mechanism that can be controlled to move the pedestal up and down relative to the semiconductor processing chamber. Such a vertical lift mechanism may be located outside the semiconductor processing chamber, requiring the stem to extend through a wall of the semiconductor processing chamber to connect to the vertical lift mechanism.

[0052] The pedestal base is generally larger than the semiconductor wafer and may include features such as heaters, cooling channels, electrostatic chucks, vacuum chucks, radio frequency (RF) electrodes, purge gas delivery systems, and the like. Some pedestal bases may have one or more large, generally flat surfaces designed to contact the semiconductor wafer over its entire underside, while other pedestal bases may be configured to support only the semiconductor wafer near its outer edge (excluding, of course, the edge of the semiconductor wafer), for example, by using spacers that elevate the semiconductor wafer above the rest of the pedestal base to provide a gap between the underside of the semiconductor wafer and the portion of the pedestal base directly below it. In any case, the pedestal base generally includes one or more wafer support features that define a first reference plane that is generally coplanar with or coincident with the underside of the semiconductor wafer supported by the wafer support features. Such wafer support features may include, for example, a single flat circular region (possibly with one or more grooves or recesses therein) that contacts the underside of the semiconductor wafer over most or all of the underside of the semiconductor wafer, or a generally flat circular region with multiple small minimum or low-contact area features (each acting as an individual wafer support feature) distributed throughout. In some implementations, such as a pedestal base configured to support a semiconductor wafer such that a gap may exist between the underside of the semiconductor wafer and a majority of the pedestal base, the pedestal base may include a removable carrier ring supported by spacers in the pedestal base at a generally higher position than the remainder of the pedestal base. Such a carrier ring may include tabs that project radially inward from an inner diameter of the carrier ring and contact the underside of the semiconductor wafer. The tabs in such implementations provide the wafer support surface of the pedestal.In an alternative pedestal base configured to support a semiconductor wafer such that a gap may exist between the underside of the semiconductor wafer and a majority of the pedestal base, the pedestal base may simply include a spacer having a surface that directly contacts the semiconductor wafer (the pedestal base need not include a carrier ring) and may hold the semiconductor wafer higher than the remainder of the pedestal base, and such surface may act as the wafer support surface in such an embodiment.

[0053] The systems described herein each include one or more wafer centering features, which collectively have one or more radially inward-facing wafer centering surfaces. Such wafer centering surfaces are positioned such that, at least during the wafer centering operation, a portion of the wafer centering surface is located between two reference planes defined by the top and bottom surfaces of the semiconductor wafer being centered. Each wafer centering surface is also positioned radially outward from the target location where the semiconductor wafer is to be centered by a distance greater than half the diameter of the semiconductor wafer. Thus, the one or more radially inward-facing wafer centering surfaces may generally circumscribe a reference circle having a diameter greater than the diameter of the semiconductor wafer. In practice, the one or more radially inward-facing wafer centering surfaces form a fence or cage that surrounds the semiconductor wafer, but may leave room for movement between the one or more radially inward-facing wafer centering surfaces and the semiconductor wafer. The one or more radially inwardly facing wafer centering surfaces can be positioned so that the difference between the diameter of the reference circle and the diameter D of the semiconductor wafer is large enough to overcome any potential eccentricity that may be expected when initially placing the semiconductor wafer on the pedestal base.

[0054] In addition to the one or more radially inwardly facing wafer centering surfaces, the systems described herein may also include one or more movement mechanisms associated with the pedestal base, configured to move various one or more components or subassemblies of such systems relative to each other. The one or more movement mechanisms may include at least one first movement mechanism configured to move the pedestal base and one of the one or more radially inwardly facing wafer centering surfaces associated with the pedestal base at least laterally relative to the other of the pedestal base and one or more radially inwardly facing wafer centering surfaces associated with the pedestal base. "Lateral" movement, in this context, refers to movement in a direction generally parallel to the first reference surface. In most systems, lateral movement generally refers to horizontal movement. However, it will be appreciated that the systems and techniques described herein can also be implemented in situations where the first reference surface is not horizontal, e.g., tilted (although it will be understood that the amount of tilt may be limited to avoid gravity-induced slippage between the semiconductor wafer and the pedestal base).

[0055] Such a system may also include a controller configured to control at least a first movement mechanism to cause the first movement mechanism to move one of the pedestal base about which the first movement mechanism is configured to move and one or more radially inward-facing wafer centering surfaces associated with the pedestal base at least laterally relative to another of the pedestal base and one or more radially inward-facing wafer centering surfaces associated with the pedestal base.

[0056] A system configured as described above can be controlled to perform a wafer centering operation in which the first movement mechanism is configured to perform one or more movements including one or more lateral components. Such movements can be selected to move the target center point of the pedestal base, i.e., a point fixed relative to the pedestal base and selected as the location relative to the pedestal base where the center of the wafer will be centered, toward the reference circle by some amount. In most embodiments, this amount can be half the difference between the diameter "d" of the reference circle and the diameter "D" of the semiconductor wafer. Of course, it will be understood that "half the difference between the diameter "d" of the reference circle and the diameter "D" of the semiconductor wafer" may include a small tolerance, such as ±150 μm, and still be considered within the acceptable wafer centering range.

[0057] In many embodiments, the first movement mechanism may be controlled to perform multiple such movements or to follow a path having a particular geometric shape, e.g., one or more circular and / or spiral paths, in which the target center point of the pedestal base remains within a circle having a radius that is half the difference between the diameter of the reference circle and the diameter of the semiconductor wafer (thus limiting such movements as described above).

[0058] If such a movement is performed when the semiconductor wafer is already perfectly centered on the target center point of the pedestal base, the edge of the wafer will ideally simply contact one or more radially inward-facing wafer centering surfaces without moving as a result of such contact. However, if the semiconductor wafer is not perfectly centered on the target center point of the pedestal base before such a movement is performed, a movement that brings the semiconductor wafer into contact with one of the one or more radially inward-facing wafer centering surfaces will generally move the semiconductor wafer radially inward relative to the target center point, thereby further centering the semiconductor wafer on the target center point. Such a movement may be performed such that multiple points on the semiconductor wafer's circumference are moved toward one of the one or more radially inward-facing wafer centering surfaces, thereby pushing the semiconductor wafer toward the target center point until the semiconductor wafer is ultimately centered thereon.

[0059] FIG. 1 illustrates exemplary simplified representations of a pedestal, semiconductor wafer, showerhead, and wafer centering features. The first moving mechanism and semiconductor processing chamber housing described above are not shown in FIG. 1, but examples thereof are provided in subsequent figures.

[0060] 1 , a showerhead 108 is provided that includes a gas inlet 110 that can supply one or more process gases to an interior plenum volume 109 of the showerhead 108. The interior plenum volume 109 may then be fluidly connected to a plurality of gas distribution ports 114 that exit the underside of the showerhead 108 through a first surface 112 of the showerhead 108. Gases that enter the showerhead 108 through the gas inlet 110 thus exit the showerhead 108 through the gas distribution ports 114. It should be understood that the term "showerhead" may be used to refer to any structure configured to distribute or deliver process gases to wafers during wafer processing operations in a semiconductor processing chamber.

[0061] 1 , a plurality of wafer centering features 130 may extend from the underside of the showerhead 108 and project downwardly toward the pedestal base 118. Each wafer centering feature 130 may have a corresponding radially inward-facing wafer centering surface 132 that is at least partially located at a lower elevation than the first surface 112.

[0062] 1 may be positioned on a pedestal 116 that includes a pedestal base 118 supported by a stem 120. The pedestal base 118 may have a wafer support feature 122. In this example, there is a single wafer support feature 122 in the form of a raised circular platform defined by a circumferential edge 121. The wafer support feature 122 defines a first reference plane 124 that coincides with the underside of the semiconductor wafer 102 that rests on the wafer support feature 122. The first reference plane 124 may also define a second reference plane 126 that is parallel to the first reference plane 124, spaced apart by the thickness T of the semiconductor wafer 102, and oriented toward the showerhead 108.

[0063] The pedestal 116 in this example may be movable along an axis 128 perpendicular to the first reference surface 124, for example, to the position shown by the dotted line. As can be seen, the pedestal 116 is movable between a first configuration in which the pedestal base 118 is positioned as shown by the solid line (e.g., a configuration in which the first reference surface 124 is below the wafer centering feature 130 by a distance equal to or greater than the thickness T of the semiconductor wafer 102) and a second configuration in which the pedestal base 118 is positioned as shown by the dotted line (e.g., a configuration in which the first reference surface 124 is within a distance equal to the thickness T of the semiconductor wafer 102 of the wafer centering feature 130). As can be seen, in the second configuration, the radially inward-facing wafer centering surface 132 extends into the space between the first reference surface 124 and the second reference surface 126. Thus, when the pedestal 116 is moved horizontally while in the second configuration, the edge of the wafer 102 eventually contacts one of the radially inward facing wafer centering surfaces 132 .

[0064] Such movement is described with reference to Figures 2a-2l, which illustrate plan views of the elements shown in Figure 1 at various stages of the wafer centering process. The showerhead 108 (excluding gas distribution ports 114), wafer centering features 130, and semiconductor wafer 102 are shown in solid lines, and the pedestal base 118 is shown in dashed lines. As seen in Figure 2a, the pedestal base 118 is shown in a centered position directly beneath the showerhead 108, as it would be during a wafer processing operation. The long-dashed circle represents the centered wafer footprint 101, which represents the footprint of the semiconductor wafer 102 when perfectly centered on the target center location 119 of the pedestal base 118. However, the wafer center 103 of the wafer 102 is now misaligned from the target center location 119.

[0065] As seen in Figure 2a, the radially inward-facing wafer centering surface 132 of wafer centering feature 130 is an arcuate surface that, at its radially innermost point, circumscribes a reference circle 136, indicated by a dashed-dotted line. Figures 2b-2l show how the pedestal base 118 moves laterally relative to the showerhead 108 through various locations so that the wafer 102 is centered relative to the pedestal base 118. References to the direction of movement in the following description use terms such as left, right, up, and down to refer to movement relative to the page orientation of each figure.

[0066] 2b, the pedestal base 118 has been moved to the right, as indicated by the rightmost arrow, a distance equal to half the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102. This causes the semiconductor wafer 102 to contact the rightmost radially inward-facing wafer centering surface 132 during part of the lateral movement of the pedestal base 118, thereby pushing the semiconductor wafer 102 to the left relative to the pedestal base 118, closer to the target center point 119.

[0067] In FIG. 2c, the pedestal base has been moved to the left, as indicated by the leftmost arrow, by the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102 (this distance is twice the distance moved in FIG. 2b, as the pedestal base 118 is first returned to its home position where it is centered on the showerhead 108, essentially reversing the movement performed in FIG. 2b, before being moved to the location shown in FIG. 2c). As can be seen, the semiconductor wafer 102 approaches, but does not contact, the leftmost radially inward-facing wafer centering surface 132. Therefore, no relative movement between the semiconductor wafer 102 and the pedestal base 118 occurs during the movement shown in FIG. 2c.

[0068] In Figure 2d, the pedestal base 118 is returned to its home position before being moved up and to the right (relative to the page orientation) along a vector 60° from horizontal by half the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102, as shown in Figure 2e. As can be seen, the semiconductor wafer 102 approaches, but does not contact, the top, radially inward-facing wafer centering surface 132 on the right side. Therefore, no relative movement occurs between the semiconductor wafer 102 and the pedestal base 118 during the movement shown in Figure 2e.

[0069] In FIG. 2f, the pedestal base has been moved downward and to the left by the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102, as indicated by the arrow at the lower left (this distance is twice the distance moved in FIG. 2e, as the pedestal base 118 is initially returned to its home position centered on the showerhead 108, essentially reversing the movement performed in FIG. 2e, before being moved to the location shown in FIG. 2f). This causes the semiconductor wafer 102 to contact the lowermost, radially inward-facing wafer centering surface 132 on the left side during part of the lateral movement of the pedestal base 118, thereby pushing the semiconductor wafer 102 upward and to the right relative to the pedestal base 118, closer to the target center point 119.

[0070] In Figure 2g, the pedestal base 118 is returned to its home position before being moved up and left (relative to the page orientation) along a vector 60° from horizontal by half the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102, as shown in Figure 2h. As can be seen, the semiconductor wafer 102 approaches, but does not contact, the top, radially inward-facing wafer centering surface 132 on the left side. Therefore, no relative movement occurs between the semiconductor wafer 102 and the pedestal base 118 during the movement shown in Figure 2h.

[0071] In FIG. 2i, the pedestal base has been moved downward and to the right by the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102, as indicated by the arrow at the lower right (this distance is twice the distance moved in FIG. 2e, as the pedestal base 118 is initially returned to its home position centered on the showerhead 108, essentially reversing the movement performed in FIG. 2h, before being moved to the location shown in FIG. 2i). This causes the semiconductor wafer 102 to contact the lowermost, radially inward-facing wafer centering surface 132 on the right side during part of the lateral movement of the pedestal base 118, thereby pushing the semiconductor wafer 102 upward and to the left relative to the pedestal base 118, closer to the target center point 119.

[0072] 2j, the pedestal base 118 is returned to its home position. At this point, the pedestal base 118 is moved from the home position toward all six of the radially inward-facing wafer centering surfaces 132, thereby pushing the semiconductor wafer 102 much closer to the target center point 119. However, as can be seen, the semiconductor wafer 102 is still somewhat off-center with respect to the target center point 119. If more precise centering of the semiconductor wafer 102 is required, the above-described movement can be repeated, with each such repetition pushing the semiconductor wafer 102 further closer to the target center point 119 until the wafer is perfectly centered on the target center point 119.

[0073] For example, in FIG. 2k, the pedestal base 118 is caused to repeat the movement illustrated in FIG. 2b, and during a portion of the lateral movement of the pedestal base 118, the semiconductor wafer 102 again contacts the right-end radially inward-facing wafer centering surface 132, thereby pushing the semiconductor wafer 102 to the left relative to the pedestal base 118 and again approaching the target center point 119.

[0074] 2l, the pedestal base 118 is returned to its home position. As can be seen, the semiconductor wafer 102 is perfectly centered on the target center point 119.

[0075] 2b-2l are reproduced in FIG. 3a and generally involve repeated radial movements from a home position to either side of a circle (shown using dashed lines) that is concentric with reference circle 136 and has a diameter equal to the difference between the diameter of reference circle 136 and the diameter of semiconductor wafer 102. As can be seen, target center point 119 of pedestal base 118 may be repeatedly advanced from the home position to one side of the circle, returned to the home position (the center of the circle), then advanced to the opposite side of the circle, and then returned to the home position again. (Although the radial movements of target center point 119 are shown along spaced paths, this is merely for ease of understanding; the actual paths may all pass through the target center point.)

[0076] Figure 3b illustrates an alternative path along which the pedestal base 118 may be moved. The path in Figure 3b is similar to that in Figure 3a, except that the target center point may change direction each time it reaches the center of the circle (rather than passing through the center of the circle and heading to the other side of the circle).

[0077] FIG. 3c illustrates another type of path along which the pedestal base 118 can be moved. The path shown in FIG. 3c is a spiral path that spirals outward from the location of the target center point when the pedestal base 118 is in its home position until it reaches a distance from that location equal to half the difference between the diameter of the reference circle 136 and the diameter of the semiconductor wafer 102, at which point the path transitions to a circular or arcuate path of the same radius as the circle. When such a path is used, the semiconductor wafer 102, even if off-center with respect to the target center point, will eventually contact successive radially inward-facing wafer centering surfaces 132 along the circumference of the circle, with each such contact pushing the semiconductor wafer closer to the target center point. Such an approach avoids large single adjustments to the position of the semiconductor wafer 102 with respect to the target center point and, therefore, may result in more accurate centering results that do not require the repetition of previously performed actions, as occurred in FIG. 2k.

[0078] Figure 3d illustrates yet another exemplary path that may be followed by pedestal base 118. In the path illustrated in Figure 3d, pedestal base 118 repeatedly follows circular paths, each with a larger diameter than the previous path, until the final circular path followed by pedestal base 118 has the same radius as a circle.

[0079] It will be understood that the above-described four paths are merely examples of paths that the pedestal base 118 may follow to center the semiconductor wafer 102 at the target center point 119. As will be apparent from further examples described below, it will also be understood that the above-described wafer centering techniques can be implemented in a similar manner, except that the wafer centering features 130 are moved relative to the pedestal base 118. For example, the showerhead 108 having the wafer centering features 130 can be moved relative to the pedestal base 118 to push the semiconductor wafer 102 toward the target center point 119. In such cases, the movement of the wafer centering features 130 relative to the pedestal base 118 can be reversed from the movement of the pedestal base 118 in the above-described examples. For example, the wafer centering features 130 may be collectively moved to follow an inward spiral path that is actually the reverse of the path of FIG. 3c.

[0080] It will be appreciated that the movement paths described above and illustrated in Figures 3a-3d may in practice be very small, for example, fitting within a circular area of ​​only a few millimeters or less, e.g., 1 mm or less. Because most wafer placement systems are capable of placing a semiconductor wafer within a few hundred microns of its intended position, the movement of the pedestal base relative to the wafer centering feature that may be required to center the wafer at the target center point can be correspondingly very small.

[0081] While the above description focuses on how the pedestal base is laterally moved to push the semiconductor wafer supported thereon to center it at a target center point, the above examples do not describe exemplary translation mechanisms that can be used to achieve such movement. The following description considers several different types of translation mechanisms, as illustrated in Figures 4a-6.

[0082] 4a-4c illustrate an exemplary semiconductor processing tool 400 that includes a semiconductor processing chamber 404. The semiconductor processing chamber 404 may have an interior volume 406 bounded by walls of the semiconductor processing chamber 404.

[0083] The semiconductor processing chamber 404 can at least partially house a showerhead 408 within its interior volume 406. The showerhead 408 can include a gas inlet 410 that can be used to provide one or more process gases to an interior plenum volume 409 of the showerhead 408. Such process gases can then exit the interior plenum volume 409 via a plurality of gas distribution ports 414 distributed across a first surface 412 of the showerhead 408. Similar to the showerhead 108, the showerhead 408 has a plurality of wafer centering features 430 fixed relative to the showerhead 408.

[0084] The interior volume 406 may also at least partially house a pedestal 416 therein. The pedestal 416 may include a pedestal base 418 supported by a stem 416. The stem 416, in this example, extends through an opening in the floor of the semiconductor processing chamber 404 and is connected to a first movement mechanism 438a. A bellows seal 488 (e.g., a metal bellows seal) may be connected to the pedestal base 418 and the semiconductor processing chamber 404 to prevent process gases from escaping the semiconductor processing chamber 404 while allowing both vertical and lateral movement of the pedestal 416 relative to the semiconductor processing chamber 404.

[0085] The first transfer mechanism 438a, in this case, is a hexapod mechanism 454. The hexapod mechanism 454 may have a base mount 456 and a movable mount 458, as well as six independently controllable linear actuators 460 that connect the base mount 456 and the movable mount 458 and provide a device commonly referred to as a "Stewart platform." The base mount 456 of the hexapod mechanism 454 may be fixedly mounted relative to the semiconductor processing chamber 404, or may at least be mounted so that it can be held stationary relative to the semiconductor processing chamber 404, while the movable mount 458 of the hexapod mechanism 454 supports a pedestal 416 that is used to support a semiconductor wafer 402 within the semiconductor processing chamber 404.

[0086] Stewart platforms are typically used in applications requiring six degrees of freedom over a relatively large range of motion, such as flight simulators, radio telescopes, and spacecraft docking systems. Such Stewart platform systems are often designed to allow the movable mount to rotate through tilts of 45° to 60° in any direction, for example, and also to translate the movable mount in any direction over significant distances. Hexapod mechanisms used in semiconductor processing tools, such as semiconductor processing tool 100, can be configured to provide greater precision with smaller travels.

[0087] By supporting the pedestal 416 on the movable mount 458 of the hexapod mechanism 454, the pedestal 416 can simultaneously move laterally and / or vertically and / or tilt or rotate as desired. Thus, the lateral movement of the pedestal base 118 described above with respect to Figures 2a-2l can be achieved, for example, in the exemplary semiconductor processing chamber 404 by controlling the hexapod mechanism 454 to cause the movable mount 458 to perform pure translational movement without any vertical movement or rotation of the semiconductor wafer 402. In practice, the hexapod mechanism 454 can be controlled to move the movable mount 458 along any desired two-dimensional path to urge the semiconductor wafer 402 inward toward a target center point with the radially inward-facing wafer centering surfaces 432 of the wafer centering features 430. The hexapod mechanism 454 can also control the pedestal base 418 to move up and down vertically, for example, so that there is a vertical gap between the semiconductor wafer 402 and the bottom portion of the wafer centering feature 430, or so that the bottom portion of the wafer centering feature 430 is within a thickness T of the first reference plane 424 (which is coincident with or flush with the underside of the semiconductor wafer 402). This effectively traps or captures the semiconductor wafer 402, as the case may be, between the pedestal base 416, the showerhead 408, and the wafer support feature 430, but then releases, allowing the semiconductor wafer to move onto or off the pedestal 416 without colliding with the wafer support feature 430.

[0088] 4b and 4c illustrate the hexapod mechanism 454 being actuated to move the movable mount 458 laterally left and right, respectively, to bring the semiconductor wafer 402 into contact with the wafer centering features 430 on either side of the showerhead 408. It will be appreciated that the hexapod mechanism 454 can also be controlled to bring the semiconductor wafer 402 into contact with any of the other wafer centering features 430.

[0089] FIG. 5 illustrates another exemplary translation mechanism that can be used as the first translation mechanism. The translation mechanism of FIG. 5 is an XY stage including a first guide 562 fixedly mounted to a base mount 556. One or more first stages 558 can be slidably mounted to the first guide 562 and actuated using one or more first motors 566 that can drive one or more first linear screws 554 (which can collectively form a first linear translation mechanism), thereby linearly translating the one or more first stages 558 left and right relative to FIG. 5. The one or more first stages 558 can in turn support one or more second guides 564 that can slidably support a second stage 560. The second stage 560 can be linearly translated along a second guide 564 by actuation of a second motor 568, which can drive a second linear screw 556 (which can collectively form a second linear translation mechanism), which advances the second stage 560 along the second guide 564. For example, by driving both the first motor 566 and the second motor 568 at different speeds and / or amounts in response to signals received from a controller, the second stage 560 (and the pedestal supported thereby) can be moved along any desired path, much like the pedestal 416 of FIGS. 4a-4c. In some implementations, the first stage 558 can be translated along a first axis that is orthogonal to a second axis along which the second stage is configured to translate.

[0090] FIG. 6 illustrates an R-theta mechanism that can be used as a first movement mechanism in some embodiments. In the R-theta mechanism, a linear translation mechanism 648 can be provided that includes a guide 662 fixedly mounted relative to a rotatable portion 649. The rotatable portion 649 can be rotatably connected to the base portion 602 and can be controllable, for example, via an electric motor, to rotate the rotatable portion 649 (and the guide 662 and other equipment that may be supported thereby) about an axis of rotation relative to the base portion 602. The rotatable portion 649 can support the linear translation mechanism 648, which includes a first portion fixedly mounted relative to the rotatable portion 649 and a second portion 658 slidably mounted to the guide 662 so that the first portion can translate along the guide 662, e.g., along a radial axis. The guide 662 can be any suitable bearing surface, e.g., a round steel bar, that can guide the movement of the second portion 658. A pedestal stem can be attached to the second portion 658. The linear translation mechanism may also include a motor 666 capable of rotating the linear screw 654 in response to input received from the controller, which, as it passes through a threaded nut fixed relative to the second portion 658, may drive the movement of the second portion 658 along the guide 662, as indicated by the double-headed arrow shown in FIG. 6. Similar to the XY stage of FIGS. 4a-4c, the R-theta mechanism may be used to move the pedestal supported thereby to follow any desired path (within the range of motion of the R-theta mechanism).

[0091] These are just some of the exemplary movement mechanisms that can be used to provide relative lateral movement between the pedestal base and one or more wafer centering features. It will be understood that any suitable mechanism can be used as the first movement mechanism, and the present disclosure is not limited to only the three examples described above.

[0092] As previously mentioned, the first moving mechanism need not necessarily be configured to move the pedestal base relative to the wafer centering features, and in some embodiments, the first moving mechanism may instead be configured to move the wafer centering features relative to the pedestal base.

[0093] 7 illustrates an example of a semiconductor processing tool configured to perform post-load wafer centering using a movable showerhead. As shown in FIG. 7, a semiconductor processing tool 700 is provided that includes a showerhead that includes a semiconductor processing chamber 704. The semiconductor processing chamber 704 can have an interior volume 706 bounded by walls of the semiconductor processing chamber 704.

[0094] The semiconductor processing chamber 704 can at least partially house a showerhead 708 within its interior volume 706. The showerhead 708 can include a gas inlet 710 that can be used to provide one or more process gases to an interior plenum volume 709 of the showerhead 708. Such process gases can then flow out of the interior plenum volume 709 via a plurality of gas distribution ports 714 distributed across a first surface 712 of the showerhead 708. Similar to showerheads 108 and 408, the showerhead 708 has a plurality of wafer centering features 730 that are spatially fixed relative to the showerhead 708.

[0095] The interior volume 706 may also, at least partially, house a pedestal 716 therein. The pedestal 716 may include a pedestal base 718 supported by a stem 716. The stem 716, in this example, extends through an opening in the floor of the semiconductor processing chamber 704 and, in some implementations, may be supported by a movement mechanism (not shown), which may, for example, allow the pedestal 716 to be moved up and down. The semiconductor wafer 702 may be supported by the pedestal base 718. A bellows seal 788a (e.g., a metal bellows seal) may connect the pedestal base 718 and the semiconductor processing chamber 704 to prevent process gases from escaping the semiconductor processing chamber 704 while allowing vertical movement of the pedestal 716 relative to the semiconductor processing chamber 704.

[0096] Similar to semiconductor processing tool 400, semiconductor processing tool 700 includes a first transfer mechanism 738a, which in this example is a hexapod mechanism 754. Hexapod mechanism 754 can have a base mount 756 and a moveable mount 758, as well as six independently controllable linear actuators 760 connecting base mount 756 and moveable mount 758 to provide a Stewart platform. Base mount 756 of hexapod mechanism 754 can be fixedly mounted relative to semiconductor processing chamber 704, or at least mounted such that it can be held stationary relative to semiconductor processing chamber 704. However, in contrast to semiconductor processing tool 400, hexapod mechanism 754 is mounted on top of the semiconductor processing chamber, and movable mounts 758 of hexapod mechanism 754 support showerhead 708 such that showerhead 708 with wafer centering features 730 can be moved laterally relative to pedestal base 718 in much the same way as pedestal base 418 can be moved laterally relative to showerhead 408 and wafer centering features 430 in the example of Figures 4a-4c.

[0097] It will also be understood that the first movement mechanism in FIG. 7 may be a different type of movement mechanism, such as an XY stage or an R-theta mechanism. Various additional exemplary embodiments illustrating different configurations of wafer centering features are described below with reference to FIGS. 8a-12b. While each of these additional examples illustrates the first movement mechanism as a hexapod mechanism, it will be understood that, as noted above, alternative movement mechanisms may be used in place of a hexapod mechanism. It should also be noted that the embodiments of FIGS. 8a-12b share many similarities with the examples of FIGS. 4a-4c and 7. For the sake of brevity, structures in FIGS. 8a-12b that are similar to those in FIGS. 4a-4c and 7 will not be described again below. Such structures in FIGS. 8a-12a that may be designated using the same last two digits as those used for the structures in FIGS. 4a-4c and 7 can be assumed to be the same as the structures in FIGS. 4a-4c and 7, unless otherwise indicated in the following description. Furthermore, it will be understood that the description of such structures with reference to Figures 4a-4c and 7 equally applies to the structures of Figures 8a-12a having reference numbers that share the same last two digits as the similar structures of Figures 4a-4c and 7.

[0098] In all of the examples described thus far, the wafer centering feature is spatially fixed relative to the showerhead, e.g., protruding downward from the underside of the showerhead. Figures 8a and 8b illustrate an exemplary semiconductor processing tool 800 in which the wafer centering feature 830 is spatially fixed relative to the semiconductor processing chamber 804, both the pedestal 816 and the showerhead 808 are configured to be movable along at least axis 828, and the pedestal base 818 is also movable laterally relative to the semiconductor processing chamber 804. For example, the pedestal base 818 can be supported by a first movement mechanism 838a, e.g., a hexapod mechanism 854, that can be controlled to move the pedestal 816 (and pedestal base 818) laterally and / or vertically. Similarly, the showerhead 808 can be connected to a second movement mechanism 838b, which can be, for example, a linear actuator or other device that can be controlled to move the showerhead 808 up and down relative to the semiconductor processing chamber 804.

[0099] As can be seen, wafer centering features 830 are actually long posts that extend downward from the ceiling or lid of semiconductor processing chamber 804 and through through-openings 842 in showerhead 808. Through-openings 842 may be sized large enough so that there is a gap extending around each wafer centering feature between the sidewall of through-opening 842 and the portion of wafer centering feature 830 located within through-opening 842. This gap may be sized so that there is no contact between wafer centering feature 830 and showerhead 808 when showerhead 808 is moved along axis 828 (e.g., by operation of second moving mechanism 838b). In some implementations, this gap may be sized to be smaller than the thickness (e.g., 1 mm to 2 mm) of a plasma sheath of a plasma that may be generated within the semiconductor processing chamber when wafer processing operations are performed. This may reduce the possibility of plasma being initiated within through-opening 842, thereby arcing and generating particulates that may contaminate semiconductor wafer 802. It will also be appreciated that the through apertures 842 may take the form of radial cutouts in the outer surface of the pedestal base plate, i.e., the wafer support features 830 are visible throughout the thickness of the pedestal base 818 when viewing the pedestal base 818 in a direction perpendicular to the axis 828. This is also true in other similar instances where through apertures are used, such as those described below.

[0100] 8a and 8b illustrate the semiconductor processing tool 800 when the showerhead 808 and pedestal base 818 are in various configurations. For example, in FIG. 8a, the showerhead 808 is elevated in a first configuration relative to the semiconductor processing chamber 804, such that the first ends of the wafer centering features 830 protrude beyond the first surface 812 of the showerhead 808 toward the pedestal base 818. The showerhead 808 can also be lowered to a second configuration, as shown in FIG. 8b, in which the first ends of the wafer centering features 830 do not extend beyond the first surface 812 of the showerhead 808, or extend beyond the first surface 812 to a lesser extent than in the first configuration.

[0101] Similarly, in FIG. 8 a, pedestal base 818 has been moved to a third configuration relative to semiconductor processing chamber 804, with first reference surface 824 within a distance T, equal to the thickness of semiconductor wafer 802, of a first end of wafer centering feature 830. While the first end of wafer centering feature 830 in FIG. 8 a is shown extending into, but not through, the space between first reference surface 824 and second reference surface 826, it will be understood that the first end of wafer centering feature 830 may also extend beyond first reference surface 824 (e.g., if wafer support feature 822 has a diameter smaller than the diameter of semiconductor wafer 802). In such a configuration, a portion of the first end of wafer centering feature 830 may still be within the thickness T of semiconductor wafer 802 of first reference surface 824 (even if other portions are spaced therefrom).

[0102] In FIG. 8 b, the pedestal base 818 has been moved downward to a fourth configuration, with the first reference surface 824 positioned above the thickness T below the first end of the wafer centering feature 830.

[0103] When the showerhead 808 is in the first configuration and the pedestal base 818 is in the third configuration, the semiconductor wafer 802 may be effectively confined between the first surface 812 and the wafer support features 822 and within a circular region having the same size, shape, and location as the first reference circle. This allows the semiconductor wafer 802 to be centered relative to the pedestal base 818 through lateral movement of the pedestal base 818 relative to the semiconductor processing chamber 804, as may be provided, for example, by the first movement mechanism 838 a.

[0104] Moving the showerhead 808 to the second configuration can at least partially “retract” the wafer centering feature 830 into the showerhead 808, thereby reducing the likelihood that the wafer centering feature will be a potential source of anomalies within the semiconductor processing chamber 804, leading to reduced wafer processing uniformity. The pedestal base 818 can likewise be moved to the fourth configuration, e.g., to allow the showerhead 808 to be lowered so that the first surface 812 is lowered to an elevation lower than the elevation of the second reference plane 826 when the pedestal base 818 was in the third configuration. The pedestal base 818 must then be moved downward to allow space for the downward movement of the showerhead 808. Moving the pedestal base 818 to the fourth configuration can also allow the semiconductor wafer 802 to be inserted into or removed from the space between the showerhead 808 and the wafer support feature 812 (e.g., when a wafer handling robot places the semiconductor wafer 802 on the pedestal base 818). If the pedestal base 818 is not lowered in this manner, any attempt to move the semiconductor wafer 802 laterally relative to the semiconductor processing chamber will result in the semiconductor wafer 802 colliding with one or more of the wafer centering features.

[0105] The semiconductor processing chamber 804 may also include bellows seals 888a and 888b therein. The bellows seals 888a and 888b may be configured to provide flexible sealing elements between the showerhead pedestal base 818 and the semiconductor processing chamber 804, and between the showerhead 808 and the semiconductor processing chamber 804. The bellows seals 888a and 888b may be metal bellows seals made of, for example, stainless steel.

[0106] 9a and 9b illustrate a semiconductor processing tool 900 that is similar in many respects to semiconductor processing tool 800. However, in semiconductor processing tool 900, wafer centering features 930 are fixedly connected to structure beneath pedestal base 918 rather than above showerhead 908. Thus, wafer centering features 930 extend upward from the floor or base of semiconductor processing chamber 904 (or other structure positioned below pedestal base 918 and fixed in position relative to semiconductor processing chamber 904) and pass through through-openings 942 in pedestal base 918. Through-openings 942 may be sized sufficiently large so that there is a gap extending around each wafer centering feature between the sidewall of through-opening 942 and the portion of wafer centering feature 930 that is located within through-opening 942. The gap can be sized so that no contact exists between the wafer centering feature 930 and the showerhead 908 when the showerhead 908 is moved along the axis 928 (e.g., by operation of the second moving mechanism 938b). The gap may also be sized to be greater than half the difference between the diameter of the semiconductor wafer 902 and the reference circle defined by the radially inward-facing wafer centering surface 932 of the wafer centering feature 930, thereby ensuring sufficient clearance between the sidewall of the through-opening 942 and a portion of the wafer centering feature 930 so that no contact occurs between the wafer centering feature 930 and the sidewall of the through-opening 942 when the pedestal base 918 moves laterally relative to the semiconductor processing chamber 904 and the wafer centering feature 930 during a wafer centering operation.

[0107] In some implementations, the gap may also be sized to be smaller than the thickness (e.g., 1 mm to 2 mm) of a plasma sheath of a plasma that may be generated within the semiconductor processing chamber when wafer processing operations are performed. This reduces the possibility of plasma being initiated within the through-opening 942, thereby causing arcing and the generation of particulates that may contaminate the semiconductor wafer 902. It will be appreciated that such a small gap may still provide sufficient clearance to accommodate wafer centering movement of the pedestal base 918 relative to the semiconductor processing chamber 904. This is because the amount of centering correction for the semiconductor wafer 902 that may often be required may be on the order of several hundred microns; for example, the difference between the diameter of the semiconductor wafer 902 and the reference circle defined by the radially inward-facing wafer centering surface 932 of the wafer centering feature 930 may be on the order of 1 to 2 millimeters or less.

[0108] 10a and 10b illustrate an exemplary semiconductor processing tool in which the wafer centering feature is not fixed relative to the semiconductor processing chamber or showerhead. As seen in FIG. 10a, the semiconductor processing chamber 1004 includes a pedestal 1016 connected to a first transfer mechanism 1038a and configured to be laterally movable relative to the semiconductor processing chamber 1004. For example, the pedestal base 1018 may be supported by a stem 1020 connected to the first transfer mechanism 1038a, e.g., a hexapod mechanism 1054, that is controllable to move the pedestal 1016 (and pedestal base 1018) laterally and / or vertically relative to the semiconductor processing chamber 1004.

[0109] 8a and 8b, wafer centering feature 1030 is provided, except that wafer centering feature 1030 is connected to one or more second movement mechanisms 1038b (e.g., linear or other actuators) configured to move wafer centering feature 1030 along axis 1028. Wafer centering feature 1030, in this example, is a long post extending downward from a ring-shaped support structure surrounding the stem of showerhead 1008 and is connected to second movement mechanism 1038b. Wafer centering feature 1030 can extend downward from the support structure and through opening 1042 to showerhead 1008.

[0110] The through openings 1042 can be sized sufficiently large so that there is a gap extending around each wafer centering feature between the sidewall of the through opening 1042 and the portion of the wafer centering feature 1030 located within the through opening 1042. As with previous examples described herein, the gap can be sized so that there is no contact between the wafer centering feature 1030 and the showerhead 1008 when the wafer centering feature 1030 is moved along the axis 1028 relative to the semiconductor processing chamber 1004, for example, by operation of the second moving mechanism 1038b. As with previous examples described herein, in some implementations, this gap can be sized to be smaller than the thickness (e.g., 1 mm to 2 mm) of a plasma sheath of a plasma that may be generated within the semiconductor processing chamber 1004 when wafer processing operations are performed. This can reduce the possibility of a plasma being initiated within the through openings 1042, thereby reducing the possibility of arcing and the generation of particulates that may contaminate the semiconductor wafer 1002.

[0111] 10a and 10b illustrate the semiconductor processing tool 1000 when the wafer centering feature 1030 and the pedestal base 1018 are in various configurations. For example, in FIG. 10a, the second moving mechanism 1038b, e.g., a linear translation mechanism, is actuated to a first position. When the second moving mechanism 1038b is in the first position, it lowers the wafer centering feature 1030 to a first configuration relative to the semiconductor processing chamber 1004, such that a first end of the wafer centering feature 1030 protrudes beyond the first surface 1012 of the showerhead 1008 toward the pedestal base 1018, e.g., the first end of the wafer centering feature 1030 extends beyond the second reference plane 1026.

[0112] When the second moving mechanism 1038b is actuated to the second position, this can move the wafer centering feature 1030 upward to a second configuration relative to the semiconductor processing chamber 1004, so that the first end of the wafer centering feature 1030 is positioned above the first surface 1012, or at least at a height higher than when the second moving mechanism 1038b was in the first position.

[0113] When the wafer centering feature 1030 is in the first configuration, its first end can be positioned such that one or more radially inward-facing centering surfaces 1032 of the wafer centering feature 1030 are positioned at least partially below the second reference surface 1026, such that when the semiconductor wafer 1002 is moved laterally by lateral movement of the pedestal base 1018 via actuation of the first movement mechanism 1038a during a wafer centering operation, the semiconductor wafer 1002 contacts at least one of the one or more radially inward-facing centering surfaces 1032 and is pushed toward a target center point associated with the pedestal base 1018. Such a configuration can also, optionally, involve moving the pedestal base 1018 along the axis 1028 such that the second reference surface 1026 is above at least a bottom-most portion of the one or more radially inward-facing centering surfaces 1032.

[0114] 10b, the wafer centering feature 1030 is retracted into the through-opening 1042 of the showerhead 1008 by actuation of the second moving mechanism 1038b. Such a configuration may, for example, reduce anomalies that may occur on the semiconductor wafer due to the localized effect of the wafer centering feature 1030 on the plasma environment generated within the semiconductor processing chamber 1004. Such a configuration may also, for example, allow the semiconductor wafer 1002 to be placed on and removed from the pedestal base 1018 during wafer load / unload operations, as described above.

[0115] The semiconductor processing chamber 1004 may also include bellows seals 1088a and 1088b therein. The bellows seals 1088a and 1088b may be configured to provide a flexible sealing element between the showerhead pedestal base 1018 and the support structure supporting the semiconductor processing chamber 1004 and wafer centering feature 1030. The bellows seals 1088a and 1088b may be metal bellows seals made of, for example, stainless steel.

[0116] Figures 11a and 11b illustrate an embodiment similar to Figures 10a and 10b, except that the second moving mechanism 1138b is located on the underside of the semiconductor processing chamber 1104, the support structure supporting the wafer centering feature 1130 is positioned within the internal volume 1106 of the semiconductor processing chamber 1104, and the wafer centering feature 1130 extends upward through a through opening 1142 in the pedestal base 1118.

[0117] 9a and 9b, the through openings 1142 can be sized large enough so that there is a gap extending around each wafer centering feature between the sidewall of the through opening 1142 and the portion of the wafer centering feature 1130 located within the through opening 1142. The gap can be sized such that there is no contact between the wafer centering feature 1130 and the showerhead 1108 when the showerhead 1108 is moved along the axis 1128 (e.g., by operation of the second moving mechanism 1138b). The gap may also be sized to be greater than half the difference between the diameter of the semiconductor wafer 1102 and the reference circle defined by the wafer centering surface 1132 facing radially inward of the wafer centering feature 1130, thereby ensuring sufficient clearance between the sidewall of the through opening 1142 and a portion of the wafer centering feature 1130 so that contact does not occur between the wafer centering feature 1130 and the sidewall of the through opening 1142 when the pedestal base 1118 moves laterally relative to the semiconductor processing chamber 1104 and the wafer centering feature 1130 during a wafer centering operation, for example, due to lateral movement caused by actuation of the first moving mechanism 1038a.

[0118] The examples described herein have thus far featured semiconductor processing tools each including a plurality of wafer centering features (e.g., posts), which collectively define a circular zone or region that acts to "enclose" a semiconductor wafer during lateral movement between the wafer centering feature and the pedestal base. However, it will be understood that the wafer centering features described herein can take other shapes and forms, such as a single peripheral wall that may have an uninterrupted circular perimeter, such that a semiconductor wafer centered thereby will contact the peripheral wall regardless of which direction the pedestal base and / or wafer centering feature are laterally moved, even if slightly off-center. The reference circle defined by such wafer centering features is, of course, the circle defined by the inward-facing, axially symmetric plane of such wafer centering feature.

[0119] 12a and 12b illustrate such an exemplary semiconductor processing tool. In FIGS. 12a and 12b, semiconductor processing tool 1200 includes a pedestal 1216 supported by a first moving mechanism 1238a within the interior volume of a semiconductor processing chamber 1204. In this example, one or more wafer centering features 1230 are provided by an annular collar including an annular wall element surrounding a showerhead 1208. The annular wall element is connected to an annular backplate, which is connected to a second moving mechanism 1238b, which is configured to move the annular collar / wafer centering feature 1230 along axis 1228 when actuated, for example, between a first position shown in FIG. 12a and a second position shown in FIG. 12b. When the one or more second moving mechanisms 1238b are in the first position, the annular wall element of the wafer centering feature 1230 extends downwardly beyond the first surface 1212 and beyond the second reference plane 1226, so that, for example, when the semiconductor wafer 1202 is moved laterally relative to the wafer centering feature by the first moving mechanism 1238a, the semiconductor wafer 1202 can come into contact with the annular wall element of the wafer centering feature 1230.

[0120] When the second moving mechanism 1238b is in the second position, the wafer centering feature 1230 can be lifted upward, thereby raising the annular wall element from the position in FIG. 12a to a position flush with the underside of the showerhead 1208 / first surface 1212, for example. In this configuration, the annular wall element can act as a radial extension of the showerhead 1208, which can help improve wafer uniformity because any anomalies that may be associated with the edge of the showerhead 1208 can be effectively moved radially outward toward the edge of the annular wall element.

[0121] In other embodiments, the annular wall element may be a fixed feature relative to the showerhead 1208, similar to the embodiment of Figures 4a-4c. For example, the showerhead 1208 may simply have an inwardly facing, axisymmetric surface extending downward from the first surface 1212. This inwardly facing, axisymmetric surface may serve as the radially inwardly facing centering surface of the wafer centering feature.

[0122] When the second moving mechanism 1238b is in the first position, lateral movement of the pedestal base 1218 relative to the wafer centering feature 1230 by actuation of the first moving mechanism 1238a can cause the semiconductor wafer 1202 to contact the annular wall element that provides the centering surface 1232 facing radially inward of the wafer centering feature 1230.

[0123] As is evident from the above examples, wafer centering features that may be used in embodiments of the concepts described herein may be implemented in a variety of different ways. Figures 13a-16b illustrate various simplified schematic diagrams of three different wafer centering feature geometries that may be used in some cases. These are merely a few examples of potential wafer centering feature geometries, and other geometries that may be used to similar effect are considered within the scope of this disclosure.

[0124] 13a and 13b illustrate a plan view and a side cross-sectional view, respectively, of a showerhead 1308 having a wafer centering feature 1330, the wafer centering feature 1330 consisting of an axisymmetric wall and defining a reference circle 1336, the reference circle 1336 having a diameter greater than the diameter D of a wafer that is centered by such wafer centering feature 1330.

[0125] 14a and 14b illustrate plan and side cross-sectional views, respectively, of a showerhead 1408 having a plurality of wafer centering features 1430, each providing an arcuate, radially inwardly facing wafer centering surface. The arcuate, radially inwardly facing wafer centering surfaces are arranged to be co-radial, e.g., have the same radius and share a common center point. As can be seen, the arcuate, radially inwardly facing wafer centering surfaces define a reference circle 1436 having a diameter greater than the diameter D of a wafer centered by such wafer centering features 1430. As can be seen, the wafer centering features 1430, in this example, are generally arcuate wall segments, arranged in a circular array with gaps between them.

[0126] 15a-15c illustrate top ( FIG. 15a ) and side ( FIG. 15b and FIG. 15c ) views of an exemplary showerhead and pedestal base including wafer centering features similar to those shown in FIGS. 14a and 14b . In FIG. 15a , a top view of a showerhead 1508 positioned on a pedestal base 1518 is shown. FIG. 15b illustrates the showerhead 1508 in a raised position relative to the pedestal base 1518, such as during a wafer loading operation. FIG. 15c illustrates the showerhead 1508 in a lowered position relative to the pedestal base 1518, such as during a wafer centering operation. The pedestal base 1518 may have multiple spacers 1517 (three in this case) extending upward from its upper surface. The spacers 1518 may be used to support the semiconductor wafer 1502 on the remaining portion of the pedestal base 1518, so that the underside of the semiconductor wafer 1502 does not actually contact any surface other than a generally small portion of the spacers 1517. As seen in FIGS. 15a-15c, three wafer centering features 1530 are provided by arcuate walls arranged in a circular array, the arcuate inward-facing surfaces of such arcuate walls can act as radially inward-facing centering surfaces. As further seen in FIGS. 15a-15c, each pair of circumferentially adjacent arcuate walls is separated by a corresponding gap, which is sized such that its radial offset from the center of the pedestal base 1518 is wider than the width of the spacers 1517, which is the same as the radial offset of the wafer centering features 1530 from the center of the showerhead 1508. The gap may be sized to be at least the width of the spacer plus the maximum expected amount of relative displacement between the pedestal base 1518 and the showerhead 1508. With the gap so sized, one or both of the pedestal base 1518 and the showerhead 1508 can be moved relative to the other of the pedestal base 1518 and the showerhead 1508 to perform wafer centering operations as previously described herein without the wafer centering features 1530 colliding with the spacers 1517.

[0127] It will be appreciated that the wafer centering feature 1530 in the embodiment of Figures 15a-15c can serve a dual purpose: it can be used to center and push the wafer during wafer centering operations, and it can also be left in the position shown in Figure 15c during wafer processing operations, effectively creating a microvolume that can act to help contain gases that enter the region above the semiconductor wafer 1502. For example, when the arrangement shown in Figures 15a-15c is used to perform semiconductor processing operations on the top surface of the semiconductor wafer 1502, process gases that may be introduced across the top surface of the semiconductor wafer 1502 can be confined to a smaller volume. While such gases may flow through the circumferential gap between the semiconductor wafer 1502 and the wafer centering feature 1530, as well as the radial gap between the spacer 1517 and the wafer centering feature 1530, such gaps are relatively small and can act as flow restrictions, facilitating the retention of process gases in the region directly above the semiconductor wafer 1502 for extended periods of time. In an alternative or additional example, the arrangements of Figures 15a-15c can be used to support backside processing of the semiconductor wafer 1502, such as deposition or etching operations performed by flowing process gases toward the underside of the semiconductor wafer 1502. In such embodiments, it may be desirable to flow an inert or non-reactive gas, such as nitrogen or argon, over the top of the semiconductor wafer 1502 to protect the top surface of the semiconductor wafer 1502 from potential exposure to the process gases that may diffuse into the space above the semiconductor wafer 1502. In such cases, the wafer centering features 1530 can similarly act as flow restriction portions that facilitate containing the inert or non-reactive gases to the region above the semiconductor wafer 1502. At the same time, such flow restriction portions can also hinder diffusion of the process gases into the space above the semiconductor wafer 1502. Thus, the wafer centering features 1530 of the embodiments of Figures 15a-15c are not only used for pre-processing wafer centering operations, but can also serve a functional purpose during wafer processing operations.

[0128] 16a and 16b illustrate plan and side cross-sectional views, respectively, of a showerhead 1608 having a plurality of wafer centering features 1630, each of which is a cylindrical post and provides an arcuate, radially inward-facing wafer centering surface. The arcuate, radially inward-facing wafer centering surfaces are arranged to have center points located outside of a reference circle 1636 that is circumscribed within the circular post. The reference circle 1636 can have a diameter greater than the diameter D of a wafer that is centered by such wafer centering features 1630.

[0129] Although the above examples are all provided with respect to wafer centering features that are part of a showerhead, it will be understood that such geometries can be implemented in any of the aforementioned examples as well.

[0130] Control of semiconductor processing tools as described herein (including the wafer centering features described above, as well as other possible equipment described above (e.g., wafer handling robots, showerheads, etc.)) can be facilitated through the use of a controller, which may be included as part of the exemplary semiconductor processing tools and / or chambers described above. The systems described above may be integrated with electronics for controlling system operation before, during, and after processing of a semiconductor wafer or substrate. Such electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. The controller may be programmed to control any of the processes disclosed herein depending on the processing requirements and / or type of system. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), valve operation, light source control for radiant heating, pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer to and from tools or chambers and other transfer tools connected or interfaced with a particular system, and / or wafer transfer to and from load locks. More specifically, such a controller may be configured to control, among other systems, one or more movement mechanisms that may be actuated to cause relative movement between the pedestal base and one or more wafer centering features, as described above. For example, such a controller may be communicatively coupled to one or more actuators, motors, or other motion-inducing components of the one or more movement mechanisms and cause such components to effect such movement by sending control signals.

[0131] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxides, surfaces, circuits, and / or wafer dies.

[0132] In some embodiments, the controller may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the “cloud” or all or part of a fab host computer system. This allows for remote access of wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, configure processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, for example, by having one or more individual controllers networked together and working together toward a common purpose (such as the processes and controls described herein). An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber in communication with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0133] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0134] As noted above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0135] The use of ordinal markers, e.g., (a), (b), (c)... or (1), (2), (3),..., etc., in this disclosure and claims, when present, should be understood as not conveying a particular order or sequence (except to the extent such order or sequence is explicitly indicated). For example, where there are three steps labeled (i), (ii), and (iii), it should be understood that these steps may be performed in any order (or simultaneously, unless contraindicated) unless otherwise indicated. For example, if step (ii) involves handling an element formed in step (i), step (ii) can be considered to occur at some point after step (i). Similarly, if step (i) involves handling an element formed in step (ii), the reverse should be understood. It should also be understood that the use of the ordinal marker "first" herein, e.g., "first item," should not be construed as suggesting, implicitly or inherently, that a "second" instance, e.g., "second item," is necessarily present.

[0136] As used herein, phrases such as "for each <item> of one or more <items>," "for each <item> of one or more <items>," and the like, should be understood to include both single and multiple items; i.e., the phrase "for each..." is understood to be used in the sense that it is used in programming languages ​​to refer to each item in a referenced population of items. For example, if the referenced population of items is a single item, "each" refers only to that single item (despite the fact that dictionary definitions of "each" often define the term to refer to "one of two or more things") and does not imply that there must be at least two of those items. Similarly, the terms "set" or "subset" should not, in and of themselves, be considered to necessarily encompass multiple items; it will be understood that a set or subset can encompass only one member or multiple members (unless the context dictates otherwise).

[0137] For purposes of this disclosure, the term "fluidically connected" is used in reference to volumes, plenums, holes, etc. that may be connected to one another directly or through one or more intervening components or volumes to form a fluid connection, similar to the way the term "electrically connected" is used in reference to components that are connected to one another to form an electrical connection. The term "fluidically interposed," when used, may refer to a component, volume, plenum, or hole that is fluidly connected to at least two other components, volumes, plenums, or holes, such that fluid flowing from one of those other components, volumes, plenums, or holes to the other or another of those components, volumes, plenums, or holes first flows through the "fluidically interposed" component before reaching the other or another of those components, volumes, plenums, or holes. For example, if a pump is fluidly interposed between a reservoir and an outlet, fluid flowing from the reservoir to the outlet first flows through the pump before reaching the outlet. The term "fluidically adjacent," when used, refers to placing a fluid element relative to another fluid element such that there are no potential fluidically interposed structures between the two elements that could potentially impede fluid flow between the two elements. For example, in a flow path having a first valve, a second valve, and a third valve arranged in sequence, the first valve is fluidly adjacent to the second valve, the second valve is fluidly adjacent to both the first valve and the third valve, and the third valve is fluidly adjacent to the second valve.

[0138] The term "between," as used herein, and when used in relation to a range of values, should be understood to include the beginning and ending values ​​of the range, unless otherwise indicated. For example, between 1 and 5 should be understood to include the numbers 1, 2, 3, 4, and 5, not just the numbers 2, 3, and 4.

[0139] The term "operably connected" should be understood to refer to two components and / or systems being directly or indirectly connected, e.g., at least one component or system being able to control the other. For example, a controller may be described as operably connected with a resistive heating unit, including the controller being connected to a sub-controller of the resistive heating unit that is electrically connected to a relay configured to controllably connect or disconnect the resistive heating unit from a power source, the power source being capable of providing an amount of power to the resistive heating unit to generate a desired degree of heating. While the controller itself likely cannot directly provide such power to the resistive heating unit due to the currents involved, the controller is still understood to be operably connected with the resistive heating unit.

[0140] It will be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes thereto will be suggested to those skilled in the art. Various details have been omitted for clarity, but various design alternatives can be implemented. Therefore, the examples should be considered illustrative rather than restrictive, and the disclosure should not be limited to the details provided herein, but may be modified within the scope of the disclosure.

[0141] While the above disclosure has focused on several specific exemplary embodiments, it should be understood that it is not limited to only the described examples, but may also apply to similar modifications and features, and such similar modifications and features are also considered to be within the scope of the present disclosure.

Claims

1. 1. A semiconductor processing tool comprising:

1. A semiconductor processing tool for processing a semiconductor wafer having a diameter D and a thickness T, comprising: a semiconductor processing chamber having a plurality of surfaces defining an interior volume thereof; a pedestal base configured to support a semiconductor wafer during wafer processing operations, the pedestal base being located within the interior volume and including one or more wafer support features configured to support the semiconductor wafer when the semiconductor wafer is placed on the pedestal base, the one or more wafer support features defining a first reference plane that coincides with a bottom surface of the semiconductor wafer when the semiconductor wafer is supported by the one or more wafer support features; a showerhead having a first surface with a plurality of gas distribution ports distributed thereon, the first surface facing the pedestal base and positioned above the pedestal base; one or more wafer centering features collectively having one or more radially inward-facing wafer centering surfaces positioned radially outward from or circumscribing a reference circle having a diameter greater than or equal to D; one or more movement mechanisms, the one or more movement mechanisms including at least a first movement mechanism configured to laterally move the pedestal base or the one or more wafer centering features, the first movement mechanism enabling the one or more wafer centering features to adjust the position of the semiconductor wafer relative to the pedestal base while the semiconductor wafer is supported by the pedestal base; a controller configured to control at least the first movement mechanism to move either the pedestal base or the one or more wafer centering features relative to the other of the pedestal base or the one or more wafer centering features; 1. A semiconductor processing tool comprising:

2. 10. The semiconductor processing tool of claim 1, the one or more wafer centering features are spatially fixed relative to the showerhead, and at least a portion or portions of the one or more radially inwardly facing surfaces are at a lower elevation than the first surface.

3. 3. The semiconductor processing tool of claim 2, The one or more wafer centering features project downwardly from the showerhead toward the pedestal base.

4. 10. The semiconductor processing tool of claim 1, The one or more wafer centering features are spatially fixed relative to the semiconductor processing chamber and extend downwardly into a through opening in the showerhead.

5. 5. The semiconductor processing tool of claim 4, both the showerhead and the pedestal base are configured to be movable relative to the semiconductor processing chamber along an axis perpendicular to the first reference plane; the showerhead is configured to be movable between a first configuration and a second configuration relative to the semiconductor processing chamber; a first end of the one or more wafer centering features extends beyond the first surface of the showerhead toward the pedestal base when the showerhead is in the first configuration; the first ends of the one or more wafer centering features do not extend beyond the first surface of the showerhead when the showerhead is in the second configuration; the pedestal base is configured to be movable relative to the semiconductor processing chamber between a third configuration and a fourth configuration; the first reference surface is within a distance T from the first ends of the one or more wafer centering features when the pedestal base is in the third configuration; the first reference surface is spaced from the first end of the one or more wafer centering features by more than the distance T when the pedestal base is in the fourth configuration; Semiconductor processing tools.

6. 10. The semiconductor processing tool of claim 1, the one or more wafer centering features extend downwardly into a through opening in the showerhead; the semiconductor processing tool further includes one or more actuators configured to be movable between a first position and a second position; the one or more wafer centering features are connected, directly or indirectly, to the one or more actuators, such that the one or more wafer centering features move along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position; the one or more wafer centering features protrude beyond the first surface of the showerhead when the one or more actuators are in the first position; the one or more wafer centering features are on the first surface of the showerhead when the one or more actuators are in the second position. Semiconductor processing tools.

7. 10. The semiconductor processing tool of claim 1, The one or more wafer centering features are spatially fixed relative to the semiconductor processing chamber and extend upwardly into a through opening in the pedestal base.

8. 8. The semiconductor processing tool of claim 7, the first translation mechanism is configured to translate the pedestal base laterally relative to the one or more wafer centering features and along an axis perpendicular to the first reference plane; the first transfer mechanism is further configured to move the pedestal base between a first configuration and a second configuration relative to the semiconductor processing chamber; the first ends of the one or more wafer centering features extend beyond the first reference plane when the pedestal base is in the first configuration; the first ends of the one or more wafer centering features do not extend beyond the first reference plane when the pedestal base is in the second configuration; Semiconductor processing tools.

9. 10. The semiconductor processing tool of claim 1, the one or more wafer centering features extend upwardly into through openings in the pedestal base; the semiconductor processing tool further includes one or more actuators configured to be movable between a first position and a second position; the one or more wafer centering features are directly or indirectly connected to the one or more actuators, such that the one or more wafer centering features move relative to the semiconductor processing chamber along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position; the one or more wafer centering features protrude beyond the first reference plane when the one or more actuators are in the first position; the one or more wafer centering features are below the first reference plane when the one or more actuators are in the second position. Semiconductor processing tools.

10. 10. The semiconductor processing tool of claim 1, the one or more wafer centering features include an annular wall element surrounding the showerhead; the semiconductor processing tool further includes one or more actuators configured to be movable between a first position and a second position; the annular wall element is connected, directly or indirectly, to the one or more actuators, such that the annular wall element moves along an axis perpendicular to the first reference plane when the one or more actuators are moved between the first position and the second position; the annular wall element protrudes beyond the first surface when the one or more actuators are in the first position; the annular wall element is at a higher position when the one or more actuators are in the second position than when the one or more actuators are in the first position; Semiconductor processing tools.

11. A semiconductor processing tool according to any one of claims 1 to 10, comprising: The semiconductor processing tool, wherein the first movement mechanism is configured to move the pedestal base at least laterally relative to the semiconductor processing chamber and the showerhead.

12. A semiconductor processing tool according to any one of claims 1 to 3, comprising: The semiconductor processing tool, wherein the first movement mechanism is configured to move the showerhead at least laterally relative to the semiconductor processing chamber and the pedestal base.

13. A semiconductor processing tool according to any one of claims 1 to 10, comprising: The semiconductor processing tool, wherein the one or more wafer centering features are cylindrical posts.

14. A semiconductor processing tool according to any one of claims 1 to 10, comprising:

10. A semiconductor processing tool, wherein the one or more radially inwardly facing wafer centering surfaces are provided by an axisymmetric wall surface having an inner diameter greater than D.

15. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the one or more radially inwardly facing wafer centering surfaces are a plurality of arcuate surfaces; Each arcuate surface has a radius greater than one-half of D; all of said arcuate surfaces have the same radius and share a common center point; Semiconductor processing tools.

16. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the one or more radially inwardly facing wafer centering surfaces are a plurality of radially inwardly facing centering surfaces; the radially inwardly facing centering surface circumscribing the reference circle; Semiconductor processing tools.

17. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the first movement mechanism is a hexapod mechanism, The base mount and a movable mount supporting the pedestal base and one of the one or more wafer centering features, the first movement mechanism being configured to move; six linear actuators, each connected at one end to the base mount and at the other end to the movable mount, the hexapod mechanism configured to move the movable mount at least laterally relative to the base mount through actuation of the linear actuators in response to one or more control signals provided by the controller; 1. A semiconductor processing tool, the semiconductor processing tool being a hexapod mechanism including:

18. A semiconductor processing tool according to any one of claims 1 to 10, comprising: The first moving mechanism includes: a first linear translation mechanism configured to translate the pedestal base and one of the one or more wafer centering features along a first lateral axis along which the first translation mechanism is configured to move in response to one or more control signals provided by the controller; a second linear translation mechanism configured to translate the pedestal base and one of the one or more wafer centering features along a second lateral axis along which the first translation mechanism is configured to move in response to the one or more control signals provided by the controller, wherein the first lateral axis and the second lateral axis are not parallel to one another; 1. A semiconductor processing tool comprising an XY translation stage having:

19. 20. The semiconductor processing tool of claim 18, The first horizontal axis is orthogonal to the second horizontal axis.

20. A semiconductor processing tool according to any one of claims 1 to 10, comprising: The first moving mechanism includes: a rotary actuator having a base portion and a rotatable portion; a linear translation mechanism having a first portion and a second portion; an R-theta mechanism having the rotational actuator is configured to rotate the rotatable portion relative to the base portion about a rotation axis in response to one or more control signals provided by the controller; the linear translation mechanism is configured to translate the second portion relative to the first portion along a radial axis in response to the one or more control signals provided by the controller; the second portion of the linear translation mechanism supports the pedestal base and one of the one or more wafer centering features that the first movement mechanism is configured to move; the rotatable portion of the rotary actuator supports the first portion of the linear translation mechanism; the radial axis is perpendicular to an axis parallel to the rotation axis; Semiconductor processing tools.

21. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the controller is further configured to control the one or more movement mechanisms to transition the pedestal base and the one or more wafer centering features between at least a first relative configuration and a second relative configuration, wherein at least a portion of at least one of the one or more wafer centering features is between the first reference surface and a second reference surface that is parallel to the first reference surface and positioned a distance T above the first reference surface in the first relative configuration, and is not between the first reference surface and the second reference surface in the second relative configuration.

22. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the controller is further configured to control the first movement mechanism such that the pedestal base performs one or more circular orbits having one or more diameters less than or equal to the diameter of the reference circle minus D.

23. 23. The semiconductor processing tool of claim 22, the controller is further configured to control the first movement mechanism such that the pedestal base performs a plurality of circular orbits, each having an increasingly larger diameter less than or equal to the diameter of the reference circle minus D.

24. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the controller is further configured to control the first movement mechanism such that the pedestal base follows a path that spirals outward from a center point, and then follows an arcuate or circular path having a diameter equal to the diameter of the reference circle minus D.

25. A semiconductor processing tool according to any one of claims 1 to 10, comprising: the controller is further configured to control the first movement mechanism to move the pedestal base along a plurality of paths radiating outward from a central region to a plurality of locations along the one or more radially inward-facing wafer centering surfaces.

Images