Integrated circuit bumps integrated with T-coils

Abstract

An integrated circuit (IC) comprising: an IC bump (510); and a T-coil (550) disposed directly below the IC bump (510), the T-coil (550) being electrically coupled to the IC bump (510) through a metallized via hole (580).

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This patent application claims priority to pending U.S. Non-Provisional Patent Application No. 18 / 081,589, filed December 14, 2022, assigned to the assignee of this patent application, and expressly incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to integrated circuits, and more particularly to integrated circuit (IC) bumps (e.g., solder balls) integrated with T-coils to improve area efficiency and signal transmission / reception performance. [Background technology]

[0003] Data communication links, such as double data rate (DDR) and serializer / deserializer (SERDES) links, are used to communicate data signals between integrated circuits (ICs) and other components. Often, data communication links include a set of parallel transmission lines, some of which may be differential, pseudo-differential, or single-ended. It is important to compensate the transmission lines to improve data rates and signal integrity. Summary of the Invention

[0004] SUMMARY OF THE INVENTION The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005] Certain aspects of the present disclosure relate to an integrated circuit (IC) that includes an IC bump and a T-coil disposed directly below the IC bump and electrically coupled to the IC bump through a metallized via hole.

[0006] Another aspect of the present disclosure relates to a data communication system including: a printed circuit board (PCB) including a set of transmission lines; a first integrated circuit (IC) mounted on the PCB, the first integrated circuit (IC) including a first set of IC interface circuits, the first IC including a first set of IC bumps each electrically coupled to the set of transmission lines; and a first set of T-coils, each T-coil of the first set being positioned directly below a respective IC bump of the first set of IC bumps, the T-coils of the first set being each electrically coupled to the first set of IC bumps through a first set of metallized via holes.

[0007] Another aspect of the present disclosure relates to a wireless communication device including: an integrated circuit (IC) including at least one antenna, a transceiver coupled to the at least one antenna, and one or more signal processing cores, the IC including a set of IC interface circuits, the IC including: a set of IC bumps electrically coupled to a set of transmission lines that respectively electrically couple the IC to the transceiver; and a set of T-coils, each T-coil of the set being disposed directly below a respective IC bump of the set of IC bumps, the set of T-coils being respectively electrically coupled to the set of IC bumps through a set of metallized via holes.

[0008] Another aspect of the present disclosure relates to an integrated circuit (IC) that includes a set of differential IC bumps and a set of differential T-coils disposed at least partially beneath the set of differential IC bumps and electrically coupled to the set of differential IC bumps, respectively, through a set of metallized via holes.

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief explanation of the drawings]

[0010] [Figure 1] 1 illustrates a block diagram of an exemplary data communication system according to one aspect of the present disclosure. [Figure 2] 1 shows a block / schematic diagram of an exemplary integrated circuit (IC) interface circuit according to another aspect of the present disclosure. [Figure 3] 1 shows a block / schematic diagram of another exemplary integrated circuit (IC) interface circuit according to another aspect of the present disclosure. [Figure 4] 1 illustrates an exemplary bump and T-coil layout diagram of an integrated circuit (IC) interface circuit according to another embodiment of the present disclosure. [Figure 5A] 1 illustrates a layout diagram of an exemplary integrated circuit (IC) interface circuit including an integrated bump / T-coil according to another embodiment of the present disclosure. [Figure 5B] 1 illustrates a cross-sectional view of an exemplary integrated circuit (IC) interface circuit including an integrated bump / T-coil according to another embodiment of the present disclosure. [Figure 6A] 10 shows a layout diagram of another exemplary integrated circuit (IC) interface circuit including an integrated bump / T-coil according to another embodiment of the present disclosure. [Figure 6B] 1 illustrates a cross-sectional view of another exemplary integrated circuit (IC) interface circuit including an integrated bump / T-coil, according to another embodiment of the present disclosure. [Figure 7A]1 illustrates a layout diagram of another exemplary integrated circuit (IC) interface circuit including an exemplary integrated differential bump / T-coil according to another aspect of the present disclosure. [Figure 7B] 1 illustrates a cross-sectional view of another exemplary integrated circuit (IC) interface circuit including an exemplary integrated differential bump / T-coil according to another embodiment of the present disclosure. [Figure 8A] 10 shows a layout diagram of another exemplary integrated circuit (IC) interface circuit including another exemplary integrated differential bump / T-coil according to another embodiment of the present disclosure. [Figure 8B] 1 illustrates a cross-sectional view of another exemplary integrated circuit (IC) interface circuit including another exemplary integrated differential bump / T-coil according to another embodiment of the present disclosure. [Figure 9] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The Detailed Description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] 1 illustrates a block diagram of an exemplary data communication system 100 according to one aspect of the present disclosure. The data communication system 100 may be a serializer-deserializer (SerDes) communication link or a double data rate (DDR) link. The data communication system 100 includes a first integrated circuit (IC) 110 and a second IC 130, both of which may be mounted on a printed circuit board (PCB) 120. The PCB 120 includes a set of differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N-data / clock signals that couple the first IC 110 to the second IC 130.

[0013] The first IC 110 includes a set of transmitters Tx1 to TxN and a set of differential T coils T1+ / T1- to TN+ / TN- respectively coupled to the differential outputs + / - of the set of transmitters Tx1 to TxN. The first IC 110 further includes a set of differential electrostatic discharge (ESD) circuits, such as ESD T1+ / ESD T1- to ESD TN+ / ESD TN- respectively coupled to the set of differential T coils T1+ / T1- to TN+ / TN-. The set of differential T coils T1+ / T1- to TN+ / TN- are respectively coupled to a set of differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N- via a set of differential IC bumps (e.g., solder balls) 112-1+ / 112-1- to 112-N+ / 112-N-.

[0014] The second IC 130 includes a set of receivers Rx1 to RxN and a set of differential T-coils R1+ / R1- to RN+ / RN- respectively coupled to the differential inputs + / - of the set of receivers Rx1 to RxN. The second IC 130 further includes a set of ESD circuits, such as ESD R1+ / R1- to ESD RN+ / RN- respectively coupled to the set of differential T-coils R1+ / R1- to RN+ / RN-. The set of differential T-coils R1+ / R1- to RN+ / RN- are respectively coupled to the set of differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N- via sets of differential IC bumps (e.g., solder balls) 132-1+ / 132-1- to 132-N+ / 132-N-.

[0015] In operation, the set of transmitters Tx1 through TxN of the first IC 110 may generate a set of N−1 data signals and associated clock signals, which may be transmitted via the set of differential T-coils T1+ / T1− through TN+ / TN−, the set of differential IC bumps 112-1+ / 112-1− through 112-N+ / 112-N−, and the set of differential transmission lines 122-1+ / 122-1− through 122-N+ / 122-N− to the second IC 130. The set of receivers Rx1 through RxN of the IC 130 may receive the set of N−1 data signals and associated clock signals via the set of differential IC bumps 132-1+ / 132-1− through 132-N+ / 132− and the set of differential T-coils R1+ / R1− through RN+ / RN−, respectively.

[0016] The set of ESD circuits ESD T1+ / T1- to ESD TN+ / TN- protects the transmitters Tx1 to TxN from electrostatic discharges that may occur from the sets of differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N-, respectively. Similarly, the set of ESD circuits ESD R1+ / R1- to ESD RN+ / RN- protects the receivers Rx1 to RxN from electrostatic discharges that may occur from the sets of differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N-, respectively.

[0017] Although data communication system 100 has been described as being unidirectional, i.e., a set of N-1 data signals and an associated clock signal are transmitted from first IC 110 to second IC 130, it should be understood that data communication system 100 may be implemented for bidirectional data signal and clock transmission. In such cases, the set of transmitters Tx1 through TxN and the set of receivers Rx1 through RxN may each be implemented as a set of transceivers. Furthermore, although data communication system 100 has been described as communicating data and clock signals over a set of differential transmission lines 122-1+ / 122-1- through 122-N+ / 122-N-, it should be understood that data communication system 100 may employ single-ended or pseudo-differential transmission lines for such data and clock signal transmission.

[0018] 2 illustrates a block / schematic diagram of an exemplary integrated circuit (IC) interface circuit 200 according to another aspect of the present disclosure. The IC interface circuit 200 may be a more detailed exemplary implementation of a circuit that interfaces the first IC 110 or the second IC 130 to one of the differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N- of the data communication system 100.

[0019] The IC interface circuit 200 includes differential IC bumps (e.g., solder balls) bump_p / bump_n (e.g., for receiving differential signals inp / inn input via differential transmission lines), differential T-coils 210+ / 210-, differential electrostatic discharge (ESD) circuits 220+ / 220-1, and a transmitter (Tx), receiver (Rx), or transceiver (Tx / Rx) 230 (for simplicity, referred to herein as transceiver (Tx / Rx) 230).

[0020] On the other hand, the positive differential T-coil 210+ is connected to a first inductor L that is magnetically coupled together by a mutual inductance coefficient “k”. 1+ and the second inductor L 2+ The first inductor L 1+ and the second inductor L 2+ is coupled in series between a first node n1+ and a second node n2+. The first node n1+ is coupled to the positive differential IC bump_p, and the second node n2+ is coupled to the positive differential port (+) of the transceiver (Tx / Rx) 230. The first inductor L 1+ and the second inductor L 2+ A third node n3+ between Vdd and Vdd is coupled to a positive differential ESD circuit 220+. The positive differential ESD circuit 220+ includes a first reverse-biased diode D 1+ and a second reverse-biased diode D 2+ and a first diode D 1+ and the second diode D 2+The node between is coincident with or coupled to the third node n3+ of the positive differential T-coil 210+.

[0021] On the other hand, the negative differential T-coil 210- is connected to a first inductor L that is magnetically coupled together by substantially the same mutual inductance coefficient "k". 1- and the second inductor L 2- The first inductor L 1- and the second inductor L 2- is coupled in series between a first node n1- and a second node n2-. The first node n1- is coupled to a negative differential IC bump bump_n, and the second node n2- is coupled to the negative differential port (-) of the transceiver (Tx / Rx) 230. The first inductor L 1- and the second inductor L 2- A third node n3− between the upper and lower voltage rails Vdd and Vdd is coupled to a negative differential ESD circuit 220−. The negative differential ESD circuit 220− includes a first reverse-biased diode D 1- and a second reverse-biased diode D 2- and a first diode D 1- and the second diode D 2- The node between is coincident with or coupled to the third node n3- of the negative differential T-coil 210-.

[0022] The differential T-coils 210+ / 210- are connected to the diodes D 1+ / D 2+ and D 1- / D 2- The differential T-coils 210+ / 210- also compensate for the parasitic capacitance associated with the differential ports (+ / -) of the transceiver (Tx / Rx) 230. The compensation provided by the differential T-coils 210+ / 210- improves the transmission of data / clock signals, thereby achieving higher data rates (bandwidth) and / or improved signal integrity.

[0023] 3 illustrates a block / schematic diagram of another exemplary integrated circuit (IC) interface circuit 300 according to another aspect of the present disclosure. The IC interface circuit 300 may be a more detailed exemplary implementation of a circuit that interfaces the first IC 110 or the second IC 130 to one of the differential transmission lines 122-1+ / 122-1- to 122-N+ / 122-N- of the data communication system 100. The IC interface circuit 300 is a variation of the IC interface circuit 200 described above.

[0024] In particular, the IC interface circuit 300 includes differential IC bumps (e.g., solder balls) bump_p / bump_n (e.g., for receiving differential signals inp / inn input via differential transmission lines), differential T-coils 310+ / 310-1, differential electrostatic discharge (ESD) circuits 320+ / 320-, and a transmitter (Tx), receiver (Rx), or transceiver (Tx / Rx) 330 (for brevity, referred to herein as transceiver (Tx / Rx) 330).

[0025] On the other hand, the positive differential T-coil 310+ is connected to a first inductor L that is magnetically coupled together by a mutual inductance coefficient “k”. 1+ and the second inductor L 2+ The first inductor L 1+ and the second inductor L 2+ are coupled in series between a first node n1+ and a second node n2+. The first node n1+ is coupled to the positive differential IC bump_p, and the second node n2+ is coupled to the positive differential ESD circuit 320+. The first inductor L 1+ and the second inductor L 2+ A third node n3+ between Vdd and Vdd is coupled to the positive differential port (+) of the transceiver (Tx / Rx) 330. The positive differential ESD circuit 320+ includes a first reverse-biased diode D coupled in series between the upper voltage rail Vdd and a lower voltage rail (e.g., ground). 1+ and a second reverse-biased diode D 2+ and a first diode D 1+ and the second diode D2+ The node between is coincident with or coupled to the second node n2+ of the positive differential T-coil 310+.

[0026] On the other hand, the negative differential T-coil 310- is connected to a first inductor L that is magnetically coupled together by substantially the same mutual inductance coefficient "k". 1- and the second inductor L 2- The first inductor L 1- and the second inductor L 2- are coupled in series between a first node n1- and a second node n2-. The first node n1- is coupled to the negative differential IC bump_p, and the second node n2- is coupled to the negative differential ESD circuit 320-. The first inductor L 1- and the second inductor L 2- A third node n3- between Vdd and Vdd is coupled to the negative differential port (-) of the transceiver (Tx / Rx) 330. The negative differential ESD circuit 320- includes a first reverse-biased diode D coupled in series between the upper and lower voltage rails Vdd and Vdd. 1- and a second reverse-biased diode D 2- and a first diode D 1- and the second diode D 2- The node between is coincident with or coupled to the second node n2- of the negative differential T-coil 310-.

[0027] Similar to the T-coils 210+ / 210− of the IC interface circuit 200, the differential T-coils 310+ / 310− are connected to the diodes D 1+ / D 2+ and D 1- / D 2-The differential T-coils 310+ / 310− also compensate for the parasitic capacitance associated with the differential ports (+ / −) of the transceiver (Tx / Rx) 330. The compensation provided by the differential T-coils 310+ / 310− improves the transmission of data / clock signals, thereby achieving higher data rates (bandwidth) and improved signal integrity.

[0028] 4 illustrates a layout diagram of an exemplary bump (e.g., solder ball) 410 and T-coil 450 of an integrated circuit (IC) interface circuit 400 according to another embodiment of the present disclosure. The IC bump 410 includes an underbump metallization (UBM) 415, a dielectric or passivation layer 420 concentrically disposed around the UBM 415, and a lower metallization layer 425 concentrically disposed below and electrically coupled to the UBM 415. The metallization layer 425 may be an aluminum bond pad (AP) layer, which is often the top metal layer of an IC. The IC interface circuit 400 further includes a metal interconnect 430 that electrically couples the UBM 415 and AP layer 425 to the T-coil 450.

[0029] The metal interconnect 430 couples to node n1 of the T-coil 450. The T-coil 450 includes a first inductor winding 455 extending from node n1 to a metallized via hole v1 on a particular metal layer (e.g., a metal layer immediately below the AP layer 425, such as metal layer M14). The T-coil 450 further includes a second inductor winding 460 extending from the metallized via hole v1 to a node n2 on another particular metal layer (e.g., a metal layer immediately below the metal layer on which the first inductor winding 455 is formed, such as metal layer M13). The first inductor winding 455 and the second inductor winding 460 may be wound in the same direction (e.g., clockwise in this example) so that they are coupled to each other. A leadout interconnect 465 to node n3 may be electrically attached to either the first inductor winding 455 or the second inductor winding 460. As previously mentioned, a transceiver, transmitter, or receiver may be coupled to either node n2 or n3, and an ESD circuit may be coupled to node n3 or n2, respectively.

[0030] Note that in IC interface circuit 400, IC bump 410 is separated from T-coil 450. For example, IC bump 410 is laterally displaced from T-coil 450, as shown in FIG. 4 . The separation between IC bump 410 and T-coil 450 requires a significant IC footprint to implement. This IC footprint is larger when there are many bump / T-coil pairs, such as in the case of data communication system 100 having many (N) parallel data lanes. For example, if data communication system 100 has N=16, there may be 64 bump / T-coil pairs, which is substantial in terms of IC footprint.

[0031] Furthermore, IC bump 410 is coupled to T-coil 450 via metal interconnect 430. Such metal interconnect 430 generally introduces undesirable parasitics that degrade bandwidth and data transmission / reception performance. Furthermore, due to high-density IC cell placement, it may be difficult to place IC bump-T-coil pairs substantially identically for each differential line and data lane, which may have the adverse effect of causing signal mismatch between differential lines of the same or different data lanes.

[0032] 5A and 5B show a layout diagram and a cross-sectional view of an exemplary integrated circuit (IC) interface circuit 500 including an integrated bump and a T-coil according to another embodiment of the present disclosure. In particular, the IC interface circuit 500 includes an IC bump (e.g., a solder ball) 510 and a T-coil 550 disposed directly below the IC bump 510. Additionally, as described in more detail herein, the IC bump 510 is electrically coupled to the T-coil 550 through a metallized via hole.

[0033] The feature of locating the T-coil 550 directly beneath the IC bump 510 within the IC utilizes the IC area or footprint in a more efficient manner than the separate IC bump 410 and T-coil 450 of the IC interface circuit 400. The feature of electrically coupling the IC bump 510 to the T-coil 550 through a metallized via hole (which is significantly shorter than the metal interconnect 430 of the IC interface circuit 400) reduces parasitics and enables improved signal transmission performance. Furthermore, because the integrated IC bump 510 and T-coil 550 have a smaller impact on the IC footprint, the IC interface circuit 500 can be replicated for multiple data lanes with reduced deformation, resulting in well-matched signal matching between differential signal transmissions for the data lanes or between sets of data lanes.

[0034] With regard to details of the IC interface circuit 500, the IC bump 510 includes an underbump metallization (UBM) 515, a dielectric or passivation layer 520 concentrically disposed around the UBM 515, and a lower metallization layer 525 concentrically disposed below and electrically coupled to the UBM 515. The metallization layer 525 may be an aluminum bond pad (AP) layer, which is often the top metal layer of an IC. The IC interface circuit 500 further includes a metallized via 580 disposed directly below and electrically coupled to the AP layer 525. Thus, the UBM 515 is electrically coupled to the T-coil 550 through the AP layer 525 and the metallized via 580.

[0035] The metallized via hole 580 may be the input node n1 of the T-coil 550. The T-coil 550 includes a first inductor winding 555 extending from node n1 (the metallized via hole 580) to another metallized via hole v1 on a particular metal layer (e.g., a metal layer directly below the AP layer 525, such as metal layer M N (where N is an integer) (e.g., metal layer M14)). The first inductor winding 555 forms a first inductor L1 of the T-coil 550. The first inductor winding 555 is disposed directly below the UBM 515 and the AP layer 525. A first dielectric layer 565, through which the metallized via hole 580 extends, separates the first inductor winding 555 from the AP layer 525.

[0036] The T-coil 550 further includes a second inductor winding 560 extending from the metallized via hole v1 to a node n2 on another particular metal layer (e.g., a metal layer immediately below the metal layer on which the first inductor winding 555 is formed, such as metal layer M(N-1) (e.g., metal layer M13)). The second inductor winding 560 forms a second inductor L2 of the T-coil 550. A second dielectric layer 570, through which the metallized via hole v1 extends, separates the second inductor winding 560 from the first inductor winding 555.

[0037] The first inductor winding 555 and the second inductor winding 560 may be wound in the same direction (e.g., clockwise when viewed from above in this example) so that they are coupled to each other. A leadout interconnect 585 for forming node n3 may be electrically coupled to either the first inductor winding 555 or the second inductor winding 560, but in this example, the leadout interconnect 585 is disposed on another metal layer (e.g., metal layer M(N-2) (e.g., metal layer M12)) and is electrically coupled to the second inductor winding 560 through a third metallized via hole that penetrates the third dielectric layer 575.

[0038] As previously mentioned, a transceiver, transmitter, or receiver may be coupled to either node n2 or n3, and an ESD circuit may be coupled to node n3 or n2, respectively. In this example, T-coil 550 includes two inductor windings 555 and 560 formed on different metal layers M and M(N-1), although it should be understood that T-coil 550 may include three or more inductor windings, each formed on three or more metal layers. Alternatively, as described in more detail below, T-coil 550 may be formed as a single inductor winding on a single metal layer, with a first portion or half of the inductor winding functioning as a first inductor L1, a second portion or half of the inductor winding functioning as a second inductor L2, and the node between the two inductor portions functioning as node n3 for electrical connection to an ESD circuit or transceiver, transmitter, or receiver.

[0039] 6A and 6B show a layout diagram and a cross-sectional view of an exemplary integrated circuit (IC) interface circuit 600 including an integrated bump and a T-coil according to another embodiment of the present disclosure. The IC interface circuit 600 is a variation of the IC interface circuit 500 in which the inductors L1 and L2 of the T-coil are formed as a single inductor winding on a single metal layer. In particular, the IC interface circuit 600 includes an IC bump (e.g., a solder ball) 610 and a T-coil 650 disposed directly below the IC bump 610. Additionally, as described in more detail herein, the IC bump 610 is electrically coupled to the T-coil 650 through a metallized via hole 660.

[0040] More specifically, the IC bump 610 includes an underbump metallization (UBM) 615, a dielectric or passivation layer 620 concentrically disposed around the UBM 615, and a lower metallization layer 625 concentrically disposed below and electrically coupled to the UBM 615. The metallization layer 625 may be an aluminum bond pad (AP) layer, which is often the top metal layer of an IC. As described, the IC interface circuit 600 further includes a metallized via 660 disposed directly below and electrically coupled to the AP layer 625 and the T-coil 650. Thus, the UBM 615 is electrically coupled to the T-coil 650 through the AP layer 625 and the metallized via 660.

[0041] The metallized via hole 660 may be the input node n1 of the T-coil 650. The T-coil 650 includes an inductor winding 655 extending from node n1 to node n2 on a particular metal layer (e.g., a metal layer directly below the AP layer 625, such as metal layer M N (where N is an integer) (e.g., metal layer M14)). A first leadout interconnect 670 to node n3 may be electrically coupled to a central region of the inductor winding 655. The inductor winding 655 is disposed directly below the UBM 615 and the AP layer 625. A dielectric layer 665, through which the metallized via hole 660 extends, separates the inductor winding 655 from the AP layer 625.

[0042] A first portion of the inductor winding 655 extending from node n1 to node n3 may form a first inductor L1 of the T-coil 650. A second portion of the inductor winding 655 extending from node n3 to node n2 may form a second inductor L2 of the T-coil 650. The T-coil 650 may include a second leadout interconnect 675 for coupling node n2 to another circuit through a metallized via hole and a different metal layer. For example, as previously described, a transceiver, transmitter, or receiver may be coupled to either node n2 or n3, and an ESD circuit may be coupled to node n3 or n2, respectively.

[0043] 7A and 7B show a layout diagram and a cross-sectional view of another example integrated circuit (IC) interface circuit 700 including example integrated differential bumps 710+ / 710− and T-coils 720+ / 720− according to another embodiment of the present disclosure. Differential bumps 710+ / 710− may each be implemented for each of the aforementioned bumps 510 or 610. Similarly, differential T-coils 720+ / 720− may each be implemented for each of the aforementioned T-coils 550 or 650. Integrated bumps 710+ / T-coils 720+ may handle the positive component of the differential signal, and integrated bumps 710− / T-coils 720− may handle the negative component of the differential signal.

[0044] In the exemplary IC interface circuit 700, the differential bumps 710+ / 710- are centered along the bump pitch axis, and the differential T-coils 720+ / 710- are also located along the bump pitch axis. In other words, the differential T-coils 720+ / 710- are located along a T-coil pitch axis that is coaxial with the bump pitch axis. Furthermore, the T-coils 720+ and 720- are partially underneath the bumps 710+ and 710-, respectively. Furthermore, the distance between the bumps 710+ and 710- is greater than the distance between the T-coils 720+ and 720- along the bump / T-coil pitch axis.

[0045] 8A and 8B show a layout diagram and a cross-sectional view of another exemplary integrated circuit (IC) interface circuit 800 including another exemplary integrated differential bumps 810+ / 810− and T-coils 820+ / 820− according to another embodiment of the present disclosure. Differential bumps 810+ / 810− may each be implemented for each of the aforementioned bumps 510 or 610. Similarly, differential T-coils 820+ / 820− may each be implemented for each of the aforementioned T-coils 550 or 650. Integrated bumps 810+ / T-coils 820+ may handle the positive component of the differential signal, and integrated bumps 810− / T-coils 820− may handle the negative component of the differential signal.

[0046] In the exemplary IC interface circuit 800, the differential bumps 810+ / 810− are center-to-center along the bump pitch axis. The differential T-coils 820+ / 810− are center-to-center along a T-coil pitch axis that is offset or spaced apart from the bump pitch axis. Similarly, the T-coils 820+ and 820− partially underlie the bumps 810+ and 810−, respectively. Similarly, the distance between the bumps 810+ and 810− along the bump pitch axis is greater than the distance between the T-coils 820+ and 820− along the T-coil pitch axis.

[0047] 9 shows a block diagram of an exemplary wireless communication device 900 according to another aspect of the present disclosure. The wireless communication device 900 may be a smartphone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0048] In particular, wireless communication device 900 includes an integrated circuit (IC) 910, which may be implemented as a system on a chip (SOC). IC 910 includes one or more signal processing cores 920 configured to generate transmit baseband (BB) signals and to process receive baseband (BB) signals. IC 910 further includes a set of interface circuits (ICs) 930-1 through 930-N coupled to a set of transmission lines 942-1 through 940-N of a baseband signal double data rate (DDR) communication link 940 that couples IC 910 to a baseband / radio frequency (BB / RF) transceiver 950. The set of interface circuits (ICs) 930-1 through 930-N may be implemented for each of IC interface circuits 200, 300, 500, 600, 700, and 800 described above.

[0049] The transceiver 950 is coupled to the one or more signal processing cores 920 to receive transmit BB signals from the one or more signal processing cores 920 and provide received BB signals to the one or more signal processing cores 920 via the BB signal DDR communication link 940. The transceiver 950 is configured to convert the transmit BB signals to transmit radio frequency (RF) signals and convert the receive RF signals to receive BB signals. The transceiver 950 is coupled to at least one antenna 960 to provide the transmit RF signals to the at least one antenna for electromagnetic radiation to a wireless medium for wireless transmission and to receive receive RF signals electromagnetically picked up from the wireless medium by the at least one antenna 960.

[0050] The following provides a summary of aspects of the disclosure.

[0051] Aspect 1: An integrated circuit (IC) comprising an IC bump and a T-coil positioned directly below the IC bump, the T-coil being electrically coupled to the IC bump through a first metallized via hole.

[0052] Aspect 2: The IC of aspect 1, wherein the T-coil includes a first inductor winding disposed on a first metal layer.

[0053] Aspect 3: An IC as described in aspect 2, wherein the first inductor winding extends from a first node proximate the first metallized via hole to a second node, and the T-coil further includes a leadout interconnect coupled to the first inductor winding at a third node between the first node and the second node.

[0054] Aspect 4: The IC of aspect 3, further comprising a transceiver, transmitter, or receiver coupled to the second node.

[0055] Aspect 5: The IC of aspect 4, further comprising an electrostatic discharge (ESD) circuit coupled to the third node.

[0056] Aspect 6: The IC of aspect 5, wherein the ESD circuit comprises a first diode and a second diode coupled in series with the first diode between the first voltage rail and the second voltage rail, and a fourth node between the first diode and the second diode is coincident with or coupled to the third node.

[0057] Aspect 7: The IC of aspect 6, wherein the first diode and the second diode are reverse biased.

[0058] Aspect 8: The IC of aspect 3, further comprising a transceiver, transmitter, or receiver coupled to a third node.

[0059] Aspect 9: The IC of aspect 9, further comprising an electrostatic discharge (ESD) circuit coupled to the second node.

[0060] Embodiment 10: An IC according to any one of embodiments 1 to 9, wherein the IC bump includes an under bump metallization (UBM) electrically coupled to the T-coil through a first metallized via.

[0061] Embodiment 11: The IC of embodiment 10, wherein the UBM is disposed on and electrically coupled to the bond pad aluminum (AP) layer.

[0062] Aspect 12: The IC of aspect 11, further comprising a dielectric layer disposed between the AP layer and the T coil, the first metallized via hole extending through the dielectric layer.

[0063] Aspect 13: An IC described in any one of aspects 1 to 12, wherein the T coil comprises a first inductor winding arranged on a first metal layer and a second inductor winding arranged on a second metal layer.

[0064] Aspect 14: The IC of aspect 13, wherein the first inductor winding extends from the first metallized via hole to the second metallized via hole.

[0065] Aspect 15: The IC of aspect 14, wherein the second inductor winding is electrically coupled to the first inductor winding through a second metallized via hole.

[0066] Aspect 16: The IC of aspect 15, further comprising a first dielectric layer disposed between the IC bump and the first inductor winding, the first metallized via hole extending through the first dielectric layer.

[0067] Aspect 17: The IC of aspect 16, further comprising a second dielectric layer disposed between the first inductor winding and the second inductor winding, the second metallized via hole extending through the second dielectric layer.

[0068] Embodiment 18: The IC of any one of embodiments 15 to 17, wherein the second inductor winding extends from the second metallized via hole to the first node.

[0069] Aspect 19: The IC of aspect 18, further comprising a transceiver, transmitter, or receiver coupled to the first node.

[0070] Aspect 20: The IC of aspect 18, further comprising an electrostatic discharge (ESD) circuit coupled to the first node.

[0071] Aspect 21: The IC of aspect 18, further comprising a leadout interconnect coupled between the first inductor winding or the second inductor winding and the second node.

[0072] Example 22: The IC of Example 21, further comprising a transceiver, transmitter, or receiver coupled to the second node.

[0073] Aspect 23: The IC of aspect 21, further comprising an electrostatic discharge (ESD) circuit coupled to the second node.

[0074] Embodiment 24: The IC of embodiment 1, wherein the IC bumps are electrically coupled to transmission lines on a printed circuit board (PCB).

[0075] Aspect 25: The IC of aspect 24, wherein the transmission line comprises a differential transmission line.

[0076] Aspect 26: A data communication system comprising: a printed circuit board (PCB) including a set of transmission lines; and a first integrated circuit (IC) mounted on the PCB, the first integrated circuit (IC) including a first set of IC interface circuits, the first IC comprising: a first set of IC bumps each electrically coupled to the set of transmission lines; and a first set of T-coils, each T-coil of the first set of T-coils positioned directly below a respective IC bump of the first set of IC bumps, and the first set of T-coils each electrically coupled to the first set of IC bumps via a first set of metallized via holes.

[0077] Aspect 27: Further comprising: a second IC mounted on the PCB, the second IC including a second set of IC interface circuitry, the second IC comprising: a second set of IC bumps each electrically coupled to the set of transmission lines; and a second set of T-coils, each T-coil of the second set of T-coils positioned directly below a respective IC bump of the second set of IC bumps, the second set of T-coils each electrically coupled to the second set of IC bumps through a second set of metallized via holes. 27. The data communication system of claim 26.

[0078] Aspect 28: A data communication system as described in aspect 27, wherein a first IC comprises a set of transmitters each coupled to a first set of T-coils and a first set of electrostatic discharge (ESD) circuits each coupled to the first set of T-coils, and a second IC comprises a set of receivers each coupled to a second set of T-coils and a second set of ESD circuits each coupled to the second set of T-coils.

[0079] Aspect 29: A data communication system as described in aspect 27, wherein a first IC comprises a first set of transceivers each coupled to a first set of T-coils and a first set of electrostatic discharge (ESD) circuits each coupled to the first set of T-coils, and a second IC comprises a second set of transceivers each coupled to a second set of T-coils and a second set of ESD circuits each coupled to the second set of T-coils.

[0080] Aspect 30: A wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) including one or more signal processing cores, the integrated circuit (IC) including a set of IC interface circuits, wherein the IC comprises: a set of IC bumps electrically coupled to a set of transmission lines that respectively electrically couple the IC to the transceiver; and a set of T-coils, each T-coil of the set of T-coils being positioned directly below a respective IC bump of the set of IC bumps, and the set of T-coils being respectively electrically coupled to the set of IC bumps via a set of metallized via holes.

[0081] Aspect 31: An integrated circuit (IC) comprising a set of differential IC bumps and a set of differential T-coils positioned at least partially directly below the set of differential IC bumps, the set of differential T-coils being each electrically coupled to the set of differential IC bumps via a set of metallized via holes.

[0082] Aspect 32: An IC as described in aspect 31, wherein the set of differential IC bumps and the set of differential T-coils are positioned substantially along the pitch axis.

[0083] Embodiment 33: An IC as described in embodiment 32, wherein the distance between the sets of differential IC bumps is greater than the distance between the sets of differential T-coils.

[0084] Aspect 34: An IC as described in aspect 31, wherein a set of differential IC bumps is located along a first pitch axis and a set of differential T coils is located along a second pitch axis, the second pitch axis being offset from the first pitch axis.

[0085] Embodiment 35: An IC as described in embodiment 34, wherein the distance between the sets of differential IC bumps along the first pitch axis is greater than the distance between the sets of differential T-coils along the second pitch axis.

[0086] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0087] 100 Data Communication Systems 110 First Integrated Circuit (IC) 112-1 Differential IC bump 120 Printed Circuit Board (PCB) 122-1 Differential transmission line 130 Second IC 132-1 Differential IC bump 200 Integrated Circuit (IC) Interface Circuit 210 Differential T-coil 220 Differential ESD circuit 230 Transmitter / Receiver (Tx / Rx) 300 Integrated Circuit (IC) Interface Circuit 310 Differential T-coil 320 Differential ESD Circuit 330 Transmitter / Receiver (Tx / Rx) 400 Integrated Circuit (IC) Interface Circuit 410 IC bump 415 Under Bump Metallization (UBM) 420 Passivation Layer 425 Metallization Layer 430 Metallic Interconnects 450 T coil 455 First inductor winding 460 Second inductor winding 465 Leadout Interconnect 500 Integrated Circuit (IC) Interface Circuit 510 Integrated IC Bumps 515 Under Bump Metallization (UBM) 520 Passivation Layer 525 Metallization Layer 550 T coil 555 First inductor winding 560 Second inductor winding 565 First Dielectric Layer 570 Second Dielectric Layer 575 Third Dielectric Layer 580 Beer Hall 585 Leadout Interconnect 600 Integrated Circuit (IC) Interface Circuit 610 IC bump 615 Under Bump Metallization (UBM) 620 Passivation Layer 625 Metallization Layer 650 T coil 655 inductor winding 660 Beer Hall 665 Dielectric Layer 670 first lead-out interconnect 675 Second Leadout Interconnect 700 Integrated Circuit (IC) Interface Circuit 710 Integrated Differential Bump 720 Differential T-coil 810 Integrated Differential Bump 820 Differential T-coil 900 Wireless Communication Devices 910 Integrated Circuits (ICs) 920 signal processing core 930-N Interface Circuits (ICs) 940 BB signal DDR communication link 950 Radio Frequency (BB / RF) Transceiver 960 Antenna

Claims

1. IC bumps; a T-coil disposed directly below the IC bump and electrically coupled to the IC bump through a first metallized via hole; An integrated circuit (IC) comprising:

2. 2. The IC of claim 1, wherein the T-coil includes a first inductor winding disposed on a first metal layer.

3. 3. The IC of claim 2, wherein the first inductor winding extends from a first node and a second node proximate the first metallized via hole, and the T-coil further includes a leadout interconnect coupled to the first inductor winding at a third node between the first node and the second node.

4. The IC of claim 3 , further comprising a transceiver, transmitter, or receiver coupled to the second node.

5. The IC of claim 4 further comprising an electrostatic discharge (ESD) circuit coupled to the third node.

6. The ESD circuit a first diode; a second diode coupled in series with the first diode between the first voltage rail and the second voltage rail; and a fourth node between the first diode and the second diode is coincident with or coupled to the third node.

7. 7. The IC of claim 6, wherein the first diode and the second diode are reverse biased.

8. The IC of claim 3 , further comprising a transceiver, transmitter, or receiver coupled to the third node.

9. The IC of claim 8 further comprising an electrostatic discharge (ESD) circuit coupled to the second node.

10. 2. The IC of claim 1, wherein the IC bump includes an underbump metallization (UBM) electrically coupled to the T-coil through the first metallized via.

11. 11. The IC of claim 10, wherein the UBM is disposed on and electrically coupled to a bond pad aluminum (AP) layer.

12. 12. The IC of claim 11, further comprising a dielectric layer disposed between the AP layer and the T-coil, the first metallized via hole extending through the dielectric layer.

13. The T coil is a first inductor winding disposed on a first metal layer; a second inductor winding disposed on the second metal layer; The IC of claim 1 .

14. 14. The IC of claim 13, wherein the first inductor winding extends from the first metallized via hole to a second metallized via hole.

15. 15. The IC of claim 14, wherein the second inductor winding is electrically coupled to the first inductor winding through the second metallized via hole.

16. 16. The IC of claim 15, further comprising a first dielectric layer disposed between the IC bump and the first inductor winding, the first metallized via hole extending through the first dielectric layer.

17. 17. The IC of claim 16, further comprising a second dielectric layer disposed between the first inductor winding and the second inductor winding, the second metallized via hole extending through the second dielectric layer.

18. 16. The IC of claim 15, wherein the second inductor winding extends from the second metallized via hole to a first node.

19. 20. The IC of claim 18, further comprising a transceiver, transmitter, or receiver coupled to the first node.

20. 20. The IC of claim 18, further comprising an electrostatic discharge (ESD) circuit coupled to the first node.

21. 20. The IC of claim 18, further comprising a leadout interconnect coupled between the first inductor winding or the second inductor winding and a second node.

22. 22. The IC of claim 21, further comprising a transceiver, transmitter, or receiver coupled to the second node.

23. 22. The IC of claim 21 further comprising an electrostatic discharge (ESD) circuit coupled to the second node.

24. The IC of claim 1 , wherein the IC bumps are electrically coupled to transmission lines on a printed circuit board (PCB).

25. 25. The IC of claim 24, wherein the transmission line comprises a differential transmission line.

26. a printed circuit board (PCB) containing a set of transmission lines; a first integrated circuit (IC) mounted on the PCB, the first integrated circuit (IC) including a first set of IC interface circuits; 1. A data communication system comprising: a first set of IC bumps electrically coupled to the set of transmission lines, respectively; a first set of T-coils, each T-coil of the first set of T-coils being positioned directly below a respective IC bump of the first set of IC bumps, the first set of T-coils being electrically coupled to the first set of IC bumps via a first set of metallized via holes; A data communication system comprising:

27. The device further includes a second IC mounted on the PCB, the second IC including a second set of IC interface circuits, the second IC comprising: a second set of IC bumps electrically coupled to the set of transmission lines, respectively; a second set of T-coils, each T-coil of the second set of T-coils being positioned directly below a respective IC bump of the second set of IC bumps, the second set of T-coils being electrically coupled to the second set of IC bumps via a second set of metallized via holes; 27. The data communication system of claim 26, comprising:

28. The first IC comprises: a set of transmitters respectively coupled to the first set of T-coils; a first set of electrostatic discharge (ESD) circuits respectively coupled to the first set of T-coils; Equipped with The second IC comprises: a set of receivers respectively coupled to the second set of T-coils; a second set of ESD circuits respectively coupled to the second set of T-coils; 28. The data communication system of claim 27, comprising:

29. The first IC comprises: a first set of transceivers respectively coupled to the first set of T-coils; a first set of electrostatic discharge (ESD) circuits respectively coupled to the first set of T-coils; Equipped with The second IC comprises: a second set of transceivers respectively coupled to the second set of T-coils; a second set of ESD circuits respectively coupled to the second set of T-coils; 28. The data communication system of claim 27, comprising:

30. at least one antenna; a transceiver coupled to the at least one antenna; an integrated circuit (IC) including one or more signal processing cores, the integrated circuit (IC) including a set of IC interface circuits; 1. A wireless communication device comprising: a set of IC bumps electrically coupled to a set of transmission lines respectively electrically coupling the IC to the transceiver; a set of T-coils, each T-coil of the set being positioned directly below a respective IC bump of the set of IC bumps, the set of T-coils being respectively electrically coupled to the set of IC bumps through a set of metallized via holes; Equipped with Wireless communication devices.

31. a set of differential IC bumps; a set of differential T-coils positioned at least partially beneath the set of differential IC bumps, the set of differential T-coils being electrically coupled to the set of differential IC bumps through a set of metallized via holes; An integrated circuit (IC) comprising:

32. 32. The IC of claim 31, wherein the set of differential IC bumps and the set of differential T-coils lie substantially along a pitch axis.

33. 33. The IC of claim 32, wherein the distance between the sets of differential IC bumps is greater than the distance between the sets of differential T-coils.

34. 32. The IC of claim 31 , wherein the set of differential IC bumps is located along a first pitch axis and the set of differential T-coils is located along a second pitch axis, the second pitch axis being offset from the first pitch axis.

35. 35. The IC of claim 34, wherein a distance between the sets of differential IC bumps along the first pitch axis is greater than a distance between the sets of differential T-coils along the second pitch axis.

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